GNU Linux-libre 4.19.286-gnu1
[releases.git] / drivers / staging / rtl8188eu / include / odm_reg.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /******************************************************************************
3  *
4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5  *
6  ******************************************************************************/
7 /*  */
8 /*  File Name: odm_reg.h */
9 /*  */
10 /*  Description: */
11 /*  */
12 /*  This file is for general register definition. */
13 /*  */
14 /*  */
15 /*  */
16 #ifndef __HAL_ODM_REG_H__
17 #define __HAL_ODM_REG_H__
18
19 /*  */
20 /*  Register Definition */
21 /*  */
22
23 /* MAC REG */
24 #define ODM_BB_RESET                                    0x002
25 #define ODM_DUMMY                                               0x4fe
26 #define ODM_EDCA_VO_PARAM                       0x500
27 #define ODM_EDCA_VI_PARAM                       0x504
28 #define ODM_EDCA_BE_PARAM                       0x508
29 #define ODM_EDCA_BK_PARAM                       0x50C
30 #define ODM_TXPAUSE                                     0x522
31
32 /* BB REG */
33 #define ODM_FPGA_PHY0_PAGE8                     0x800
34 #define ODM_PSD_SETTING                         0x808
35 #define ODM_AFE_SETTING                         0x818
36 #define ODM_TXAGC_B_6_18                                0x830
37 #define ODM_TXAGC_B_24_54                       0x834
38 #define ODM_TXAGC_B_MCS32_5                     0x838
39 #define ODM_TXAGC_B_MCS0_MCS3           0x83c
40 #define ODM_TXAGC_B_MCS4_MCS7           0x848
41 #define ODM_TXAGC_B_MCS8_MCS11          0x84c
42 #define ODM_ANALOG_REGISTER                     0x85c
43 #define ODM_RF_INTERFACE_OUTPUT         0x860
44 #define ODM_TXAGC_B_MCS12_MCS15 0x868
45 #define ODM_TXAGC_B_11_A_2_11           0x86c
46 #define ODM_AD_DA_LSB_MASK                      0x874
47 #define ODM_ENABLE_3_WIRE                       0x88c
48 #define ODM_PSD_REPORT                          0x8b4
49 #define ODM_R_ANT_SELECT                                0x90c
50 #define ODM_CCK_ANT_SELECT                      0xa07
51 #define ODM_CCK_PD_THRESH                       0xa0a
52 #define ODM_CCK_RF_REG1                         0xa11
53 #define ODM_CCK_MATCH_FILTER                    0xa20
54 #define ODM_CCK_RAKE_MAC                                0xa2e
55 #define ODM_CCK_CNT_RESET                       0xa2d
56 #define ODM_CCK_TX_DIVERSITY                    0xa2f
57 #define ODM_CCK_FA_CNT_MSB                      0xa5b
58 #define ODM_CCK_FA_CNT_LSB                      0xa5c
59 #define ODM_CCK_NEW_FUNCTION            0xa75
60 #define ODM_OFDM_PHY0_PAGE_C            0xc00
61 #define ODM_OFDM_RX_ANT                         0xc04
62 #define ODM_R_A_RXIQI                                   0xc14
63 #define ODM_R_A_AGC_CORE1                       0xc50
64 #define ODM_R_A_AGC_CORE2                       0xc54
65 #define ODM_R_B_AGC_CORE1                       0xc58
66 #define ODM_R_AGC_PAR                                   0xc70
67 #define ODM_R_HTSTF_AGC_PAR                     0xc7c
68 #define ODM_TX_PWR_TRAINING_A           0xc90
69 #define ODM_TX_PWR_TRAINING_B           0xc98
70 #define ODM_OFDM_FA_CNT1                                0xcf0
71 #define ODM_OFDM_PHY0_PAGE_D            0xd00
72 #define ODM_OFDM_FA_CNT2                                0xda0
73 #define ODM_OFDM_FA_CNT3                                0xda4
74 #define ODM_OFDM_FA_CNT4                                0xda8
75 #define ODM_TXAGC_A_6_18                                0xe00
76 #define ODM_TXAGC_A_24_54                       0xe04
77 #define ODM_TXAGC_A_1_MCS32                     0xe08
78 #define ODM_TXAGC_A_MCS0_MCS3           0xe10
79 #define ODM_TXAGC_A_MCS4_MCS7           0xe14
80 #define ODM_TXAGC_A_MCS8_MCS11          0xe18
81 #define ODM_TXAGC_A_MCS12_MCS15         0xe1c
82
83 /* RF REG */
84 #define ODM_GAIN_SETTING                                0x00
85 #define ODM_CHANNEL                                     0x18
86
87 /* Ant Detect Reg */
88 #define ODM_DPDT                                                0x300
89
90 /* PSD Init */
91 #define ODM_PSDREG                                      0x808
92
93 /* 92D Path Div */
94 #define PATHDIV_REG                                     0xB30
95 #define PATHDIV_TRI                                     0xBA0
96
97
98 /*  */
99 /*  Bitmap Definition */
100 /*  */
101
102 #define BIT_FA_RESET                                    BIT(0)
103
104
105
106 #endif