drivers/staging/rtl8723bs/hal/hal_com.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _HAL_COM_C_
  16
  17 #include <drv_types.h>
  18 #include <rtw_debug.h>
  19 #include "hal_com_h2c.h"
  20
  21 #include "odm_precomp.h"
  22
  23 u8 rtw_hal_data_init(struct adapter *padapter)
  24 {
  25         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  26                 padapter->hal_data_sz = sizeof(struct hal_com_data);
  27                 padapter->HalData = vzalloc(padapter->hal_data_sz);
  28                 if (padapter->HalData == NULL) {
  29                         DBG_8192C("cannot alloc memory for HAL DATA\n");
  30                         return _FAIL;
  31                 }
  32         }
  33         return _SUCCESS;
  34 }
  35
  36 void rtw_hal_data_deinit(struct adapter *padapter)
  37 {
  38         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  39                 if (padapter->HalData) {
  40                         phy_free_filebuf(padapter);
  41                         vfree(padapter->HalData);
  42                         padapter->HalData = NULL;
  43                         padapter->hal_data_sz = 0;
  44                 }
  45         }
  46 }
  47
  48
  49 void dump_chip_info(HAL_VERSION ChipVersion)
  50 {
  51         int cnt = 0;
  52         u8 buf[128];
  53
  54         cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
  55         cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
  56         if (IS_CHIP_VENDOR_TSMC(ChipVersion))
  57                 cnt += sprintf((buf+cnt), "%s_", "TSMC");
  58         else if (IS_CHIP_VENDOR_UMC(ChipVersion))
  59                 cnt += sprintf((buf+cnt), "%s_", "UMC");
  60         else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
  61                 cnt += sprintf((buf+cnt), "%s_", "SMIC");
  62
  63         if (IS_A_CUT(ChipVersion))
  64                 cnt += sprintf((buf+cnt), "A_CUT_");
  65         else if (IS_B_CUT(ChipVersion))
  66                 cnt += sprintf((buf+cnt), "B_CUT_");
  67         else if (IS_C_CUT(ChipVersion))
  68                 cnt += sprintf((buf+cnt), "C_CUT_");
  69         else if (IS_D_CUT(ChipVersion))
  70                 cnt += sprintf((buf+cnt), "D_CUT_");
  71         else if (IS_E_CUT(ChipVersion))
  72                 cnt += sprintf((buf+cnt), "E_CUT_");
  73         else if (IS_I_CUT(ChipVersion))
  74                 cnt += sprintf((buf+cnt), "I_CUT_");
  75         else if (IS_J_CUT(ChipVersion))
  76                 cnt += sprintf((buf+cnt), "J_CUT_");
  77         else if (IS_K_CUT(ChipVersion))
  78                 cnt += sprintf((buf+cnt), "K_CUT_");
  79         else
  80                 cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
  81
  82         if (IS_1T1R(ChipVersion))
  83                 cnt += sprintf((buf+cnt), "1T1R_");
  84         else if (IS_1T2R(ChipVersion))
  85                 cnt += sprintf((buf+cnt), "1T2R_");
  86         else if (IS_2T2R(ChipVersion))
  87                 cnt += sprintf((buf+cnt), "2T2R_");
  88         else
  89                 cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
  90
  91         cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
  92
  93         DBG_871X("%s", buf);
  94 }
  95
  96
  97 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK  0x80
  98
  99 /*
 100  * Description:
 101  *Use hardware(efuse), driver parameter(registry) and default channel plan
 102  *to decide which one should be used.
 103  *
 104  * Parameters:
 105  *padapter                      pointer of adapter
 106  *hw_channel_plan               channel plan from HW (efuse/eeprom)
 107  *                                      BIT[7] software configure mode; 0:Enable, 1:disable
 108  *                                      BIT[6:0] Channel Plan
 109  *sw_channel_plan               channel plan from SW (registry/module param)
 110  *def_channel_plan      channel plan used when HW/SW both invalid
 111  *AutoLoadFail          efuse autoload fail or not
 112  *
 113  * Return:
 114  *Final channel plan decision
 115  *
 116  */
 117 u8 hal_com_config_channel_plan(
 118         struct adapter *padapter,
 119         u8 hw_channel_plan,
 120         u8 sw_channel_plan,
 121         u8 def_channel_plan,
 122         bool AutoLoadFail
 123 )
 124 {
 125         struct hal_com_data *pHalData;
 126         u8 chnlPlan;
 127
 128         pHalData = GET_HAL_DATA(padapter);
 129         pHalData->bDisableSWChannelPlan = false;
 130         chnlPlan = def_channel_plan;
 131
 132         if (0xFF == hw_channel_plan)
 133                 AutoLoadFail = true;
 134
 135         if (false == AutoLoadFail) {
 136                 u8 hw_chnlPlan;
 137
 138                 hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
 139                 if (rtw_is_channel_plan_valid(hw_chnlPlan)) {
 140 #ifndef CONFIG_SW_CHANNEL_PLAN
 141                         if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
 142                                 pHalData->bDisableSWChannelPlan = true;
 143 #endif /*  !CONFIG_SW_CHANNEL_PLAN */
 144
 145                         chnlPlan = hw_chnlPlan;
 146                 }
 147         }
 148
 149         if (
 150                 (false == pHalData->bDisableSWChannelPlan) &&
 151                 rtw_is_channel_plan_valid(sw_channel_plan)
 152         )
 153                 chnlPlan = sw_channel_plan;
 154
 155         return chnlPlan;
 156 }
 157
 158 bool HAL_IsLegalChannel(struct adapter *Adapter, u32 Channel)
 159 {
 160         bool bLegalChannel = true;
 161
 162         if (Channel > 14) {
 163                 bLegalChannel = false;
 164                 DBG_871X("Channel > 14 but wireless_mode do not support 5G\n");
 165         } else if ((Channel <= 14) && (Channel >= 1)) {
 166                 if (IsSupported24G(Adapter->registrypriv.wireless_mode) == false) {
 167                         bLegalChannel = false;
 168                         DBG_871X("(Channel <= 14) && (Channel >= 1) but wireless_mode do not support 2.4G\n");
 169                 }
 170         } else {
 171                 bLegalChannel = false;
 172                 DBG_871X("Channel is Invalid !!!\n");
 173         }
 174
 175         return bLegalChannel;
 176 }
 177
 178 u8 MRateToHwRate(u8 rate)
 179 {
 180         u8 ret = DESC_RATE1M;
 181
 182         switch (rate) {
 183         case MGN_1M:
 184                 ret = DESC_RATE1M;
 185                 break;
 186         case MGN_2M:
 187                 ret = DESC_RATE2M;
 188                 break;
 189         case MGN_5_5M:
 190                 ret = DESC_RATE5_5M;
 191                 break;
 192         case MGN_11M:
 193                 ret = DESC_RATE11M;
 194                 break;
 195         case MGN_6M:
 196                 ret = DESC_RATE6M;
 197                 break;
 198         case MGN_9M:
 199                 ret = DESC_RATE9M;
 200                 break;
 201         case MGN_12M:
 202                 ret = DESC_RATE12M;
 203                 break;
 204         case MGN_18M:
 205                 ret = DESC_RATE18M;
 206                 break;
 207         case MGN_24M:
 208                 ret = DESC_RATE24M;
 209                 break;
 210         case MGN_36M:
 211                 ret = DESC_RATE36M;
 212                 break;
 213         case MGN_48M:
 214                 ret = DESC_RATE48M;
 215                 break;
 216         case MGN_54M:
 217                 ret = DESC_RATE54M;
 218                 break;
 219         case MGN_MCS0:
 220                 ret = DESC_RATEMCS0;
 221                 break;
 222         case MGN_MCS1:
 223                 ret = DESC_RATEMCS1;
 224                 break;
 225         case MGN_MCS2:
 226                 ret = DESC_RATEMCS2;
 227                 break;
 228         case MGN_MCS3:
 229                 ret = DESC_RATEMCS3;
 230                 break;
 231         case MGN_MCS4:
 232                 ret = DESC_RATEMCS4;
 233                 break;
 234         case MGN_MCS5:
 235                 ret = DESC_RATEMCS5;
 236                 break;
 237         case MGN_MCS6:
 238                 ret = DESC_RATEMCS6;
 239                 break;
 240         case MGN_MCS7:
 241                 ret = DESC_RATEMCS7;
 242                 break;
 243         case MGN_MCS8:
 244                 ret = DESC_RATEMCS8;
 245                 break;
 246         case MGN_MCS9:
 247                 ret = DESC_RATEMCS9;
 248                 break;
 249         case MGN_MCS10:
 250                 ret = DESC_RATEMCS10;
 251                 break;
 252         case MGN_MCS11:
 253                 ret = DESC_RATEMCS11;
 254                 break;
 255         case MGN_MCS12:
 256                 ret = DESC_RATEMCS12;
 257                 break;
 258         case MGN_MCS13:
 259                 ret = DESC_RATEMCS13;
 260                 break;
 261         case MGN_MCS14:
 262                 ret = DESC_RATEMCS14;
 263                 break;
 264         case MGN_MCS15:
 265                 ret = DESC_RATEMCS15;
 266                 break;
 267         case MGN_MCS16:
 268                 ret = DESC_RATEMCS16;
 269                 break;
 270         case MGN_MCS17:
 271                 ret = DESC_RATEMCS17;
 272                 break;
 273         case MGN_MCS18:
 274                 ret = DESC_RATEMCS18;
 275                 break;
 276         case MGN_MCS19:
 277                 ret = DESC_RATEMCS19;
 278                 break;
 279         case MGN_MCS20:
 280                 ret = DESC_RATEMCS20;
 281                 break;
 282         case MGN_MCS21:
 283                 ret = DESC_RATEMCS21;
 284                 break;
 285         case MGN_MCS22:
 286                 ret = DESC_RATEMCS22;
 287                 break;
 288         case MGN_MCS23:
 289                 ret = DESC_RATEMCS23;
 290                 break;
 291         case MGN_MCS24:
 292                 ret = DESC_RATEMCS24;
 293                 break;
 294         case MGN_MCS25:
 295                 ret = DESC_RATEMCS25;
 296                 break;
 297         case MGN_MCS26:
 298                 ret = DESC_RATEMCS26;
 299                 break;
 300         case MGN_MCS27:
 301                 ret = DESC_RATEMCS27;
 302                 break;
 303         case MGN_MCS28:
 304                 ret = DESC_RATEMCS28;
 305                 break;
 306         case MGN_MCS29:
 307                 ret = DESC_RATEMCS29;
 308                 break;
 309         case MGN_MCS30:
 310                 ret = DESC_RATEMCS30;
 311                 break;
 312         case MGN_MCS31:
 313                 ret = DESC_RATEMCS31;
 314                 break;
 315         case MGN_VHT1SS_MCS0:
 316                 ret = DESC_RATEVHTSS1MCS0;
 317                 break;
 318         case MGN_VHT1SS_MCS1:
 319                 ret = DESC_RATEVHTSS1MCS1;
 320                 break;
 321         case MGN_VHT1SS_MCS2:
 322                 ret = DESC_RATEVHTSS1MCS2;
 323                 break;
 324         case MGN_VHT1SS_MCS3:
 325                 ret = DESC_RATEVHTSS1MCS3;
 326                 break;
 327         case MGN_VHT1SS_MCS4:
 328                 ret = DESC_RATEVHTSS1MCS4;
 329                 break;
 330         case MGN_VHT1SS_MCS5:
 331                 ret = DESC_RATEVHTSS1MCS5;
 332                 break;
 333         case MGN_VHT1SS_MCS6:
 334                 ret = DESC_RATEVHTSS1MCS6;
 335                 break;
 336         case MGN_VHT1SS_MCS7:
 337                 ret = DESC_RATEVHTSS1MCS7;
 338                 break;
 339         case MGN_VHT1SS_MCS8:
 340                 ret = DESC_RATEVHTSS1MCS8;
 341                 break;
 342         case MGN_VHT1SS_MCS9:
 343                 ret = DESC_RATEVHTSS1MCS9;
 344                 break;
 345         case MGN_VHT2SS_MCS0:
 346                 ret = DESC_RATEVHTSS2MCS0;
 347                 break;
 348         case MGN_VHT2SS_MCS1:
 349                 ret = DESC_RATEVHTSS2MCS1;
 350                 break;
 351         case MGN_VHT2SS_MCS2:
 352                 ret = DESC_RATEVHTSS2MCS2;
 353                 break;
 354         case MGN_VHT2SS_MCS3:
 355                 ret = DESC_RATEVHTSS2MCS3;
 356                 break;
 357         case MGN_VHT2SS_MCS4:
 358                 ret = DESC_RATEVHTSS2MCS4;
 359                 break;
 360         case MGN_VHT2SS_MCS5:
 361                 ret = DESC_RATEVHTSS2MCS5;
 362                 break;
 363         case MGN_VHT2SS_MCS6:
 364                 ret = DESC_RATEVHTSS2MCS6;
 365                 break;
 366         case MGN_VHT2SS_MCS7:
 367                 ret = DESC_RATEVHTSS2MCS7;
 368                 break;
 369         case MGN_VHT2SS_MCS8:
 370                 ret = DESC_RATEVHTSS2MCS8;
 371                 break;
 372         case MGN_VHT2SS_MCS9:
 373                 ret = DESC_RATEVHTSS2MCS9;
 374                 break;
 375         case MGN_VHT3SS_MCS0:
 376                 ret = DESC_RATEVHTSS3MCS0;
 377                 break;
 378         case MGN_VHT3SS_MCS1:
 379                 ret = DESC_RATEVHTSS3MCS1;
 380                 break;
 381         case MGN_VHT3SS_MCS2:
 382                 ret = DESC_RATEVHTSS3MCS2;
 383                 break;
 384         case MGN_VHT3SS_MCS3:
 385                 ret = DESC_RATEVHTSS3MCS3;
 386                 break;
 387         case MGN_VHT3SS_MCS4:
 388                 ret = DESC_RATEVHTSS3MCS4;
 389                 break;
 390         case MGN_VHT3SS_MCS5:
 391                 ret = DESC_RATEVHTSS3MCS5;
 392                 break;
 393         case MGN_VHT3SS_MCS6:
 394                 ret = DESC_RATEVHTSS3MCS6;
 395                 break;
 396         case MGN_VHT3SS_MCS7:
 397                 ret = DESC_RATEVHTSS3MCS7;
 398                 break;
 399         case MGN_VHT3SS_MCS8:
 400                 ret = DESC_RATEVHTSS3MCS8;
 401                 break;
 402         case MGN_VHT3SS_MCS9:
 403                 ret = DESC_RATEVHTSS3MCS9;
 404                 break;
 405         case MGN_VHT4SS_MCS0:
 406                 ret = DESC_RATEVHTSS4MCS0;
 407                 break;
 408         case MGN_VHT4SS_MCS1:
 409                 ret = DESC_RATEVHTSS4MCS1;
 410                 break;
 411         case MGN_VHT4SS_MCS2:
 412                 ret = DESC_RATEVHTSS4MCS2;
 413                 break;
 414         case MGN_VHT4SS_MCS3:
 415                 ret = DESC_RATEVHTSS4MCS3;
 416                 break;
 417         case MGN_VHT4SS_MCS4:
 418                 ret = DESC_RATEVHTSS4MCS4;
 419                 break;
 420         case MGN_VHT4SS_MCS5:
 421                 ret = DESC_RATEVHTSS4MCS5;
 422                 break;
 423         case MGN_VHT4SS_MCS6:
 424                 ret = DESC_RATEVHTSS4MCS6;
 425                 break;
 426         case MGN_VHT4SS_MCS7:
 427                 ret = DESC_RATEVHTSS4MCS7;
 428                 break;
 429         case MGN_VHT4SS_MCS8:
 430                 ret = DESC_RATEVHTSS4MCS8;
 431                 break;
 432         case MGN_VHT4SS_MCS9:
 433                 ret = DESC_RATEVHTSS4MCS9;
 434                 break;
 435         default:
 436                 break;
 437         }
 438
 439         return ret;
 440 }
 441
 442 u8 HwRateToMRate(u8 rate)
 443 {
 444         u8 ret_rate = MGN_1M;
 445
 446         switch (rate) {
 447         case DESC_RATE1M:
 448                 ret_rate = MGN_1M;
 449                 break;
 450         case DESC_RATE2M:
 451                 ret_rate = MGN_2M;
 452                 break;
 453         case DESC_RATE5_5M:
 454                 ret_rate = MGN_5_5M;
 455                 break;
 456         case DESC_RATE11M:
 457                 ret_rate = MGN_11M;
 458                 break;
 459         case DESC_RATE6M:
 460                 ret_rate = MGN_6M;
 461                 break;
 462         case DESC_RATE9M:
 463                 ret_rate = MGN_9M;
 464                 break;
 465         case DESC_RATE12M:
 466                 ret_rate = MGN_12M;
 467                 break;
 468         case DESC_RATE18M:
 469                 ret_rate = MGN_18M;
 470                 break;
 471         case DESC_RATE24M:
 472                 ret_rate = MGN_24M;
 473                 break;
 474         case DESC_RATE36M:
 475                 ret_rate = MGN_36M;
 476                 break;
 477         case DESC_RATE48M:
 478                 ret_rate = MGN_48M;
 479                 break;
 480         case DESC_RATE54M:
 481                 ret_rate = MGN_54M;
 482                 break;
 483         case DESC_RATEMCS0:
 484                 ret_rate = MGN_MCS0;
 485                 break;
 486         case DESC_RATEMCS1:
 487                 ret_rate = MGN_MCS1;
 488                 break;
 489         case DESC_RATEMCS2:
 490                 ret_rate = MGN_MCS2;
 491                 break;
 492         case DESC_RATEMCS3:
 493                 ret_rate = MGN_MCS3;
 494                 break;
 495         case DESC_RATEMCS4:
 496                 ret_rate = MGN_MCS4;
 497                 break;
 498         case DESC_RATEMCS5:
 499                 ret_rate = MGN_MCS5;
 500                 break;
 501         case DESC_RATEMCS6:
 502                 ret_rate = MGN_MCS6;
 503                 break;
 504         case DESC_RATEMCS7:
 505                 ret_rate = MGN_MCS7;
 506                 break;
 507         case DESC_RATEMCS8:
 508                 ret_rate = MGN_MCS8;
 509                 break;
 510         case DESC_RATEMCS9:
 511                 ret_rate = MGN_MCS9;
 512                 break;
 513         case DESC_RATEMCS10:
 514                 ret_rate = MGN_MCS10;
 515                 break;
 516         case DESC_RATEMCS11:
 517                 ret_rate = MGN_MCS11;
 518                 break;
 519         case DESC_RATEMCS12:
 520                 ret_rate = MGN_MCS12;
 521                 break;
 522         case DESC_RATEMCS13:
 523                 ret_rate = MGN_MCS13;
 524                 break;
 525         case DESC_RATEMCS14:
 526                 ret_rate = MGN_MCS14;
 527                 break;
 528         case DESC_RATEMCS15:
 529                 ret_rate = MGN_MCS15;
 530                 break;
 531         case DESC_RATEMCS16:
 532                 ret_rate = MGN_MCS16;
 533                 break;
 534         case DESC_RATEMCS17:
 535                 ret_rate = MGN_MCS17;
 536                 break;
 537         case DESC_RATEMCS18:
 538                 ret_rate = MGN_MCS18;
 539                 break;
 540         case DESC_RATEMCS19:
 541                 ret_rate = MGN_MCS19;
 542                 break;
 543         case DESC_RATEMCS20:
 544                 ret_rate = MGN_MCS20;
 545                 break;
 546         case DESC_RATEMCS21:
 547                 ret_rate = MGN_MCS21;
 548                 break;
 549         case DESC_RATEMCS22:
 550                 ret_rate = MGN_MCS22;
 551                 break;
 552         case DESC_RATEMCS23:
 553                 ret_rate = MGN_MCS23;
 554                 break;
 555         case DESC_RATEMCS24:
 556                 ret_rate = MGN_MCS24;
 557                 break;
 558         case DESC_RATEMCS25:
 559                 ret_rate = MGN_MCS25;
 560                 break;
 561         case DESC_RATEMCS26:
 562                 ret_rate = MGN_MCS26;
 563                 break;
 564         case DESC_RATEMCS27:
 565                 ret_rate = MGN_MCS27;
 566                 break;
 567         case DESC_RATEMCS28:
 568                 ret_rate = MGN_MCS28;
 569                 break;
 570         case DESC_RATEMCS29:
 571                 ret_rate = MGN_MCS29;
 572                 break;
 573         case DESC_RATEMCS30:
 574                 ret_rate = MGN_MCS30;
 575                 break;
 576         case DESC_RATEMCS31:
 577                 ret_rate = MGN_MCS31;
 578                 break;
 579         case DESC_RATEVHTSS1MCS0:
 580                 ret_rate = MGN_VHT1SS_MCS0;
 581                 break;
 582         case DESC_RATEVHTSS1MCS1:
 583                 ret_rate = MGN_VHT1SS_MCS1;
 584                 break;
 585         case DESC_RATEVHTSS1MCS2:
 586                 ret_rate = MGN_VHT1SS_MCS2;
 587                 break;
 588         case DESC_RATEVHTSS1MCS3:
 589                 ret_rate = MGN_VHT1SS_MCS3;
 590                 break;
 591         case DESC_RATEVHTSS1MCS4:
 592                 ret_rate = MGN_VHT1SS_MCS4;
 593                 break;
 594         case DESC_RATEVHTSS1MCS5:
 595                 ret_rate = MGN_VHT1SS_MCS5;
 596                 break;
 597         case DESC_RATEVHTSS1MCS6:
 598                 ret_rate = MGN_VHT1SS_MCS6;
 599                 break;
 600         case DESC_RATEVHTSS1MCS7:
 601                 ret_rate = MGN_VHT1SS_MCS7;
 602                 break;
 603         case DESC_RATEVHTSS1MCS8:
 604                 ret_rate = MGN_VHT1SS_MCS8;
 605                 break;
 606         case DESC_RATEVHTSS1MCS9:
 607                 ret_rate = MGN_VHT1SS_MCS9;
 608                 break;
 609         case DESC_RATEVHTSS2MCS0:
 610                 ret_rate = MGN_VHT2SS_MCS0;
 611                 break;
 612         case DESC_RATEVHTSS2MCS1:
 613                 ret_rate = MGN_VHT2SS_MCS1;
 614                 break;
 615         case DESC_RATEVHTSS2MCS2:
 616                 ret_rate = MGN_VHT2SS_MCS2;
 617                 break;
 618         case DESC_RATEVHTSS2MCS3:
 619                 ret_rate = MGN_VHT2SS_MCS3;
 620                 break;
 621         case DESC_RATEVHTSS2MCS4:
 622                 ret_rate = MGN_VHT2SS_MCS4;
 623                 break;
 624         case DESC_RATEVHTSS2MCS5:
 625                 ret_rate = MGN_VHT2SS_MCS5;
 626                 break;
 627         case DESC_RATEVHTSS2MCS6:
 628                 ret_rate = MGN_VHT2SS_MCS6;
 629                 break;
 630         case DESC_RATEVHTSS2MCS7:
 631                 ret_rate = MGN_VHT2SS_MCS7;
 632                 break;
 633         case DESC_RATEVHTSS2MCS8:
 634                 ret_rate = MGN_VHT2SS_MCS8;
 635                 break;
 636         case DESC_RATEVHTSS2MCS9:
 637                 ret_rate = MGN_VHT2SS_MCS9;
 638                 break;
 639         case DESC_RATEVHTSS3MCS0:
 640                 ret_rate = MGN_VHT3SS_MCS0;
 641                 break;
 642         case DESC_RATEVHTSS3MCS1:
 643                 ret_rate = MGN_VHT3SS_MCS1;
 644                 break;
 645         case DESC_RATEVHTSS3MCS2:
 646                 ret_rate = MGN_VHT3SS_MCS2;
 647                 break;
 648         case DESC_RATEVHTSS3MCS3:
 649                 ret_rate = MGN_VHT3SS_MCS3;
 650                 break;
 651         case DESC_RATEVHTSS3MCS4:
 652                 ret_rate = MGN_VHT3SS_MCS4;
 653                 break;
 654         case DESC_RATEVHTSS3MCS5:
 655                 ret_rate = MGN_VHT3SS_MCS5;
 656                 break;
 657         case DESC_RATEVHTSS3MCS6:
 658                 ret_rate = MGN_VHT3SS_MCS6;
 659                 break;
 660         case DESC_RATEVHTSS3MCS7:
 661                 ret_rate = MGN_VHT3SS_MCS7;
 662                 break;
 663         case DESC_RATEVHTSS3MCS8:
 664                 ret_rate = MGN_VHT3SS_MCS8;
 665                 break;
 666         case DESC_RATEVHTSS3MCS9:
 667                 ret_rate = MGN_VHT3SS_MCS9;
 668                 break;
 669         case DESC_RATEVHTSS4MCS0:
 670                 ret_rate = MGN_VHT4SS_MCS0;
 671                 break;
 672         case DESC_RATEVHTSS4MCS1:
 673                 ret_rate = MGN_VHT4SS_MCS1;
 674                 break;
 675         case DESC_RATEVHTSS4MCS2:
 676                 ret_rate = MGN_VHT4SS_MCS2;
 677                 break;
 678         case DESC_RATEVHTSS4MCS3:
 679                 ret_rate = MGN_VHT4SS_MCS3;
 680                 break;
 681         case DESC_RATEVHTSS4MCS4:
 682                 ret_rate = MGN_VHT4SS_MCS4;
 683                 break;
 684         case DESC_RATEVHTSS4MCS5:
 685                 ret_rate = MGN_VHT4SS_MCS5;
 686                 break;
 687         case DESC_RATEVHTSS4MCS6:
 688                 ret_rate = MGN_VHT4SS_MCS6;
 689                 break;
 690         case DESC_RATEVHTSS4MCS7:
 691                 ret_rate = MGN_VHT4SS_MCS7;
 692                 break;
 693         case DESC_RATEVHTSS4MCS8:
 694                 ret_rate = MGN_VHT4SS_MCS8;
 695                 break;
 696         case DESC_RATEVHTSS4MCS9:
 697                 ret_rate = MGN_VHT4SS_MCS9;
 698                 break;
 699
 700         default:
 701                 DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
 702                 break;
 703         }
 704
 705         return ret_rate;
 706 }
 707
 708 void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
 709 {
 710         u8 i, is_brate, brate;
 711
 712         for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
 713
 714                 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
 715                 brate = mBratesOS[i] & 0x7f;
 716
 717                 if (is_brate) {
 718                         switch (brate) {
 719                         case IEEE80211_CCK_RATE_1MB:
 720                                 *pBrateCfg |= RATE_1M;
 721                                 break;
 722                         case IEEE80211_CCK_RATE_2MB:
 723                                 *pBrateCfg |= RATE_2M;
 724                                 break;
 725                         case IEEE80211_CCK_RATE_5MB:
 726                                 *pBrateCfg |= RATE_5_5M;
 727                                 break;
 728                         case IEEE80211_CCK_RATE_11MB:
 729                                 *pBrateCfg |= RATE_11M;
 730                                 break;
 731                         case IEEE80211_OFDM_RATE_6MB:
 732                                 *pBrateCfg |= RATE_6M;
 733                                 break;
 734                         case IEEE80211_OFDM_RATE_9MB:
 735                                 *pBrateCfg |= RATE_9M;
 736                                 break;
 737                         case IEEE80211_OFDM_RATE_12MB:
 738                                 *pBrateCfg |= RATE_12M;
 739                                 break;
 740                         case IEEE80211_OFDM_RATE_18MB:
 741                                 *pBrateCfg |= RATE_18M;
 742                                 break;
 743                         case IEEE80211_OFDM_RATE_24MB:
 744                                 *pBrateCfg |= RATE_24M;
 745                                 break;
 746                         case IEEE80211_OFDM_RATE_36MB:
 747                                 *pBrateCfg |= RATE_36M;
 748                                 break;
 749                         case IEEE80211_OFDM_RATE_48MB:
 750                                 *pBrateCfg |= RATE_48M;
 751                                 break;
 752                         case IEEE80211_OFDM_RATE_54MB:
 753                                 *pBrateCfg |= RATE_54M;
 754                                 break;
 755                         }
 756                 }
 757         }
 758 }
 759
 760 static void _OneOutPipeMapping(struct adapter *padapter)
 761 {
 762         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 763
 764         pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 765         pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 766         pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
 767         pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 768
 769         pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 770         pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 771         pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 772         pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 773 }
 774
 775 static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 776 {
 777         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 778
 779         if (bWIFICfg) { /* WMM */
 780
 781                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 782                 /*   0,         1,      0,      1,      0,      0,      0,      0,              0       }; */
 783                 /* 0:ep_0 num, 1:ep_1 num */
 784
 785                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
 786                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 787                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 788                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 789
 790                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 791                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 792                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 793                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 794
 795         } else { /* typical setting */
 796
 797
 798                 /* BK,  BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 799                 /*   1,         1,      0,      0,      0,      0,      0,      0,              0       }; */
 800                 /* 0:ep_0 num, 1:ep_1 num */
 801
 802                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 803                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 804                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 805                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 806
 807                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 808                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 809                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 810                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 811
 812         }
 813
 814 }
 815
 816 static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 817 {
 818         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 819
 820         if (bWIFICfg) { /* for WMM */
 821
 822                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 823                 /*   1,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 824                 /* 0:H, 1:N, 2:L */
 825
 826                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 827                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 828                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 829                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 830
 831                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 832                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 833                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 834                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 835
 836         } else { /* typical setting */
 837
 838
 839                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 840                 /*   2,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 841                 /* 0:H, 1:N, 2:L */
 842
 843                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 844                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 845                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 846                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
 847
 848                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 849                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 850                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 851                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 852         }
 853
 854 }
 855
 856 bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
 857 {
 858         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 859
 860         bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
 861
 862         bool result = true;
 863
 864         switch (NumOutPipe) {
 865         case 2:
 866                 _TwoOutPipeMapping(padapter, bWIFICfg);
 867                 break;
 868         case 3:
 869         case 4:
 870                 _ThreeOutPipeMapping(padapter, bWIFICfg);
 871                 break;
 872         case 1:
 873                 _OneOutPipeMapping(padapter);
 874                 break;
 875         default:
 876                 result = false;
 877                 break;
 878         }
 879
 880         return result;
 881
 882 }
 883
 884 void hal_init_macaddr(struct adapter *adapter)
 885 {
 886         rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
 887 }
 888
 889 void rtw_init_hal_com_default_value(struct adapter *Adapter)
 890 {
 891         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 892
 893         pHalData->AntDetection = 1;
 894 }
 895
 896 /*
 897 * C2H event format:
 898 * Field  TRIGGER                CONTENT    CMD_SEQ      CMD_LEN          CMD_ID
 899 * BITS   [127:120]      [119:16]      [15:8]              [7:4]            [3:0]
 900 */
 901
 902 void c2h_evt_clear(struct adapter *adapter)
 903 {
 904         rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
 905 }
 906
 907 /*
 908 * C2H event format:
 909 * Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
 910 * BITS    [127:120]   [119:112]    [111:16]          [15:8]         [7:0]
 911 */
 912 s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
 913 {
 914         s32 ret = _FAIL;
 915         struct c2h_evt_hdr_88xx *c2h_evt;
 916         int i;
 917         u8 trigger;
 918
 919         if (buf == NULL)
 920                 goto exit;
 921
 922         trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 923
 924         if (trigger == C2H_EVT_HOST_CLOSE)
 925                 goto exit; /* Not ready */
 926         else if (trigger != C2H_EVT_FW_CLOSE)
 927                 goto clear_evt; /* Not a valid value */
 928
 929         c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
 930
 931         memset(c2h_evt, 0, 16);
 932
 933         c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
 934         c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
 935         c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
 936
 937         RT_PRINT_DATA(
 938                 _module_hal_init_c_,
 939                 _drv_info_,
 940                 "c2h_evt_read(): ",
 941                 &c2h_evt,
 942                 sizeof(c2h_evt)
 943         );
 944
 945         DBG_871X(
 946                 "%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
 947                 __func__,
 948                 c2h_evt->id,
 949                 c2h_evt->plen,
 950                 c2h_evt->seq,
 951                 trigger
 952         );
 953
 954         /* Read the content */
 955         for (i = 0; i < c2h_evt->plen; i++)
 956                 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
 957
 958         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
 959                 c2h_evt->payload, c2h_evt->plen);
 960
 961         ret = _SUCCESS;
 962
 963 clear_evt:
 964         /*
 965         * Clear event to notify FW we have read the command.
 966         * If this field isn't clear, the FW won't update the next command message.
 967         */
 968         c2h_evt_clear(adapter);
 969 exit:
 970         return ret;
 971 }
 972
 973
 974 u8  rtw_hal_networktype_to_raid(struct adapter *adapter, struct sta_info *psta)
 975 {
 976         return networktype_to_raid_ex(adapter, psta);
 977 }
 978
 979 u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
 980 {
 981
 982         u8 raid;
 983         raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B : RATEID_IDX_G;
 984         return raid;
 985 }
 986
 987 void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
 988 {
 989         u8 i, rf_type, limit;
 990         u32 tx_ra_bitmap;
 991
 992         if (psta == NULL)
 993                 return;
 994
 995         tx_ra_bitmap = 0;
 996
 997         /* b/g mode ra_bitmap */
 998         for (i = 0; i < sizeof(psta->bssrateset); i++) {
 999                 if (psta->bssrateset[i])
1000                         tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
1001         }
1002
1003         /* n mode ra_bitmap */
1004         if (psta->htpriv.ht_option) {
1005                 rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
1006                 if (rf_type == RF_2T2R)
1007                         limit = 16; /*  2R */
1008                 else
1009                         limit = 8; /*   1R */
1010
1011                 for (i = 0; i < limit; i++) {
1012                         if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
1013                                 tx_ra_bitmap |= BIT(i+12);
1014                 }
1015         }
1016
1017         psta->ra_mask = tx_ra_bitmap;
1018         psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
1019 }
1020
1021 void hw_var_port_switch(struct adapter *adapter)
1022 {
1023 }
1024
1025 void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1026 {
1027         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1028         DM_ODM_T *odm = &(hal_data->odmpriv);
1029
1030         switch (variable) {
1031         case HW_VAR_PORT_SWITCH:
1032                 hw_var_port_switch(adapter);
1033                 break;
1034         case HW_VAR_INIT_RTS_RATE:
1035                 rtw_warn_on(1);
1036                 break;
1037         case HW_VAR_SEC_CFG:
1038         {
1039                 u16 reg_scr;
1040
1041                 reg_scr = rtw_read16(adapter, REG_SECCFG);
1042                 rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1043         }
1044                 break;
1045         case HW_VAR_SEC_DK_CFG:
1046         {
1047                 struct security_priv *sec = &adapter->securitypriv;
1048                 u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1049
1050                 if (val) { /* Enable default key related setting */
1051                         reg_scr |= SCR_TXBCUSEDK;
1052                         if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1053                                 reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1054                 } else /* Disable default key related setting */
1055                         reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1056
1057                 rtw_write8(adapter, REG_SECCFG, reg_scr);
1058         }
1059                 break;
1060         case HW_VAR_DM_FLAG:
1061                 odm->SupportAbility = *((u32 *)val);
1062                 break;
1063         case HW_VAR_DM_FUNC_OP:
1064                 if (*((u8 *)val) == true) {
1065                         /* save dm flag */
1066                         odm->BK_SupportAbility = odm->SupportAbility;
1067                 } else {
1068                         /* restore dm flag */
1069                         odm->SupportAbility = odm->BK_SupportAbility;
1070                 }
1071                 break;
1072         case HW_VAR_DM_FUNC_SET:
1073                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1074                         struct dm_priv *dm = &hal_data->dmpriv;
1075                         dm->DMFlag = dm->InitDMFlag;
1076                         odm->SupportAbility = dm->InitODMFlag;
1077                 } else {
1078                         odm->SupportAbility |= *((u32 *)val);
1079                 }
1080                 break;
1081         case HW_VAR_DM_FUNC_CLR:
1082                 /*
1083                 * input is already a mask to clear function
1084                 * don't invert it again! George, Lucas@20130513
1085                 */
1086                 odm->SupportAbility &= *((u32 *)val);
1087                 break;
1088         case HW_VAR_AMPDU_MIN_SPACE:
1089                 /* TODO - Is something needed here? */
1090                 break;
1091         case HW_VAR_WIRELESS_MODE:
1092                 /* TODO - Is something needed here? */
1093                 break;
1094         default:
1095                 DBG_871X_LEVEL(
1096                         _drv_always_,
1097                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1098                         FUNC_ADPT_ARG(adapter),
1099                         variable
1100                 );
1101                 break;
1102         }
1103 }
1104
1105 void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1106 {
1107         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1108         DM_ODM_T *odm = &(hal_data->odmpriv);
1109
1110         switch (variable) {
1111         case HW_VAR_BASIC_RATE:
1112                 *((u16 *)val) = hal_data->BasicRateSet;
1113                 break;
1114         case HW_VAR_DM_FLAG:
1115                 *((u32 *)val) = odm->SupportAbility;
1116                 break;
1117         case HW_VAR_RF_TYPE:
1118                 *((u8 *)val) = hal_data->rf_type;
1119                 break;
1120         default:
1121                 DBG_871X_LEVEL(
1122                         _drv_always_,
1123                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1124                         FUNC_ADPT_ARG(adapter),
1125                         variable
1126                 );
1127                 break;
1128         }
1129 }
1130
1131
1132
1133
1134 u8 SetHalDefVar(
1135         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1136 )
1137 {
1138         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1139         DM_ODM_T *odm = &(hal_data->odmpriv);
1140         u8 bResult = _SUCCESS;
1141
1142         switch (variable) {
1143         case HW_DEF_FA_CNT_DUMP:
1144                 /* ODM_COMP_COMMON */
1145                 if (*((u8 *)value))
1146                         odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
1147                 else
1148                         odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
1149                 break;
1150         case HAL_DEF_DBG_RX_INFO_DUMP:
1151                 DBG_871X("============ Rx Info dump ===================\n");
1152                 DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
1153                         odm->bLinked, odm->RSSI_Min);
1154
1155                 if (odm->bLinked) {
1156                         DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1157                                 HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1158
1159                         #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1160                         rtw_dump_raw_rssi_info(adapter);
1161                         #endif
1162                 }
1163                 break;
1164         case HW_DEF_ODM_DBG_FLAG:
1165                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
1166                 break;
1167         case HW_DEF_ODM_DBG_LEVEL:
1168                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
1169                 break;
1170         case HAL_DEF_DBG_DM_FUNC:
1171         {
1172                 u8 dm_func = *((u8 *)value);
1173                 struct dm_priv *dm = &hal_data->dmpriv;
1174
1175                 if (dm_func == 0) { /* disable all dynamic func */
1176                         odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1177                         DBG_8192C("==> Disable all dynamic function...\n");
1178                 } else if (dm_func == 1) {/* disable DIG */
1179                         odm->SupportAbility  &= (~DYNAMIC_BB_DIG);
1180                         DBG_8192C("==> Disable DIG...\n");
1181                 } else if (dm_func == 2) {/* disable High power */
1182                         odm->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1183                 } else if (dm_func == 3) {/* disable tx power tracking */
1184                         odm->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
1185                         DBG_8192C("==> Disable tx power tracking...\n");
1186                 } else if (dm_func == 4) {/* disable BT coexistence */
1187                         dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1188                 } else if (dm_func == 5) {/* disable antenna diversity */
1189                         odm->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
1190                 } else if (dm_func == 6) {/* turn on all dynamic func */
1191                         if (!(odm->SupportAbility  & DYNAMIC_BB_DIG)) {
1192                                 DIG_T   *pDigTable = &odm->DM_DigTable;
1193                                 pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
1194                         }
1195                         dm->DMFlag |= DYNAMIC_FUNC_BT;
1196                         odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1197                         DBG_8192C("==> Turn on all dynamic function...\n");
1198                 }
1199         }
1200                 break;
1201         case HAL_DEF_DBG_DUMP_RXPKT:
1202                 hal_data->bDumpRxPkt = *((u8 *)value);
1203                 break;
1204         case HAL_DEF_DBG_DUMP_TXPKT:
1205                 hal_data->bDumpTxPkt = *((u8 *)value);
1206                 break;
1207         case HAL_DEF_ANT_DETECT:
1208                 hal_data->AntDetection = *((u8 *)value);
1209                 break;
1210         default:
1211                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1212                 bResult = _FAIL;
1213                 break;
1214         }
1215
1216         return bResult;
1217 }
1218
1219 u8 GetHalDefVar(
1220         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1221 )
1222 {
1223         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1224         DM_ODM_T *odm = &(hal_data->odmpriv);
1225         u8 bResult = _SUCCESS;
1226
1227         switch (variable) {
1228         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1229                 {
1230                         struct mlme_priv *pmlmepriv;
1231                         struct sta_priv *pstapriv;
1232                         struct sta_info *psta;
1233
1234                         pmlmepriv = &adapter->mlmepriv;
1235                         pstapriv = &adapter->stapriv;
1236                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1237                         if (psta)
1238                                 *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1239                 }
1240                 break;
1241         case HW_DEF_ODM_DBG_FLAG:
1242                 *((u64 *)value) = odm->DebugComponents;
1243                 break;
1244         case HW_DEF_ODM_DBG_LEVEL:
1245                 *((u32 *)value) = odm->DebugLevel;
1246                 break;
1247         case HAL_DEF_DBG_DM_FUNC:
1248                 *((u32 *)value) = hal_data->odmpriv.SupportAbility;
1249                 break;
1250         case HAL_DEF_DBG_DUMP_RXPKT:
1251                 *((u8 *)value) = hal_data->bDumpRxPkt;
1252                 break;
1253         case HAL_DEF_DBG_DUMP_TXPKT:
1254                 *((u8 *)value) = hal_data->bDumpTxPkt;
1255                 break;
1256         case HAL_DEF_ANT_DETECT:
1257                 *((u8 *)value) = hal_data->AntDetection;
1258                 break;
1259         case HAL_DEF_MACID_SLEEP:
1260                 *(u8 *)value = false;
1261                 break;
1262         case HAL_DEF_TX_PAGE_SIZE:
1263                 *((u32 *)value) = PAGE_SIZE_128;
1264                 break;
1265         default:
1266                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1267                 bResult = _FAIL;
1268                 break;
1269         }
1270
1271         return bResult;
1272 }
1273
1274 void GetHalODMVar(
1275         struct adapter *Adapter,
1276         enum HAL_ODM_VARIABLE eVariable,
1277         void *pValue1,
1278         void *pValue2
1279 )
1280 {
1281         switch (eVariable) {
1282 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1283         case HAL_ODM_NOISE_MONITOR:
1284                 {
1285                         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1286                         u8 chan = *(u8 *)pValue1;
1287                         *(s16 *)pValue2 = pHalData->noise[chan];
1288                         #ifdef DBG_NOISE_MONITOR
1289                         DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1290                                 chan, pHalData->noise[chan]);
1291                         #endif
1292
1293                 }
1294                 break;
1295 #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1296         default:
1297                 break;
1298         }
1299 }
1300
1301 void SetHalODMVar(
1302         struct adapter *Adapter,
1303         enum HAL_ODM_VARIABLE eVariable,
1304         void *pValue1,
1305         bool bSet
1306 )
1307 {
1308         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1309         PDM_ODM_T podmpriv = &pHalData->odmpriv;
1310         /* _irqL irqL; */
1311         switch (eVariable) {
1312         case HAL_ODM_STA_INFO:
1313                 {
1314                         struct sta_info *psta = pValue1;
1315                         if (bSet) {
1316                                 DBG_8192C("### Set STA_(%d) info ###\n", psta->mac_id);
1317                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1318                         } else {
1319                                 DBG_8192C("### Clean STA_(%d) info ###\n", psta->mac_id);
1320                                 /* spin_lock_bh(&pHalData->odm_stainfo_lock); */
1321                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1322
1323                                 /* spin_unlock_bh(&pHalData->odm_stainfo_lock); */
1324                     }
1325                 }
1326                 break;
1327         case HAL_ODM_P2P_STATE:
1328                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1329                 break;
1330         case HAL_ODM_WIFI_DISPLAY_STATE:
1331                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1332                 break;
1333         #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1334         case HAL_ODM_NOISE_MONITOR:
1335                 {
1336                         struct noise_info *pinfo = pValue1;
1337
1338                         #ifdef DBG_NOISE_MONITOR
1339                         DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d, IGIValue:0x%02x, max_time:%d (ms) ###\n",
1340                                 pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1341                         #endif
1342
1343                         pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1344                         DBG_871X("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
1345                         #ifdef DBG_NOISE_MONITOR
1346                         DBG_871X("noise_a = %d, noise_b = %d  noise_all:%d\n",
1347                                 podmpriv->noise_level.noise[ODM_RF_PATH_A],
1348                                 podmpriv->noise_level.noise[ODM_RF_PATH_B],
1349                                 podmpriv->noise_level.noise_all);
1350                         #endif
1351                 }
1352                 break;
1353         #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1354
1355         default:
1356                 break;
1357         }
1358 }
1359
1360
1361 bool eqNByte(u8 *str1, u8 *str2, u32 num)
1362 {
1363         if (num == 0)
1364                 return false;
1365         while (num > 0) {
1366                 num--;
1367                 if (str1[num] != str2[num])
1368                         return false;
1369         }
1370         return true;
1371 }
1372
1373 /*  */
1374 /*      Description: */
1375 /*              Return true if chTmp is represent for hex digit and */
1376 /*              false otherwise. */
1377 /*  */
1378 /*  */
1379 bool IsHexDigit(char chTmp)
1380 {
1381         if (
1382                 (chTmp >= '0' && chTmp <= '9') ||
1383                 (chTmp >= 'a' && chTmp <= 'f') ||
1384                 (chTmp >= 'A' && chTmp <= 'F')
1385         )
1386                 return true;
1387         else
1388                 return false;
1389 }
1390
1391
1392 /*  */
1393 /*      Description: */
1394 /*              Translate a character to hex digit. */
1395 /*  */
1396 u32 MapCharToHexDigit(char chTmp)
1397 {
1398         if (chTmp >= '0' && chTmp <= '9')
1399                 return (chTmp - '0');
1400         else if (chTmp >= 'a' && chTmp <= 'f')
1401                 return (10 + (chTmp - 'a'));
1402         else if (chTmp >= 'A' && chTmp <= 'F')
1403                 return (10 + (chTmp - 'A'));
1404         else
1405                 return 0;
1406 }
1407
1408
1409
1410 /*      Description: */
1411 /*              Parse hex number from the string pucStr. */
1412 bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove)
1413 {
1414         char *szScan = szStr;
1415
1416         /*  Check input parameter. */
1417         if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
1418                 DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
1419                          szStr, pu4bVal, pu4bMove);
1420                 return false;
1421         }
1422
1423         /*  Initialize output. */
1424         *pu4bMove = 0;
1425         *pu4bVal = 0;
1426
1427         /*  Skip leading space. */
1428         while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1429                 szScan++;
1430                 (*pu4bMove)++;
1431         }
1432
1433         /*  Skip leading '0x' or '0X'. */
1434         if (*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) {
1435                 szScan += 2;
1436                 (*pu4bMove) += 2;
1437         }
1438
1439         /*  Check if szScan is now pointer to a character for hex digit, */
1440         /*  if not, it means this is not a valid hex number. */
1441         if (!IsHexDigit(*szScan))
1442                 return false;
1443
1444         /*  Parse each digit. */
1445         do {
1446                 (*pu4bVal) <<= 4;
1447                 *pu4bVal += MapCharToHexDigit(*szScan);
1448
1449                 szScan++;
1450                 (*pu4bMove)++;
1451         } while (IsHexDigit(*szScan));
1452
1453         return true;
1454 }
1455
1456 bool GetFractionValueFromString(
1457         char *szStr, u8 *pInteger, u8 *pFraction, u32 *pu4bMove
1458 )
1459 {
1460         char *szScan = szStr;
1461
1462         /*  Initialize output. */
1463         *pu4bMove = 0;
1464         *pInteger = 0;
1465         *pFraction = 0;
1466
1467         /*  Skip leading space. */
1468         while (*szScan != '\0' &&       (*szScan == ' ' || *szScan == '\t')) {
1469                 ++szScan;
1470                 ++(*pu4bMove);
1471         }
1472
1473         /*  Parse each digit. */
1474         do {
1475                 (*pInteger) *= 10;
1476                 *pInteger += (*szScan - '0');
1477
1478                 ++szScan;
1479                 ++(*pu4bMove);
1480
1481                 if (*szScan == '.') {
1482                         ++szScan;
1483                         ++(*pu4bMove);
1484
1485                         if (*szScan < '0' || *szScan > '9')
1486                                 return false;
1487                         else {
1488                                 *pFraction = *szScan - '0';
1489                                 ++szScan;
1490                                 ++(*pu4bMove);
1491                                 return true;
1492                         }
1493                 }
1494         } while (*szScan >= '0' && *szScan <= '9');
1495
1496         return true;
1497 }
1498
1499 /*  */
1500 /*      Description: */
1501 /*              Return true if szStr is comment out with leading "//". */
1502 /*  */
1503 bool IsCommentString(char *szStr)
1504 {
1505         if (*szStr == '/' && *(szStr+1) == '/')
1506                 return true;
1507         else
1508                 return false;
1509 }
1510
1511 bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
1512 {
1513         u16 i = 0;
1514         *pInt = 0;
1515
1516         while (Str[i] != '\0') {
1517                 if (Str[i] >= '0' && Str[i] <= '9') {
1518                         *pInt *= 10;
1519                         *pInt += (Str[i] - '0');
1520                 } else
1521                         return false;
1522
1523                 ++i;
1524         }
1525
1526         return true;
1527 }
1528
1529 /*  <20121004, Kordan> For example,
1530  *  ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from
1531  *  a string "Hello [Kordan]".
1532  *  If RightQualifier does not exist, it will hang in the while loop
1533  */
1534 bool ParseQualifiedString(
1535         char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
1536 )
1537 {
1538         u32 i = 0, j = 0;
1539         char c = In[(*Start)++];
1540
1541         if (c != LeftQualifier)
1542                 return false;
1543
1544         i = (*Start);
1545         while ((c = In[(*Start)++]) != RightQualifier)
1546                 ; /*  find ']' */
1547         j = (*Start) - 2;
1548         strncpy((char *)Out, (const char *)(In+i), j-i+1);
1549
1550         return true;
1551 }
1552
1553 bool isAllSpaceOrTab(u8 *data, u8 size)
1554 {
1555         u8 cnt = 0, NumOfSpaceAndTab = 0;
1556
1557         while (size > cnt) {
1558                 if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
1559                         ++NumOfSpaceAndTab;
1560
1561                 ++cnt;
1562         }
1563
1564         return size == NumOfSpaceAndTab;
1565 }
1566
1567
1568 void rtw_hal_check_rxfifo_full(struct adapter *adapter)
1569 {
1570         struct dvobj_priv *psdpriv = adapter->dvobj;
1571         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1572         int save_cnt = false;
1573
1574         /* switch counter to RX fifo */
1575         /* printk("8723b or 8192e , MAC_667 set 0xf0\n"); */
1576         rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1577         save_cnt = true;
1578         /* todo: other chips */
1579
1580         if (save_cnt) {
1581                 /* rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); */
1582                 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1583                 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1584                 pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1585         }
1586 }
1587
1588 void linked_info_dump(struct adapter *padapter, u8 benable)
1589 {
1590         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1591
1592         if (padapter->bLinkInfoDump == benable)
1593                 return;
1594
1595         DBG_871X("%s %s\n", __func__, (benable) ? "enable" : "disable");
1596
1597         if (benable) {
1598                 pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
1599                 rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1600
1601                 pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
1602                 rtw_pm_set_ips(padapter, IPS_NONE);
1603         } else {
1604                 rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1605
1606                 rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1607         }
1608         padapter->bLinkInfoDump = benable;
1609 }
1610
1611 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1612 void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
1613 {
1614         u8 isCCKrate, rf_path;
1615         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1616         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1617
1618         DBG_871X_SEL_NL(
1619                 sel,
1620                 "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1621                 HDATA_RATE(psample_pkt_rssi->data_rate),
1622                 psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all
1623         );
1624
1625         isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? true : false;
1626
1627         if (isCCKrate)
1628                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1629
1630         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1631                 DBG_871X_SEL_NL(
1632                         sel,
1633                         "RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)\n",
1634                         rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path],
1635                         psample_pkt_rssi->mimo_singal_quality[rf_path]
1636                 );
1637
1638                 if (!isCCKrate) {
1639                         DBG_871X_SEL_NL(
1640                                 sel,
1641                                 "\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1642                                 psample_pkt_rssi->ofdm_pwr[rf_path],
1643                                 psample_pkt_rssi->ofdm_snr[rf_path]
1644                         );
1645                 }
1646         }
1647 }
1648
1649 void rtw_dump_raw_rssi_info(struct adapter *padapter)
1650 {
1651         u8 isCCKrate, rf_path;
1652         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1653         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1654         DBG_871X("============ RAW Rx Info dump ===================\n");
1655         DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1656                         HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1657
1658         isCCKrate = (psample_pkt_rssi->data_rate <= DESC_RATE11M) ? true : false;
1659
1660         if (isCCKrate)
1661                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1662
1663         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1664                 DBG_871X("RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)"
1665                         , rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path], psample_pkt_rssi->mimo_singal_quality[rf_path]);
1666
1667                 if (!isCCKrate) {
1668                         printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1669                         psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
1670                 } else {
1671                         printk("\n");
1672                 }
1673         }
1674 }
1675
1676 void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
1677 {
1678         u8 isCCKrate, rf_path;
1679         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1680         struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1681
1682         PODM_PHY_INFO_T pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1683         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1684
1685         psample_pkt_rssi->data_rate = pattrib->data_rate;
1686         isCCKrate = (pattrib->data_rate <= DESC_RATE11M) ? true : false;
1687
1688         psample_pkt_rssi->pwdball = pPhyInfo->RxPWDBAll;
1689         psample_pkt_rssi->pwr_all = pPhyInfo->RecvSignalPower;
1690
1691         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1692                 psample_pkt_rssi->mimo_singal_strength[rf_path] = pPhyInfo->RxMIMOSignalStrength[rf_path];
1693                 psample_pkt_rssi->mimo_singal_quality[rf_path] = pPhyInfo->RxMIMOSignalQuality[rf_path];
1694                 if (!isCCKrate) {
1695                         psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1696                         psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1697                 }
1698         }
1699 }
1700 #endif
1701
1702 static u32 Array_kfreemap[] = {
1703         0xf8, 0xe,
1704         0xf6, 0xc,
1705         0xf4, 0xa,
1706         0xf2, 0x8,
1707         0xf0, 0x6,
1708         0xf3, 0x4,
1709         0xf5, 0x2,
1710         0xf7, 0x0,
1711         0xf9, 0x0,
1712         0xfc, 0x0,
1713 };
1714
1715 void rtw_bb_rf_gain_offset(struct adapter *padapter)
1716 {
1717         u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
1718         u32 res, i = 0;
1719         u32 ArrayLen = sizeof(Array_kfreemap)/sizeof(u32);
1720         u32 *Array = Array_kfreemap;
1721         u32 v1 = 0, v2 = 0, target = 0;
1722         /* DBG_871X("+%s value: 0x%02x+\n", __func__, value); */
1723
1724         if (value & BIT4) {
1725                 DBG_871X("Offset RF Gain.\n");
1726                 DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
1727                 if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
1728                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1729                         res &= 0xfff87fff;
1730                         DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
1731                         /* res &= 0xfff87fff; */
1732                         for (i = 0; i < ArrayLen; i += 2) {
1733                                 v1 = Array[i];
1734                                 v2 = Array[i+1];
1735                                 if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
1736                                         DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
1737                                         target = v2;
1738                                         break;
1739                                 }
1740                         }
1741                         DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
1742                         PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
1743
1744                         /* res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; */
1745                         /* rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); */
1746                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1747                         DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
1748                 } else
1749                         DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x  != 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
1750         } else
1751                 DBG_871X("Using the default RF gain.\n");
1752 }