drivers/staging/rtl8723bs/hal/hal_com.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   5  *
   6  ******************************************************************************/
   7 #define _HAL_COM_C_
   8
   9 #include <linux/kernel.h>
  10 #include <drv_types.h>
  11 #include <rtw_debug.h>
  12 #include "hal_com_h2c.h"
  13
  14 #include "odm_precomp.h"
  15
  16 u8 rtw_hal_data_init(struct adapter *padapter)
  17 {
  18         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  19                 padapter->hal_data_sz = sizeof(struct hal_com_data);
  20                 padapter->HalData = vzalloc(padapter->hal_data_sz);
  21                 if (padapter->HalData == NULL) {
  22                         DBG_8192C("cannot alloc memory for HAL DATA\n");
  23                         return _FAIL;
  24                 }
  25         }
  26         return _SUCCESS;
  27 }
  28
  29 void rtw_hal_data_deinit(struct adapter *padapter)
  30 {
  31         if (is_primary_adapter(padapter)) {     /* if (padapter->isprimary) */
  32                 if (padapter->HalData) {
  33                         phy_free_filebuf(padapter);
  34                         vfree(padapter->HalData);
  35                         padapter->HalData = NULL;
  36                         padapter->hal_data_sz = 0;
  37                 }
  38         }
  39 }
  40
  41
  42 void dump_chip_info(HAL_VERSION ChipVersion)
  43 {
  44         int cnt = 0;
  45         u8 buf[128];
  46
  47         cnt += sprintf((buf+cnt), "Chip Version Info: CHIP_8723B_");
  48         cnt += sprintf((buf+cnt), "%s_", IS_NORMAL_CHIP(ChipVersion) ? "Normal_Chip" : "Test_Chip");
  49         if (IS_CHIP_VENDOR_TSMC(ChipVersion))
  50                 cnt += sprintf((buf+cnt), "%s_", "TSMC");
  51         else if (IS_CHIP_VENDOR_UMC(ChipVersion))
  52                 cnt += sprintf((buf+cnt), "%s_", "UMC");
  53         else if (IS_CHIP_VENDOR_SMIC(ChipVersion))
  54                 cnt += sprintf((buf+cnt), "%s_", "SMIC");
  55
  56         if (IS_A_CUT(ChipVersion))
  57                 cnt += sprintf((buf+cnt), "A_CUT_");
  58         else if (IS_B_CUT(ChipVersion))
  59                 cnt += sprintf((buf+cnt), "B_CUT_");
  60         else if (IS_C_CUT(ChipVersion))
  61                 cnt += sprintf((buf+cnt), "C_CUT_");
  62         else if (IS_D_CUT(ChipVersion))
  63                 cnt += sprintf((buf+cnt), "D_CUT_");
  64         else if (IS_E_CUT(ChipVersion))
  65                 cnt += sprintf((buf+cnt), "E_CUT_");
  66         else if (IS_I_CUT(ChipVersion))
  67                 cnt += sprintf((buf+cnt), "I_CUT_");
  68         else if (IS_J_CUT(ChipVersion))
  69                 cnt += sprintf((buf+cnt), "J_CUT_");
  70         else if (IS_K_CUT(ChipVersion))
  71                 cnt += sprintf((buf+cnt), "K_CUT_");
  72         else
  73                 cnt += sprintf((buf+cnt), "UNKNOWN_CUT(%d)_", ChipVersion.CUTVersion);
  74
  75         if (IS_1T1R(ChipVersion))
  76                 cnt += sprintf((buf+cnt), "1T1R_");
  77         else if (IS_1T2R(ChipVersion))
  78                 cnt += sprintf((buf+cnt), "1T2R_");
  79         else if (IS_2T2R(ChipVersion))
  80                 cnt += sprintf((buf+cnt), "2T2R_");
  81         else
  82                 cnt += sprintf((buf+cnt), "UNKNOWN_RFTYPE(%d)_", ChipVersion.RFType);
  83
  84         cnt += sprintf((buf+cnt), "RomVer(%d)\n", ChipVersion.ROMVer);
  85
  86         DBG_871X("%s", buf);
  87 }
  88
  89
  90 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK  0x80
  91
  92 /*
  93  * Description:
  94  *Use hardware(efuse), driver parameter(registry) and default channel plan
  95  *to decide which one should be used.
  96  *
  97  * Parameters:
  98  *padapter                      pointer of adapter
  99  *hw_channel_plan               channel plan from HW (efuse/eeprom)
 100  *                                      BIT[7] software configure mode; 0:Enable, 1:disable
 101  *                                      BIT[6:0] Channel Plan
 102  *sw_channel_plan               channel plan from SW (registry/module param)
 103  *def_channel_plan      channel plan used when HW/SW both invalid
 104  *AutoLoadFail          efuse autoload fail or not
 105  *
 106  * Return:
 107  *Final channel plan decision
 108  *
 109  */
 110 u8 hal_com_config_channel_plan(
 111         struct adapter *padapter,
 112         u8 hw_channel_plan,
 113         u8 sw_channel_plan,
 114         u8 def_channel_plan,
 115         bool AutoLoadFail
 116 )
 117 {
 118         struct hal_com_data *pHalData;
 119         u8 chnlPlan;
 120
 121         pHalData = GET_HAL_DATA(padapter);
 122         pHalData->bDisableSWChannelPlan = false;
 123         chnlPlan = def_channel_plan;
 124
 125         if (0xFF == hw_channel_plan)
 126                 AutoLoadFail = true;
 127
 128         if (false == AutoLoadFail) {
 129                 u8 hw_chnlPlan;
 130
 131                 hw_chnlPlan = hw_channel_plan & (~EEPROM_CHANNEL_PLAN_BY_HW_MASK);
 132                 if (rtw_is_channel_plan_valid(hw_chnlPlan)) {
 133 #ifndef CONFIG_SW_CHANNEL_PLAN
 134                         if (hw_channel_plan & EEPROM_CHANNEL_PLAN_BY_HW_MASK)
 135                                 pHalData->bDisableSWChannelPlan = true;
 136 #endif /*  !CONFIG_SW_CHANNEL_PLAN */
 137
 138                         chnlPlan = hw_chnlPlan;
 139                 }
 140         }
 141
 142         if (
 143                 (false == pHalData->bDisableSWChannelPlan) &&
 144                 rtw_is_channel_plan_valid(sw_channel_plan)
 145         )
 146                 chnlPlan = sw_channel_plan;
 147
 148         return chnlPlan;
 149 }
 150
 151 bool HAL_IsLegalChannel(struct adapter *Adapter, u32 Channel)
 152 {
 153         bool bLegalChannel = true;
 154
 155         if (Channel > 14) {
 156                 bLegalChannel = false;
 157                 DBG_871X("Channel > 14 but wireless_mode do not support 5G\n");
 158         } else if ((Channel <= 14) && (Channel >= 1)) {
 159                 if (IsSupported24G(Adapter->registrypriv.wireless_mode) == false) {
 160                         bLegalChannel = false;
 161                         DBG_871X("(Channel <= 14) && (Channel >= 1) but wireless_mode do not support 2.4G\n");
 162                 }
 163         } else {
 164                 bLegalChannel = false;
 165                 DBG_871X("Channel is Invalid !!!\n");
 166         }
 167
 168         return bLegalChannel;
 169 }
 170
 171 u8 MRateToHwRate(u8 rate)
 172 {
 173         u8 ret = DESC_RATE1M;
 174
 175         switch (rate) {
 176         case MGN_1M:
 177                 ret = DESC_RATE1M;
 178                 break;
 179         case MGN_2M:
 180                 ret = DESC_RATE2M;
 181                 break;
 182         case MGN_5_5M:
 183                 ret = DESC_RATE5_5M;
 184                 break;
 185         case MGN_11M:
 186                 ret = DESC_RATE11M;
 187                 break;
 188         case MGN_6M:
 189                 ret = DESC_RATE6M;
 190                 break;
 191         case MGN_9M:
 192                 ret = DESC_RATE9M;
 193                 break;
 194         case MGN_12M:
 195                 ret = DESC_RATE12M;
 196                 break;
 197         case MGN_18M:
 198                 ret = DESC_RATE18M;
 199                 break;
 200         case MGN_24M:
 201                 ret = DESC_RATE24M;
 202                 break;
 203         case MGN_36M:
 204                 ret = DESC_RATE36M;
 205                 break;
 206         case MGN_48M:
 207                 ret = DESC_RATE48M;
 208                 break;
 209         case MGN_54M:
 210                 ret = DESC_RATE54M;
 211                 break;
 212         case MGN_MCS0:
 213                 ret = DESC_RATEMCS0;
 214                 break;
 215         case MGN_MCS1:
 216                 ret = DESC_RATEMCS1;
 217                 break;
 218         case MGN_MCS2:
 219                 ret = DESC_RATEMCS2;
 220                 break;
 221         case MGN_MCS3:
 222                 ret = DESC_RATEMCS3;
 223                 break;
 224         case MGN_MCS4:
 225                 ret = DESC_RATEMCS4;
 226                 break;
 227         case MGN_MCS5:
 228                 ret = DESC_RATEMCS5;
 229                 break;
 230         case MGN_MCS6:
 231                 ret = DESC_RATEMCS6;
 232                 break;
 233         case MGN_MCS7:
 234                 ret = DESC_RATEMCS7;
 235                 break;
 236         case MGN_MCS8:
 237                 ret = DESC_RATEMCS8;
 238                 break;
 239         case MGN_MCS9:
 240                 ret = DESC_RATEMCS9;
 241                 break;
 242         case MGN_MCS10:
 243                 ret = DESC_RATEMCS10;
 244                 break;
 245         case MGN_MCS11:
 246                 ret = DESC_RATEMCS11;
 247                 break;
 248         case MGN_MCS12:
 249                 ret = DESC_RATEMCS12;
 250                 break;
 251         case MGN_MCS13:
 252                 ret = DESC_RATEMCS13;
 253                 break;
 254         case MGN_MCS14:
 255                 ret = DESC_RATEMCS14;
 256                 break;
 257         case MGN_MCS15:
 258                 ret = DESC_RATEMCS15;
 259                 break;
 260         case MGN_MCS16:
 261                 ret = DESC_RATEMCS16;
 262                 break;
 263         case MGN_MCS17:
 264                 ret = DESC_RATEMCS17;
 265                 break;
 266         case MGN_MCS18:
 267                 ret = DESC_RATEMCS18;
 268                 break;
 269         case MGN_MCS19:
 270                 ret = DESC_RATEMCS19;
 271                 break;
 272         case MGN_MCS20:
 273                 ret = DESC_RATEMCS20;
 274                 break;
 275         case MGN_MCS21:
 276                 ret = DESC_RATEMCS21;
 277                 break;
 278         case MGN_MCS22:
 279                 ret = DESC_RATEMCS22;
 280                 break;
 281         case MGN_MCS23:
 282                 ret = DESC_RATEMCS23;
 283                 break;
 284         case MGN_MCS24:
 285                 ret = DESC_RATEMCS24;
 286                 break;
 287         case MGN_MCS25:
 288                 ret = DESC_RATEMCS25;
 289                 break;
 290         case MGN_MCS26:
 291                 ret = DESC_RATEMCS26;
 292                 break;
 293         case MGN_MCS27:
 294                 ret = DESC_RATEMCS27;
 295                 break;
 296         case MGN_MCS28:
 297                 ret = DESC_RATEMCS28;
 298                 break;
 299         case MGN_MCS29:
 300                 ret = DESC_RATEMCS29;
 301                 break;
 302         case MGN_MCS30:
 303                 ret = DESC_RATEMCS30;
 304                 break;
 305         case MGN_MCS31:
 306                 ret = DESC_RATEMCS31;
 307                 break;
 308         case MGN_VHT1SS_MCS0:
 309                 ret = DESC_RATEVHTSS1MCS0;
 310                 break;
 311         case MGN_VHT1SS_MCS1:
 312                 ret = DESC_RATEVHTSS1MCS1;
 313                 break;
 314         case MGN_VHT1SS_MCS2:
 315                 ret = DESC_RATEVHTSS1MCS2;
 316                 break;
 317         case MGN_VHT1SS_MCS3:
 318                 ret = DESC_RATEVHTSS1MCS3;
 319                 break;
 320         case MGN_VHT1SS_MCS4:
 321                 ret = DESC_RATEVHTSS1MCS4;
 322                 break;
 323         case MGN_VHT1SS_MCS5:
 324                 ret = DESC_RATEVHTSS1MCS5;
 325                 break;
 326         case MGN_VHT1SS_MCS6:
 327                 ret = DESC_RATEVHTSS1MCS6;
 328                 break;
 329         case MGN_VHT1SS_MCS7:
 330                 ret = DESC_RATEVHTSS1MCS7;
 331                 break;
 332         case MGN_VHT1SS_MCS8:
 333                 ret = DESC_RATEVHTSS1MCS8;
 334                 break;
 335         case MGN_VHT1SS_MCS9:
 336                 ret = DESC_RATEVHTSS1MCS9;
 337                 break;
 338         case MGN_VHT2SS_MCS0:
 339                 ret = DESC_RATEVHTSS2MCS0;
 340                 break;
 341         case MGN_VHT2SS_MCS1:
 342                 ret = DESC_RATEVHTSS2MCS1;
 343                 break;
 344         case MGN_VHT2SS_MCS2:
 345                 ret = DESC_RATEVHTSS2MCS2;
 346                 break;
 347         case MGN_VHT2SS_MCS3:
 348                 ret = DESC_RATEVHTSS2MCS3;
 349                 break;
 350         case MGN_VHT2SS_MCS4:
 351                 ret = DESC_RATEVHTSS2MCS4;
 352                 break;
 353         case MGN_VHT2SS_MCS5:
 354                 ret = DESC_RATEVHTSS2MCS5;
 355                 break;
 356         case MGN_VHT2SS_MCS6:
 357                 ret = DESC_RATEVHTSS2MCS6;
 358                 break;
 359         case MGN_VHT2SS_MCS7:
 360                 ret = DESC_RATEVHTSS2MCS7;
 361                 break;
 362         case MGN_VHT2SS_MCS8:
 363                 ret = DESC_RATEVHTSS2MCS8;
 364                 break;
 365         case MGN_VHT2SS_MCS9:
 366                 ret = DESC_RATEVHTSS2MCS9;
 367                 break;
 368         case MGN_VHT3SS_MCS0:
 369                 ret = DESC_RATEVHTSS3MCS0;
 370                 break;
 371         case MGN_VHT3SS_MCS1:
 372                 ret = DESC_RATEVHTSS3MCS1;
 373                 break;
 374         case MGN_VHT3SS_MCS2:
 375                 ret = DESC_RATEVHTSS3MCS2;
 376                 break;
 377         case MGN_VHT3SS_MCS3:
 378                 ret = DESC_RATEVHTSS3MCS3;
 379                 break;
 380         case MGN_VHT3SS_MCS4:
 381                 ret = DESC_RATEVHTSS3MCS4;
 382                 break;
 383         case MGN_VHT3SS_MCS5:
 384                 ret = DESC_RATEVHTSS3MCS5;
 385                 break;
 386         case MGN_VHT3SS_MCS6:
 387                 ret = DESC_RATEVHTSS3MCS6;
 388                 break;
 389         case MGN_VHT3SS_MCS7:
 390                 ret = DESC_RATEVHTSS3MCS7;
 391                 break;
 392         case MGN_VHT3SS_MCS8:
 393                 ret = DESC_RATEVHTSS3MCS8;
 394                 break;
 395         case MGN_VHT3SS_MCS9:
 396                 ret = DESC_RATEVHTSS3MCS9;
 397                 break;
 398         case MGN_VHT4SS_MCS0:
 399                 ret = DESC_RATEVHTSS4MCS0;
 400                 break;
 401         case MGN_VHT4SS_MCS1:
 402                 ret = DESC_RATEVHTSS4MCS1;
 403                 break;
 404         case MGN_VHT4SS_MCS2:
 405                 ret = DESC_RATEVHTSS4MCS2;
 406                 break;
 407         case MGN_VHT4SS_MCS3:
 408                 ret = DESC_RATEVHTSS4MCS3;
 409                 break;
 410         case MGN_VHT4SS_MCS4:
 411                 ret = DESC_RATEVHTSS4MCS4;
 412                 break;
 413         case MGN_VHT4SS_MCS5:
 414                 ret = DESC_RATEVHTSS4MCS5;
 415                 break;
 416         case MGN_VHT4SS_MCS6:
 417                 ret = DESC_RATEVHTSS4MCS6;
 418                 break;
 419         case MGN_VHT4SS_MCS7:
 420                 ret = DESC_RATEVHTSS4MCS7;
 421                 break;
 422         case MGN_VHT4SS_MCS8:
 423                 ret = DESC_RATEVHTSS4MCS8;
 424                 break;
 425         case MGN_VHT4SS_MCS9:
 426                 ret = DESC_RATEVHTSS4MCS9;
 427                 break;
 428         default:
 429                 break;
 430         }
 431
 432         return ret;
 433 }
 434
 435 u8 HwRateToMRate(u8 rate)
 436 {
 437         u8 ret_rate = MGN_1M;
 438
 439         switch (rate) {
 440         case DESC_RATE1M:
 441                 ret_rate = MGN_1M;
 442                 break;
 443         case DESC_RATE2M:
 444                 ret_rate = MGN_2M;
 445                 break;
 446         case DESC_RATE5_5M:
 447                 ret_rate = MGN_5_5M;
 448                 break;
 449         case DESC_RATE11M:
 450                 ret_rate = MGN_11M;
 451                 break;
 452         case DESC_RATE6M:
 453                 ret_rate = MGN_6M;
 454                 break;
 455         case DESC_RATE9M:
 456                 ret_rate = MGN_9M;
 457                 break;
 458         case DESC_RATE12M:
 459                 ret_rate = MGN_12M;
 460                 break;
 461         case DESC_RATE18M:
 462                 ret_rate = MGN_18M;
 463                 break;
 464         case DESC_RATE24M:
 465                 ret_rate = MGN_24M;
 466                 break;
 467         case DESC_RATE36M:
 468                 ret_rate = MGN_36M;
 469                 break;
 470         case DESC_RATE48M:
 471                 ret_rate = MGN_48M;
 472                 break;
 473         case DESC_RATE54M:
 474                 ret_rate = MGN_54M;
 475                 break;
 476         case DESC_RATEMCS0:
 477                 ret_rate = MGN_MCS0;
 478                 break;
 479         case DESC_RATEMCS1:
 480                 ret_rate = MGN_MCS1;
 481                 break;
 482         case DESC_RATEMCS2:
 483                 ret_rate = MGN_MCS2;
 484                 break;
 485         case DESC_RATEMCS3:
 486                 ret_rate = MGN_MCS3;
 487                 break;
 488         case DESC_RATEMCS4:
 489                 ret_rate = MGN_MCS4;
 490                 break;
 491         case DESC_RATEMCS5:
 492                 ret_rate = MGN_MCS5;
 493                 break;
 494         case DESC_RATEMCS6:
 495                 ret_rate = MGN_MCS6;
 496                 break;
 497         case DESC_RATEMCS7:
 498                 ret_rate = MGN_MCS7;
 499                 break;
 500         case DESC_RATEMCS8:
 501                 ret_rate = MGN_MCS8;
 502                 break;
 503         case DESC_RATEMCS9:
 504                 ret_rate = MGN_MCS9;
 505                 break;
 506         case DESC_RATEMCS10:
 507                 ret_rate = MGN_MCS10;
 508                 break;
 509         case DESC_RATEMCS11:
 510                 ret_rate = MGN_MCS11;
 511                 break;
 512         case DESC_RATEMCS12:
 513                 ret_rate = MGN_MCS12;
 514                 break;
 515         case DESC_RATEMCS13:
 516                 ret_rate = MGN_MCS13;
 517                 break;
 518         case DESC_RATEMCS14:
 519                 ret_rate = MGN_MCS14;
 520                 break;
 521         case DESC_RATEMCS15:
 522                 ret_rate = MGN_MCS15;
 523                 break;
 524         case DESC_RATEMCS16:
 525                 ret_rate = MGN_MCS16;
 526                 break;
 527         case DESC_RATEMCS17:
 528                 ret_rate = MGN_MCS17;
 529                 break;
 530         case DESC_RATEMCS18:
 531                 ret_rate = MGN_MCS18;
 532                 break;
 533         case DESC_RATEMCS19:
 534                 ret_rate = MGN_MCS19;
 535                 break;
 536         case DESC_RATEMCS20:
 537                 ret_rate = MGN_MCS20;
 538                 break;
 539         case DESC_RATEMCS21:
 540                 ret_rate = MGN_MCS21;
 541                 break;
 542         case DESC_RATEMCS22:
 543                 ret_rate = MGN_MCS22;
 544                 break;
 545         case DESC_RATEMCS23:
 546                 ret_rate = MGN_MCS23;
 547                 break;
 548         case DESC_RATEMCS24:
 549                 ret_rate = MGN_MCS24;
 550                 break;
 551         case DESC_RATEMCS25:
 552                 ret_rate = MGN_MCS25;
 553                 break;
 554         case DESC_RATEMCS26:
 555                 ret_rate = MGN_MCS26;
 556                 break;
 557         case DESC_RATEMCS27:
 558                 ret_rate = MGN_MCS27;
 559                 break;
 560         case DESC_RATEMCS28:
 561                 ret_rate = MGN_MCS28;
 562                 break;
 563         case DESC_RATEMCS29:
 564                 ret_rate = MGN_MCS29;
 565                 break;
 566         case DESC_RATEMCS30:
 567                 ret_rate = MGN_MCS30;
 568                 break;
 569         case DESC_RATEMCS31:
 570                 ret_rate = MGN_MCS31;
 571                 break;
 572         case DESC_RATEVHTSS1MCS0:
 573                 ret_rate = MGN_VHT1SS_MCS0;
 574                 break;
 575         case DESC_RATEVHTSS1MCS1:
 576                 ret_rate = MGN_VHT1SS_MCS1;
 577                 break;
 578         case DESC_RATEVHTSS1MCS2:
 579                 ret_rate = MGN_VHT1SS_MCS2;
 580                 break;
 581         case DESC_RATEVHTSS1MCS3:
 582                 ret_rate = MGN_VHT1SS_MCS3;
 583                 break;
 584         case DESC_RATEVHTSS1MCS4:
 585                 ret_rate = MGN_VHT1SS_MCS4;
 586                 break;
 587         case DESC_RATEVHTSS1MCS5:
 588                 ret_rate = MGN_VHT1SS_MCS5;
 589                 break;
 590         case DESC_RATEVHTSS1MCS6:
 591                 ret_rate = MGN_VHT1SS_MCS6;
 592                 break;
 593         case DESC_RATEVHTSS1MCS7:
 594                 ret_rate = MGN_VHT1SS_MCS7;
 595                 break;
 596         case DESC_RATEVHTSS1MCS8:
 597                 ret_rate = MGN_VHT1SS_MCS8;
 598                 break;
 599         case DESC_RATEVHTSS1MCS9:
 600                 ret_rate = MGN_VHT1SS_MCS9;
 601                 break;
 602         case DESC_RATEVHTSS2MCS0:
 603                 ret_rate = MGN_VHT2SS_MCS0;
 604                 break;
 605         case DESC_RATEVHTSS2MCS1:
 606                 ret_rate = MGN_VHT2SS_MCS1;
 607                 break;
 608         case DESC_RATEVHTSS2MCS2:
 609                 ret_rate = MGN_VHT2SS_MCS2;
 610                 break;
 611         case DESC_RATEVHTSS2MCS3:
 612                 ret_rate = MGN_VHT2SS_MCS3;
 613                 break;
 614         case DESC_RATEVHTSS2MCS4:
 615                 ret_rate = MGN_VHT2SS_MCS4;
 616                 break;
 617         case DESC_RATEVHTSS2MCS5:
 618                 ret_rate = MGN_VHT2SS_MCS5;
 619                 break;
 620         case DESC_RATEVHTSS2MCS6:
 621                 ret_rate = MGN_VHT2SS_MCS6;
 622                 break;
 623         case DESC_RATEVHTSS2MCS7:
 624                 ret_rate = MGN_VHT2SS_MCS7;
 625                 break;
 626         case DESC_RATEVHTSS2MCS8:
 627                 ret_rate = MGN_VHT2SS_MCS8;
 628                 break;
 629         case DESC_RATEVHTSS2MCS9:
 630                 ret_rate = MGN_VHT2SS_MCS9;
 631                 break;
 632         case DESC_RATEVHTSS3MCS0:
 633                 ret_rate = MGN_VHT3SS_MCS0;
 634                 break;
 635         case DESC_RATEVHTSS3MCS1:
 636                 ret_rate = MGN_VHT3SS_MCS1;
 637                 break;
 638         case DESC_RATEVHTSS3MCS2:
 639                 ret_rate = MGN_VHT3SS_MCS2;
 640                 break;
 641         case DESC_RATEVHTSS3MCS3:
 642                 ret_rate = MGN_VHT3SS_MCS3;
 643                 break;
 644         case DESC_RATEVHTSS3MCS4:
 645                 ret_rate = MGN_VHT3SS_MCS4;
 646                 break;
 647         case DESC_RATEVHTSS3MCS5:
 648                 ret_rate = MGN_VHT3SS_MCS5;
 649                 break;
 650         case DESC_RATEVHTSS3MCS6:
 651                 ret_rate = MGN_VHT3SS_MCS6;
 652                 break;
 653         case DESC_RATEVHTSS3MCS7:
 654                 ret_rate = MGN_VHT3SS_MCS7;
 655                 break;
 656         case DESC_RATEVHTSS3MCS8:
 657                 ret_rate = MGN_VHT3SS_MCS8;
 658                 break;
 659         case DESC_RATEVHTSS3MCS9:
 660                 ret_rate = MGN_VHT3SS_MCS9;
 661                 break;
 662         case DESC_RATEVHTSS4MCS0:
 663                 ret_rate = MGN_VHT4SS_MCS0;
 664                 break;
 665         case DESC_RATEVHTSS4MCS1:
 666                 ret_rate = MGN_VHT4SS_MCS1;
 667                 break;
 668         case DESC_RATEVHTSS4MCS2:
 669                 ret_rate = MGN_VHT4SS_MCS2;
 670                 break;
 671         case DESC_RATEVHTSS4MCS3:
 672                 ret_rate = MGN_VHT4SS_MCS3;
 673                 break;
 674         case DESC_RATEVHTSS4MCS4:
 675                 ret_rate = MGN_VHT4SS_MCS4;
 676                 break;
 677         case DESC_RATEVHTSS4MCS5:
 678                 ret_rate = MGN_VHT4SS_MCS5;
 679                 break;
 680         case DESC_RATEVHTSS4MCS6:
 681                 ret_rate = MGN_VHT4SS_MCS6;
 682                 break;
 683         case DESC_RATEVHTSS4MCS7:
 684                 ret_rate = MGN_VHT4SS_MCS7;
 685                 break;
 686         case DESC_RATEVHTSS4MCS8:
 687                 ret_rate = MGN_VHT4SS_MCS8;
 688                 break;
 689         case DESC_RATEVHTSS4MCS9:
 690                 ret_rate = MGN_VHT4SS_MCS9;
 691                 break;
 692
 693         default:
 694                 DBG_871X("HwRateToMRate(): Non supported Rate [%x]!!!\n", rate);
 695                 break;
 696         }
 697
 698         return ret_rate;
 699 }
 700
 701 void HalSetBrateCfg(struct adapter *Adapter, u8 *mBratesOS, u16 *pBrateCfg)
 702 {
 703         u8 i, is_brate, brate;
 704
 705         for (i = 0; i < NDIS_802_11_LENGTH_RATES_EX; i++) {
 706
 707                 is_brate = mBratesOS[i] & IEEE80211_BASIC_RATE_MASK;
 708                 brate = mBratesOS[i] & 0x7f;
 709
 710                 if (is_brate) {
 711                         switch (brate) {
 712                         case IEEE80211_CCK_RATE_1MB:
 713                                 *pBrateCfg |= RATE_1M;
 714                                 break;
 715                         case IEEE80211_CCK_RATE_2MB:
 716                                 *pBrateCfg |= RATE_2M;
 717                                 break;
 718                         case IEEE80211_CCK_RATE_5MB:
 719                                 *pBrateCfg |= RATE_5_5M;
 720                                 break;
 721                         case IEEE80211_CCK_RATE_11MB:
 722                                 *pBrateCfg |= RATE_11M;
 723                                 break;
 724                         case IEEE80211_OFDM_RATE_6MB:
 725                                 *pBrateCfg |= RATE_6M;
 726                                 break;
 727                         case IEEE80211_OFDM_RATE_9MB:
 728                                 *pBrateCfg |= RATE_9M;
 729                                 break;
 730                         case IEEE80211_OFDM_RATE_12MB:
 731                                 *pBrateCfg |= RATE_12M;
 732                                 break;
 733                         case IEEE80211_OFDM_RATE_18MB:
 734                                 *pBrateCfg |= RATE_18M;
 735                                 break;
 736                         case IEEE80211_OFDM_RATE_24MB:
 737                                 *pBrateCfg |= RATE_24M;
 738                                 break;
 739                         case IEEE80211_OFDM_RATE_36MB:
 740                                 *pBrateCfg |= RATE_36M;
 741                                 break;
 742                         case IEEE80211_OFDM_RATE_48MB:
 743                                 *pBrateCfg |= RATE_48M;
 744                                 break;
 745                         case IEEE80211_OFDM_RATE_54MB:
 746                                 *pBrateCfg |= RATE_54M;
 747                                 break;
 748                         }
 749                 }
 750         }
 751 }
 752
 753 static void _OneOutPipeMapping(struct adapter *padapter)
 754 {
 755         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 756
 757         pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 758         pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 759         pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[0];/* BE */
 760         pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 761
 762         pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 763         pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 764         pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 765         pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 766 }
 767
 768 static void _TwoOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 769 {
 770         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 771
 772         if (bWIFICfg) { /* WMM */
 773
 774                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 775                 /*   0,         1,      0,      1,      0,      0,      0,      0,              0       }; */
 776                 /* 0:ep_0 num, 1:ep_1 num */
 777
 778                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[1];/* VO */
 779                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 780                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 781                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[0];/* BK */
 782
 783                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 784                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 785                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 786                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 787
 788         } else { /* typical setting */
 789
 790
 791                 /* BK,  BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 792                 /*   1,         1,      0,      0,      0,      0,      0,      0,              0       }; */
 793                 /* 0:ep_0 num, 1:ep_1 num */
 794
 795                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 796                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[0];/* VI */
 797                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[1];/* BE */
 798                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 799
 800                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 801                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 802                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 803                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 804
 805         }
 806
 807 }
 808
 809 static void _ThreeOutPipeMapping(struct adapter *padapter, bool bWIFICfg)
 810 {
 811         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
 812
 813         if (bWIFICfg) { /* for WMM */
 814
 815                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 816                 /*   1,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 817                 /* 0:H, 1:N, 2:L */
 818
 819                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 820                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 821                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 822                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[1];/* BK */
 823
 824                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 825                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 826                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 827                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 828
 829         } else { /* typical setting */
 830
 831
 832                 /*      BK,     BE,     VI,     VO,     BCN,    CMD, MGT, HIGH, HCCA */
 833                 /*   2,         2,      1,      0,      0,      0,      0,      0,              0       }; */
 834                 /* 0:H, 1:N, 2:L */
 835
 836                 pdvobjpriv->Queue2Pipe[0] = pdvobjpriv->RtOutPipe[0];/* VO */
 837                 pdvobjpriv->Queue2Pipe[1] = pdvobjpriv->RtOutPipe[1];/* VI */
 838                 pdvobjpriv->Queue2Pipe[2] = pdvobjpriv->RtOutPipe[2];/* BE */
 839                 pdvobjpriv->Queue2Pipe[3] = pdvobjpriv->RtOutPipe[2];/* BK */
 840
 841                 pdvobjpriv->Queue2Pipe[4] = pdvobjpriv->RtOutPipe[0];/* BCN */
 842                 pdvobjpriv->Queue2Pipe[5] = pdvobjpriv->RtOutPipe[0];/* MGT */
 843                 pdvobjpriv->Queue2Pipe[6] = pdvobjpriv->RtOutPipe[0];/* HIGH */
 844                 pdvobjpriv->Queue2Pipe[7] = pdvobjpriv->RtOutPipe[0];/* TXCMD */
 845         }
 846
 847 }
 848
 849 bool Hal_MappingOutPipe(struct adapter *padapter, u8 NumOutPipe)
 850 {
 851         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 852
 853         bool bWIFICfg = (pregistrypriv->wifi_spec) ? true : false;
 854
 855         bool result = true;
 856
 857         switch (NumOutPipe) {
 858         case 2:
 859                 _TwoOutPipeMapping(padapter, bWIFICfg);
 860                 break;
 861         case 3:
 862         case 4:
 863                 _ThreeOutPipeMapping(padapter, bWIFICfg);
 864                 break;
 865         case 1:
 866                 _OneOutPipeMapping(padapter);
 867                 break;
 868         default:
 869                 result = false;
 870                 break;
 871         }
 872
 873         return result;
 874
 875 }
 876
 877 void hal_init_macaddr(struct adapter *adapter)
 878 {
 879         rtw_hal_set_hwreg(adapter, HW_VAR_MAC_ADDR, adapter->eeprompriv.mac_addr);
 880 }
 881
 882 void rtw_init_hal_com_default_value(struct adapter *Adapter)
 883 {
 884         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 885
 886         pHalData->AntDetection = 1;
 887 }
 888
 889 /*
 890 * C2H event format:
 891 * Field  TRIGGER                CONTENT    CMD_SEQ      CMD_LEN          CMD_ID
 892 * BITS   [127:120]      [119:16]      [15:8]              [7:4]            [3:0]
 893 */
 894
 895 void c2h_evt_clear(struct adapter *adapter)
 896 {
 897         rtw_write8(adapter, REG_C2HEVT_CLEAR, C2H_EVT_HOST_CLOSE);
 898 }
 899
 900 /*
 901 * C2H event format:
 902 * Field    TRIGGER    CMD_LEN    CONTENT    CMD_SEQ    CMD_ID
 903 * BITS    [127:120]   [119:112]    [111:16]          [15:8]         [7:0]
 904 */
 905 s32 c2h_evt_read_88xx(struct adapter *adapter, u8 *buf)
 906 {
 907         s32 ret = _FAIL;
 908         struct c2h_evt_hdr_88xx *c2h_evt;
 909         int i;
 910         u8 trigger;
 911
 912         if (buf == NULL)
 913                 goto exit;
 914
 915         trigger = rtw_read8(adapter, REG_C2HEVT_CLEAR);
 916
 917         if (trigger == C2H_EVT_HOST_CLOSE)
 918                 goto exit; /* Not ready */
 919         else if (trigger != C2H_EVT_FW_CLOSE)
 920                 goto clear_evt; /* Not a valid value */
 921
 922         c2h_evt = (struct c2h_evt_hdr_88xx *)buf;
 923
 924         memset(c2h_evt, 0, 16);
 925
 926         c2h_evt->id = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL);
 927         c2h_evt->seq = rtw_read8(adapter, REG_C2HEVT_CMD_SEQ_88XX);
 928         c2h_evt->plen = rtw_read8(adapter, REG_C2HEVT_CMD_LEN_88XX);
 929
 930         RT_PRINT_DATA(
 931                 _module_hal_init_c_,
 932                 _drv_info_,
 933                 "c2h_evt_read(): ",
 934                 &c2h_evt,
 935                 sizeof(c2h_evt)
 936         );
 937
 938         DBG_871X(
 939                 "%s id:%u, len:%u, seq:%u, trigger:0x%02x\n",
 940                 __func__,
 941                 c2h_evt->id,
 942                 c2h_evt->plen,
 943                 c2h_evt->seq,
 944                 trigger
 945         );
 946
 947         /* Read the content */
 948         for (i = 0; i < c2h_evt->plen; i++)
 949                 c2h_evt->payload[i] = rtw_read8(adapter, REG_C2HEVT_MSG_NORMAL + 2 + i);
 950
 951         RT_PRINT_DATA(_module_hal_init_c_, _drv_info_, "c2h_evt_read(): Command Content:\n",
 952                 c2h_evt->payload, c2h_evt->plen);
 953
 954         ret = _SUCCESS;
 955
 956 clear_evt:
 957         /*
 958         * Clear event to notify FW we have read the command.
 959         * If this field isn't clear, the FW won't update the next command message.
 960         */
 961         c2h_evt_clear(adapter);
 962 exit:
 963         return ret;
 964 }
 965
 966
 967 u8  rtw_hal_networktype_to_raid(struct adapter *adapter, struct sta_info *psta)
 968 {
 969         return networktype_to_raid_ex(adapter, psta);
 970 }
 971
 972 u8 rtw_get_mgntframe_raid(struct adapter *adapter, unsigned char network_type)
 973 {
 974
 975         u8 raid;
 976         raid = (network_type & WIRELESS_11B) ? RATEID_IDX_B : RATEID_IDX_G;
 977         return raid;
 978 }
 979
 980 void rtw_hal_update_sta_rate_mask(struct adapter *padapter, struct sta_info *psta)
 981 {
 982         u8 i, rf_type, limit;
 983         u32 tx_ra_bitmap;
 984
 985         if (psta == NULL)
 986                 return;
 987
 988         tx_ra_bitmap = 0;
 989
 990         /* b/g mode ra_bitmap */
 991         for (i = 0; i < sizeof(psta->bssrateset); i++) {
 992                 if (psta->bssrateset[i])
 993                         tx_ra_bitmap |= rtw_get_bit_value_from_ieee_value(psta->bssrateset[i]&0x7f);
 994         }
 995
 996         /* n mode ra_bitmap */
 997         if (psta->htpriv.ht_option) {
 998                 rtw_hal_get_hwreg(padapter, HW_VAR_RF_TYPE, (u8 *)(&rf_type));
 999                 if (rf_type == RF_2T2R)
1000                         limit = 16; /*  2R */
1001                 else
1002                         limit = 8; /*   1R */
1003
1004                 for (i = 0; i < limit; i++) {
1005                         if (psta->htpriv.ht_cap.supp_mcs_set[i/8] & BIT(i%8))
1006                                 tx_ra_bitmap |= BIT(i+12);
1007                 }
1008         }
1009
1010         psta->ra_mask = tx_ra_bitmap;
1011         psta->init_rate = get_highest_rate_idx(tx_ra_bitmap)&0x3f;
1012 }
1013
1014 void hw_var_port_switch(struct adapter *adapter)
1015 {
1016 }
1017
1018 void SetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1019 {
1020         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1021         DM_ODM_T *odm = &(hal_data->odmpriv);
1022
1023         switch (variable) {
1024         case HW_VAR_PORT_SWITCH:
1025                 hw_var_port_switch(adapter);
1026                 break;
1027         case HW_VAR_INIT_RTS_RATE:
1028                 rtw_warn_on(1);
1029                 break;
1030         case HW_VAR_SEC_CFG:
1031         {
1032                 u16 reg_scr;
1033
1034                 reg_scr = rtw_read16(adapter, REG_SECCFG);
1035                 rtw_write16(adapter, REG_SECCFG, reg_scr|SCR_CHK_KEYID|SCR_RxDecEnable|SCR_TxEncEnable);
1036         }
1037                 break;
1038         case HW_VAR_SEC_DK_CFG:
1039         {
1040                 struct security_priv *sec = &adapter->securitypriv;
1041                 u8 reg_scr = rtw_read8(adapter, REG_SECCFG);
1042
1043                 if (val) { /* Enable default key related setting */
1044                         reg_scr |= SCR_TXBCUSEDK;
1045                         if (sec->dot11AuthAlgrthm != dot11AuthAlgrthm_8021X)
1046                                 reg_scr |= (SCR_RxUseDK|SCR_TxUseDK);
1047                 } else /* Disable default key related setting */
1048                         reg_scr &= ~(SCR_RXBCUSEDK|SCR_TXBCUSEDK|SCR_RxUseDK|SCR_TxUseDK);
1049
1050                 rtw_write8(adapter, REG_SECCFG, reg_scr);
1051         }
1052                 break;
1053         case HW_VAR_DM_FLAG:
1054                 odm->SupportAbility = *((u32 *)val);
1055                 break;
1056         case HW_VAR_DM_FUNC_OP:
1057                 if (*((u8 *)val) == true) {
1058                         /* save dm flag */
1059                         odm->BK_SupportAbility = odm->SupportAbility;
1060                 } else {
1061                         /* restore dm flag */
1062                         odm->SupportAbility = odm->BK_SupportAbility;
1063                 }
1064                 break;
1065         case HW_VAR_DM_FUNC_SET:
1066                 if (*((u32 *)val) == DYNAMIC_ALL_FUNC_ENABLE) {
1067                         struct dm_priv *dm = &hal_data->dmpriv;
1068                         dm->DMFlag = dm->InitDMFlag;
1069                         odm->SupportAbility = dm->InitODMFlag;
1070                 } else {
1071                         odm->SupportAbility |= *((u32 *)val);
1072                 }
1073                 break;
1074         case HW_VAR_DM_FUNC_CLR:
1075                 /*
1076                 * input is already a mask to clear function
1077                 * don't invert it again! George, Lucas@20130513
1078                 */
1079                 odm->SupportAbility &= *((u32 *)val);
1080                 break;
1081         case HW_VAR_AMPDU_MIN_SPACE:
1082                 /* TODO - Is something needed here? */
1083                 break;
1084         case HW_VAR_WIRELESS_MODE:
1085                 /* TODO - Is something needed here? */
1086                 break;
1087         default:
1088                 DBG_871X_LEVEL(
1089                         _drv_always_,
1090                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1091                         FUNC_ADPT_ARG(adapter),
1092                         variable
1093                 );
1094                 break;
1095         }
1096 }
1097
1098 void GetHwReg(struct adapter *adapter, u8 variable, u8 *val)
1099 {
1100         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1101         DM_ODM_T *odm = &(hal_data->odmpriv);
1102
1103         switch (variable) {
1104         case HW_VAR_BASIC_RATE:
1105                 *((u16 *)val) = hal_data->BasicRateSet;
1106                 break;
1107         case HW_VAR_DM_FLAG:
1108                 *((u32 *)val) = odm->SupportAbility;
1109                 break;
1110         case HW_VAR_RF_TYPE:
1111                 *((u8 *)val) = hal_data->rf_type;
1112                 break;
1113         default:
1114                 DBG_871X_LEVEL(
1115                         _drv_always_,
1116                         FUNC_ADPT_FMT" variable(%d) not defined!\n",
1117                         FUNC_ADPT_ARG(adapter),
1118                         variable
1119                 );
1120                 break;
1121         }
1122 }
1123
1124
1125
1126
1127 u8 SetHalDefVar(
1128         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1129 )
1130 {
1131         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1132         DM_ODM_T *odm = &(hal_data->odmpriv);
1133         u8 bResult = _SUCCESS;
1134
1135         switch (variable) {
1136         case HW_DEF_FA_CNT_DUMP:
1137                 /* ODM_COMP_COMMON */
1138                 if (*((u8 *)value))
1139                         odm->DebugComponents |= (ODM_COMP_DIG | ODM_COMP_FA_CNT);
1140                 else
1141                         odm->DebugComponents &= ~(ODM_COMP_DIG | ODM_COMP_FA_CNT);
1142                 break;
1143         case HAL_DEF_DBG_RX_INFO_DUMP:
1144                 DBG_871X("============ Rx Info dump ===================\n");
1145                 DBG_871X("bLinked = %d, RSSI_Min = %d(%%)\n",
1146                         odm->bLinked, odm->RSSI_Min);
1147
1148                 if (odm->bLinked) {
1149                         DBG_871X("RxRate = %s, RSSI_A = %d(%%), RSSI_B = %d(%%)\n",
1150                                 HDATA_RATE(odm->RxRate), odm->RSSI_A, odm->RSSI_B);
1151
1152                         #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1153                         rtw_dump_raw_rssi_info(adapter);
1154                         #endif
1155                 }
1156                 break;
1157         case HW_DEF_ODM_DBG_FLAG:
1158                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_COMP, *((u64 *)value));
1159                 break;
1160         case HW_DEF_ODM_DBG_LEVEL:
1161                 ODM_CmnInfoUpdate(odm, ODM_CMNINFO_DBG_LEVEL, *((u32 *)value));
1162                 break;
1163         case HAL_DEF_DBG_DM_FUNC:
1164         {
1165                 u8 dm_func = *((u8 *)value);
1166                 struct dm_priv *dm = &hal_data->dmpriv;
1167
1168                 if (dm_func == 0) { /* disable all dynamic func */
1169                         odm->SupportAbility = DYNAMIC_FUNC_DISABLE;
1170                         DBG_8192C("==> Disable all dynamic function...\n");
1171                 } else if (dm_func == 1) {/* disable DIG */
1172                         odm->SupportAbility  &= (~DYNAMIC_BB_DIG);
1173                         DBG_8192C("==> Disable DIG...\n");
1174                 } else if (dm_func == 2) {/* disable High power */
1175                         odm->SupportAbility  &= (~DYNAMIC_BB_DYNAMIC_TXPWR);
1176                 } else if (dm_func == 3) {/* disable tx power tracking */
1177                         odm->SupportAbility  &= (~DYNAMIC_RF_CALIBRATION);
1178                         DBG_8192C("==> Disable tx power tracking...\n");
1179                 } else if (dm_func == 4) {/* disable BT coexistence */
1180                         dm->DMFlag &= (~DYNAMIC_FUNC_BT);
1181                 } else if (dm_func == 5) {/* disable antenna diversity */
1182                         odm->SupportAbility  &= (~DYNAMIC_BB_ANT_DIV);
1183                 } else if (dm_func == 6) {/* turn on all dynamic func */
1184                         if (!(odm->SupportAbility  & DYNAMIC_BB_DIG)) {
1185                                 DIG_T   *pDigTable = &odm->DM_DigTable;
1186                                 pDigTable->CurIGValue = rtw_read8(adapter, 0xc50);
1187                         }
1188                         dm->DMFlag |= DYNAMIC_FUNC_BT;
1189                         odm->SupportAbility = DYNAMIC_ALL_FUNC_ENABLE;
1190                         DBG_8192C("==> Turn on all dynamic function...\n");
1191                 }
1192         }
1193                 break;
1194         case HAL_DEF_DBG_DUMP_RXPKT:
1195                 hal_data->bDumpRxPkt = *((u8 *)value);
1196                 break;
1197         case HAL_DEF_DBG_DUMP_TXPKT:
1198                 hal_data->bDumpTxPkt = *((u8 *)value);
1199                 break;
1200         case HAL_DEF_ANT_DETECT:
1201                 hal_data->AntDetection = *((u8 *)value);
1202                 break;
1203         default:
1204                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1205                 bResult = _FAIL;
1206                 break;
1207         }
1208
1209         return bResult;
1210 }
1211
1212 u8 GetHalDefVar(
1213         struct adapter *adapter, enum HAL_DEF_VARIABLE variable, void *value
1214 )
1215 {
1216         struct hal_com_data *hal_data = GET_HAL_DATA(adapter);
1217         DM_ODM_T *odm = &(hal_data->odmpriv);
1218         u8 bResult = _SUCCESS;
1219
1220         switch (variable) {
1221         case HAL_DEF_UNDERCORATEDSMOOTHEDPWDB:
1222                 {
1223                         struct mlme_priv *pmlmepriv;
1224                         struct sta_priv *pstapriv;
1225                         struct sta_info *psta;
1226
1227                         pmlmepriv = &adapter->mlmepriv;
1228                         pstapriv = &adapter->stapriv;
1229                         psta = rtw_get_stainfo(pstapriv, pmlmepriv->cur_network.network.MacAddress);
1230                         if (psta)
1231                                 *((int *)value) = psta->rssi_stat.UndecoratedSmoothedPWDB;
1232                 }
1233                 break;
1234         case HW_DEF_ODM_DBG_FLAG:
1235                 *((u64 *)value) = odm->DebugComponents;
1236                 break;
1237         case HW_DEF_ODM_DBG_LEVEL:
1238                 *((u32 *)value) = odm->DebugLevel;
1239                 break;
1240         case HAL_DEF_DBG_DM_FUNC:
1241                 *((u32 *)value) = hal_data->odmpriv.SupportAbility;
1242                 break;
1243         case HAL_DEF_DBG_DUMP_RXPKT:
1244                 *((u8 *)value) = hal_data->bDumpRxPkt;
1245                 break;
1246         case HAL_DEF_DBG_DUMP_TXPKT:
1247                 *((u8 *)value) = hal_data->bDumpTxPkt;
1248                 break;
1249         case HAL_DEF_ANT_DETECT:
1250                 *((u8 *)value) = hal_data->AntDetection;
1251                 break;
1252         case HAL_DEF_MACID_SLEEP:
1253                 *(u8 *)value = false;
1254                 break;
1255         case HAL_DEF_TX_PAGE_SIZE:
1256                 *((u32 *)value) = PAGE_SIZE_128;
1257                 break;
1258         default:
1259                 DBG_871X_LEVEL(_drv_always_, "%s: [WARNING] HAL_DEF_VARIABLE(%d) not defined!\n", __func__, variable);
1260                 bResult = _FAIL;
1261                 break;
1262         }
1263
1264         return bResult;
1265 }
1266
1267 void GetHalODMVar(
1268         struct adapter *Adapter,
1269         enum HAL_ODM_VARIABLE eVariable,
1270         void *pValue1,
1271         void *pValue2
1272 )
1273 {
1274         switch (eVariable) {
1275 #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1276         case HAL_ODM_NOISE_MONITOR:
1277                 {
1278                         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1279                         u8 chan = *(u8 *)pValue1;
1280                         *(s16 *)pValue2 = pHalData->noise[chan];
1281                         #ifdef DBG_NOISE_MONITOR
1282                         DBG_8192C("### Noise monitor chan(%d)-noise:%d (dBm) ###\n",
1283                                 chan, pHalData->noise[chan]);
1284                         #endif
1285
1286                 }
1287                 break;
1288 #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1289         default:
1290                 break;
1291         }
1292 }
1293
1294 void SetHalODMVar(
1295         struct adapter *Adapter,
1296         enum HAL_ODM_VARIABLE eVariable,
1297         void *pValue1,
1298         bool bSet
1299 )
1300 {
1301         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
1302         PDM_ODM_T podmpriv = &pHalData->odmpriv;
1303         /* _irqL irqL; */
1304         switch (eVariable) {
1305         case HAL_ODM_STA_INFO:
1306                 {
1307                         struct sta_info *psta = pValue1;
1308                         if (bSet) {
1309                                 DBG_8192C("### Set STA_(%d) info ###\n", psta->mac_id);
1310                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, psta);
1311                         } else {
1312                                 DBG_8192C("### Clean STA_(%d) info ###\n", psta->mac_id);
1313                                 /* spin_lock_bh(&pHalData->odm_stainfo_lock); */
1314                                 ODM_CmnInfoPtrArrayHook(podmpriv, ODM_CMNINFO_STA_STATUS, psta->mac_id, NULL);
1315
1316                                 /* spin_unlock_bh(&pHalData->odm_stainfo_lock); */
1317                     }
1318                 }
1319                 break;
1320         case HAL_ODM_P2P_STATE:
1321                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DIRECT, bSet);
1322                 break;
1323         case HAL_ODM_WIFI_DISPLAY_STATE:
1324                         ODM_CmnInfoUpdate(podmpriv, ODM_CMNINFO_WIFI_DISPLAY, bSet);
1325                 break;
1326         #if defined(CONFIG_SIGNAL_DISPLAY_DBM) && defined(CONFIG_BACKGROUND_NOISE_MONITOR)
1327         case HAL_ODM_NOISE_MONITOR:
1328                 {
1329                         struct noise_info *pinfo = pValue1;
1330
1331                         #ifdef DBG_NOISE_MONITOR
1332                         DBG_8192C("### Noise monitor chan(%d)-bPauseDIG:%d, IGIValue:0x%02x, max_time:%d (ms) ###\n",
1333                                 pinfo->chan, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1334                         #endif
1335
1336                         pHalData->noise[pinfo->chan] = ODM_InbandNoise_Monitor(podmpriv, pinfo->bPauseDIG, pinfo->IGIValue, pinfo->max_time);
1337                         DBG_871X("chan_%d, noise = %d (dBm)\n", pinfo->chan, pHalData->noise[pinfo->chan]);
1338                         #ifdef DBG_NOISE_MONITOR
1339                         DBG_871X("noise_a = %d, noise_b = %d  noise_all:%d\n",
1340                                 podmpriv->noise_level.noise[ODM_RF_PATH_A],
1341                                 podmpriv->noise_level.noise[ODM_RF_PATH_B],
1342                                 podmpriv->noise_level.noise_all);
1343                         #endif
1344                 }
1345                 break;
1346         #endif/* ifdef CONFIG_BACKGROUND_NOISE_MONITOR */
1347
1348         default:
1349                 break;
1350         }
1351 }
1352
1353
1354 bool eqNByte(u8 *str1, u8 *str2, u32 num)
1355 {
1356         if (num == 0)
1357                 return false;
1358         while (num > 0) {
1359                 num--;
1360                 if (str1[num] != str2[num])
1361                         return false;
1362         }
1363         return true;
1364 }
1365
1366 /*  */
1367 /*      Description: */
1368 /*              Return true if chTmp is represent for hex digit and */
1369 /*              false otherwise. */
1370 /*  */
1371 /*  */
1372 bool IsHexDigit(char chTmp)
1373 {
1374         if (
1375                 (chTmp >= '0' && chTmp <= '9') ||
1376                 (chTmp >= 'a' && chTmp <= 'f') ||
1377                 (chTmp >= 'A' && chTmp <= 'F')
1378         )
1379                 return true;
1380         else
1381                 return false;
1382 }
1383
1384
1385 /*  */
1386 /*      Description: */
1387 /*              Translate a character to hex digit. */
1388 /*  */
1389 u32 MapCharToHexDigit(char chTmp)
1390 {
1391         if (chTmp >= '0' && chTmp <= '9')
1392                 return (chTmp - '0');
1393         else if (chTmp >= 'a' && chTmp <= 'f')
1394                 return (10 + (chTmp - 'a'));
1395         else if (chTmp >= 'A' && chTmp <= 'F')
1396                 return (10 + (chTmp - 'A'));
1397         else
1398                 return 0;
1399 }
1400
1401
1402
1403 /*      Description: */
1404 /*              Parse hex number from the string pucStr. */
1405 bool GetHexValueFromString(char *szStr, u32 *pu4bVal, u32 *pu4bMove)
1406 {
1407         char *szScan = szStr;
1408
1409         /*  Check input parameter. */
1410         if (szStr == NULL || pu4bVal == NULL || pu4bMove == NULL) {
1411                 DBG_871X("GetHexValueFromString(): Invalid input arguments! szStr: %p, pu4bVal: %p, pu4bMove: %p\n",
1412                          szStr, pu4bVal, pu4bMove);
1413                 return false;
1414         }
1415
1416         /*  Initialize output. */
1417         *pu4bMove = 0;
1418         *pu4bVal = 0;
1419
1420         /*  Skip leading space. */
1421         while (*szScan != '\0' && (*szScan == ' ' || *szScan == '\t')) {
1422                 szScan++;
1423                 (*pu4bMove)++;
1424         }
1425
1426         /*  Skip leading '0x' or '0X'. */
1427         if (*szScan == '0' && (*(szScan+1) == 'x' || *(szScan+1) == 'X')) {
1428                 szScan += 2;
1429                 (*pu4bMove) += 2;
1430         }
1431
1432         /*  Check if szScan is now pointer to a character for hex digit, */
1433         /*  if not, it means this is not a valid hex number. */
1434         if (!IsHexDigit(*szScan))
1435                 return false;
1436
1437         /*  Parse each digit. */
1438         do {
1439                 (*pu4bVal) <<= 4;
1440                 *pu4bVal += MapCharToHexDigit(*szScan);
1441
1442                 szScan++;
1443                 (*pu4bMove)++;
1444         } while (IsHexDigit(*szScan));
1445
1446         return true;
1447 }
1448
1449 bool GetFractionValueFromString(
1450         char *szStr, u8 *pInteger, u8 *pFraction, u32 *pu4bMove
1451 )
1452 {
1453         char *szScan = szStr;
1454
1455         /*  Initialize output. */
1456         *pu4bMove = 0;
1457         *pInteger = 0;
1458         *pFraction = 0;
1459
1460         /*  Skip leading space. */
1461         while (*szScan != '\0' &&       (*szScan == ' ' || *szScan == '\t')) {
1462                 ++szScan;
1463                 ++(*pu4bMove);
1464         }
1465
1466         /*  Parse each digit. */
1467         do {
1468                 (*pInteger) *= 10;
1469                 *pInteger += (*szScan - '0');
1470
1471                 ++szScan;
1472                 ++(*pu4bMove);
1473
1474                 if (*szScan == '.') {
1475                         ++szScan;
1476                         ++(*pu4bMove);
1477
1478                         if (*szScan < '0' || *szScan > '9')
1479                                 return false;
1480                         else {
1481                                 *pFraction = *szScan - '0';
1482                                 ++szScan;
1483                                 ++(*pu4bMove);
1484                                 return true;
1485                         }
1486                 }
1487         } while (*szScan >= '0' && *szScan <= '9');
1488
1489         return true;
1490 }
1491
1492 /*  */
1493 /*      Description: */
1494 /*              Return true if szStr is comment out with leading "//". */
1495 /*  */
1496 bool IsCommentString(char *szStr)
1497 {
1498         if (*szStr == '/' && *(szStr+1) == '/')
1499                 return true;
1500         else
1501                 return false;
1502 }
1503
1504 bool GetU1ByteIntegerFromStringInDecimal(char *Str, u8 *pInt)
1505 {
1506         u16 i = 0;
1507         *pInt = 0;
1508
1509         while (Str[i] != '\0') {
1510                 if (Str[i] >= '0' && Str[i] <= '9') {
1511                         *pInt *= 10;
1512                         *pInt += (Str[i] - '0');
1513                 } else
1514                         return false;
1515
1516                 ++i;
1517         }
1518
1519         return true;
1520 }
1521
1522 /*  <20121004, Kordan> For example,
1523  *  ParseQualifiedString(inString, 0, outString, '[', ']') gets "Kordan" from
1524  *  a string "Hello [Kordan]".
1525  *  If RightQualifier does not exist, it will hang in the while loop
1526  */
1527 bool ParseQualifiedString(
1528         char *In, u32 *Start, char *Out, char LeftQualifier, char RightQualifier
1529 )
1530 {
1531         u32 i = 0, j = 0;
1532         char c = In[(*Start)++];
1533
1534         if (c != LeftQualifier)
1535                 return false;
1536
1537         i = (*Start);
1538         while ((c = In[(*Start)++]) != RightQualifier)
1539                 ; /*  find ']' */
1540         j = (*Start) - 2;
1541         strncpy((char *)Out, (const char *)(In+i), j-i+1);
1542
1543         return true;
1544 }
1545
1546 bool isAllSpaceOrTab(u8 *data, u8 size)
1547 {
1548         u8 cnt = 0, NumOfSpaceAndTab = 0;
1549
1550         while (size > cnt) {
1551                 if (data[cnt] == ' ' || data[cnt] == '\t' || data[cnt] == '\0')
1552                         ++NumOfSpaceAndTab;
1553
1554                 ++cnt;
1555         }
1556
1557         return size == NumOfSpaceAndTab;
1558 }
1559
1560
1561 void rtw_hal_check_rxfifo_full(struct adapter *adapter)
1562 {
1563         struct dvobj_priv *psdpriv = adapter->dvobj;
1564         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1565         int save_cnt = false;
1566
1567         /* switch counter to RX fifo */
1568         /* printk("8723b or 8192e , MAC_667 set 0xf0\n"); */
1569         rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xf0);
1570         save_cnt = true;
1571         /* todo: other chips */
1572
1573         if (save_cnt) {
1574                 /* rtw_write8(adapter, REG_RXERR_RPT+3, rtw_read8(adapter, REG_RXERR_RPT+3)|0xa0); */
1575                 pdbgpriv->dbg_rx_fifo_last_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow;
1576                 pdbgpriv->dbg_rx_fifo_curr_overflow = rtw_read16(adapter, REG_RXERR_RPT);
1577                 pdbgpriv->dbg_rx_fifo_diff_overflow = pdbgpriv->dbg_rx_fifo_curr_overflow-pdbgpriv->dbg_rx_fifo_last_overflow;
1578         }
1579 }
1580
1581 void linked_info_dump(struct adapter *padapter, u8 benable)
1582 {
1583         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(padapter);
1584
1585         if (padapter->bLinkInfoDump == benable)
1586                 return;
1587
1588         DBG_871X("%s %s\n", __func__, (benable) ? "enable" : "disable");
1589
1590         if (benable) {
1591                 pwrctrlpriv->org_power_mgnt = pwrctrlpriv->power_mgnt;/* keep org value */
1592                 rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1593
1594                 pwrctrlpriv->ips_org_mode = pwrctrlpriv->ips_mode;/* keep org value */
1595                 rtw_pm_set_ips(padapter, IPS_NONE);
1596         } else {
1597                 rtw_pm_set_ips(padapter, pwrctrlpriv->ips_org_mode);
1598
1599                 rtw_pm_set_lps(padapter, pwrctrlpriv->ips_org_mode);
1600         }
1601         padapter->bLinkInfoDump = benable;
1602 }
1603
1604 #ifdef DBG_RX_SIGNAL_DISPLAY_RAW_DATA
1605 void rtw_get_raw_rssi_info(void *sel, struct adapter *padapter)
1606 {
1607         u8 isCCKrate, rf_path;
1608         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1609         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1610
1611         DBG_871X_SEL_NL(
1612                 sel,
1613                 "RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1614                 HDATA_RATE(psample_pkt_rssi->data_rate),
1615                 psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all
1616         );
1617
1618         isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1619
1620         if (isCCKrate)
1621                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1622
1623         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1624                 DBG_871X_SEL_NL(
1625                         sel,
1626                         "RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)\n",
1627                         rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path],
1628                         psample_pkt_rssi->mimo_singal_quality[rf_path]
1629                 );
1630
1631                 if (!isCCKrate) {
1632                         DBG_871X_SEL_NL(
1633                                 sel,
1634                                 "\trx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1635                                 psample_pkt_rssi->ofdm_pwr[rf_path],
1636                                 psample_pkt_rssi->ofdm_snr[rf_path]
1637                         );
1638                 }
1639         }
1640 }
1641
1642 void rtw_dump_raw_rssi_info(struct adapter *padapter)
1643 {
1644         u8 isCCKrate, rf_path;
1645         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1646         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1647         DBG_871X("============ RAW Rx Info dump ===================\n");
1648         DBG_871X("RxRate = %s, PWDBALL = %d(%%), rx_pwr_all = %d(dBm)\n",
1649                         HDATA_RATE(psample_pkt_rssi->data_rate), psample_pkt_rssi->pwdball, psample_pkt_rssi->pwr_all);
1650
1651         isCCKrate = psample_pkt_rssi->data_rate <= DESC_RATE11M;
1652
1653         if (isCCKrate)
1654                 psample_pkt_rssi->mimo_singal_strength[0] = psample_pkt_rssi->pwdball;
1655
1656         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1657                 DBG_871X("RF_PATH_%d =>singal_strength:%d(%%), singal_quality:%d(%%)"
1658                         , rf_path, psample_pkt_rssi->mimo_singal_strength[rf_path], psample_pkt_rssi->mimo_singal_quality[rf_path]);
1659
1660                 if (!isCCKrate) {
1661                         printk(", rx_ofdm_pwr:%d(dBm), rx_ofdm_snr:%d(dB)\n",
1662                         psample_pkt_rssi->ofdm_pwr[rf_path], psample_pkt_rssi->ofdm_snr[rf_path]);
1663                 } else {
1664                         printk("\n");
1665                 }
1666         }
1667 }
1668
1669 void rtw_store_phy_info(struct adapter *padapter, union recv_frame *prframe)
1670 {
1671         u8 isCCKrate, rf_path;
1672         struct hal_com_data *pHalData =  GET_HAL_DATA(padapter);
1673         struct rx_pkt_attrib *pattrib = &prframe->u.hdr.attrib;
1674
1675         struct odm_phy_info *pPhyInfo  = (PODM_PHY_INFO_T)(&pattrib->phy_info);
1676         struct rx_raw_rssi *psample_pkt_rssi = &padapter->recvpriv.raw_rssi_info;
1677
1678         psample_pkt_rssi->data_rate = pattrib->data_rate;
1679         isCCKrate = pattrib->data_rate <= DESC_RATE11M;
1680
1681         psample_pkt_rssi->pwdball = pPhyInfo->rx_pwd_ba11;
1682         psample_pkt_rssi->pwr_all = pPhyInfo->recv_signal_power;
1683
1684         for (rf_path = 0; rf_path < pHalData->NumTotalRFPath; rf_path++) {
1685                 psample_pkt_rssi->mimo_singal_strength[rf_path] = pPhyInfo->rx_mimo_signal_strength[rf_path];
1686                 psample_pkt_rssi->mimo_singal_quality[rf_path] = pPhyInfo->rx_mimo_signal_quality[rf_path];
1687                 if (!isCCKrate) {
1688                         psample_pkt_rssi->ofdm_pwr[rf_path] = pPhyInfo->RxPwr[rf_path];
1689                         psample_pkt_rssi->ofdm_snr[rf_path] = pPhyInfo->RxSNR[rf_path];
1690                 }
1691         }
1692 }
1693 #endif
1694
1695 static u32 Array_kfreemap[] = {
1696         0xf8, 0xe,
1697         0xf6, 0xc,
1698         0xf4, 0xa,
1699         0xf2, 0x8,
1700         0xf0, 0x6,
1701         0xf3, 0x4,
1702         0xf5, 0x2,
1703         0xf7, 0x0,
1704         0xf9, 0x0,
1705         0xfc, 0x0,
1706 };
1707
1708 void rtw_bb_rf_gain_offset(struct adapter *padapter)
1709 {
1710         u8 value = padapter->eeprompriv.EEPROMRFGainOffset;
1711         u32 res, i = 0;
1712         u32 *Array = Array_kfreemap;
1713         u32 v1 = 0, v2 = 0, target = 0;
1714         /* DBG_871X("+%s value: 0x%02x+\n", __func__, value); */
1715
1716         if (value & BIT4) {
1717                 DBG_871X("Offset RF Gain.\n");
1718                 DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal);
1719                 if (padapter->eeprompriv.EEPROMRFGainVal != 0xff) {
1720                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1721                         res &= 0xfff87fff;
1722                         DBG_871X("Offset RF Gain. before reg 0x7f = 0x%08x\n", res);
1723                         /* res &= 0xfff87fff; */
1724                         for (i = 0; i < ARRAY_SIZE(Array_kfreemap); i += 2) {
1725                                 v1 = Array[i];
1726                                 v2 = Array[i+1];
1727                                 if (v1 == padapter->eeprompriv.EEPROMRFGainVal) {
1728                                         DBG_871X("Offset RF Gain. got v1 = 0x%x , v2 = 0x%x\n", v1, v2);
1729                                         target = v2;
1730                                         break;
1731                                 }
1732                         }
1733                         DBG_871X("padapter->eeprompriv.EEPROMRFGainVal = 0x%x , Gain offset Target Value = 0x%x\n", padapter->eeprompriv.EEPROMRFGainVal, target);
1734                         PHY_SetRFReg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, BIT18|BIT17|BIT16|BIT15, target);
1735
1736                         /* res |= (padapter->eeprompriv.EEPROMRFGainVal & 0x0f)<< 15; */
1737                         /* rtw_hal_write_rfreg(padapter, RF_PATH_A, REG_RF_BB_GAIN_OFFSET, RF_GAIN_OFFSET_MASK, res); */
1738                         res = rtw_hal_read_rfreg(padapter, RF_PATH_A, 0x7f, 0xffffffff);
1739                         DBG_871X("Offset RF Gain. After reg 0x7f = 0x%08x\n", res);
1740                 } else
1741                         DBG_871X("Offset RF Gain.  padapter->eeprompriv.EEPROMRFGainVal = 0x%x  != 0xff, didn't run Kfree\n", padapter->eeprompriv.EEPROMRFGainVal);
1742         } else
1743                 DBG_871X("Using the default RF gain.\n");
1744 }