1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 ******************************************************************************/
17 #ifndef __HALDMOUTSRC_H__
18 #define __HALDMOUTSRC_H__
21 #include "odm_EdcaTurboCheck.h"
23 #include "odm_PathDiv.h"
24 #include "odm_DynamicBBPowerSaving.h"
25 #include "odm_DynamicTxPower.h"
26 #include "odm_CfoTracking.h"
27 #include "odm_NoiseMonitor.h"
32 #define TRAFFIC_HIGH 1
36 /* 3 Tx Power Tracking */
37 /* 3 ============================================================ */
38 #define DPK_DELTA_MAPPING_NUM 13
39 #define index_mapping_HP_NUM 15
40 #define OFDM_TABLE_SIZE 43
41 #define CCK_TABLE_SIZE 33
42 #define TXSCALE_TABLE_SIZE 37
43 #define TXPWR_TRACK_TABLE_SIZE 30
44 #define DELTA_SWINGIDX_SIZE 30
48 /* 3 ============================================================ */
50 #define AFH_PSD 1 /* 0:normal PSD scan, 1: only do 20 pts PSD */
51 #define MODE_40M 0 /* 0:20M, 1:40M */
53 #define PSD_CHMIN 20 /* Minimum channel number for BT AFH */
54 #define SIR_STEP_SIZE 3
55 #define Smooth_Size_1 5
57 #define Smooth_Size_2 10
59 #define Smooth_Size_3 20
61 #define Smooth_Step_Size 5
62 #define Adaptive_SIR 1
64 #define PSD_SCAN_INTERVAL 700 /* ms */
66 /* 8723A High Power IGI Setting */
67 #define DM_DIG_HIGH_PWR_IGI_LOWER_BOUND 0x22
68 #define DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND 0x28
69 #define DM_DIG_HIGH_PWR_THRESHOLD 0x3a
70 #define DM_DIG_LOW_PWR_THRESHOLD 0x14
73 #define ANTTESTALL 0x00 /* Ant A or B will be Testing */
74 #define ANTTESTA 0x01 /* Ant A will be Testing */
75 #define ANTTESTB 0x02 /* Ant B will be testing */
77 #define PS_MODE_ACTIVE 0x01
79 /* for 8723A Ant Definition--2012--06--07 due to different IC may be different ANT define */
80 #define MAIN_ANT 1 /* Ant A or Ant Main */
81 #define AUX_ANT 2 /* AntB or Ant Aux */
82 #define MAX_ANT 3 /* 3 for AP using */
85 /* Antenna Diversity Type */
88 /* structure and define */
90 /* Remove DIG by Yuchen */
92 /* Remoce BB power saving by Yuchn */
94 /* Remove DIG by yuchen */
96 typedef struct _Dynamic_Primary_CCA {
104 } Pri_CCA_T, *pPri_CCA_T;
106 typedef struct _Rate_Adaptive_Table_ {
110 typedef struct _RX_High_Power_ {
113 u8 PSD_bitmap_RXHP[80];
118 bool First_time_enter;
124 #define ASSOCIATE_ENTRY_NUM 32 /* Max size of AsocEntry[]. */
125 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
127 /* This indicates two different the steps. */
128 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
129 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
130 /* with original RSSI to determine if it is necessary to switch antenna. */
131 #define SWAW_STEP_PEAK 0
132 #define SWAW_STEP_DETERMINE 1
136 #define TRAFFIC_LOW 0
137 #define TRAFFIC_HIGH 1
138 #define TRAFFIC_UltraLOW 2
140 typedef struct _SW_Antenna_Switch_ {
148 u8 bTriggerAntennaSwitch;
152 u16 Single_Ant_Counter;
153 u16 Dual_Ant_Counter;
154 u16 Aux_FailDetec_Counter;
157 /* Before link Antenna Switch check */
158 u8 SWAS_NoLink_State;
159 u32 SWAS_NoLink_BK_Reg860;
160 u32 SWAS_NoLink_BK_Reg92c;
161 u32 SWAS_NoLink_BK_Reg948;
162 bool ANTA_ON; /* To indicate Ant A is or not */
163 bool ANTB_ON; /* To indicate Ant B is on or not */
164 bool Pre_Aux_FailDetec;
165 bool RSSI_AntDect_bResult;
183 RT_TIMER SwAntennaSwitchTimer;
184 RT_TIMER SwAntennaSwitchTimer_8723B;
185 u32 PktCnt_SWAntDivByCtrlFrame;
186 bool bSWAntDivByCtrlFrame;
189 /* Remove Edca by YuChen */
192 typedef struct _ODM_RATE_ADAPTIVE {
193 u8 Type; /* DM_Type_ByFW/DM_Type_ByDriver */
194 u8 LdpcThres; /* if RSSI > LdpcThres => switch from LPDC to BCC */
197 u8 HighRSSIThresh; /* if RSSI > HighRSSIThresh => RATRState is DM_RATR_STA_HIGH */
198 u8 LowRSSIThresh; /* if RSSI <= LowRSSIThresh => RATRState is DM_RATR_STA_LOW */
199 u8 RATRState; /* Current RSSI level, DM_RATR_STA_HIGH/DM_RATR_STA_MIDDLE/DM_RATR_STA_LOW */
201 } ODM_RATE_ADAPTIVE, *PODM_RATE_ADAPTIVE;
204 #define IQK_MAC_REG_NUM 4
205 #define IQK_ADDA_REG_NUM 16
206 #define IQK_BB_REG_NUM_MAX 10
207 #define IQK_BB_REG_NUM 9
208 #define HP_THERMAL_NUM 8
210 #define AVG_THERMAL_NUM 8
211 #define IQK_Matrix_REG_NUM 8
212 #define IQK_Matrix_Settings_NUM 14 /* Channels_2_4G_NUM */
214 #define DM_Type_ByFW 0
215 #define DM_Type_ByDriver 1
218 /* Declare for common info */
220 #define MAX_PATH_NUM_92CS 2
221 #define MAX_PATH_NUM_8188E 1
222 #define MAX_PATH_NUM_8192E 2
223 #define MAX_PATH_NUM_8723B 1
224 #define MAX_PATH_NUM_8812A 2
225 #define MAX_PATH_NUM_8821A 1
226 #define MAX_PATH_NUM_8814A 4
227 #define MAX_PATH_NUM_8822B 2
230 #define IQK_THRESHOLD 8
231 #define DPK_THRESHOLD 4
233 typedef struct _ODM_Phy_Status_Info_ {
235 /* Be care, if you want to add any element please insert between */
236 /* RxPWDBAll & SignalStrength. */
240 u8 SignalQuality; /* in 0-100 index. */
241 s8 RxMIMOSignalQuality[4]; /* per-path's EVM */
242 u8 RxMIMOEVMdbm[4]; /* per-path's EVM dbm */
244 u8 RxMIMOSignalStrength[4];/* in 0~100 index */
246 u16 Cfo_short[4]; /* per-path's Cfo_short */
247 u16 Cfo_tail[4]; /* per-path's Cfo_tail */
249 s8 RxPower; /* in dBm Translate from PWdB */
250 s8 RecvSignalPower; /* Real power in dBm for this packet, no beautification and aggregation. Keep this raw info to be used for the other procedures. */
251 u8 BTRxRSSIPercentage;
252 u8 SignalStrength; /* in 0-100 index. */
254 s8 RxPwr[4]; /* per-path's pwdb */
256 u8 RxSNR[4]; /* per-path's SNR */
259 } ODM_PHY_INFO_T, *PODM_PHY_INFO_T;
262 typedef struct _ODM_Per_Pkt_Info_ {
266 bool bPacketMatchBSSID;
270 } ODM_PACKET_INFO_T, *PODM_PACKET_INFO_T;
273 typedef struct _ODM_Phy_Dbg_Info_ {
274 /* ODM Write, debug info */
277 u32 NumQryPhyStatusCCK;
278 u32 NumQryPhyStatusOFDM;
283 } ODM_PHY_DBG_INFO_T;
286 typedef struct _ODM_Mac_Status_Info_ {
291 typedef enum tag_Dynamic_ODM_Support_Ability_Type {
293 ODM_DIG = 0x00000001,
294 ODM_HIGH_POWER = 0x00000002,
295 ODM_CCK_CCA_TH = 0x00000004,
296 ODM_FA_STATISTICS = 0x00000008,
297 ODM_RAMASK = 0x00000010,
298 ODM_RSSI_MONITOR = 0x00000020,
299 ODM_SW_ANTDIV = 0x00000040,
300 ODM_HW_ANTDIV = 0x00000080,
301 ODM_BB_PWRSV = 0x00000100,
302 ODM_2TPATHDIV = 0x00000200,
303 ODM_1TPATHDIV = 0x00000400,
304 ODM_PSD2AFH = 0x00000800
308 /* 2011/20/20 MH For MP driver RT_WLAN_STA = STA_INFO_T */
309 /* Please declare below ODM relative info in your STA info structure. */
311 typedef struct _ODM_STA_INFO {
313 bool bUsed; /* record the sta status link or not? */
314 /* u8 WirelessMode; */
315 u8 IOTPeer; /* Enum value. HT_IOT_PEER_E */
318 /* 1 PHY_STATUS_INFO */
319 u8 RSSI_Path[4]; /* */
325 /* 1 TX_INFO (may changed by IC) */
326 /* TX_INFO_T pTxInfo; Define in IC folder. Move lower layer. */
329 /* Please use compile flag to disabe the strcutrue for other IC except 88E. */
330 /* Move To lower layer. */
332 /* ODM Write Wilson will handle this part(said by Luke.Lee) */
333 /* TX_RPT_T pTxRpt; Define in IC folder. Move lower layer. */
334 } ODM_STA_INFO_T, *PODM_STA_INFO_T;
337 /* 2011/10/20 MH Define Common info enum for all team. */
339 typedef enum _ODM_Common_Info_Definition {
342 /* HOOK BEFORE REG INIT----------- */
343 ODM_CMNINFO_PLATFORM = 0,
344 ODM_CMNINFO_ABILITY, /* ODM_ABILITY_E */
345 ODM_CMNINFO_INTERFACE, /* ODM_INTERFACE_E */
346 ODM_CMNINFO_MP_TEST_CHIP,
347 ODM_CMNINFO_IC_TYPE, /* ODM_IC_TYPE_E */
348 ODM_CMNINFO_CUT_VER, /* ODM_CUT_VERSION_E */
349 ODM_CMNINFO_FAB_VER, /* ODM_FAB_E */
350 ODM_CMNINFO_RF_TYPE, /* ODM_RF_PATH_E or ODM_RF_TYPE_E? */
351 ODM_CMNINFO_RFE_TYPE,
352 ODM_CMNINFO_BOARD_TYPE, /* ODM_BOARD_TYPE_E */
353 ODM_CMNINFO_PACKAGE_TYPE,
354 ODM_CMNINFO_EXT_LNA, /* true */
355 ODM_CMNINFO_5G_EXT_LNA,
357 ODM_CMNINFO_5G_EXT_PA,
362 ODM_CMNINFO_EXT_TRSW,
363 ODM_CMNINFO_PATCH_ID, /* CUSTOMER ID */
364 ODM_CMNINFO_BINHCT_TEST,
365 ODM_CMNINFO_BWIFI_TEST,
366 ODM_CMNINFO_SMART_CONCURRENT,
367 /* HOOK BEFORE REG INIT----------- */
371 /* POINTER REFERENCE----------- */
372 ODM_CMNINFO_MAC_PHY_MODE, /* ODM_MAC_PHY_MODE_E */
375 ODM_CMNINFO_WM_MODE, /* ODM_WIRELESS_MODE_E */
376 ODM_CMNINFO_BAND, /* ODM_BAND_TYPE_E */
377 ODM_CMNINFO_SEC_CHNL_OFFSET, /* ODM_SEC_CHNL_OFFSET_E */
378 ODM_CMNINFO_SEC_MODE, /* ODM_SECURITY_E */
379 ODM_CMNINFO_BW, /* ODM_BW_E */
381 ODM_CMNINFO_FORCED_RATE,
383 ODM_CMNINFO_DMSP_GET_VALUE,
384 ODM_CMNINFO_BUDDY_ADAPTOR,
385 ODM_CMNINFO_DMSP_IS_MASTER,
387 ODM_CMNINFO_POWER_SAVING,
388 ODM_CMNINFO_ONE_PATH_CCA, /* ODM_CCA_PATH_E */
389 ODM_CMNINFO_DRV_STOP,
392 ODM_CMNINFO_ANT_TEST,
393 ODM_CMNINFO_NET_CLOSED,
395 /* ODM_CMNINFO_RTSTA_AID, For win driver only? */
396 ODM_CMNINFO_FORCED_IGI_LB,
397 ODM_CMNINFO_IS1ANTENNA,
398 ODM_CMNINFO_RFDEFAULTPATH,
399 /* POINTER REFERENCE----------- */
401 /* CALL BY VALUE------------- */
402 ODM_CMNINFO_WIFI_DIRECT,
403 ODM_CMNINFO_WIFI_DISPLAY,
404 ODM_CMNINFO_LINK_IN_PROGRESS,
406 ODM_CMNINFO_STATION_STATE,
407 ODM_CMNINFO_RSSI_MIN,
408 ODM_CMNINFO_DBG_COMP, /* u64 */
409 ODM_CMNINFO_DBG_LEVEL, /* u32 */
410 ODM_CMNINFO_RA_THRESHOLD_HIGH, /* u8 */
411 ODM_CMNINFO_RA_THRESHOLD_LOW, /* u8 */
412 ODM_CMNINFO_RF_ANTENNA_TYPE, /* u8 */
413 ODM_CMNINFO_BT_ENABLED,
414 ODM_CMNINFO_BT_HS_CONNECT_PROCESS,
415 ODM_CMNINFO_BT_HS_RSSI,
416 ODM_CMNINFO_BT_OPERATION,
417 ODM_CMNINFO_BT_LIMITED_DIG, /* Need to Limited Dig or not */
418 ODM_CMNINFO_BT_DISABLE_EDCA,
419 /* CALL BY VALUE------------- */
421 /* Dynamic ptr array hook itms. */
422 ODM_CMNINFO_STA_STATUS,
423 ODM_CMNINFO_PHY_STATUS,
424 ODM_CMNINFO_MAC_STATUS,
431 /* 2011/10/20 MH Define ODM support ability. ODM_CMNINFO_ABILITY */
432 typedef enum _ODM_Support_Ability_Definition {
434 /* BB ODM section BIT 0-15 */
437 ODM_BB_RA_MASK = BIT1,
438 ODM_BB_DYNAMIC_TXPWR = BIT2,
439 ODM_BB_FA_CNT = BIT3,
440 ODM_BB_RSSI_MONITOR = BIT4,
441 ODM_BB_CCK_PD = BIT5,
442 ODM_BB_ANT_DIV = BIT6,
443 ODM_BB_PWR_SAVE = BIT7,
444 ODM_BB_PWR_TRAIN = BIT8,
445 ODM_BB_RATE_ADAPTIVE = BIT9,
446 ODM_BB_PATH_DIV = BIT10,
449 ODM_BB_ADAPTIVITY = BIT13,
450 ODM_BB_CFO_TRACKING = BIT14,
452 /* MAC DM section BIT 16-23 */
453 ODM_MAC_EDCA_TURBO = BIT16,
454 ODM_MAC_EARLY_MODE = BIT17,
456 /* RF ODM section BIT 24-31 */
457 ODM_RF_TX_PWR_TRACK = BIT24,
458 ODM_RF_RX_GAIN_TRACK = BIT25,
459 ODM_RF_CALIBRATION = BIT26,
462 /* ODM_CMNINFO_INTERFACE */
463 typedef enum tag_ODM_Support_Interface_Definition {
468 /* ODM_CMNINFO_IC_TYPE */
469 typedef enum tag_ODM_Support_IC_Type_Definition {
473 /* ODM_CMNINFO_CUT_VER */
474 typedef enum tag_ODM_Cut_Version_Definition {
488 /* ODM_CMNINFO_FAB_VER */
489 typedef enum tag_ODM_Fab_Version_Definition {
494 /* ODM_CMNINFO_RF_TYPE */
496 /* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
498 typedef enum tag_ODM_RF_Path_Bit_Definition {
510 typedef enum tag_ODM_RF_Type_Definition {
523 /* ODM Dynamic common info value definition */
526 /* typedef enum _MACPHY_MODE_8192D{ */
527 /* SINGLEMAC_SINGLEPHY, */
528 /* DUALMAC_DUALPHY, */
529 /* DUALMAC_SINGLEPHY, */
530 /* MACPHY_MODE_8192D,*PMACPHY_MODE_8192D; */
531 /* Above is the original define in MP driver. Please use the same define. THX. */
532 typedef enum tag_ODM_MAC_PHY_Mode_Definition {
536 } ODM_MAC_PHY_MODE_E;
539 typedef enum tag_BT_Coexist_Definition {
546 /* ODM_CMNINFO_OP_MODE */
547 typedef enum tag_Operation_Mode_Definition {
551 ODM_POWERSAVE = BIT3,
553 ODM_CLIENT_MODE = BIT5,
555 ODM_WIFI_DIRECT = BIT7,
556 ODM_WIFI_DISPLAY = BIT8,
557 } ODM_OPERATION_MODE_E;
559 /* ODM_CMNINFO_WM_MODE */
560 typedef enum tag_Wireless_Mode_Definition {
569 } ODM_WIRELESS_MODE_E;
571 /* ODM_CMNINFO_BAND */
572 typedef enum tag_Band_Type_Definition {
579 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
580 typedef enum tag_Secondary_Channel_Offset_Definition {
584 } ODM_SEC_CHNL_OFFSET_E;
586 /* ODM_CMNINFO_SEC_MODE */
587 typedef enum tag_Security_Definition {
594 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
599 typedef enum tag_Bandwidth_Definition {
608 /* ODM_CMNINFO_BOARD_TYPE */
609 /* For non-AC-series IC , ODM_BOARD_5G_EXT_PA and ODM_BOARD_5G_EXT_LNA are ignored */
610 /* For AC-series IC, external PA & LNA can be indivisuallly added on 2.4G and/or 5G */
611 typedef enum tag_Board_Definition {
612 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
613 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1 = mini card. */
614 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
615 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
616 ODM_BOARD_EXT_PA = BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
617 ODM_BOARD_EXT_LNA = BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
618 ODM_BOARD_EXT_TRSW = BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
619 ODM_BOARD_EXT_PA_5G = BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
620 ODM_BOARD_EXT_LNA_5G = BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
623 typedef enum tag_ODM_Package_Definition {
624 ODM_PACKAGE_DEFAULT = 0,
625 ODM_PACKAGE_QFN68 = BIT(0),
626 ODM_PACKAGE_TFBGA90 = BIT(1),
627 ODM_PACKAGE_TFBGA79 = BIT(2),
628 } ODM_Package_TYPE_E;
630 typedef enum tag_ODM_TYPE_GPA_Definition {
632 TYPE_GPA1 = BIT(1)|BIT(0)
635 typedef enum tag_ODM_TYPE_APA_Definition {
637 TYPE_APA1 = BIT(1)|BIT(0)
640 typedef enum tag_ODM_TYPE_GLNA_Definition {
642 TYPE_GLNA1 = BIT(2)|BIT(0),
643 TYPE_GLNA2 = BIT(3)|BIT(1),
644 TYPE_GLNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
647 typedef enum tag_ODM_TYPE_ALNA_Definition {
649 TYPE_ALNA1 = BIT(2)|BIT(0),
650 TYPE_ALNA2 = BIT(3)|BIT(1),
651 TYPE_ALNA3 = BIT(3)|BIT(2)|BIT(1)|BIT(0)
654 /* ODM_CMNINFO_ONE_PATH_CCA */
655 typedef enum tag_CCA_Path {
662 typedef struct _ODM_RA_Info_ {
683 u8 PTActive; /* on or off */
684 u8 PTTryState; /* 0 trying state, 1 for decision state */
685 u8 PTStage; /* 0~6 */
686 u8 PTStopCount; /* Stop PT counter */
687 u8 PTPreRate; /* if rate change do PT */
688 u8 PTPreRssi; /* if RSSI change 5% do PT */
689 u8 PTModeSS; /* decide whitch rate should do PT */
690 u8 RAstage; /* StageRA, decide how many times RA will be done between PT */
692 } ODM_RA_INFO_T, *PODM_RA_INFO_T;
694 typedef struct _IQK_MATRIX_REGS_SETTING {
696 s32 Value[3][IQK_Matrix_REG_NUM];
697 bool bBWIqkResultSaved[3];
698 } IQK_MATRIX_REGS_SETTING, *PIQK_MATRIX_REGS_SETTING;
701 /* Remove PATHDIV_PARA struct to odm_PathDiv.h */
703 typedef struct ODM_RF_Calibration_Structure {
704 /* for tx power tracking */
706 u32 RegA24; /* for TempCCK */
713 bool bTXPowerTrackingInit;
714 bool bTXPowerTracking;
715 u8 TxPowerTrackControl; /* for mp mode, turn off txpwrtracking as default */
717 u8 InternalPA5G[2]; /* pathA / pathB */
719 u8 ThermalMeter[2]; /* ThermalMeter, index 0 for RFIC0, and 1 for RFIC1 */
724 u8 ThermalValue_AVG[AVG_THERMAL_NUM];
725 u8 ThermalValue_AVG_index;
726 u8 ThermalValue_RxGain;
727 u8 ThermalValue_Crystal;
728 u8 ThermalValue_DPKstore;
729 u8 ThermalValue_DPKtrack;
730 bool TxPowerTrackingInProgress;
732 bool bReloadtxpowerindex;
734 u32 TXPowerTrackingCallbackCnt; /* cosa add for debug */
737 /* Tx power Tracking ------------------------- */
740 u8 OFDM_index[MAX_RF_PATH];
741 s8 PowerIndexOffset[MAX_RF_PATH];
742 s8 DeltaPowerIndex[MAX_RF_PATH];
743 s8 DeltaPowerIndexLast[MAX_RF_PATH];
744 bool bTxPowerChanged;
746 u8 ThermalValue_HP[HP_THERMAL_NUM];
747 u8 ThermalValue_HP_index;
748 IQK_MATRIX_REGS_SETTING IQKMatrixRegSetting[IQK_Matrix_Settings_NUM];
753 s8 BBSwingDiff2G, BBSwingDiff5G; /* Unit: dB */
754 u8 DeltaSwingTableIdx_2GCCKA_P[DELTA_SWINGIDX_SIZE];
755 u8 DeltaSwingTableIdx_2GCCKA_N[DELTA_SWINGIDX_SIZE];
756 u8 DeltaSwingTableIdx_2GCCKB_P[DELTA_SWINGIDX_SIZE];
757 u8 DeltaSwingTableIdx_2GCCKB_N[DELTA_SWINGIDX_SIZE];
758 u8 DeltaSwingTableIdx_2GA_P[DELTA_SWINGIDX_SIZE];
759 u8 DeltaSwingTableIdx_2GA_N[DELTA_SWINGIDX_SIZE];
760 u8 DeltaSwingTableIdx_2GB_P[DELTA_SWINGIDX_SIZE];
761 u8 DeltaSwingTableIdx_2GB_N[DELTA_SWINGIDX_SIZE];
762 u8 DeltaSwingTableIdx_5GA_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
763 u8 DeltaSwingTableIdx_5GA_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
764 u8 DeltaSwingTableIdx_5GB_P[BAND_NUM][DELTA_SWINGIDX_SIZE];
765 u8 DeltaSwingTableIdx_5GB_N[BAND_NUM][DELTA_SWINGIDX_SIZE];
766 u8 DeltaSwingTableIdx_2GA_P_8188E[DELTA_SWINGIDX_SIZE];
767 u8 DeltaSwingTableIdx_2GA_N_8188E[DELTA_SWINGIDX_SIZE];
781 bool bIQKInitialized;
783 bool bAntennaDetected;
784 u32 ADDA_backup[IQK_ADDA_REG_NUM];
785 u32 IQK_MAC_backup[IQK_MAC_REG_NUM];
786 u32 IQK_BB_backup_recover[9];
787 u32 IQK_BB_backup[IQK_BB_REG_NUM];
788 u32 TxIQC_8723B[2][3][2]; /* { {S1: 0xc94, 0xc80, 0xc4c} , {S0: 0xc9c, 0xc88, 0xc4c}} */
789 u32 RxIQC_8723B[2][2][2]; /* { {S1: 0xc14, 0xca0} , {S0: 0xc14, 0xca0}} */
793 u32 APKoutput[2][2]; /* path A/B; output1_1a/output1_2a */
795 u8 bAPKThermalMeterIgnore;
805 } ODM_RF_CAL_T, *PODM_RF_CAL_T;
807 /* ODM Dynamic common info value definition */
810 typedef struct _FAST_ANTENNA_TRAINNING_ {
821 u8 antsel_a[ODM_ASSOCIATE_ENTRY_NUM];
822 u8 antsel_b[ODM_ASSOCIATE_ENTRY_NUM];
823 u8 antsel_c[ODM_ASSOCIATE_ENTRY_NUM];
824 u32 MainAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
825 u32 AuxAnt_Sum[ODM_ASSOCIATE_ENTRY_NUM];
826 u32 MainAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
827 u32 AuxAnt_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
831 u8 idx_AntDiv_counter_2G;
832 u8 idx_AntDiv_counter_5G;
834 u32 CCK_counter_main;
836 u32 OFDM_counter_main;
837 u32 OFDM_counter_aux;
840 u32 CCK_CtrlFrame_Cnt_main;
841 u32 CCK_CtrlFrame_Cnt_aux;
842 u32 OFDM_CtrlFrame_Cnt_main;
843 u32 OFDM_CtrlFrame_Cnt_aux;
844 u32 MainAnt_CtrlFrame_Sum;
845 u32 AuxAnt_CtrlFrame_Sum;
846 u32 MainAnt_CtrlFrame_Cnt;
847 u32 AuxAnt_CtrlFrame_Cnt;
851 typedef enum _FAT_STATE {
852 FAT_NORMAL_STATE = 0,
853 FAT_TRAINING_STATE = 1,
854 } FAT_STATE_E, *PFAT_STATE_E;
856 typedef enum _ANT_DIV_TYPE {
858 CG_TRX_HW_ANTDIV = 0x01,
859 CGCS_RX_HW_ANTDIV = 0x02,
860 FIXED_HW_ANTDIV = 0x03,
861 CG_TRX_SMART_ANTDIV = 0x04,
862 CGCS_RX_SW_ANTDIV = 0x05,
863 S0S1_SW_ANTDIV = 0x06 /* 8723B intrnal switch S0 S1 */
864 } ANT_DIV_TYPE_E, *PANT_DIV_TYPE_E;
866 typedef struct _ODM_PATH_DIVERSITY_ {
868 u8 PathSel[ODM_ASSOCIATE_ENTRY_NUM];
869 u32 PathA_Sum[ODM_ASSOCIATE_ENTRY_NUM];
870 u32 PathB_Sum[ODM_ASSOCIATE_ENTRY_NUM];
871 u32 PathA_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
872 u32 PathB_Cnt[ODM_ASSOCIATE_ENTRY_NUM];
873 } PATHDIV_T, *pPATHDIV_T;
876 typedef enum _BASEBAND_CONFIG_PHY_REG_PG_VALUE_TYPE{
877 PHY_REG_PG_RELATIVE_VALUE = 0,
878 PHY_REG_PG_EXACT_VALUE = 1
883 /* Antenna detection information from single tone mechanism, added by Roger, 2012.11.27. */
885 typedef struct _ANT_DETECTED_INFO {
890 } ANT_DETECTED_INFO, *PANT_DETECTED_INFO;
893 /* 2011/09/22 MH Copy from SD4 defined structure. We use to support PHY DM integration. */
895 typedef struct DM_Out_Source_Dynamic_Mechanism_Structure {
896 /* RT_TIMER FastAntTrainingTimer; */
898 /* Add for different team use temporarily */
900 struct adapter *Adapter; /* For CE/NIC team */
901 /* WHen you use Adapter or priv pointer, you must make sure the pointer is ready. */
904 PHY_REG_PG_TYPE PhyRegPgValueType;
910 u32 NumQryPhyStatusAll; /* CCK + OFDM */
911 u32 LastNumQryPhyStatusAll;
913 bool MPDIG_2G; /* off MPDIG */
916 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
918 u8 RFPathRxEnable; /* ODM_CMNINFO_RFPATH_ENABLE */
920 /* ODM HANDLE, DRIVER NEEDS NOT TO HOOK------ */
922 /* REMOVED COMMON INFO---------- */
923 /* u8 PseudoMacPhyMode; */
924 /* bool *BTCoexist; */
925 /* bool PseudoBtCoexist; */
928 /* bool bClientMode; */
929 /* bool bAdHocMode; */
930 /* bool bSlaveOfDMSP; */
931 /* REMOVED COMMON INFO---------- */
934 /* 1 COMMON INFORMATION */
939 /* HOOK BEFORE REG INIT----------- */
940 /* ODM Platform info AP/ADSL/CE/MP = 1/2/3/4 */
942 /* ODM Support Ability DIG/RATR/TX_PWR_TRACK/ ?K?K = 1/2/3/?K */
944 /* ODM PCIE/USB/SDIO = 1/2/3 */
946 /* ODM composite or independent. Bit oriented/ 92C+92D+ .... or any other type = 1/2/3/... */
948 /* Cut Version TestChip/A-cut/B-cut... = 0/1/2/3/... */
950 /* Fab Version TSMC/UMC = 0/1 */
952 /* RF Type 4T4R/3T3R/2T2R/1T2R/1T1R/... */
955 /* Board Type Normal/HighPower/MiniCard/SLIM/Combo/... = 0/1/2/3/4/... */
962 /* with external LNA NO/Yes = 0/1 */
965 /* with external PA NO/Yes = 0/1 */
968 /* with external TRSW NO/Yes = 0/1 */
970 u8 PatchID; /* Customer ID */
974 bool bDualMacSmartConcurrent;
975 u32 BK_SupportAbility;
977 /* HOOK BEFORE REG INIT----------- */
982 /* POINTER REFERENCE----------- */
986 struct adapter *adapter_temp;
988 /* MAC PHY Mode SMSP/DMSP/DMDP = 0/1/2 */
990 /* TX Unicast byte count */
991 u64 *pNumTxBytesUnicast;
992 /* RX Unicast byte count */
993 u64 *pNumRxBytesUnicast;
994 /* Wireless mode B/G/A/N = BIT0/BIT1/BIT2/BIT3 */
995 u8 *pwirelessmode; /* ODM_WIRELESS_MODE_E */
996 /* Frequence band 2.4G/5G = 0/1 */
998 /* Secondary channel offset don't_care/below/above = 0/1/2 */
1000 /* Security mode Open/WEP/AES/TKIP = 0/1/2/3 */
1002 /* BW info 20M/40M/80M = 0/1/2 */
1004 /* Central channel location Ch1/Ch2/.... */
1005 u8 *pChannel; /* central channel number */
1007 /* Common info for 92D DMSP */
1009 bool *pbGetValueFromOtherMac;
1010 struct adapter **pBuddyAdapter;
1011 bool *pbMasterOfDMSP; /* MAC0: master, MAC1: slave */
1012 /* Common info for Status */
1013 bool *pbScanInProcess;
1014 bool *pbPowerSaving;
1015 /* CCA Path 2-path/path-A/path-B = 0/1/2; using ODM_CCA_PATH_E. */
1017 /* pMgntInfo->AntennaTest */
1023 /* For 8723B IQK----------- */
1028 /* POINTER REFERENCE----------- */
1029 u16 *pForcedDataRate;
1030 /* CALL BY VALUE------------- */
1031 bool bLinkInProcess;
1038 u8 InterfaceIndex; /* Add for 92D dual MAC: 0--Mac0 1--Mac1 */
1041 /* Common info for BTDM */
1042 bool bBtEnabled; /* BT is disabled */
1043 bool bBtConnectProcess; /* BT HS is under connection progress. */
1044 u8 btHsRssi; /* BT HS mode wifi rssi value. */
1045 bool bBtHsOperation; /* BT HS mode is under progress */
1046 bool bBtDisableEdcaTurbo; /* Under some condition, don't enable the EDCA Turbo */
1047 bool bBtLimitedDig; /* BT is busy. */
1048 /* CALL BY VALUE------------- */
1061 u32 TxagcOffsetValueA;
1062 bool IsTxagcOffsetPositiveA;
1063 u32 TxagcOffsetValueB;
1064 bool IsTxagcOffsetPositiveB;
1068 bool IsBbSwingOffsetPositiveA;
1070 bool IsBbSwingOffsetPositiveB;
1072 s8 TH_EDCCA_HL_diff;
1086 bool H2C_RARpt_connect;
1088 /* add by Yu Cehn for adaptivtiy */
1089 bool adaptivity_flag;
1092 bool Carrier_Sense_enable;
1102 u8 Adaptivity_IGI_upper;
1106 ODM_NOISE_MONITOR noise_level;/* ODM_MAX_CHANNEL_NUM]; */
1108 /* 2 Define STA info. */
1110 /* 2012/01/12 MH For MP, we need to reduce one array pointer for default port.?? */
1111 PSTA_INFO_T pODM_StaInfo[ODM_ASSOCIATE_ENTRY_NUM];
1114 /* 2012/02/14 MH Add to share 88E ra with other SW team. */
1115 /* We need to colelct all support abilit to a proper area. */
1119 /* Define ........... */
1121 /* Latest packet phy info (ODM write) */
1122 ODM_PHY_DBG_INFO_T PhyDbgInfo;
1123 /* PHY_INFO_88E PhyInfo; */
1125 /* Latest packet phy info (ODM write) */
1126 ODM_MAC_INFO *pMacInfo;
1127 /* MAC_INFO_88E MacInfo; */
1129 /* Different Team independt structure?? */
1132 /* TX_RTP_CMN TX_retrpo; */
1133 /* TX_RTP_88E TX_retrpo; */
1134 /* TX_RTP_8195 TX_retrpo; */
1142 Pri_CCA_T DM_PriCCA;
1143 RXHP_T DM_RXHP_Table;
1145 false_ALARM_STATISTICS FalseAlmCnt;
1146 false_ALARM_STATISTICS FlaseAlmCntBuddyAdapter;
1147 SWAT_T DM_SWAT_Table;
1149 CFO_TRACKING DM_CfoTrack;
1151 EDCA_T DM_EDCA_Table;
1153 PATHDIV_T DM_PathDiv;
1154 /* Copy from SD4 structure */
1156 /* ================================================== */
1161 /* u8 PSD_Report_RXHP[80]; Add By Gary */
1162 /* u8 PSD_func_flag; Add By Gary */
1164 /* u8 bDMInitialGainEnable; */
1165 /* u8 binitialized; for dm_initial_gain_Multi_STA use. */
1166 /* for Antenna diversity */
1167 /* u8 AntDivCfg; 0:OFF , 1:ON, 2:by efuse */
1168 /* PSTA_INFO_T RSSI_target; */
1170 bool *pbDriverStopped;
1171 bool *pbDriverIsGoingToPnpSetPowerSleep;
1172 bool *pinit_adpt_in_progress;
1175 bool bUserAssignLevel;
1177 u8 RSSI_BT; /* come from BT */
1180 bool bDMInitialGainEnable;
1183 RT_TIMER MPT_DIGTimer;
1185 /* for rate adaptive, in fact, 88c/92c fw will handle this */
1188 ODM_RATE_ADAPTIVE RateAdaptive;
1190 ANT_DETECTED_INFO AntDetectedInfo; /* Antenna detected information for RSSI tool */
1192 ODM_RF_CAL_T RFCalibrateInfo;
1195 /* TX power tracking */
1197 u8 BbSwingIdxOfdm[MAX_RF_PATH];
1198 u8 BbSwingIdxOfdmCurrent;
1199 u8 BbSwingIdxOfdmBase[MAX_RF_PATH];
1200 bool BbSwingFlagOfdm;
1202 u8 BbSwingIdxCckCurrent;
1203 u8 BbSwingIdxCckBase;
1204 u8 DefaultOfdmIndex;
1206 bool BbSwingFlagCck;
1208 s8 Absolute_OFDMSwingIdx[MAX_RF_PATH];
1209 s8 Remnant_OFDMSwingIdx[MAX_RF_PATH];
1210 s8 Remnant_CCKSwingIdx;
1211 s8 Modify_TxAGC_Value; /* Remnat compensate value at TxAGC */
1212 bool Modify_TxAGC_Flag_PathA;
1213 bool Modify_TxAGC_Flag_PathB;
1214 bool Modify_TxAGC_Flag_PathC;
1215 bool Modify_TxAGC_Flag_PathD;
1216 bool Modify_TxAGC_Flag_PathA_CCK;
1218 s8 KfreeOffset[MAX_RF_PATH];
1220 /* ODM system resource. */
1223 /* ODM relative time. */
1224 RT_TIMER PathDivSwitchTimer;
1225 /* 2011.09.27 add for Path Diversity */
1226 RT_TIMER CCKPathDiversityTimer;
1227 RT_TIMER FastAntTrainingTimer;
1229 /* ODM relative workitem. */
1231 #if (BEAMFORMING_SUPPORT == 1)
1232 RT_BEAMFORMING_INFO BeamformingInfo;
1234 } DM_ODM_T, *PDM_ODM_T; /* DM_Dynamic_Mechanism_Structure */
1236 #define ODM_RF_PATH_MAX 2
1238 typedef enum _ODM_RF_RADIO_PATH {
1239 ODM_RF_PATH_A = 0, /* Radio Path A */
1240 ODM_RF_PATH_B = 1, /* Radio Path B */
1241 ODM_RF_PATH_C = 2, /* Radio Path C */
1242 ODM_RF_PATH_D = 3, /* Radio Path D */
1253 /* ODM_RF_PATH_MAX, Max RF number 90 support */
1254 } ODM_RF_RADIO_PATH_E, *PODM_RF_RADIO_PATH_E;
1256 typedef enum _ODM_RF_CONTENT {
1257 odm_radioa_txt = 0x1000,
1258 odm_radiob_txt = 0x1001,
1259 odm_radioc_txt = 0x1002,
1260 odm_radiod_txt = 0x1003
1263 typedef enum _ODM_BB_Config_Type {
1266 CONFIG_BB_AGC_TAB_2G,
1267 CONFIG_BB_AGC_TAB_5G,
1268 CONFIG_BB_PHY_REG_PG,
1269 CONFIG_BB_PHY_REG_MP,
1270 CONFIG_BB_AGC_TAB_DIFF,
1271 } ODM_BB_Config_Type, *PODM_BB_Config_Type;
1273 typedef enum _ODM_RF_Config_Type {
1275 CONFIG_RF_TXPWR_LMT,
1276 } ODM_RF_Config_Type, *PODM_RF_Config_Type;
1278 typedef enum _ODM_FW_Config_Type {
1284 CONFIG_FW_AP_WoWLAN,
1286 } ODM_FW_Config_Type;
1289 typedef enum _RT_STATUS {
1294 RT_STATUS_INVALID_CONTEXT,
1295 RT_STATUS_INVALID_PARAMETER,
1296 RT_STATUS_NOT_SUPPORT,
1297 RT_STATUS_OS_API_FAILED,
1298 } RT_STATUS, *PRT_STATUS;
1304 /* include "odm_function.h" */
1306 /* 3 =========================================================== */
1308 /* 3 =========================================================== */
1310 /* Remove DIG by Yuchen */
1312 /* 3 =========================================================== */
1313 /* 3 AGC RX High Power Mode */
1314 /* 3 =========================================================== */
1315 #define LNA_Low_Gain_1 0x64
1316 #define LNA_Low_Gain_2 0x5A
1317 #define LNA_Low_Gain_3 0x58
1319 #define FA_RXHP_TH1 5000
1320 #define FA_RXHP_TH2 1500
1321 #define FA_RXHP_TH3 800
1322 #define FA_RXHP_TH4 600
1323 #define FA_RXHP_TH5 500
1325 /* 3 =========================================================== */
1327 /* 3 =========================================================== */
1329 /* 3 =========================================================== */
1330 /* 3 Dynamic Tx Power */
1331 /* 3 =========================================================== */
1332 /* Dynamic Tx Power Control Threshold */
1334 /* 3 =========================================================== */
1335 /* 3 Rate Adaptive */
1336 /* 3 =========================================================== */
1337 #define DM_RATR_STA_INIT 0
1338 #define DM_RATR_STA_HIGH 1
1339 #define DM_RATR_STA_MIDDLE 2
1340 #define DM_RATR_STA_LOW 3
1342 /* 3 =========================================================== */
1343 /* 3 BB Power Save */
1344 /* 3 =========================================================== */
1346 typedef enum tag_1R_CCA_Type_Definition {
1352 typedef enum tag_RF_Type_Definition {
1358 /* 3 =========================================================== */
1359 /* 3 Antenna Diversity */
1360 /* 3 =========================================================== */
1361 typedef enum tag_SW_Antenna_Switch_Definition {
1368 /* Maximal number of antenna detection mechanism needs to perform, added by Roger, 2011.12.28. */
1369 #define MAX_ANTENNA_DETECTION_CNT 10
1372 /* Extern Global Variables. */
1374 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE];
1375 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];
1376 extern u8 CCKSwingTable_Ch14[CCK_TABLE_SIZE][8];
1378 extern u32 OFDMSwingTable_New[OFDM_TABLE_SIZE];
1379 extern u8 CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8];
1380 extern u8 CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8];
1382 extern u32 TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE];
1385 /* check Sta pointer valid or not */
1387 #define IS_STA_VALID(pSta) (pSta)
1388 /* 20100514 Joseph: Add definition for antenna switching test after link. */
1389 /* This indicates two different the steps. */
1390 /* In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air. */
1391 /* In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK */
1392 /* with original RSSI to determine if it is necessary to switch antenna. */
1393 #define SWAW_STEP_PEAK 0
1394 #define SWAW_STEP_DETERMINE 1
1396 /* Remove DIG by yuchen */
1398 void ODM_SetAntenna(PDM_ODM_T pDM_Odm, u8 Antenna);
1401 /* Remove BB power saving by Yuchen */
1403 #define dm_CheckTXPowerTracking ODM_TXPowerTrackingCheck
1404 void ODM_TXPowerTrackingCheck(PDM_ODM_T pDM_Odm);
1406 bool ODM_RAStateCheck(
1413 #define dm_SWAW_RSSI_Check ODM_SwAntDivChkPerPktRssi
1414 void ODM_SwAntDivChkPerPktRssi(
1417 PODM_PHY_INFO_T pPhyInfo
1420 u32 ODM_Get_Rate_Bitmap(
1427 #if (BEAMFORMING_SUPPORT == 1)
1428 BEAMFORMING_CAP Beamforming_GetEntryBeamCapByMacId(PMGNT_INFO pMgntInfo, u8 MacId);
1431 void odm_TXPowerTrackingInit(PDM_ODM_T pDM_Odm);
1433 void ODM_DMInit(PDM_ODM_T pDM_Odm);
1435 void ODM_DMWatchdog(PDM_ODM_T pDM_Odm); /* For common use in the future */
1437 void ODM_CmnInfoInit(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, u32 Value);
1439 void ODM_CmnInfoHook(PDM_ODM_T pDM_Odm, ODM_CMNINFO_E CmnInfo, void *pValue);
1441 void ODM_CmnInfoPtrArrayHook(
1443 ODM_CMNINFO_E CmnInfo,
1448 void ODM_CmnInfoUpdate(PDM_ODM_T pDM_Odm, u32 CmnInfo, u64 Value);
1450 void ODM_InitAllTimers(PDM_ODM_T pDM_Odm);
1452 void ODM_CancelAllTimers(PDM_ODM_T pDM_Odm);
1454 void ODM_ReleaseAllTimers(PDM_ODM_T pDM_Odm);
1456 void ODM_AntselStatistics_88C(
1463 void ODM_DynamicARFBSelect(PDM_ODM_T pDM_Odm, u8 rate, bool Collision_State);