drivers/staging/rtl8723bs/hal/rtl8723b_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _RTL8723B_PHYCFG_C_
  16
  17 #include <drv_types.h>
  18 #include <rtw_debug.h>
  19 #include <rtl8723b_hal.h>
  20
  21
  22 /*---------------------------Define Local Constant---------------------------*/
  23 /* Channel switch:The size of command tables for switch channel*/
  24 #define MAX_PRECMD_CNT 16
  25 #define MAX_RFDEPENDCMD_CNT 16
  26 #define MAX_POSTCMD_CNT 16
  27
  28 #define MAX_DOZE_WAITING_TIMES_9x 64
  29
  30 /**
  31 * Function:     phy_CalculateBitShift
  32 *
  33 * OverView:     Get shifted position of the BitMask
  34 *
  35 * Input:
  36 *               u32     BitMask,
  37 *
  38 * Output:       none
  39 * Return:               u32     Return the shift bit bit position of the mask
  40 */
  41 static  u32 phy_CalculateBitShift(u32 BitMask)
  42 {
  43         u32 i;
  44
  45         for (i = 0; i <= 31; i++) {
  46                 if (((BitMask>>i) &  0x1) == 1)
  47                         break;
  48         }
  49         return i;
  50 }
  51
  52
  53 /**
  54 * Function:     PHY_QueryBBReg
  55 *
  56 * OverView:     Read "sepcific bits" from BB register
  57 *
  58 * Input:
  59 *               struct adapter *        Adapter,
  60 *               u32             RegAddr,        The target address to be readback
  61 *               u32             BitMask         The target bit position in the target address
  62 *                                                       to be readback
  63 * Output:       None
  64 * Return:               u32             Data            The readback register value
  65 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
  66 */
  67 u32 PHY_QueryBBReg_8723B(struct adapter *Adapter, u32 RegAddr, u32 BitMask)
  68 {
  69         u32 ReturnValue = 0, OriginalValue, BitShift;
  70
  71 #if (DISABLE_BB_RF == 1)
  72         return 0;
  73 #endif
  74
  75         /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask)); */
  76
  77         OriginalValue = rtw_read32(Adapter, RegAddr);
  78         BitShift = phy_CalculateBitShift(BitMask);
  79         ReturnValue = (OriginalValue & BitMask) >> BitShift;
  80
  81         return ReturnValue;
  82
  83 }
  84
  85
  86 /**
  87 * Function:     PHY_SetBBReg
  88 *
  89 * OverView:     Write "Specific bits" to BB register (page 8~)
  90 *
  91 * Input:
  92 *               struct adapter *        Adapter,
  93 *               u32             RegAddr,        The target address to be modified
  94 *               u32             BitMask         The target bit position in the target address
  95 *                                                               to be modified
  96 *               u32             Data            The new register value in the target bit position
  97 *                                                               of the target address
  98 *
  99 * Output:       None
 100 * Return:               None
 101 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 102 */
 103
 104 void PHY_SetBBReg_8723B(
 105         struct adapter *Adapter,
 106         u32 RegAddr,
 107         u32 BitMask,
 108         u32 Data
 109 )
 110 {
 111         /* u16 BBWaitCounter    = 0; */
 112         u32 OriginalValue, BitShift;
 113
 114 #if (DISABLE_BB_RF == 1)
 115         return;
 116 #endif
 117
 118         /* RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data)); */
 119
 120         if (BitMask != bMaskDWord) { /* if not "double word" write */
 121                 OriginalValue = rtw_read32(Adapter, RegAddr);
 122                 BitShift = phy_CalculateBitShift(BitMask);
 123                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
 124         }
 125
 126         rtw_write32(Adapter, RegAddr, Data);
 127
 128 }
 129
 130
 131 /*  */
 132 /*  2. RF register R/W API */
 133 /*  */
 134
 135 static u32 phy_RFSerialRead_8723B(
 136         struct adapter *Adapter, enum RF_PATH eRFPath, u32 Offset
 137 )
 138 {
 139         u32 retValue = 0;
 140         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 141         struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 142         u32 NewOffset;
 143         u32 tmplong2;
 144         u8 RfPiEnable = 0;
 145         u32 MaskforPhySet = 0;
 146         int i = 0;
 147
 148         /*  */
 149         /*  Make sure RF register offset is correct */
 150         /*  */
 151         Offset &= 0xff;
 152
 153         NewOffset = Offset;
 154
 155         if (eRFPath == RF_PATH_A) {
 156                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);;
 157                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  /* T65 RF */
 158                 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
 159         } else {
 160                 tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord);
 161                 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  /* T65 RF */
 162                 PHY_SetBBReg(Adapter, rFPGA0_XB_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2&(~bLSSIReadEdge));
 163         }
 164
 165         tmplong2 = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord);
 166         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 & (~bLSSIReadEdge));
 167         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2|MaskforPhySet, bMaskDWord, tmplong2 | bLSSIReadEdge);
 168
 169         udelay(10);
 170
 171         for (i = 0; i < 2; i++)
 172                 udelay(MAX_STALL_TIME);
 173         udelay(10);
 174
 175         if (eRFPath == RF_PATH_A)
 176                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1|MaskforPhySet, BIT8);
 177         else if (eRFPath == RF_PATH_B)
 178                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1|MaskforPhySet, BIT8);
 179
 180         if (RfPiEnable) {
 181                 /*  Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF */
 182                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi|MaskforPhySet, bLSSIReadBackData);
 183
 184                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-PI : 0x%x\n", retValue)); */
 185         } else {
 186                 /* Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF */
 187                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack|MaskforPhySet, bLSSIReadBackData);
 188
 189                 /* RT_DISP(FINIT, INIT_RF, ("Readback from RF-SI : 0x%x\n", retValue)); */
 190         }
 191         return retValue;
 192
 193 }
 194
 195 /**
 196 * Function:     phy_RFSerialWrite_8723B
 197 *
 198 * OverView:     Write data to RF register (page 8~)
 199 *
 200 * Input:
 201 *               struct adapter *        Adapter,
 202 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 203 *               u32             Offset,         The target address to be read
 204 *               u32             Data            The new register Data in the target bit position
 205 *                                                               of the target to be read
 206 *
 207 * Output:       None
 208 * Return:               None
 209 * Note:         Threre are three types of serial operations:
 210 *               1. Software serial write
 211 *               2. Hardware LSSI-Low Speed Serial Interface
 212 *               3. Hardware HSSI-High speed
 213 *               serial write. Driver need to implement (1) and (2).
 214 *               This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 215  *
 216  * Note:                  For RF8256 only
 217  *               The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 218  *               4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 219  *               to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 220  *               programming guide" for more details.
 221  *               Thus, we define a sub-finction for RTL8526 register address conversion
 222  *             ===========================================================
 223  *               Register Mode          RegCTL[1]               RegCTL[0]               Note
 224  *                                                      (Reg00[12])             (Reg00[10])
 225  *             ===========================================================
 226  *               Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 227  *             ------------------------------------------------------------------
 228  *               Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 229  *             ------------------------------------------------------------------
 230  *               Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 231  *             ------------------------------------------------------------------
 232  *
 233  *2008/09/02    MH      Add 92S RF definition
 234  *
 235  *
 236  *
 237 */
 238 static void phy_RFSerialWrite_8723B(
 239         struct adapter *Adapter,
 240         enum RF_PATH eRFPath,
 241         u32 Offset,
 242         u32 Data
 243 )
 244 {
 245         u32 DataAndAddr = 0;
 246         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 247         struct bb_register_def *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 248         u32 NewOffset;
 249
 250         Offset &= 0xff;
 251
 252         /*  */
 253         /*  Switch page for 8256 RF IC */
 254         /*  */
 255         NewOffset = Offset;
 256
 257         /*  */
 258         /*  Put write addr in [5:0]  and write data in [31:16] */
 259         /*  */
 260         /* DataAndAddr = (Data<<16) | (NewOffset&0x3f); */
 261         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       /*  T65 RF */
 262
 263         /*  */
 264         /*  Write Operation */
 265         /*  */
 266         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 267         /* RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]= 0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr)); */
 268
 269 }
 270
 271
 272 /**
 273 * Function:     PHY_QueryRFReg
 274 *
 275 * OverView:     Query "Specific bits" to RF register (page 8~)
 276 *
 277 * Input:
 278 *               struct adapter *        Adapter,
 279 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 280 *               u32             RegAddr,        The target address to be read
 281 *               u32             BitMask         The target bit position in the target address
 282 *                                                               to be read
 283 *
 284 * Output:       None
 285 * Return:               u32             Readback value
 286 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 287 */
 288 u32 PHY_QueryRFReg_8723B(
 289         struct adapter *Adapter,
 290         u8 eRFPath,
 291         u32 RegAddr,
 292         u32 BitMask
 293 )
 294 {
 295         u32 Original_Value, Readback_Value, BitShift;
 296
 297 #if (DISABLE_BB_RF == 1)
 298         return 0;
 299 #endif
 300
 301         Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
 302
 303         BitShift =  phy_CalculateBitShift(BitMask);
 304         Readback_Value = (Original_Value & BitMask) >> BitShift;
 305
 306         return Readback_Value;
 307 }
 308
 309 /**
 310 * Function:     PHY_SetRFReg
 311 *
 312 * OverView:     Write "Specific bits" to RF register (page 8~)
 313 *
 314 * Input:
 315 *               struct adapter *        Adapter,
 316 *               RF_PATH                 eRFPath,        Radio path of A/B/C/D
 317 *               u32             RegAddr,        The target address to be modified
 318 *               u32             BitMask         The target bit position in the target address
 319 *                                                               to be modified
 320 *               u32             Data            The new register Data in the target bit position
 321 *                                                               of the target address
 322 *
 323 * Output:       None
 324 * Return:               None
 325 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 326 */
 327 void PHY_SetRFReg_8723B(
 328         struct adapter *Adapter,
 329         u8 eRFPath,
 330         u32 RegAddr,
 331         u32 BitMask,
 332         u32 Data
 333 )
 334 {
 335         u32 Original_Value, BitShift;
 336
 337 #if (DISABLE_BB_RF == 1)
 338         return;
 339 #endif
 340
 341         /*  RF data is 12 bits only */
 342         if (BitMask != bRFRegOffsetMask) {
 343                 Original_Value = phy_RFSerialRead_8723B(Adapter, eRFPath, RegAddr);
 344                 BitShift =  phy_CalculateBitShift(BitMask);
 345                 Data = ((Original_Value & (~BitMask)) | (Data<<BitShift));
 346         }
 347
 348         phy_RFSerialWrite_8723B(Adapter, eRFPath, RegAddr, Data);
 349 }
 350
 351
 352 /*  */
 353 /*  3. Initial MAC/BB/RF config by reading MAC/BB/RF txt. */
 354 /*  */
 355
 356
 357 /*-----------------------------------------------------------------------------
 358  * Function:    PHY_MACConfig8192C
 359  *
 360  * Overview:    Condig MAC by header file or parameter file.
 361  *
 362  * Input:       NONE
 363  *
 364  * Output:      NONE
 365  *
 366  * Return:      NONE
 367  *
 368  * Revised History:
 369  *  When                Who             Remark
 370  *  08/12/2008  MHC             Create Version 0.
 371  *
 372  *---------------------------------------------------------------------------
 373  */
 374 s32 PHY_MACConfig8723B(struct adapter *Adapter)
 375 {
 376         int rtStatus = _SUCCESS;
 377         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
 378         s8 *pszMACRegFile;
 379         s8 sz8723MACRegFile[] = RTL8723B_PHY_MACREG;
 380
 381
 382         pszMACRegFile = sz8723MACRegFile;
 383
 384         /*  */
 385         /*  Config MAC */
 386         /*  */
 387         rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
 388         if (rtStatus == _FAIL) {
 389                 ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv);
 390                 rtStatus = _SUCCESS;
 391         }
 392
 393         return rtStatus;
 394 }
 395
 396 /**
 397 * Function:     phy_InitBBRFRegisterDefinition
 398 *
 399 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 400 *
 401 * Input:
 402 *               struct adapter *        Adapter,
 403 *
 404 * Output:       None
 405 * Return:               None
 406 * Note:         The initialization value is constant and it should never be changes
 407 */
 408 static void phy_InitBBRFRegisterDefinition(struct adapter *Adapter)
 409 {
 410         struct hal_com_data             *pHalData = GET_HAL_DATA(Adapter);
 411
 412         /*  RF Interface Sowrtware Control */
 413         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 LSBs if read 32-bit from 0x870 */
 414         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; /*  16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
 415
 416         /*  RF Interface Output (and Enable) */
 417         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x860 */
 418         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; /*  16 LSBs if read 32-bit from 0x864 */
 419
 420         /*  RF Interface (Output and)  Enable */
 421         pHalData->PHYRegDef[ODM_RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
 422         pHalData->PHYRegDef[ODM_RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; /*  16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
 423
 424         pHalData->PHYRegDef[ODM_RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; /* LSSI Parameter */
 425         pHalData->PHYRegDef[ODM_RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 426
 427         pHalData->PHYRegDef[ODM_RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  /* wire control parameter2 */
 428         pHalData->PHYRegDef[ODM_RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  /* wire control parameter2 */
 429
 430         /*  Tranceiver Readback LSSI/HSPI mode */
 431         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 432         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 433         pHalData->PHYRegDef[ODM_RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 434         pHalData->PHYRegDef[ODM_RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 435
 436 }
 437
 438 static int phy_BB8723b_Config_ParaFile(struct adapter *Adapter)
 439 {
 440         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 441         int rtStatus = _SUCCESS;
 442         u8 sz8723BBRegFile[] = RTL8723B_PHY_REG;
 443         u8 sz8723AGCTableFile[] = RTL8723B_AGC_TAB;
 444         u8 sz8723BBBRegPgFile[] = RTL8723B_PHY_REG_PG;
 445         u8 sz8723BBRegMpFile[] = RTL8723B_PHY_REG_MP;
 446         u8 sz8723BRFTxPwrLmtFile[] = RTL8723B_TXPWR_LMT;
 447         u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile = NULL, *pszRFTxPwrLmtFile = NULL;
 448
 449         pszBBRegFile = sz8723BBRegFile;
 450         pszAGCTableFile = sz8723AGCTableFile;
 451         pszBBRegPgFile = sz8723BBBRegPgFile;
 452         pszBBRegMpFile = sz8723BBRegMpFile;
 453         pszRFTxPwrLmtFile = sz8723BRFTxPwrLmtFile;
 454
 455         /*  Read Tx Power Limit File */
 456         PHY_InitTxPowerLimit(Adapter);
 457         if (
 458                 Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
 459                 (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
 460         ) {
 461                 if (PHY_ConfigRFWithPowerLimitTableParaFile(Adapter, pszRFTxPwrLmtFile) == _FAIL) {
 462                         if (HAL_STATUS_SUCCESS != ODM_ConfigRFWithHeaderFile(&pHalData->odmpriv, CONFIG_RF_TXPWR_LMT, (ODM_RF_RADIO_PATH_E)0))
 463                                 rtStatus = _FAIL;
 464                 }
 465
 466                 if (rtStatus != _SUCCESS) {
 467                         DBG_871X("%s():Read Tx power limit fail\n", __func__);
 468                         goto phy_BB8190_Config_ParaFile_Fail;
 469                 }
 470         }
 471
 472         /*  */
 473         /*  1. Read PHY_REG.TXT BB INIT!! */
 474         /*  */
 475         if (phy_ConfigBBWithParaFile(Adapter, pszBBRegFile, CONFIG_BB_PHY_REG) ==
 476                 _FAIL) {
 477                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
 478                         rtStatus = _FAIL;
 479         }
 480
 481         if (rtStatus != _SUCCESS) {
 482                 DBG_8192C("%s():Write BB Reg Fail!!", __func__);
 483                 goto phy_BB8190_Config_ParaFile_Fail;
 484         }
 485
 486         /*  If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt */
 487         PHY_InitTxPowerByRate(Adapter);
 488         if (
 489                 Adapter->registrypriv.RegEnableTxPowerByRate == 1 ||
 490                 (Adapter->registrypriv.RegEnableTxPowerByRate == 2 && pHalData->EEPROMRegulatory != 2)
 491         ) {
 492                 if (phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile) ==
 493                         _FAIL) {
 494                         if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG_PG))
 495                                 rtStatus = _FAIL;
 496                 }
 497
 498                 if (pHalData->odmpriv.PhyRegPgValueType == PHY_REG_PG_EXACT_VALUE)
 499                         PHY_TxPowerByRateConfiguration(Adapter);
 500
 501                 if (
 502                         Adapter->registrypriv.RegEnableTxPowerLimit == 1 ||
 503                         (Adapter->registrypriv.RegEnableTxPowerLimit == 2 && pHalData->EEPROMRegulatory == 1)
 504                 )
 505                         PHY_ConvertTxPowerLimitToPowerIndex(Adapter);
 506
 507                 if (rtStatus != _SUCCESS) {
 508                         DBG_8192C("%s():BB_PG Reg Fail!!\n", __func__);
 509                 }
 510         }
 511
 512         /*  */
 513         /*  2. Read BB AGC table Initialization */
 514         /*  */
 515         if (phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile,
 516                                      CONFIG_BB_AGC_TAB) == _FAIL) {
 517                 if (HAL_STATUS_SUCCESS != ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
 518                         rtStatus = _FAIL;
 519         }
 520
 521         if (rtStatus != _SUCCESS) {
 522                 DBG_8192C("%s():AGC Table Fail\n", __func__);
 523                 goto phy_BB8190_Config_ParaFile_Fail;
 524         }
 525
 526 phy_BB8190_Config_ParaFile_Fail:
 527
 528         return rtStatus;
 529 }
 530
 531
 532 int PHY_BBConfig8723B(struct adapter *Adapter)
 533 {
 534         int     rtStatus = _SUCCESS;
 535         struct hal_com_data     *pHalData = GET_HAL_DATA(Adapter);
 536         u32 RegVal;
 537         u8 CrystalCap;
 538
 539         phy_InitBBRFRegisterDefinition(Adapter);
 540
 541         /*  Enable BB and RF */
 542         RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
 543         rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
 544
 545         rtw_write32(Adapter, 0x948, 0x280);     /*  Others use Antenna S1 */
 546
 547         rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
 548
 549         msleep(1);
 550
 551         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x1, 0xfffff, 0x780);
 552
 553         rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
 554
 555         rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
 556
 557         /*  */
 558         /*  Config BB and AGC */
 559         /*  */
 560         rtStatus = phy_BB8723b_Config_ParaFile(Adapter);
 561
 562         /*  0x2C[23:18] = 0x2C[17:12] = CrystalCap */
 563         CrystalCap = pHalData->CrystalCap & 0x3F;
 564         PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
 565
 566         return rtStatus;
 567 }
 568
 569 static void phy_LCK_8723B(struct adapter *Adapter)
 570 {
 571         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFBE0);
 572         PHY_SetRFReg(Adapter, RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, 0x8C01);
 573         mdelay(200);
 574         PHY_SetRFReg(Adapter, RF_PATH_A, 0xB0, bRFRegOffsetMask, 0xDFFE0);
 575 }
 576
 577 int PHY_RFConfig8723B(struct adapter *Adapter)
 578 {
 579         int rtStatus = _SUCCESS;
 580
 581         /*  */
 582         /*  RF config */
 583         /*  */
 584         rtStatus = PHY_RF6052_Config8723B(Adapter);
 585
 586         phy_LCK_8723B(Adapter);
 587         /* PHY_BB8723B_Config_1T(Adapter); */
 588
 589         return rtStatus;
 590 }
 591
 592 /**************************************************************************************************************
 593  *   Description:
 594  *       The low-level interface to set TxAGC , called by both MP and Normal Driver.
 595  *
 596  *                                                                                    <20120830, Kordan>
 597  **************************************************************************************************************/
 598
 599 void PHY_SetTxPowerIndex_8723B(
 600         struct adapter *Adapter,
 601         u32 PowerIndex,
 602         u8 RFPath,
 603         u8 Rate
 604 )
 605 {
 606         if (RFPath == ODM_RF_PATH_A || RFPath == ODM_RF_PATH_B) {
 607                 switch (Rate) {
 608                 case MGN_1M:
 609                         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, PowerIndex);
 610                         break;
 611                 case MGN_2M:
 612                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte1, PowerIndex);
 613                         break;
 614                 case MGN_5_5M:
 615                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte2, PowerIndex);
 616                         break;
 617                 case MGN_11M:
 618                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, bMaskByte3, PowerIndex);
 619                         break;
 620
 621                 case MGN_6M:
 622                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte0, PowerIndex);
 623                         break;
 624                 case MGN_9M:
 625                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte1, PowerIndex);
 626                         break;
 627                 case MGN_12M:
 628                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte2, PowerIndex);
 629                         break;
 630                 case MGN_18M:
 631                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskByte3, PowerIndex);
 632                         break;
 633
 634                 case MGN_24M:
 635                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte0, PowerIndex);
 636                         break;
 637                 case MGN_36M:
 638                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte1, PowerIndex);
 639                         break;
 640                 case MGN_48M:
 641                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte2, PowerIndex);
 642                         break;
 643                 case MGN_54M:
 644                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskByte3, PowerIndex);
 645                         break;
 646
 647                 case MGN_MCS0:
 648                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte0, PowerIndex);
 649                         break;
 650                 case MGN_MCS1:
 651                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte1, PowerIndex);
 652                         break;
 653                 case MGN_MCS2:
 654                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte2, PowerIndex);
 655                         break;
 656                 case MGN_MCS3:
 657                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskByte3, PowerIndex);
 658                         break;
 659
 660                 case MGN_MCS4:
 661                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte0, PowerIndex);
 662                         break;
 663                 case MGN_MCS5:
 664                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte1, PowerIndex);
 665                         break;
 666                 case MGN_MCS6:
 667                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte2, PowerIndex);
 668                         break;
 669                 case MGN_MCS7:
 670                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskByte3, PowerIndex);
 671                         break;
 672
 673                 default:
 674                         DBG_871X("Invalid Rate!!\n");
 675                         break;
 676                 }
 677         } else {
 678                 RT_TRACE(_module_hal_init_c_, _drv_err_, ("Invalid RFPath!!\n"));
 679         }
 680 }
 681
 682 u8 PHY_GetTxPowerIndex_8723B(
 683         struct adapter *padapter,
 684         u8 RFPath,
 685         u8 Rate,
 686         enum CHANNEL_WIDTH BandWidth,
 687         u8 Channel
 688 )
 689 {
 690         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 691         s8 txPower = 0, powerDiffByRate = 0, limit = 0;
 692         bool bIn24G = false;
 693
 694         /* DBG_871X("===>%s\n", __func__); */
 695
 696         txPower = (s8) PHY_GetTxPowerIndexBase(padapter, RFPath, Rate, BandWidth, Channel, &bIn24G);
 697         powerDiffByRate = PHY_GetTxPowerByRate(padapter, BAND_ON_2_4G, ODM_RF_PATH_A, RF_1TX, Rate);
 698
 699         limit = PHY_GetTxPowerLimit(
 700                 padapter,
 701                 padapter->registrypriv.RegPwrTblSel,
 702                 (u8)(!bIn24G),
 703                 pHalData->CurrentChannelBW,
 704                 RFPath,
 705                 Rate,
 706                 pHalData->CurrentChannel
 707         );
 708
 709         powerDiffByRate = powerDiffByRate > limit ? limit : powerDiffByRate;
 710         txPower += powerDiffByRate;
 711
 712         txPower += PHY_GetTxPowerTrackingOffset(padapter, RFPath, Rate);
 713
 714         if (txPower > MAX_POWER_INDEX)
 715                 txPower = MAX_POWER_INDEX;
 716
 717         /* DBG_871X("Final Tx Power(RF-%c, Channel: %d) = %d(0x%X)\n", ((RFPath == 0)?'A':'B'), Channel, txPower, txPower)); */
 718         return (u8) txPower;
 719 }
 720
 721 void PHY_SetTxPowerLevel8723B(struct adapter *Adapter, u8 Channel)
 722 {
 723         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 724         PDM_ODM_T pDM_Odm = &pHalData->odmpriv;
 725         pFAT_T pDM_FatTable = &pDM_Odm->DM_FatTable;
 726         u8 RFPath = ODM_RF_PATH_A;
 727
 728         if (pHalData->AntDivCfg) {/*  antenna diversity Enable */
 729                 RFPath = ((pDM_FatTable->RxIdleAnt == MAIN_ANT) ? ODM_RF_PATH_A : ODM_RF_PATH_B);
 730         } else { /*  antenna diversity disable */
 731                 RFPath = pHalData->ant_path;
 732         }
 733
 734         RT_TRACE(_module_hal_init_c_, _drv_info_, ("==>PHY_SetTxPowerLevel8723B()\n"));
 735
 736         PHY_SetTxPowerLevelByPath(Adapter, Channel, RFPath);
 737
 738         RT_TRACE(_module_hal_init_c_, _drv_info_, ("<==PHY_SetTxPowerLevel8723B()\n"));
 739 }
 740
 741 void PHY_GetTxPowerLevel8723B(struct adapter *Adapter, s32 *powerlevel)
 742 {
 743 }
 744
 745 static void phy_SetRegBW_8723B(
 746         struct adapter *Adapter, enum CHANNEL_WIDTH CurrentBW
 747 )
 748 {
 749         u16 RegRfMod_BW, u2tmp = 0;
 750         RegRfMod_BW = rtw_read16(Adapter, REG_TRXPTCL_CTL_8723B);
 751
 752         switch (CurrentBW) {
 753         case CHANNEL_WIDTH_20:
 754                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (RegRfMod_BW & 0xFE7F)); /*  BIT 7 = 0, BIT 8 = 0 */
 755                 break;
 756
 757         case CHANNEL_WIDTH_40:
 758                 u2tmp = RegRfMod_BW | BIT7;
 759                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFEFF)); /*  BIT 7 = 1, BIT 8 = 0 */
 760                 break;
 761
 762         case CHANNEL_WIDTH_80:
 763                 u2tmp = RegRfMod_BW | BIT8;
 764                 rtw_write16(Adapter, REG_TRXPTCL_CTL_8723B, (u2tmp & 0xFF7F)); /*  BIT 7 = 0, BIT 8 = 1 */
 765                 break;
 766
 767         default:
 768                 DBG_871X("phy_PostSetBWMode8723B():     unknown Bandwidth: %#X\n", CurrentBW);
 769                 break;
 770         }
 771 }
 772
 773 static u8 phy_GetSecondaryChnl_8723B(struct adapter *Adapter)
 774 {
 775         u8 SCSettingOf40 = 0, SCSettingOf20 = 0;
 776         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 777
 778         RT_TRACE(
 779                 _module_hal_init_c_,
 780                 _drv_info_,
 781                 (
 782                         "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur80MhzPrimeSC %d, pHalData->nCur40MhzPrimeSC %d\n",
 783                         pHalData->CurrentChannelBW,
 784                         pHalData->nCur80MhzPrimeSC,
 785                         pHalData->nCur40MhzPrimeSC
 786                 )
 787         );
 788         if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_80) {
 789                 if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 790                         SCSettingOf40 = VHT_DATA_SC_40_LOWER_OF_80MHZ;
 791                 else if (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 792                         SCSettingOf40 = VHT_DATA_SC_40_UPPER_OF_80MHZ;
 793                 else
 794                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 795
 796                 if (
 797                         (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
 798                         (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 799                 )
 800                         SCSettingOf20 = VHT_DATA_SC_20_LOWEST_OF_80MHZ;
 801                 else if (
 802                         (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
 803                         (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 804                 )
 805                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
 806                 else if (
 807                         (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) &&
 808                         (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 809                 )
 810                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
 811                 else if (
 812                         (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER) &&
 813                         (pHalData->nCur80MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 814                 )
 815                         SCSettingOf20 = VHT_DATA_SC_20_UPPERST_OF_80MHZ;
 816                 else
 817                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 818         } else if (pHalData->CurrentChannelBW == CHANNEL_WIDTH_40) {
 819                 RT_TRACE(
 820                         _module_hal_init_c_,
 821                         _drv_info_,
 822                         (
 823                                 "SCMapping: VHT Case: pHalData->CurrentChannelBW %d, pHalData->nCur40MhzPrimeSC %d\n",
 824                                 pHalData->CurrentChannelBW,
 825                                 pHalData->nCur40MhzPrimeSC
 826                         )
 827                 );
 828
 829                 if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_UPPER)
 830                         SCSettingOf20 = VHT_DATA_SC_20_UPPER_OF_80MHZ;
 831                 else if (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER)
 832                         SCSettingOf20 = VHT_DATA_SC_20_LOWER_OF_80MHZ;
 833                 else
 834                         RT_TRACE(_module_hal_init_c_, _drv_err_, ("SCMapping: Not Correct Primary40MHz Setting\n"));
 835         }
 836
 837         RT_TRACE(_module_hal_init_c_, _drv_info_, ("SCMapping: SC Value %x\n", ((SCSettingOf40 << 4) | SCSettingOf20)));
 838         return  ((SCSettingOf40 << 4) | SCSettingOf20);
 839 }
 840
 841 static void phy_PostSetBwMode8723B(struct adapter *Adapter)
 842 {
 843         u8 SubChnlNum = 0;
 844         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 845
 846
 847         /* 3 Set Reg668 Reg440 BW */
 848         phy_SetRegBW_8723B(Adapter, pHalData->CurrentChannelBW);
 849
 850         /* 3 Set Reg483 */
 851         SubChnlNum = phy_GetSecondaryChnl_8723B(Adapter);
 852         rtw_write8(Adapter, REG_DATA_SC_8723B, SubChnlNum);
 853
 854         /* 3 */
 855         /* 3<2>Set PHY related register */
 856         /* 3 */
 857         switch (pHalData->CurrentChannelBW) {
 858         /* 20 MHz channel*/
 859         case CHANNEL_WIDTH_20:
 860                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
 861
 862                 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
 863
 864 /*                      PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1); */
 865
 866                 PHY_SetBBReg(Adapter, rOFDM0_TxPseudoNoiseWgt, (BIT31|BIT30), 0x0);
 867                 break;
 868
 869         /* 40 MHz channel*/
 870         case CHANNEL_WIDTH_40:
 871                 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
 872
 873                 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
 874
 875                 /*  Set Control channel to upper or lower. These settings are required only for 40MHz */
 876                 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
 877
 878                 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
 879
 880 /* PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0); */
 881
 882                 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
 883
 884                 break;
 885
 886         default:
 887                 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("phy_SetBWMode8723B(): unknown Bandwidth: %#X\n"\
 888                                         , pHalData->CurrentChannelBW));*/
 889                 break;
 890         }
 891
 892         /* 3<3>Set RF related register */
 893         PHY_RF6052SetBandwidth8723B(Adapter, pHalData->CurrentChannelBW);
 894 }
 895
 896 static void phy_SwChnl8723B(struct adapter *padapter)
 897 {
 898         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 899         u8 channelToSW = pHalData->CurrentChannel;
 900
 901         if (pHalData->rf_chip == RF_PSEUDO_11N) {
 902                 /* RT_TRACE(COMP_MLME, DBG_LOUD, ("phy_SwChnl8723B: return for PSEUDO\n")); */
 903                 return;
 904         }
 905         pHalData->RfRegChnlVal[0] = ((pHalData->RfRegChnlVal[0] & 0xfffff00) | channelToSW);
 906         PHY_SetRFReg(padapter, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
 907         PHY_SetRFReg(padapter, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, pHalData->RfRegChnlVal[0]);
 908
 909         DBG_8192C("===>phy_SwChnl8723B: Channel = %d\n", channelToSW);
 910 }
 911
 912 static void phy_SwChnlAndSetBwMode8723B(struct adapter *Adapter)
 913 {
 914         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 915
 916         /* RT_TRACE(COMP_SCAN, DBG_LOUD, ("phy_SwChnlAndSetBwMode8723B(): bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW)); */
 917         if (Adapter->bNotifyChannelChange) {
 918                 DBG_871X("[%s] bSwChnl =%d, ch =%d, bSetChnlBW =%d, bw =%d\n",
 919                         __func__,
 920                         pHalData->bSwChnl,
 921                         pHalData->CurrentChannel,
 922                         pHalData->bSetChnlBW,
 923                         pHalData->CurrentChannelBW);
 924         }
 925
 926         if (Adapter->bDriverStopped || Adapter->bSurpriseRemoved)
 927                 return;
 928
 929         if (pHalData->bSwChnl) {
 930                 phy_SwChnl8723B(Adapter);
 931                 pHalData->bSwChnl = false;
 932         }
 933
 934         if (pHalData->bSetChnlBW) {
 935                 phy_PostSetBwMode8723B(Adapter);
 936                 pHalData->bSetChnlBW = false;
 937         }
 938
 939         PHY_SetTxPowerLevel8723B(Adapter, pHalData->CurrentChannel);
 940 }
 941
 942 static void PHY_HandleSwChnlAndSetBW8723B(
 943         struct adapter *Adapter,
 944         bool bSwitchChannel,
 945         bool bSetBandWidth,
 946         u8 ChannelNum,
 947         enum CHANNEL_WIDTH ChnlWidth,
 948         enum EXTCHNL_OFFSET ExtChnlOffsetOf40MHz,
 949         enum EXTCHNL_OFFSET ExtChnlOffsetOf80MHz,
 950         u8 CenterFrequencyIndex1
 951 )
 952 {
 953         /* static bool          bInitialzed = false; */
 954         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 955         u8 tmpChannel = pHalData->CurrentChannel;
 956         enum CHANNEL_WIDTH tmpBW = pHalData->CurrentChannelBW;
 957         u8 tmpnCur40MhzPrimeSC = pHalData->nCur40MhzPrimeSC;
 958         u8 tmpnCur80MhzPrimeSC = pHalData->nCur80MhzPrimeSC;
 959         u8 tmpCenterFrequencyIndex1 = pHalData->CurrentCenterFrequencyIndex1;
 960
 961         /* DBG_871X("=> PHY_HandleSwChnlAndSetBW8812: bSwitchChannel %d, bSetBandWidth %d\n", bSwitchChannel, bSetBandWidth); */
 962
 963         /* check is swchnl or setbw */
 964         if (!bSwitchChannel && !bSetBandWidth) {
 965                 DBG_871X("PHY_HandleSwChnlAndSetBW8812:  not switch channel and not set bandwidth\n");
 966                 return;
 967         }
 968
 969         /* skip change for channel or bandwidth is the same */
 970         if (bSwitchChannel) {
 971                 /* if (pHalData->CurrentChannel != ChannelNum) */
 972                 {
 973                         if (HAL_IsLegalChannel(Adapter, ChannelNum))
 974                                 pHalData->bSwChnl = true;
 975                 }
 976         }
 977
 978         if (bSetBandWidth)
 979                 pHalData->bSetChnlBW = true;
 980
 981         if (!pHalData->bSetChnlBW && !pHalData->bSwChnl) {
 982                 /* DBG_871X("<= PHY_HandleSwChnlAndSetBW8812: bSwChnl %d, bSetChnlBW %d\n", pHalData->bSwChnl, pHalData->bSetChnlBW); */
 983                 return;
 984         }
 985
 986
 987         if (pHalData->bSwChnl) {
 988                 pHalData->CurrentChannel = ChannelNum;
 989                 pHalData->CurrentCenterFrequencyIndex1 = ChannelNum;
 990         }
 991
 992
 993         if (pHalData->bSetChnlBW) {
 994                 pHalData->CurrentChannelBW = ChnlWidth;
 995                 pHalData->nCur40MhzPrimeSC = ExtChnlOffsetOf40MHz;
 996                 pHalData->nCur80MhzPrimeSC = ExtChnlOffsetOf80MHz;
 997                 pHalData->CurrentCenterFrequencyIndex1 = CenterFrequencyIndex1;
 998         }
 999
1000         /* Switch workitem or set timer to do switch channel or setbandwidth operation */
1001         if ((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved)) {
1002                 phy_SwChnlAndSetBwMode8723B(Adapter);
1003         } else {
1004                 if (pHalData->bSwChnl) {
1005                         pHalData->CurrentChannel = tmpChannel;
1006                         pHalData->CurrentCenterFrequencyIndex1 = tmpChannel;
1007                 }
1008
1009                 if (pHalData->bSetChnlBW) {
1010                         pHalData->CurrentChannelBW = tmpBW;
1011                         pHalData->nCur40MhzPrimeSC = tmpnCur40MhzPrimeSC;
1012                         pHalData->nCur80MhzPrimeSC = tmpnCur80MhzPrimeSC;
1013                         pHalData->CurrentCenterFrequencyIndex1 = tmpCenterFrequencyIndex1;
1014                 }
1015         }
1016 }
1017
1018 void PHY_SetBWMode8723B(
1019         struct adapter *Adapter,
1020         enum CHANNEL_WIDTH Bandwidth, /*  20M or 40M */
1021         unsigned char Offset /*  Upper, Lower, or Don't care */
1022 )
1023 {
1024         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1025
1026         PHY_HandleSwChnlAndSetBW8723B(Adapter, false, true, pHalData->CurrentChannel, Bandwidth, Offset, Offset, pHalData->CurrentChannel);
1027 }
1028
1029 /*  Call after initialization */
1030 void PHY_SwChnl8723B(struct adapter *Adapter, u8 channel)
1031 {
1032         PHY_HandleSwChnlAndSetBW8723B(Adapter, true, false, channel, 0, 0, 0, channel);
1033 }
1034
1035 void PHY_SetSwChnlBWMode8723B(
1036         struct adapter *Adapter,
1037         u8 channel,
1038         enum CHANNEL_WIDTH Bandwidth,
1039         u8 Offset40,
1040         u8 Offset80
1041 )
1042 {
1043         /* DBG_871X("%s() ===>\n", __func__); */
1044
1045         PHY_HandleSwChnlAndSetBW8723B(Adapter, true, true, channel, Bandwidth, Offset40, Offset80, channel);
1046
1047         /* DBG_871X("<==%s()\n", __func__); */
1048 }