drivers/staging/rtl8723bs/hal/sdio_halinit.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  ******************************************************************************/
  15 #define _SDIO_HALINIT_C_
  16
  17 #include <drv_types.h>
  18 #include <rtw_debug.h>
  19 #include <rtl8723b_hal.h>
  20
  21 #include "hal_com_h2c.h"
  22 /*
  23  * Description:
  24  *Call power on sequence to enable card
  25  *
  26  * Return:
  27  *_SUCCESS      enable success
  28  *_FAIL         enable fail
  29  */
  30 static u8 CardEnable(struct adapter *padapter)
  31 {
  32         u8 bMacPwrCtrlOn;
  33         u8 ret = _FAIL;
  34
  35
  36         rtw_hal_get_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  37         if (bMacPwrCtrlOn == false) {
  38                 /*  RSV_CTRL 0x1C[7:0] = 0x00 */
  39                 /*  unlock ISO/CLK/Power control register */
  40                 rtw_write8(padapter, REG_RSV_CTRL, 0x0);
  41
  42                 ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_enable_flow);
  43                 if (ret == _SUCCESS) {
  44                         u8 bMacPwrCtrlOn = true;
  45                         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
  46                 }
  47         } else
  48                 ret = _SUCCESS;
  49
  50         return ret;
  51 }
  52
  53 #ifdef CONFIG_GPIO_WAKEUP
  54 /* we set it high under init and fw will */
  55 /* give us Low Pulse when host wake up */
  56 void HostWakeUpGpioClear(struct adapter *Adapter)
  57 {
  58         u32 value32;
  59
  60         value32 = rtw_read32(Adapter, REG_GPIO_PIN_CTRL_2);
  61
  62         /* set GPIO 12 1 */
  63         value32 |= BIT(12);/* 4+8 */
  64         /* GPIO 12 out put */
  65         value32 |= BIT(20);/* 4+16 */
  66
  67         rtw_write32(Adapter, REG_GPIO_PIN_CTRL_2, value32);
  68 } /* HostWakeUpGpioClear */
  69
  70 void HalSetOutPutGPIO(struct adapter *padapter, u8 index, u8 OutPutValue)
  71 {
  72         if (index <= 7) {
  73                 /* config GPIO mode */
  74                 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 3) & ~BIT(index));
  75
  76                 /* config GPIO Sel */
  77                 /* 0: input */
  78                 /* 1: output */
  79                 rtw_write8(padapter, REG_GPIO_PIN_CTRL + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 2) | BIT(index));
  80
  81                 /* set output value */
  82                 if (OutPutValue)
  83                         rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) | BIT(index));
  84                 else
  85                         rtw_write8(padapter, REG_GPIO_PIN_CTRL + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL + 1) & ~BIT(index));
  86         } else {
  87                 /* 88C Series: */
  88                 /* index: 11~8 transform to 3~0 */
  89                 /* 8723 Series: */
  90                 /* index: 12~8 transform to 4~0 */
  91                 index -= 8;
  92
  93                 /* config GPIO mode */
  94                 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 3, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 3) & ~BIT(index));
  95
  96                 /* config GPIO Sel */
  97                 /* 0: input */
  98                 /* 1: output */
  99                 rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 2, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 2) | BIT(index));
 100
 101                 /* set output value */
 102                 if (OutPutValue)
 103                         rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) | BIT(index));
 104                 else
 105                         rtw_write8(padapter, REG_GPIO_PIN_CTRL_2 + 1, rtw_read8(padapter, REG_GPIO_PIN_CTRL_2 + 1) & ~BIT(index));
 106         }
 107 }
 108 #endif
 109
 110 static
 111 u8 _InitPowerOn_8723BS(struct adapter *padapter)
 112 {
 113         u8 value8;
 114         u16 value16;
 115         u32 value32;
 116         u8 ret;
 117 /*      u8 bMacPwrCtrlOn; */
 118
 119
 120         /*  all of these MUST be configured before power on */
 121 #ifdef CONFIG_EXT_CLK
 122         /*  Use external crystal(XTAL) */
 123         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B+2);
 124         value8 |=  BIT(7);
 125         rtw_write8(padapter, REG_PAD_CTRL1_8723B+2, value8);
 126
 127         /*  CLK_REQ High active or Low Active */
 128         /*  Request GPIO polarity: */
 129         /*  0: low active */
 130         /*  1: high active */
 131         value8 = rtw_read8(padapter, REG_MULTI_FUNC_CTRL+1);
 132         value8 |= BIT(5);
 133         rtw_write8(padapter, REG_MULTI_FUNC_CTRL+1, value8);
 134 #endif /*  CONFIG_EXT_CLK */
 135
 136         /*  only cmd52 can be used before power on(card enable) */
 137         ret = CardEnable(padapter);
 138         if (ret == false) {
 139                 RT_TRACE(
 140                         _module_hci_hal_init_c_,
 141                         _drv_emerg_,
 142                         ("%s: run power on flow fail\n", __func__)
 143                 );
 144                 return _FAIL;
 145         }
 146
 147         /*  Radio-Off Pin Trigger */
 148         value8 = rtw_read8(padapter, REG_GPIO_INTM+1);
 149         value8 |= BIT(1); /*  Enable falling edge triggering interrupt */
 150         rtw_write8(padapter, REG_GPIO_INTM+1, value8);
 151         value8 = rtw_read8(padapter, REG_GPIO_IO_SEL_2+1);
 152         value8 |= BIT(1);
 153         rtw_write8(padapter, REG_GPIO_IO_SEL_2+1, value8);
 154
 155         /*  Enable power down and GPIO interrupt */
 156         value16 = rtw_read16(padapter, REG_APS_FSMCO);
 157         value16 |= EnPDN; /*  Enable HW power down and RF on */
 158         rtw_write16(padapter, REG_APS_FSMCO, value16);
 159
 160         /*  Enable CMD53 R/W Operation */
 161 /*      bMacPwrCtrlOn = true; */
 162 /*      rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn); */
 163
 164         rtw_write8(padapter, REG_CR, 0x00);
 165         /*  Enable MAC DMA/WMAC/SCHEDULE/SEC block */
 166         value16 = rtw_read16(padapter, REG_CR);
 167         value16 |= (
 168                 HCI_TXDMA_EN |
 169                 HCI_RXDMA_EN |
 170                 TXDMA_EN |
 171                 RXDMA_EN |
 172                 PROTOCOL_EN |
 173                 SCHEDULE_EN |
 174                 ENSEC |
 175                 CALTMR_EN
 176         );
 177         rtw_write16(padapter, REG_CR, value16);
 178
 179         rtw_btcoex_PowerOnSetting(padapter);
 180
 181         /*  external switch to S1 */
 182         /*  0x38[11] = 0x1 */
 183         /*  0x4c[23] = 0x1 */
 184         /*  0x64[0] = 0 */
 185         value16 = rtw_read16(padapter, REG_PWR_DATA);
 186         /*  Switch the control of EESK, EECS to RFC for DPDT or Antenna switch */
 187         value16 |= BIT(11); /*  BIT_EEPRPAD_RFE_CTRL_EN */
 188         rtw_write16(padapter, REG_PWR_DATA, value16);
 189 /*      DBG_8192C("%s: REG_PWR_DATA(0x%x) = 0x%04X\n", __func__, REG_PWR_DATA, rtw_read16(padapter, REG_PWR_DATA)); */
 190
 191         value32 = rtw_read32(padapter, REG_LEDCFG0);
 192         value32 |= BIT(23); /*  DPDT_SEL_EN, 1 for SW control */
 193         rtw_write32(padapter, REG_LEDCFG0, value32);
 194 /*      DBG_8192C("%s: REG_LEDCFG0(0x%x) = 0x%08X\n", __func__, REG_LEDCFG0, rtw_read32(padapter, REG_LEDCFG0)); */
 195
 196         value8 = rtw_read8(padapter, REG_PAD_CTRL1_8723B);
 197         value8 &= ~BIT(0); /*  BIT_SW_DPDT_SEL_DATA, DPDT_SEL default configuration */
 198         rtw_write8(padapter, REG_PAD_CTRL1_8723B, value8);
 199 /*      DBG_8192C("%s: REG_PAD_CTRL1(0x%x) = 0x%02X\n", __func__, REG_PAD_CTRL1_8723B, rtw_read8(padapter, REG_PAD_CTRL1_8723B)); */
 200
 201 #ifdef CONFIG_GPIO_WAKEUP
 202         HostWakeUpGpioClear(padapter);
 203 #endif
 204
 205         return _SUCCESS;
 206 }
 207
 208 /* Tx Page FIFO threshold */
 209 static void _init_available_page_threshold(struct adapter *padapter, u8 numHQ, u8 numNQ, u8 numLQ, u8 numPubQ)
 210 {
 211         u16 HQ_threshold, NQ_threshold, LQ_threshold;
 212
 213         HQ_threshold = (numPubQ + numHQ + 1) >> 1;
 214         HQ_threshold |= (HQ_threshold<<8);
 215
 216         NQ_threshold = (numPubQ + numNQ + 1) >> 1;
 217         NQ_threshold |= (NQ_threshold<<8);
 218
 219         LQ_threshold = (numPubQ + numLQ + 1) >> 1;
 220         LQ_threshold |= (LQ_threshold<<8);
 221
 222         rtw_write16(padapter, 0x218, HQ_threshold);
 223         rtw_write16(padapter, 0x21A, NQ_threshold);
 224         rtw_write16(padapter, 0x21C, LQ_threshold);
 225         DBG_8192C("%s(): Enable Tx FIFO Page Threshold H:0x%x, N:0x%x, L:0x%x\n", __func__, HQ_threshold, NQ_threshold, LQ_threshold);
 226 }
 227
 228 static void _InitQueueReservedPage(struct adapter *padapter)
 229 {
 230         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 231         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 232         u32 numHQ = 0;
 233         u32 numLQ = 0;
 234         u32 numNQ = 0;
 235         u32 numPubQ;
 236         u32 value32;
 237         u8 value8;
 238         bool bWiFiConfig        = pregistrypriv->wifi_spec;
 239
 240         if (pHalData->OutEpQueueSel & TX_SELE_HQ)
 241                 numHQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_HPQ_8723B : NORMAL_PAGE_NUM_HPQ_8723B;
 242
 243         if (pHalData->OutEpQueueSel & TX_SELE_LQ)
 244                 numLQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_LPQ_8723B : NORMAL_PAGE_NUM_LPQ_8723B;
 245
 246         /*  NOTE: This step shall be proceed before writting REG_RQPN. */
 247         if (pHalData->OutEpQueueSel & TX_SELE_NQ)
 248                 numNQ = bWiFiConfig ? WMM_NORMAL_PAGE_NUM_NPQ_8723B : NORMAL_PAGE_NUM_NPQ_8723B;
 249
 250         numPubQ = TX_TOTAL_PAGE_NUMBER_8723B - numHQ - numLQ - numNQ;
 251
 252         value8 = (u8)_NPQ(numNQ);
 253         rtw_write8(padapter, REG_RQPN_NPQ, value8);
 254
 255         /*  TX DMA */
 256         value32 = _HPQ(numHQ) | _LPQ(numLQ) | _PUBQ(numPubQ) | LD_RQPN;
 257         rtw_write32(padapter, REG_RQPN, value32);
 258
 259         rtw_hal_set_sdio_tx_max_length(padapter, numHQ, numNQ, numLQ, numPubQ);
 260
 261         _init_available_page_threshold(padapter, numHQ, numNQ, numLQ, numPubQ);
 262 }
 263
 264 static void _InitTxBufferBoundary(struct adapter *padapter)
 265 {
 266         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 267
 268         /* u16 txdmactrl; */
 269         u8 txpktbuf_bndy;
 270
 271         if (!pregistrypriv->wifi_spec) {
 272                 txpktbuf_bndy = TX_PAGE_BOUNDARY_8723B;
 273         } else {
 274                 /* for WMM */
 275                 txpktbuf_bndy = WMM_NORMAL_TX_PAGE_BOUNDARY_8723B;
 276         }
 277
 278         rtw_write8(padapter, REG_TXPKTBUF_BCNQ_BDNY_8723B, txpktbuf_bndy);
 279         rtw_write8(padapter, REG_TXPKTBUF_MGQ_BDNY_8723B, txpktbuf_bndy);
 280         rtw_write8(padapter, REG_TXPKTBUF_WMAC_LBK_BF_HD_8723B, txpktbuf_bndy);
 281         rtw_write8(padapter, REG_TRXFF_BNDY, txpktbuf_bndy);
 282         rtw_write8(padapter, REG_TDECTRL+1, txpktbuf_bndy);
 283 }
 284
 285 static void _InitNormalChipRegPriority(
 286         struct adapter *Adapter,
 287         u16 beQ,
 288         u16 bkQ,
 289         u16 viQ,
 290         u16 voQ,
 291         u16 mgtQ,
 292         u16 hiQ
 293 )
 294 {
 295         u16 value16 = (rtw_read16(Adapter, REG_TRXDMA_CTRL) & 0x7);
 296
 297         value16 |=
 298                 _TXDMA_BEQ_MAP(beQ)  |
 299                 _TXDMA_BKQ_MAP(bkQ)  |
 300                 _TXDMA_VIQ_MAP(viQ)  |
 301                 _TXDMA_VOQ_MAP(voQ)  |
 302                 _TXDMA_MGQ_MAP(mgtQ) |
 303                 _TXDMA_HIQ_MAP(hiQ);
 304
 305         rtw_write16(Adapter, REG_TRXDMA_CTRL, value16);
 306 }
 307
 308 static void _InitNormalChipOneOutEpPriority(struct adapter *Adapter)
 309 {
 310         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 311
 312         u16 value = 0;
 313         switch (pHalData->OutEpQueueSel) {
 314         case TX_SELE_HQ:
 315                 value = QUEUE_HIGH;
 316                 break;
 317         case TX_SELE_LQ:
 318                 value = QUEUE_LOW;
 319                 break;
 320         case TX_SELE_NQ:
 321                 value = QUEUE_NORMAL;
 322                 break;
 323         default:
 324                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 325                 break;
 326         }
 327
 328         _InitNormalChipRegPriority(
 329                 Adapter, value, value, value, value, value, value
 330         );
 331
 332 }
 333
 334 static void _InitNormalChipTwoOutEpPriority(struct adapter *Adapter)
 335 {
 336         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 337         struct registry_priv *pregistrypriv = &Adapter->registrypriv;
 338         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 339
 340
 341         u16 valueHi = 0;
 342         u16 valueLow = 0;
 343
 344         switch (pHalData->OutEpQueueSel) {
 345         case (TX_SELE_HQ | TX_SELE_LQ):
 346                 valueHi = QUEUE_HIGH;
 347                 valueLow = QUEUE_LOW;
 348                 break;
 349         case (TX_SELE_NQ | TX_SELE_LQ):
 350                 valueHi = QUEUE_NORMAL;
 351                 valueLow = QUEUE_LOW;
 352                 break;
 353         case (TX_SELE_HQ | TX_SELE_NQ):
 354                 valueHi = QUEUE_HIGH;
 355                 valueLow = QUEUE_NORMAL;
 356                 break;
 357         default:
 358                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 359                 break;
 360         }
 361
 362         if (!pregistrypriv->wifi_spec) {
 363                 beQ = valueLow;
 364                 bkQ = valueLow;
 365                 viQ = valueHi;
 366                 voQ = valueHi;
 367                 mgtQ = valueHi;
 368                 hiQ = valueHi;
 369         } else {
 370                 /* for WMM , CONFIG_OUT_EP_WIFI_MODE */
 371                 beQ = valueLow;
 372                 bkQ = valueHi;
 373                 viQ = valueHi;
 374                 voQ = valueLow;
 375                 mgtQ = valueHi;
 376                 hiQ = valueHi;
 377         }
 378
 379         _InitNormalChipRegPriority(Adapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 380
 381 }
 382
 383 static void _InitNormalChipThreeOutEpPriority(struct adapter *padapter)
 384 {
 385         struct registry_priv *pregistrypriv = &padapter->registrypriv;
 386         u16 beQ, bkQ, viQ, voQ, mgtQ, hiQ;
 387
 388         if (!pregistrypriv->wifi_spec) {
 389                 /*  typical setting */
 390                 beQ = QUEUE_LOW;
 391                 bkQ = QUEUE_LOW;
 392                 viQ = QUEUE_NORMAL;
 393                 voQ = QUEUE_HIGH;
 394                 mgtQ = QUEUE_HIGH;
 395                 hiQ = QUEUE_HIGH;
 396         } else {
 397                 /*  for WMM */
 398                 beQ = QUEUE_LOW;
 399                 bkQ = QUEUE_NORMAL;
 400                 viQ = QUEUE_NORMAL;
 401                 voQ = QUEUE_HIGH;
 402                 mgtQ = QUEUE_HIGH;
 403                 hiQ = QUEUE_HIGH;
 404         }
 405         _InitNormalChipRegPriority(padapter, beQ, bkQ, viQ, voQ, mgtQ, hiQ);
 406 }
 407
 408 static void _InitNormalChipQueuePriority(struct adapter *Adapter)
 409 {
 410         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 411
 412         switch (pHalData->OutEpNumber) {
 413         case 1:
 414                 _InitNormalChipOneOutEpPriority(Adapter);
 415                 break;
 416         case 2:
 417                 _InitNormalChipTwoOutEpPriority(Adapter);
 418                 break;
 419         case 3:
 420                 _InitNormalChipThreeOutEpPriority(Adapter);
 421                 break;
 422         default:
 423                 /* RT_ASSERT(false, ("Shall not reach here!\n")); */
 424                 break;
 425         }
 426
 427
 428 }
 429
 430 static void _InitQueuePriority(struct adapter *padapter)
 431 {
 432         _InitNormalChipQueuePriority(padapter);
 433 }
 434
 435 static void _InitPageBoundary(struct adapter *padapter)
 436 {
 437         /*  RX Page Boundary */
 438         u16 rxff_bndy = RX_DMA_BOUNDARY_8723B;
 439
 440         rtw_write16(padapter, (REG_TRXFF_BNDY + 2), rxff_bndy);
 441 }
 442
 443 static void _InitTransferPageSize(struct adapter *padapter)
 444 {
 445         /*  Tx page size is always 128. */
 446
 447         u8 value8;
 448         value8 = _PSRX(PBP_128) | _PSTX(PBP_128);
 449         rtw_write8(padapter, REG_PBP, value8);
 450 }
 451
 452 static void _InitDriverInfoSize(struct adapter *padapter, u8 drvInfoSize)
 453 {
 454         rtw_write8(padapter, REG_RX_DRVINFO_SZ, drvInfoSize);
 455 }
 456
 457 static void _InitNetworkType(struct adapter *padapter)
 458 {
 459         u32 value32;
 460
 461         value32 = rtw_read32(padapter, REG_CR);
 462
 463         /*  TODO: use the other function to set network type */
 464 /*      value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AD_HOC); */
 465         value32 = (value32 & ~MASK_NETTYPE) | _NETTYPE(NT_LINK_AP);
 466
 467         rtw_write32(padapter, REG_CR, value32);
 468 }
 469
 470 static void _InitWMACSetting(struct adapter *padapter)
 471 {
 472         struct hal_com_data *pHalData;
 473         u16 value16;
 474
 475
 476         pHalData = GET_HAL_DATA(padapter);
 477
 478         pHalData->ReceiveConfig = 0;
 479         pHalData->ReceiveConfig |= RCR_APM | RCR_AM | RCR_AB;
 480         pHalData->ReceiveConfig |= RCR_CBSSID_DATA | RCR_CBSSID_BCN | RCR_AMF;
 481         pHalData->ReceiveConfig |= RCR_HTC_LOC_CTRL;
 482         pHalData->ReceiveConfig |= RCR_APP_PHYST_RXFF | RCR_APP_ICV | RCR_APP_MIC;
 483         rtw_write32(padapter, REG_RCR, pHalData->ReceiveConfig);
 484
 485         /*  Accept all multicast address */
 486         rtw_write32(padapter, REG_MAR, 0xFFFFFFFF);
 487         rtw_write32(padapter, REG_MAR + 4, 0xFFFFFFFF);
 488
 489         /*  Accept all data frames */
 490         value16 = 0xFFFF;
 491         rtw_write16(padapter, REG_RXFLTMAP2, value16);
 492
 493         /*  2010.09.08 hpfan */
 494         /*  Since ADF is removed from RCR, ps-poll will not be indicate to driver, */
 495         /*  RxFilterMap should mask ps-poll to gurantee AP mode can rx ps-poll. */
 496         value16 = 0x400;
 497         rtw_write16(padapter, REG_RXFLTMAP1, value16);
 498
 499         /*  Accept all management frames */
 500         value16 = 0xFFFF;
 501         rtw_write16(padapter, REG_RXFLTMAP0, value16);
 502 }
 503
 504 static void _InitAdaptiveCtrl(struct adapter *padapter)
 505 {
 506         u16 value16;
 507         u32 value32;
 508
 509         /*  Response Rate Set */
 510         value32 = rtw_read32(padapter, REG_RRSR);
 511         value32 &= ~RATE_BITMAP_ALL;
 512         value32 |= RATE_RRSR_CCK_ONLY_1M;
 513         rtw_write32(padapter, REG_RRSR, value32);
 514
 515         /*  CF-END Threshold */
 516         /* m_spIoBase->rtw_write8(REG_CFEND_TH, 0x1); */
 517
 518         /*  SIFS (used in NAV) */
 519         value16 = _SPEC_SIFS_CCK(0x10) | _SPEC_SIFS_OFDM(0x10);
 520         rtw_write16(padapter, REG_SPEC_SIFS, value16);
 521
 522         /*  Retry Limit */
 523         value16 = _LRL(0x30) | _SRL(0x30);
 524         rtw_write16(padapter, REG_RL, value16);
 525 }
 526
 527 static void _InitEDCA(struct adapter *padapter)
 528 {
 529         /*  Set Spec SIFS (used in NAV) */
 530         rtw_write16(padapter, REG_SPEC_SIFS, 0x100a);
 531         rtw_write16(padapter, REG_MAC_SPEC_SIFS, 0x100a);
 532
 533         /*  Set SIFS for CCK */
 534         rtw_write16(padapter, REG_SIFS_CTX, 0x100a);
 535
 536         /*  Set SIFS for OFDM */
 537         rtw_write16(padapter, REG_SIFS_TRX, 0x100a);
 538
 539         /*  TXOP */
 540         rtw_write32(padapter, REG_EDCA_BE_PARAM, 0x005EA42B);
 541         rtw_write32(padapter, REG_EDCA_BK_PARAM, 0x0000A44F);
 542         rtw_write32(padapter, REG_EDCA_VI_PARAM, 0x005EA324);
 543         rtw_write32(padapter, REG_EDCA_VO_PARAM, 0x002FA226);
 544 }
 545
 546 static void _InitRetryFunction(struct adapter *padapter)
 547 {
 548         u8 value8;
 549
 550         value8 = rtw_read8(padapter, REG_FWHW_TXQ_CTRL);
 551         value8 |= EN_AMPDU_RTY_NEW;
 552         rtw_write8(padapter, REG_FWHW_TXQ_CTRL, value8);
 553
 554         /*  Set ACK timeout */
 555         rtw_write8(padapter, REG_ACKTO, 0x40);
 556 }
 557
 558 static void HalRxAggr8723BSdio(struct adapter *padapter)
 559 {
 560         struct registry_priv *pregistrypriv;
 561         u8 valueDMATimeout;
 562         u8 valueDMAPageCount;
 563
 564
 565         pregistrypriv = &padapter->registrypriv;
 566
 567         if (pregistrypriv->wifi_spec) {
 568                 /*  2010.04.27 hpfan */
 569                 /*  Adjust RxAggrTimeout to close to zero disable RxAggr, suggested by designer */
 570                 /*  Timeout value is calculated by 34 / (2^n) */
 571                 valueDMATimeout = 0x06;
 572                 valueDMAPageCount = 0x06;
 573         } else {
 574                 /*  20130530, Isaac@SD1 suggest 3 kinds of parameter */
 575                 /*  TX/RX Balance */
 576                 valueDMATimeout = 0x06;
 577                 valueDMAPageCount = 0x06;
 578         }
 579
 580         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH+1, valueDMATimeout);
 581         rtw_write8(padapter, REG_RXDMA_AGG_PG_TH, valueDMAPageCount);
 582 }
 583
 584 static void sdio_AggSettingRxUpdate(struct adapter *padapter)
 585 {
 586         struct hal_com_data *pHalData;
 587         u8 valueDMA;
 588         u8 valueRxAggCtrl = 0;
 589         u8 aggBurstNum = 3;  /* 0:1, 1:2, 2:3, 3:4 */
 590         u8 aggBurstSize = 0;  /* 0:1K, 1:512Byte, 2:256Byte... */
 591
 592         pHalData = GET_HAL_DATA(padapter);
 593
 594         valueDMA = rtw_read8(padapter, REG_TRXDMA_CTRL);
 595         valueDMA |= RXDMA_AGG_EN;
 596         rtw_write8(padapter, REG_TRXDMA_CTRL, valueDMA);
 597
 598         valueRxAggCtrl |= RXDMA_AGG_MODE_EN;
 599         valueRxAggCtrl |= ((aggBurstNum<<2) & 0x0C);
 600         valueRxAggCtrl |= ((aggBurstSize<<4) & 0x30);
 601         rtw_write8(padapter, REG_RXDMA_MODE_CTRL_8723B, valueRxAggCtrl);/* RxAggLowThresh = 4*1K */
 602 }
 603
 604 static void _initSdioAggregationSetting(struct adapter *padapter)
 605 {
 606         struct hal_com_data     *pHalData = GET_HAL_DATA(padapter);
 607
 608         /*  Tx aggregation setting */
 609 /*      sdio_AggSettingTxUpdate(padapter); */
 610
 611         /*  Rx aggregation setting */
 612         HalRxAggr8723BSdio(padapter);
 613
 614         sdio_AggSettingRxUpdate(padapter);
 615
 616         /*  201/12/10 MH Add for USB agg mode dynamic switch. */
 617         pHalData->UsbRxHighSpeedMode = false;
 618 }
 619
 620 static void _InitOperationMode(struct adapter *padapter)
 621 {
 622         struct hal_com_data *pHalData;
 623         struct mlme_ext_priv *pmlmeext;
 624         u8 regBwOpMode = 0;
 625         u32 regRATR = 0, regRRSR = 0;
 626
 627         pHalData = GET_HAL_DATA(padapter);
 628         pmlmeext = &padapter->mlmeextpriv;
 629
 630         /* 1 This part need to modified according to the rate set we filtered!! */
 631         /*  */
 632         /*  Set RRSR, RATR, and REG_BWOPMODE registers */
 633         /*  */
 634         switch (pmlmeext->cur_wireless_mode) {
 635         case WIRELESS_MODE_B:
 636                 regBwOpMode = BW_OPMODE_20MHZ;
 637                 regRATR = RATE_ALL_CCK;
 638                 regRRSR = RATE_ALL_CCK;
 639                 break;
 640         case WIRELESS_MODE_A:
 641 /*                      RT_ASSERT(false, ("Error wireless a mode\n")); */
 642                 break;
 643         case WIRELESS_MODE_G:
 644                 regBwOpMode = BW_OPMODE_20MHZ;
 645                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 646                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 647                 break;
 648         case WIRELESS_MODE_AUTO:
 649                 regBwOpMode = BW_OPMODE_20MHZ;
 650                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 651                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 652                 break;
 653         case WIRELESS_MODE_N_24G:
 654                 /*  It support CCK rate by default. */
 655                 /*  CCK rate will be filtered out only when associated AP does not support it. */
 656                 regBwOpMode = BW_OPMODE_20MHZ;
 657                 regRATR = RATE_ALL_CCK | RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 658                 regRRSR = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
 659                 break;
 660         case WIRELESS_MODE_N_5G:
 661 /*                      RT_ASSERT(false, ("Error wireless mode")); */
 662                 regBwOpMode = BW_OPMODE_5G;
 663                 regRATR = RATE_ALL_OFDM_AG | RATE_ALL_OFDM_1SS | RATE_ALL_OFDM_2SS;
 664                 regRRSR = RATE_ALL_OFDM_AG;
 665                 break;
 666
 667         default: /* for MacOSX compiler warning. */
 668                 break;
 669         }
 670
 671         rtw_write8(padapter, REG_BWOPMODE, regBwOpMode);
 672
 673 }
 674
 675 static void _InitInterrupt(struct adapter *padapter)
 676 {
 677         /*  HISR - turn all off */
 678         rtw_write32(padapter, REG_HISR, 0);
 679
 680         /*  HIMR - turn all off */
 681         rtw_write32(padapter, REG_HIMR, 0);
 682
 683         /*  */
 684         /*  Initialize and enable SDIO Host Interrupt. */
 685         /*  */
 686         InitInterrupt8723BSdio(padapter);
 687
 688         /*  */
 689         /*  Initialize system Host Interrupt. */
 690         /*  */
 691         InitSysInterrupt8723BSdio(padapter);
 692 }
 693
 694 static void _InitRFType(struct adapter *padapter)
 695 {
 696         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
 697
 698 #if     DISABLE_BB_RF
 699         pHalData->rf_chip       = RF_PSEUDO_11N;
 700         return;
 701 #endif
 702
 703         pHalData->rf_chip       = RF_6052;
 704
 705         pHalData->rf_type = RF_1T1R;
 706         DBG_8192C("Set RF Chip ID to RF_6052 and RF type to 1T1R.\n");
 707 }
 708
 709 static void _RfPowerSave(struct adapter *padapter)
 710 {
 711 /* YJ, TODO */
 712 }
 713
 714 /*  */
 715 /*  2010/08/09 MH Add for power down check. */
 716 /*  */
 717 static bool HalDetectPwrDownMode(struct adapter *Adapter)
 718 {
 719         u8 tmpvalue;
 720         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
 721         struct pwrctrl_priv *pwrctrlpriv = adapter_to_pwrctl(Adapter);
 722
 723
 724         EFUSE_ShadowRead(Adapter, 1, 0x7B/*EEPROM_RF_OPT3_92C*/, (u32 *)&tmpvalue);
 725
 726         /*  2010/08/25 MH INF priority > PDN Efuse value. */
 727         if (tmpvalue & BIT4 && pwrctrlpriv->reg_pdnmode)
 728                 pHalData->pwrdown = true;
 729         else
 730                 pHalData->pwrdown = false;
 731
 732         DBG_8192C("HalDetectPwrDownMode(): PDN =%d\n", pHalData->pwrdown);
 733
 734         return pHalData->pwrdown;
 735 }       /*  HalDetectPwrDownMode */
 736
 737 static u32 rtl8723bs_hal_init(struct adapter *padapter)
 738 {
 739         s32 ret;
 740         struct hal_com_data *pHalData;
 741         struct pwrctrl_priv *pwrctrlpriv;
 742         struct registry_priv *pregistrypriv;
 743         u32 NavUpper = WiFiNavUpperUs;
 744         u8 u1bTmp;
 745
 746         pHalData = GET_HAL_DATA(padapter);
 747         pwrctrlpriv = adapter_to_pwrctl(padapter);
 748         pregistrypriv = &padapter->registrypriv;
 749
 750         if (
 751                 adapter_to_pwrctl(padapter)->bips_processing == true &&
 752                 adapter_to_pwrctl(padapter)->pre_ips_type == 0
 753         ) {
 754                 unsigned long start_time;
 755                 u8 cpwm_orig, cpwm_now;
 756                 u8 val8, bMacPwrCtrlOn = true;
 757
 758                 DBG_871X("%s: Leaving IPS in FWLPS state\n", __func__);
 759
 760                 /* for polling cpwm */
 761                 cpwm_orig = 0;
 762                 rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_orig);
 763
 764                 /* ser rpwm */
 765                 val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
 766                 val8 &= 0x80;
 767                 val8 += 0x80;
 768                 val8 |= BIT(6);
 769                 rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
 770                 DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
 771                 adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
 772
 773                 /* do polling cpwm */
 774                 start_time = jiffies;
 775                 do {
 776
 777                         mdelay(1);
 778
 779                         rtw_hal_get_hwreg(padapter, HW_VAR_CPWM, &cpwm_now);
 780                         if ((cpwm_orig ^ cpwm_now) & 0x80)
 781                                 break;
 782
 783                         if (jiffies_to_msecs(jiffies - start_time) > 100) {
 784                                 DBG_871X("%s: polling cpwm timeout when leaving IPS in FWLPS state\n", __func__);
 785                                 break;
 786                         }
 787                 } while (1);
 788
 789                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0);
 790
 791                 rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
 792
 793                 rtw_btcoex_HAL_Initialize(padapter, false);
 794
 795                 return _SUCCESS;
 796         }
 797
 798 #ifdef CONFIG_WOWLAN
 799         if (rtw_read8(padapter, REG_MCUFWDL)&BIT7) {
 800                 u8 reg_val = 0;
 801                 DBG_871X("+Reset Entry+\n");
 802                 rtw_write8(padapter, REG_MCUFWDL, 0x00);
 803                 _8051Reset8723(padapter);
 804                 /* reset BB */
 805                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN);
 806                 reg_val &= ~(BIT(0) | BIT(1));
 807                 rtw_write8(padapter, REG_SYS_FUNC_EN, reg_val);
 808                 /* reset RF */
 809                 rtw_write8(padapter, REG_RF_CTRL, 0);
 810                 /* reset TRX path */
 811                 rtw_write16(padapter, REG_CR, 0);
 812                 /* reset MAC, Digital Core */
 813                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
 814                 reg_val &= ~(BIT(4) | BIT(7));
 815                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
 816                 reg_val = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
 817                 reg_val |= BIT(4) | BIT(7);
 818                 rtw_write8(padapter, REG_SYS_FUNC_EN+1, reg_val);
 819                 DBG_871X("-Reset Entry-\n");
 820         }
 821 #endif /* CONFIG_WOWLAN */
 822         /*  Disable Interrupt first. */
 823 /*      rtw_hal_disable_interrupt(padapter); */
 824
 825         ret = _InitPowerOn_8723BS(padapter);
 826         if (_FAIL == ret) {
 827                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("Failed to init Power On!\n"));
 828                 return _FAIL;
 829         }
 830
 831         rtw_write8(padapter, REG_EARLY_MODE_CONTROL, 0);
 832
 833         ret = rtl8723b_FirmwareDownload(padapter, false);
 834         if (ret != _SUCCESS) {
 835                 RT_TRACE(_module_hci_hal_init_c_, _drv_err_, ("%s: Download Firmware failed!!\n", __func__));
 836                 padapter->bFWReady = false;
 837                 pHalData->fw_ractrl = false;
 838                 return ret;
 839         } else {
 840                 RT_TRACE(_module_hci_hal_init_c_, _drv_notice_, ("rtl8723bs_hal_init(): Download Firmware Success!!\n"));
 841                 padapter->bFWReady = true;
 842                 pHalData->fw_ractrl = true;
 843         }
 844
 845         rtl8723b_InitializeFirmwareVars(padapter);
 846
 847 /*      SIC_Init(padapter); */
 848
 849         if (pwrctrlpriv->reg_rfoff == true)
 850                 pwrctrlpriv->rf_pwrstate = rf_off;
 851
 852         /*  2010/08/09 MH We need to check if we need to turnon or off RF after detecting */
 853         /*  HW GPIO pin. Before PHY_RFConfig8192C. */
 854         HalDetectPwrDownMode(padapter);
 855
 856         /*  Set RF type for BB/RF configuration */
 857         _InitRFType(padapter);
 858
 859         /*  Save target channel */
 860         /*  <Roger_Notes> Current Channel will be updated again later. */
 861         pHalData->CurrentChannel = 6;
 862
 863 #if (HAL_MAC_ENABLE == 1)
 864         ret = PHY_MACConfig8723B(padapter);
 865         if (ret != _SUCCESS) {
 866                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure MAC!!\n"));
 867                 return ret;
 868         }
 869 #endif
 870         /*  */
 871         /* d. Initialize BB related configurations. */
 872         /*  */
 873 #if (HAL_BB_ENABLE == 1)
 874         ret = PHY_BBConfig8723B(padapter);
 875         if (ret != _SUCCESS) {
 876                 RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure BB!!\n"));
 877                 return ret;
 878         }
 879 #endif
 880
 881         /*  If RF is on, we need to init RF. Otherwise, skip the procedure. */
 882         /*  We need to follow SU method to change the RF cfg.txt. Default disable RF TX/RX mode. */
 883         /* if (pHalData->eRFPowerState == eRfOn) */
 884         {
 885 #if (HAL_RF_ENABLE == 1)
 886                 ret = PHY_RFConfig8723B(padapter);
 887                 if (ret != _SUCCESS) {
 888                         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Initializepadapter8192CSdio(): Fail to configure RF!!\n"));
 889                         return ret;
 890                 }
 891 #endif
 892         }
 893
 894         /*  */
 895         /*  Joseph Note: Keep RfRegChnlVal for later use. */
 896         /*  */
 897         pHalData->RfRegChnlVal[0] =
 898                 PHY_QueryRFReg(padapter, (enum RF_PATH)0, RF_CHNLBW, bRFRegOffsetMask);
 899         pHalData->RfRegChnlVal[1] =
 900                 PHY_QueryRFReg(padapter, (enum RF_PATH)1, RF_CHNLBW, bRFRegOffsetMask);
 901
 902
 903         /* if (!pHalData->bMACFuncEnable) { */
 904         _InitQueueReservedPage(padapter);
 905         _InitTxBufferBoundary(padapter);
 906
 907         /*  init LLT after tx buffer boundary is defined */
 908         ret = rtl8723b_InitLLTTable(padapter);
 909         if (_SUCCESS != ret) {
 910                 DBG_8192C("%s: Failed to init LLT Table!\n", __func__);
 911                 return _FAIL;
 912         }
 913         /*  */
 914         _InitQueuePriority(padapter);
 915         _InitPageBoundary(padapter);
 916         _InitTransferPageSize(padapter);
 917
 918         /*  Get Rx PHY status in order to report RSSI and others. */
 919         _InitDriverInfoSize(padapter, DRVINFO_SZ);
 920         hal_init_macaddr(padapter);
 921         _InitNetworkType(padapter);
 922         _InitWMACSetting(padapter);
 923         _InitAdaptiveCtrl(padapter);
 924         _InitEDCA(padapter);
 925         _InitRetryFunction(padapter);
 926         _initSdioAggregationSetting(padapter);
 927         _InitOperationMode(padapter);
 928         rtl8723b_InitBeaconParameters(padapter);
 929         _InitInterrupt(padapter);
 930         _InitBurstPktLen_8723BS(padapter);
 931
 932         /* YJ, TODO */
 933         rtw_write8(padapter, REG_SECONDARY_CCA_CTRL_8723B, 0x3);        /*  CCA */
 934         rtw_write8(padapter, 0x976, 0); /*  hpfan_todo: 2nd CCA related */
 935
 936         rtw_write16(padapter, REG_PKT_VO_VI_LIFE_TIME, 0x0400); /*  unit: 256us. 256ms */
 937         rtw_write16(padapter, REG_PKT_BE_BK_LIFE_TIME, 0x0400); /*  unit: 256us. 256ms */
 938
 939         invalidate_cam_all(padapter);
 940
 941         rtw_hal_set_chnl_bw(padapter, padapter->registrypriv.channel,
 942                 CHANNEL_WIDTH_20, HAL_PRIME_CHNL_OFFSET_DONT_CARE, HAL_PRIME_CHNL_OFFSET_DONT_CARE);
 943
 944         /*  Record original value for template. This is arough data, we can only use the data */
 945         /*  for power adjust. The value can not be adjustde according to different power!!! */
 946 /*      pHalData->OriginalCckTxPwrIdx = pHalData->CurrentCckTxPwrIdx; */
 947 /*      pHalData->OriginalOfdm24GTxPwrIdx = pHalData->CurrentOfdm24GTxPwrIdx; */
 948
 949         rtl8723b_InitAntenna_Selection(padapter);
 950
 951         /*  */
 952         /*  Disable BAR, suggested by Scott */
 953         /*  2010.04.09 add by hpfan */
 954         /*  */
 955         rtw_write32(padapter, REG_BAR_MODE_CTRL, 0x0201ffff);
 956
 957         /*  HW SEQ CTRL */
 958         /*  set 0x0 to 0xFF by tynli. Default enable HW SEQ NUM. */
 959         rtw_write8(padapter, REG_HWSEQ_CTRL, 0xFF);
 960
 961
 962         /*  */
 963         /*  Configure SDIO TxRx Control to enable Rx DMA timer masking. */
 964         /*  2010.02.24. */
 965         /*  */
 966         rtw_write32(padapter, SDIO_LOCAL_BASE|SDIO_REG_TX_CTRL, 0);
 967
 968         _RfPowerSave(padapter);
 969
 970
 971         rtl8723b_InitHalDm(padapter);
 972
 973         /* DbgPrint("pHalData->DefaultTxPwrDbm = %d\n", pHalData->DefaultTxPwrDbm); */
 974
 975         /*  */
 976         /*  Update current Tx FIFO page status. */
 977         /*  */
 978         HalQueryTxBufferStatus8723BSdio(padapter);
 979         HalQueryTxOQTBufferStatus8723BSdio(padapter);
 980         pHalData->SdioTxOQTMaxFreeSpace = pHalData->SdioTxOQTFreeSpace;
 981
 982         /*  Enable MACTXEN/MACRXEN block */
 983         u1bTmp = rtw_read8(padapter, REG_CR);
 984         u1bTmp |= (MACTXEN | MACRXEN);
 985         rtw_write8(padapter, REG_CR, u1bTmp);
 986
 987         rtw_hal_set_hwreg(padapter, HW_VAR_NAV_UPPER, (u8 *)&NavUpper);
 988
 989         /* ack for xmit mgmt frames. */
 990         rtw_write32(padapter, REG_FWHW_TXQ_CTRL, rtw_read32(padapter, REG_FWHW_TXQ_CTRL)|BIT(12));
 991
 992 /*      pHalData->PreRpwmVal = SdioLocalCmd52Read1Byte(padapter, SDIO_REG_HRPWM1) & 0x80; */
 993
 994         {
 995                 pwrctrlpriv->rf_pwrstate = rf_on;
 996
 997                 if (pwrctrlpriv->rf_pwrstate == rf_on) {
 998                         struct pwrctrl_priv *pwrpriv;
 999                         unsigned long start_time;
1000                         u8 restore_iqk_rst;
1001                         u8 b2Ant;
1002                         u8 h2cCmdBuf;
1003
1004                         pwrpriv = adapter_to_pwrctl(padapter);
1005
1006                         PHY_LCCalibrate_8723B(&pHalData->odmpriv);
1007
1008                         /* Inform WiFi FW that it is the beginning of IQK */
1009                         h2cCmdBuf = 1;
1010                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1011
1012                         start_time = jiffies;
1013                         do {
1014                                 if (rtw_read8(padapter, 0x1e7) & 0x01)
1015                                         break;
1016
1017                                 msleep(50);
1018                         } while (jiffies_to_msecs(jiffies - start_time) <= 400);
1019
1020                         rtw_btcoex_IQKNotify(padapter, true);
1021
1022                         restore_iqk_rst = (pwrpriv->bips_processing == true) ? true : false;
1023                         b2Ant = pHalData->EEPROMBluetoothAntNum == Ant_x2 ? true : false;
1024                         PHY_IQCalibrate_8723B(padapter, false, restore_iqk_rst, b2Ant, pHalData->ant_path);
1025                         pHalData->odmpriv.RFCalibrateInfo.bIQKInitialized = true;
1026
1027                         rtw_btcoex_IQKNotify(padapter, false);
1028
1029                         /* Inform WiFi FW that it is the finish of IQK */
1030                         h2cCmdBuf = 0;
1031                         FillH2CCmd8723B(padapter, H2C_8723B_BT_WLAN_CALIBRATION, 1, &h2cCmdBuf);
1032
1033                         ODM_TXPowerTrackingCheck(&pHalData->odmpriv);
1034                 }
1035         }
1036
1037         /*  Init BT hw config. */
1038         rtw_btcoex_HAL_Initialize(padapter, false);
1039
1040         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-%s\n", __func__));
1041
1042         return _SUCCESS;
1043 }
1044
1045 /*  */
1046 /*  Description: */
1047 /*      RTL8723e card disable power sequence v003 which suggested by Scott. */
1048 /*  */
1049 /*  First created by tynli. 2011.01.28. */
1050 /*  */
1051 static void CardDisableRTL8723BSdio(struct adapter *padapter)
1052 {
1053         u8 u1bTmp;
1054         u8 bMacPwrCtrlOn;
1055         u8 ret = _FAIL;
1056
1057         /*  Run LPS WL RFOFF flow */
1058         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_enter_lps_flow);
1059         if (ret == _FAIL) {
1060                 DBG_8192C(KERN_ERR "%s: run RF OFF flow fail!\n", __func__);
1061         }
1062
1063         /*      ==== Reset digital sequence   ====== */
1064
1065         u1bTmp = rtw_read8(padapter, REG_MCUFWDL);
1066         if ((u1bTmp & RAM_DL_SEL) && padapter->bFWReady) /* 8051 RAM code */
1067                 rtl8723b_FirmwareSelfReset(padapter);
1068
1069         /*  Reset MCU 0x2[10]= 0. Suggested by Filen. 2011.01.26. by tynli. */
1070         u1bTmp = rtw_read8(padapter, REG_SYS_FUNC_EN+1);
1071         u1bTmp &= ~BIT(2);      /*  0x2[10], FEN_CPUEN */
1072         rtw_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp);
1073
1074         /*  MCUFWDL 0x80[1:0]= 0 */
1075         /*  reset MCU ready status */
1076         rtw_write8(padapter, REG_MCUFWDL, 0);
1077
1078         /*  Reset MCU IO Wrapper, added by Roger, 2011.08.30 */
1079         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1080         u1bTmp &= ~BIT(0);
1081         rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1082         u1bTmp = rtw_read8(padapter, REG_RSV_CTRL+1);
1083         u1bTmp |= BIT(0);
1084         rtw_write8(padapter, REG_RSV_CTRL+1, u1bTmp);
1085
1086         /*      ==== Reset digital sequence end ====== */
1087
1088         bMacPwrCtrlOn = false;  /*  Disable CMD53 R/W */
1089         ret = false;
1090         rtw_hal_set_hwreg(padapter, HW_VAR_APFM_ON_MAC, &bMacPwrCtrlOn);
1091         ret = HalPwrSeqCmdParsing(padapter, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, rtl8723B_card_disable_flow);
1092         if (ret == false) {
1093                 DBG_8192C(KERN_ERR "%s: run CARD DISABLE flow fail!\n", __func__);
1094         }
1095 }
1096
1097 static u32 rtl8723bs_hal_deinit(struct adapter *padapter)
1098 {
1099         struct dvobj_priv *psdpriv = padapter->dvobj;
1100         struct debug_priv *pdbgpriv = &psdpriv->drv_dbg;
1101
1102         if (padapter->hw_init_completed == true) {
1103                 if (adapter_to_pwrctl(padapter)->bips_processing == true) {
1104                         if (padapter->netif_up == true) {
1105                                 int cnt = 0;
1106                                 u8 val8 = 0;
1107
1108                                 DBG_871X("%s: issue H2C to FW when entering IPS\n", __func__);
1109
1110                                 rtl8723b_set_FwPwrModeInIPS_cmd(padapter, 0x3);
1111                                 /* poll 0x1cc to make sure H2C command already finished by FW; MAC_0x1cc = 0 means H2C done by FW. */
1112                                 do {
1113                                         val8 = rtw_read8(padapter, REG_HMETFR);
1114                                         cnt++;
1115                                         DBG_871X("%s  polling REG_HMETFR = 0x%x, cnt =%d\n", __func__, val8, cnt);
1116                                         mdelay(10);
1117                                 } while (cnt < 100 && (val8 != 0));
1118                                 /* H2C done, enter 32k */
1119                                 if (val8 == 0) {
1120                                         /* ser rpwm to enter 32k */
1121                                         val8 = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1);
1122                                         val8 += 0x80;
1123                                         val8 |= BIT(0);
1124                                         rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1125                                         DBG_871X("%s: write rpwm =%02x\n", __func__, val8);
1126                                         adapter_to_pwrctl(padapter)->tog = (val8 + 0x80) & 0x80;
1127                                         cnt = val8 = 0;
1128                                         do {
1129                                                 val8 = rtw_read8(padapter, REG_CR);
1130                                                 cnt++;
1131                                                 DBG_871X("%s  polling 0x100 = 0x%x, cnt =%d\n", __func__, val8, cnt);
1132                                                 mdelay(10);
1133                                         } while (cnt < 100 && (val8 != 0xEA));
1134                                 } else {
1135                                         DBG_871X(
1136                                                 "MAC_1C0 =%08x, MAC_1C4 =%08x, MAC_1C8 =%08x, MAC_1CC =%08x\n",
1137                                                 rtw_read32(padapter, 0x1c0),
1138                                                 rtw_read32(padapter, 0x1c4),
1139                                                 rtw_read32(padapter, 0x1c8),
1140                                                 rtw_read32(padapter, 0x1cc)
1141                                         );
1142                                 }
1143
1144                                 DBG_871X(
1145                                         "polling done when entering IPS, check result : 0x100 = 0x%x, cnt =%d, MAC_1cc = 0x%02x\n",
1146                                         rtw_read8(padapter, REG_CR),
1147                                         cnt,
1148                                         rtw_read8(padapter, REG_HMETFR)
1149                                 );
1150
1151                                 adapter_to_pwrctl(padapter)->pre_ips_type = 0;
1152
1153                         } else {
1154                                 pdbgpriv->dbg_carddisable_cnt++;
1155                                 CardDisableRTL8723BSdio(padapter);
1156
1157                                 adapter_to_pwrctl(padapter)->pre_ips_type = 1;
1158                         }
1159
1160                 } else {
1161                         pdbgpriv->dbg_carddisable_cnt++;
1162                         CardDisableRTL8723BSdio(padapter);
1163                 }
1164         } else
1165                 pdbgpriv->dbg_deinit_fail_cnt++;
1166
1167         return _SUCCESS;
1168 }
1169
1170 static u32 rtl8723bs_inirp_init(struct adapter *padapter)
1171 {
1172         return _SUCCESS;
1173 }
1174
1175 static u32 rtl8723bs_inirp_deinit(struct adapter *padapter)
1176 {
1177         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+rtl8723bs_inirp_deinit\n"));
1178
1179         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("-rtl8723bs_inirp_deinit\n"));
1180
1181         return _SUCCESS;
1182 }
1183
1184 static void rtl8723bs_init_default_value(struct adapter *padapter)
1185 {
1186         struct hal_com_data *pHalData;
1187
1188
1189         pHalData = GET_HAL_DATA(padapter);
1190
1191         rtl8723b_init_default_value(padapter);
1192
1193         /*  interface related variable */
1194         pHalData->SdioRxFIFOCnt = 0;
1195 }
1196
1197 static void rtl8723bs_interface_configure(struct adapter *padapter)
1198 {
1199         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1200         struct dvobj_priv *pdvobjpriv = adapter_to_dvobj(padapter);
1201         struct registry_priv *pregistrypriv = &padapter->registrypriv;
1202         bool bWiFiConfig = pregistrypriv->wifi_spec;
1203
1204
1205         pdvobjpriv->RtOutPipe[0] = WLAN_TX_HIQ_DEVICE_ID;
1206         pdvobjpriv->RtOutPipe[1] = WLAN_TX_MIQ_DEVICE_ID;
1207         pdvobjpriv->RtOutPipe[2] = WLAN_TX_LOQ_DEVICE_ID;
1208
1209         if (bWiFiConfig)
1210                 pHalData->OutEpNumber = 2;
1211         else
1212                 pHalData->OutEpNumber = SDIO_MAX_TX_QUEUE;
1213
1214         switch (pHalData->OutEpNumber) {
1215         case 3:
1216                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_LQ|TX_SELE_NQ;
1217                 break;
1218         case 2:
1219                 pHalData->OutEpQueueSel = TX_SELE_HQ | TX_SELE_NQ;
1220                 break;
1221         case 1:
1222                 pHalData->OutEpQueueSel = TX_SELE_HQ;
1223                 break;
1224         default:
1225                 break;
1226         }
1227
1228         Hal_MappingOutPipe(padapter, pHalData->OutEpNumber);
1229 }
1230
1231 /*  */
1232 /*      Description: */
1233 /*              We should set Efuse cell selection to WiFi cell in default. */
1234 /*  */
1235 /*      Assumption: */
1236 /*              PASSIVE_LEVEL */
1237 /*  */
1238 /*      Added by Roger, 2010.11.23. */
1239 /*  */
1240 static void _EfuseCellSel(struct adapter *padapter)
1241 {
1242         u32 value32;
1243
1244         value32 = rtw_read32(padapter, EFUSE_TEST);
1245         value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1246         rtw_write32(padapter, EFUSE_TEST, value32);
1247 }
1248
1249 static void _ReadRFType(struct adapter *Adapter)
1250 {
1251         struct hal_com_data *pHalData = GET_HAL_DATA(Adapter);
1252
1253 #if DISABLE_BB_RF
1254         pHalData->rf_chip = RF_PSEUDO_11N;
1255 #else
1256         pHalData->rf_chip = RF_6052;
1257 #endif
1258 }
1259
1260
1261 static void Hal_EfuseParseMACAddr_8723BS(
1262         struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1263 )
1264 {
1265         u16 i;
1266         u8 sMacAddr[6] = {0x00, 0xE0, 0x4C, 0xb7, 0x23, 0x00};
1267         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1268
1269         if (AutoLoadFail) {
1270 /*              sMacAddr[5] = (u8)GetRandomNumber(1, 254); */
1271                 for (i = 0; i < 6; i++)
1272                         pEEPROM->mac_addr[i] = sMacAddr[i];
1273         } else {
1274                 /* Read Permanent MAC address */
1275                 memcpy(pEEPROM->mac_addr, &hwinfo[EEPROM_MAC_ADDR_8723BS], ETH_ALEN);
1276         }
1277 /*      NicIFSetMacAddress(padapter, padapter->PermanentAddress); */
1278
1279         RT_TRACE(
1280                 _module_hci_hal_init_c_,
1281                 _drv_notice_,
1282                 (
1283                         "Hal_EfuseParseMACAddr_8723BS: Permanent Address = %02x-%02x-%02x-%02x-%02x-%02x\n",
1284                         pEEPROM->mac_addr[0],
1285                         pEEPROM->mac_addr[1],
1286                         pEEPROM->mac_addr[2],
1287                         pEEPROM->mac_addr[3],
1288                         pEEPROM->mac_addr[4],
1289                         pEEPROM->mac_addr[5]
1290                 )
1291         );
1292 }
1293
1294 static void Hal_EfuseParseBoardType_8723BS(
1295         struct adapter *padapter, u8 *hwinfo, bool AutoLoadFail
1296 )
1297 {
1298         struct hal_com_data *pHalData = GET_HAL_DATA(padapter);
1299
1300         if (!AutoLoadFail) {
1301                 pHalData->BoardType = (hwinfo[EEPROM_RF_BOARD_OPTION_8723B] & 0xE0) >> 5;
1302                 if (pHalData->BoardType == 0xFF)
1303                         pHalData->BoardType = (EEPROM_DEFAULT_BOARD_OPTION&0xE0)>>5;
1304         } else
1305                 pHalData->BoardType = 0;
1306         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("Board Type: 0x%2x\n", pHalData->BoardType));
1307 }
1308
1309 static void _ReadEfuseInfo8723BS(struct adapter *padapter)
1310 {
1311         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1312         u8 *hwinfo = NULL;
1313
1314         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("====>_ReadEfuseInfo8723BS()\n"));
1315
1316         /*  */
1317         /*  This part read and parse the eeprom/efuse content */
1318         /*  */
1319
1320         if (sizeof(pEEPROM->efuse_eeprom_data) < HWSET_MAX_SIZE_8723B)
1321                 DBG_871X("[WARNING] size of efuse_eeprom_data is less than HWSET_MAX_SIZE_8723B!\n");
1322
1323         hwinfo = pEEPROM->efuse_eeprom_data;
1324
1325         Hal_InitPGData(padapter, hwinfo);
1326
1327         Hal_EfuseParseIDCode(padapter, hwinfo);
1328         Hal_EfuseParseEEPROMVer_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1329
1330         Hal_EfuseParseMACAddr_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1331
1332         Hal_EfuseParseTxPowerInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1333         Hal_EfuseParseBoardType_8723BS(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1334
1335         /*  */
1336         /*  Read Bluetooth co-exist and initialize */
1337         /*  */
1338         Hal_EfuseParsePackageType_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1339         Hal_EfuseParseBTCoexistInfo_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1340         Hal_EfuseParseChnlPlan_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1341         Hal_EfuseParseXtal_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1342         Hal_EfuseParseThermalMeter_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1343         Hal_EfuseParseAntennaDiversity_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1344         Hal_EfuseParseCustomerID_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1345
1346         Hal_EfuseParseVoltage_8723B(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1347
1348 #ifdef CONFIG_WOWLAN
1349         Hal_DetectWoWMode(padapter);
1350 #endif
1351
1352         Hal_ReadRFGainOffset(padapter, hwinfo, pEEPROM->bautoload_fail_flag);
1353
1354         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("<==== _ReadEfuseInfo8723BS()\n"));
1355 }
1356
1357 static void _ReadPROMContent(struct adapter *padapter)
1358 {
1359         struct eeprom_priv *pEEPROM = GET_EEPROM_EFUSE_PRIV(padapter);
1360         u8      eeValue;
1361
1362         eeValue = rtw_read8(padapter, REG_9346CR);
1363         /*  To check system boot selection. */
1364         pEEPROM->EepromOrEfuse = (eeValue & BOOT_FROM_EEPROM) ? true : false;
1365         pEEPROM->bautoload_fail_flag = (eeValue & EEPROM_EN) ? false : true;
1366
1367         RT_TRACE(_module_hci_hal_init_c_, _drv_info_,
1368                  ("%s: 9346CR = 0x%02X, Boot from %s, Autoload %s\n",
1369                   __func__, eeValue,
1370                   (pEEPROM->EepromOrEfuse ? "EEPROM" : "EFUSE"),
1371                   (pEEPROM->bautoload_fail_flag ? "Fail" : "OK")));
1372
1373 /*      pHalData->EEType = IS_BOOT_FROM_EEPROM(Adapter) ? EEPROM_93C46 : EEPROM_BOOT_EFUSE; */
1374
1375         _ReadEfuseInfo8723BS(padapter);
1376 }
1377
1378 static void _InitOtherVariable(struct adapter *Adapter)
1379 {
1380 }
1381
1382 /*  */
1383 /*      Description: */
1384 /*              Read HW adapter information by E-Fuse or EEPROM according CR9346 reported. */
1385 /*  */
1386 /*      Assumption: */
1387 /*              PASSIVE_LEVEL (SDIO interface) */
1388 /*  */
1389 /*  */
1390 static s32 _ReadAdapterInfo8723BS(struct adapter *padapter)
1391 {
1392         u8 val8;
1393         unsigned long start;
1394
1395         RT_TRACE(_module_hci_hal_init_c_, _drv_info_, ("+_ReadAdapterInfo8723BS\n"));
1396
1397         /*  before access eFuse, make sure card enable has been called */
1398         if (padapter->hw_init_completed == false)
1399                 _InitPowerOn_8723BS(padapter);
1400
1401
1402         val8 = rtw_read8(padapter, 0x4e);
1403         MSG_8192C("%s, 0x4e = 0x%x\n", __func__, val8);
1404         val8 |= BIT(6);
1405         rtw_write8(padapter, 0x4e, val8);
1406
1407
1408         start = jiffies;
1409
1410         _EfuseCellSel(padapter);
1411         _ReadRFType(padapter);
1412         _ReadPROMContent(padapter);
1413         _InitOtherVariable(padapter);
1414
1415         if (padapter->hw_init_completed == false) {
1416                 rtw_write8(padapter, 0x67, 0x00); /*  for BT, Switch Ant control to BT */
1417                 CardDisableRTL8723BSdio(padapter);/* for the power consumption issue,  wifi ko module is loaded during booting, but wifi GUI is off */
1418         }
1419
1420
1421         MSG_8192C("<==== _ReadAdapterInfo8723BS in %d ms\n", jiffies_to_msecs(jiffies - start));
1422
1423         return _SUCCESS;
1424 }
1425
1426 static void ReadAdapterInfo8723BS(struct adapter *padapter)
1427 {
1428         /*  Read EEPROM size before call any EEPROM function */
1429         padapter->EepromAddressSize = GetEEPROMSize8723B(padapter);
1430
1431         _ReadAdapterInfo8723BS(padapter);
1432 }
1433
1434 /*
1435  * If variable not handled here,
1436  * some variables will be processed in SetHwReg8723B()
1437  */
1438 static void SetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1439 {
1440         struct hal_com_data *pHalData;
1441         u8 val8;
1442
1443 #if defined(CONFIG_WOWLAN) || defined(CONFIG_AP_WOWLAN)
1444         struct wowlan_ioctl_param *poidparam;
1445         struct pwrctrl_priv *pwrctl = adapter_to_pwrctl(padapter);
1446         int res;
1447         u32 tmp;
1448         u16 len = 0;
1449         u8 trycnt = 100;
1450         u32 himr = 0;
1451 #if defined(CONFIG_WOWLAN)
1452         struct security_priv *psecuritypriv = &padapter->securitypriv;
1453         struct mlme_priv *pmlmepriv = &padapter->mlmepriv;
1454         struct sta_info *psta = NULL;
1455         u64 iv_low = 0, iv_high = 0;
1456         u8 mstatus = (*(u8 *)val);
1457 #endif
1458 #endif
1459
1460         pHalData = GET_HAL_DATA(padapter);
1461
1462         switch (variable) {
1463         case HW_VAR_SET_RPWM:
1464                 /*  rpwm value only use BIT0(clock bit) , BIT6(Ack bit), and BIT7(Toggle bit) */
1465                 /*  BIT0 value - 1: 32k, 0:40MHz. */
1466                 /*  BIT6 value - 1: report cpwm value after success set, 0:do not report. */
1467                 /*  BIT7 value - Toggle bit change. */
1468                 {
1469                         val8 = *val;
1470                         val8 &= 0xC1;
1471                         rtw_write8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HRPWM1, val8);
1472                 }
1473                 break;
1474         case HW_VAR_SET_REQ_FW_PS:
1475                 {
1476                         u8 req_fw_ps = 0;
1477                         req_fw_ps = rtw_read8(padapter, 0x8f);
1478                         req_fw_ps |= 0x10;
1479                         rtw_write8(padapter, 0x8f, req_fw_ps);
1480                 }
1481                 break;
1482         case HW_VAR_RXDMA_AGG_PG_TH:
1483                 val8 = *val;
1484                 break;
1485
1486 #ifdef CONFIG_WOWLAN
1487         case HW_VAR_WOWLAN:
1488         {
1489                 poidparam = (struct wowlan_ioctl_param *)val;
1490                 switch (poidparam->subcode) {
1491                 case WOWLAN_ENABLE:
1492                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_ENABLE\n");
1493
1494                         /* backup data rate to register 0x8b for wowlan FW */
1495                         rtw_write8(padapter, 0x8d, 1);
1496                         rtw_write8(padapter, 0x8c, 0);
1497                         rtw_write8(padapter, 0x8f, 0x40);
1498                         rtw_write8(padapter, 0x8b,
1499                         rtw_read8(padapter, 0x2f0));
1500
1501                         /*  1. Download WOWLAN FW */
1502                         DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1503                         SetFwRelatedForWoWLAN8723b(padapter, true);
1504
1505                         /*  2. RX DMA stop */
1506                         DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1507                         rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1508                         do {
1509                                 if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
1510                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1511                                         break;
1512                                 } else {
1513                                         /*  If RX_DMA is not idle, receive one pkt from DMA */
1514                                         res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1515                                         len = le16_to_cpu(tmp);
1516                                         DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1517                                         if (len > 0)
1518                                                 res = RecvOnePkt(padapter, len);
1519                                         else
1520                                                 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1521
1522                                         DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1523                                 }
1524                         } while (trycnt--);
1525                         if (trycnt == 0)
1526                                 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1527
1528                         /*  3. Clear IMR and ISR */
1529                         DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1530                         tmp = 0;
1531                         sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1532                         sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1533                         sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1534                         sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1535
1536                         /*  4. Enable CPWM2 only */
1537                         DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1538                         sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1539                         DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1540
1541                         himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
1542                         sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1543
1544                         sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1545                         DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1546
1547                         /*  5. Set Enable WOWLAN H2C command. */
1548                         DBG_871X_LEVEL(_drv_always_, "Set Enable WOWLan cmd\n");
1549                         rtl8723b_set_wowlan_cmd(padapter, 1);
1550
1551                         /*  6. Check EnableWoWlan CMD is ready */
1552                         if (!pwrctl->wowlan_pno_enable) {
1553                                 DBG_871X_LEVEL(_drv_always_, "Check EnableWoWlan CMD is ready\n");
1554                                 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1555                                 trycnt = 10;
1556                                 while (!(mstatus&BIT1) && trycnt > 1) {
1557                                         mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1558                                         DBG_871X("Loop index: %d :0x%02x\n", trycnt, mstatus);
1559                                         trycnt--;
1560                                         msleep(2);
1561                                 }
1562                         }
1563                         break;
1564
1565                 case WOWLAN_DISABLE:
1566                         DBG_871X_LEVEL(_drv_always_, "WOWLAN_DISABLE\n");
1567
1568                         psta = rtw_get_stainfo(&padapter->stapriv, get_bssid(pmlmepriv));
1569                         if (psta != NULL)
1570                                 rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_DISCONNECT, psta->mac_id);
1571                         else
1572                                 DBG_871X("psta is null\n");
1573
1574                         /*  1. Read wakeup reason */
1575                         pwrctl->wowlan_wake_reason = rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1576                         DBG_871X_LEVEL(
1577                                 _drv_always_,
1578                                 "wakeup_reason: 0x%02x, mac_630 = 0x%08x, mac_634 = 0x%08x, mac_1c0 = 0x%08x, mac_1c4 = 0x%08x"
1579                                 ", mac_494 = 0x%08x, , mac_498 = 0x%08x, mac_49c = 0x%08x, mac_608 = 0x%08x, mac_4a0 = 0x%08x, mac_4a4 = 0x%08x\n"
1580                                 ", mac_1cc = 0x%08x, mac_2f0 = 0x%08x, mac_2f4 = 0x%08x, mac_2f8 = 0x%08x, mac_2fc = 0x%08x, mac_8c = 0x%08x",
1581                                 pwrctl->wowlan_wake_reason,
1582                                 rtw_read32(padapter, REG_WOWLAN_GTK_DBG1),
1583                                 rtw_read32(padapter, REG_WOWLAN_GTK_DBG2),
1584                                 rtw_read32(padapter, 0x1c0),
1585                                 rtw_read32(padapter, 0x1c4),
1586                                 rtw_read32(padapter, 0x494),
1587                                 rtw_read32(padapter, 0x498),
1588                                 rtw_read32(padapter, 0x49c),
1589                                 rtw_read32(padapter, 0x608),
1590                                 rtw_read32(padapter, 0x4a0),
1591                                 rtw_read32(padapter, 0x4a4),
1592                                 rtw_read32(padapter, 0x1cc),
1593                                 rtw_read32(padapter, 0x2f0),
1594                                 rtw_read32(padapter, 0x2f4),
1595                                 rtw_read32(padapter, 0x2f8),
1596                                 rtw_read32(padapter, 0x2fc),
1597                                 rtw_read32(padapter, 0x8c)
1598                         );
1599 #ifdef CONFIG_PNO_SET_DEBUG
1600                         DBG_871X("0x1b9: 0x%02x, 0x632: 0x%02x\n", rtw_read8(padapter, 0x1b9), rtw_read8(padapter, 0x632));
1601                         DBG_871X("0x4fc: 0x%02x, 0x4fd: 0x%02x\n", rtw_read8(padapter, 0x4fc), rtw_read8(padapter, 0x4fd));
1602                         DBG_871X("TXDMA STATUS: 0x%08x\n", rtw_read32(padapter, REG_TXDMA_STATUS));
1603 #endif
1604
1605                         {
1606                                 /*  2.  Set Disable WOWLAN H2C command. */
1607                                 DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1608                                 rtl8723b_set_wowlan_cmd(padapter, 0);
1609
1610                                 /*  3. Check Disable WoWlan CMD ready. */
1611                                 DBG_871X_LEVEL(_drv_always_, "Check DisableWoWlan CMD is ready\n");
1612                                 mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1613                                 trycnt = 50;
1614                                 while (mstatus&BIT1 && trycnt > 1) {
1615                                         mstatus = rtw_read8(padapter, REG_WOW_CTRL);
1616                                         DBG_871X_LEVEL(_drv_always_, "Loop index: %d :0x%02x\n", trycnt, mstatus);
1617                                         trycnt--;
1618                                         msleep(10);
1619                                 }
1620
1621                                 if (mstatus & BIT1) {
1622                                         DBG_871X_LEVEL(_drv_always_, "Disable WOW mode fail!!\n");
1623                                         DBG_871X("Set 0x690 = 0x00\n");
1624                                         rtw_write8(padapter, REG_WOW_CTRL, (rtw_read8(padapter, REG_WOW_CTRL)&0xf0));
1625                                         DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1626                                         rtw_write32(padapter, REG_RXPKT_NUM, (rtw_read32(padapter, REG_RXPKT_NUM)&(~RW_RELEASE_EN)));
1627                                 }
1628
1629                                 /*  3.1 read fw iv */
1630                                 iv_low = rtw_read32(padapter, REG_TXPKTBUF_IV_LOW);
1631                                         /* only low two bytes is PN, check AES_IV macro for detail */
1632                                 iv_low &= 0xffff;
1633                                 iv_high = rtw_read32(padapter, REG_TXPKTBUF_IV_HIGH);
1634                                         /* get the real packet number */
1635                                 pwrctl->wowlan_fw_iv = iv_high << 16 | iv_low;
1636                                 DBG_871X_LEVEL(_drv_always_, "fw_iv: 0x%016llx\n", pwrctl->wowlan_fw_iv);
1637                                 /* Update TX iv data. */
1638                                 rtw_set_sec_pn(padapter);
1639
1640                                 /*  3.2 read GTK index and key */
1641                                 if (
1642                                         psecuritypriv->binstallKCK_KEK == true &&
1643                                         psecuritypriv->dot11PrivacyAlgrthm == _AES_
1644                                 ) {
1645                                         u8 gtk_keyindex = 0;
1646                                         u8 get_key[16];
1647                                         /* read gtk key index */
1648                                         gtk_keyindex = rtw_read8(padapter, 0x48c);
1649
1650                                         if (gtk_keyindex < 4) {
1651                                                 psecuritypriv->dot118021XGrpKeyid = gtk_keyindex;
1652                                                 read_cam(padapter, gtk_keyindex, get_key);
1653                                                 memcpy(psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].skey, get_key, 16);
1654                                                 DBG_871X_LEVEL(
1655                                                         _drv_always_,
1656                                                         "GTK (%d) = 0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
1657                                                         gtk_keyindex,
1658                                                         psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[0],
1659                                                         psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[1],
1660                                                         psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[2],
1661                                                         psecuritypriv->dot118021XGrpKey[psecuritypriv->dot118021XGrpKeyid].lkey[3]
1662                                                 );
1663                                         } else
1664                                                 DBG_871X_LEVEL(_drv_always_, "GTK index =%d\n", gtk_keyindex);
1665                                 }
1666
1667                                 /*  4. Re-download Normal FW. */
1668                                 DBG_871X_LEVEL(_drv_always_, "Re-download Normal FW!\n");
1669                                 SetFwRelatedForWoWLAN8723b(padapter, false);
1670                         }
1671 #ifdef CONFIG_GPIO_WAKEUP
1672                         DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1673                         HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1674 #endif
1675
1676                         /*  5. Download reserved pages and report media status if needed. */
1677                         if (
1678                                 (pwrctl->wowlan_wake_reason != FWDecisionDisconnect) &&
1679                                 (pwrctl->wowlan_wake_reason != Rx_Pairwisekey) &&
1680                                 (pwrctl->wowlan_wake_reason != Rx_DisAssoc) &&
1681                                 (pwrctl->wowlan_wake_reason != Rx_DeAuth)
1682                         ) {
1683                                 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1684                                 if (psta != NULL)
1685                                         rtl8723b_set_FwMediaStatusRpt_cmd(padapter, RT_MEDIA_CONNECT, psta->mac_id);
1686                         }
1687 #ifdef CONFIG_PNO_SUPPORT
1688                         rtw_write8(padapter, 0x1b8, 0);
1689                         DBG_871X("reset 0x1b8: %d\n", rtw_read8(padapter, 0x1b8));
1690                         rtw_write8(padapter, 0x1b9, 0);
1691                         DBG_871X("reset 0x1b9: %d\n", rtw_read8(padapter, 0x1b9));
1692                         rtw_write8(padapter, REG_PNO_STATUS, 0);
1693                         DBG_871X("reset REG_PNO_STATUS: %d\n", rtw_read8(padapter, REG_PNO_STATUS));
1694 #endif
1695                         break;
1696
1697                 default:
1698                         break;
1699                 }
1700         }
1701         break;
1702 #endif /* CONFIG_WOWLAN */
1703 #ifdef CONFIG_AP_WOWLAN
1704         case HW_VAR_AP_WOWLAN:
1705         {
1706                 poidparam = (struct wowlan_ioctl_param *)val;
1707                 switch (poidparam->subcode) {
1708                 case WOWLAN_AP_ENABLE:
1709                         DBG_871X("%s, WOWLAN_AP_ENABLE\n", __func__);
1710                         /*  1. Download WOWLAN FW */
1711                         DBG_871X_LEVEL(_drv_always_, "Re-download WoWlan FW!\n");
1712                         SetFwRelatedForWoWLAN8723b(padapter, true);
1713
1714                         /*  2. RX DMA stop */
1715                         DBG_871X_LEVEL(_drv_always_, "Pause DMA\n");
1716                         rtw_write32(padapter, REG_RXPKT_NUM,
1717                                 (rtw_read32(padapter, REG_RXPKT_NUM)|RW_RELEASE_EN));
1718                         do {
1719                                 if ((rtw_read32(padapter, REG_RXPKT_NUM)&RXDMA_IDLE)) {
1720                                         DBG_871X_LEVEL(_drv_always_, "RX_DMA_IDLE is true\n");
1721                                         break;
1722                                 } else {
1723                                         /*  If RX_DMA is not idle, receive one pkt from DMA */
1724                                         res = sdio_local_read(padapter, SDIO_REG_RX0_REQ_LEN, 4, (u8 *)&tmp);
1725                                         len = le16_to_cpu(tmp);
1726
1727                                         DBG_871X_LEVEL(_drv_always_, "RX len:%d\n", len);
1728                                         if (len > 0)
1729                                                 res = RecvOnePkt(padapter, len);
1730                                         else
1731                                                 DBG_871X_LEVEL(_drv_always_, "read length fail %d\n", len);
1732
1733                                         DBG_871X_LEVEL(_drv_always_, "RecvOnePkt Result: %d\n", res);
1734                                 }
1735                         } while (trycnt--);
1736
1737                         if (trycnt == 0)
1738                                 DBG_871X_LEVEL(_drv_always_, "Stop RX DMA failed......\n");
1739
1740                         /*  3. Clear IMR and ISR */
1741                         DBG_871X_LEVEL(_drv_always_, "Clear IMR and ISR\n");
1742                         tmp = 0;
1743                         sdio_local_write(padapter, SDIO_REG_HIMR_ON, 4, (u8 *)&tmp);
1744                         sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1745                         sdio_local_read(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1746                         sdio_local_write(padapter, SDIO_REG_HISR, 4, (u8 *)&tmp);
1747
1748                         /*  4. Enable CPWM2 only */
1749                         DBG_871X_LEVEL(_drv_always_, "Enable only CPWM2\n");
1750                         sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1751                         DBG_871X("DisableInterruptButCpwm28723BSdio(): Read SDIO_REG_HIMR: 0x%08x\n", tmp);
1752
1753                         himr = cpu_to_le32(SDIO_HIMR_DISABLED)|SDIO_HIMR_CPWM2_MSK;
1754                         sdio_local_write(padapter, SDIO_REG_HIMR, 4, (u8 *)&himr);
1755
1756                         sdio_local_read(padapter, SDIO_REG_HIMR, 4, (u8 *)&tmp);
1757                         DBG_871X("DisableInterruptButCpwm28723BSdio(): Read again SDIO_REG_HIMR: 0x%08x\n", tmp);
1758
1759                         /*  5. Set Enable WOWLAN H2C command. */
1760                         DBG_871X_LEVEL(_drv_always_, "Set Enable AP WOWLan cmd\n");
1761                         rtl8723b_set_ap_wowlan_cmd(padapter, 1);
1762                         /*  6. add some delay for H2C cmd ready */
1763                         msleep(10);
1764
1765                         rtw_write8(padapter, REG_WOWLAN_WAKE_REASON, 0);
1766                         break;
1767                 case WOWLAN_AP_DISABLE:
1768                         DBG_871X("%s, WOWLAN_AP_DISABLE\n", __func__);
1769                         /*  1. Read wakeup reason */
1770                         pwrctl->wowlan_wake_reason =
1771                                 rtw_read8(padapter, REG_WOWLAN_WAKE_REASON);
1772
1773                         DBG_871X_LEVEL(_drv_always_, "wakeup_reason: 0x%02x\n",
1774                                         pwrctl->wowlan_wake_reason);
1775
1776                         /*  2.  Set Disable WOWLAN H2C command. */
1777                         DBG_871X_LEVEL(_drv_always_, "Set Disable WOWLan cmd\n");
1778                         rtl8723b_set_ap_wowlan_cmd(padapter, 0);
1779                         /*  6. add some delay for H2C cmd ready */
1780                         msleep(2);
1781
1782                         DBG_871X_LEVEL(_drv_always_, "Release RXDMA\n");
1783
1784                         rtw_write32(padapter, REG_RXPKT_NUM,
1785                                 (rtw_read32(padapter, REG_RXPKT_NUM) & (~RW_RELEASE_EN)));
1786
1787                         SetFwRelatedForWoWLAN8723b(padapter, false);
1788
1789 #ifdef CONFIG_GPIO_WAKEUP
1790                 DBG_871X_LEVEL(_drv_always_, "Set Wake GPIO to high for default.\n");
1791                 HalSetOutPutGPIO(padapter, WAKEUP_GPIO_IDX, 1);
1792 #endif /* CONFIG_GPIO_WAKEUP */
1793                 rtl8723b_set_FwJoinBssRpt_cmd(padapter, RT_MEDIA_CONNECT);
1794                 issue_beacon(padapter, 0);
1795                 break;
1796                 default:
1797                         break;
1798         }
1799 }
1800         break;
1801 #endif /* CONFIG_AP_WOWLAN */
1802         case HW_VAR_DM_IN_LPS:
1803                 rtl8723b_hal_dm_in_lps(padapter);
1804                 break;
1805         default:
1806                 SetHwReg8723B(padapter, variable, val);
1807                 break;
1808         }
1809 }
1810
1811 /*
1812  * If variable not handled here,
1813  * some variables will be processed in GetHwReg8723B()
1814  */
1815 static void GetHwReg8723BS(struct adapter *padapter, u8 variable, u8 *val)
1816 {
1817         switch (variable) {
1818         case HW_VAR_CPWM:
1819                 *val = rtw_read8(padapter, SDIO_LOCAL_BASE|SDIO_REG_HCPWM1_8723B);
1820                 break;
1821
1822         case HW_VAR_FW_PS_STATE:
1823                 {
1824                         /* 3. read dword 0x88               driver read fw ps state */
1825                         *((u16 *)val) = rtw_read16(padapter, 0x88);
1826                 }
1827                 break;
1828         default:
1829                 GetHwReg8723B(padapter, variable, val);
1830                 break;
1831         }
1832 }
1833
1834 static void SetHwRegWithBuf8723B(struct adapter *padapter, u8 variable, u8 *pbuf, int len)
1835 {
1836         switch (variable) {
1837         case HW_VAR_C2H_HANDLE:
1838                 /* DBG_8192C("%s len =%d\n", __func__, len); */
1839                 C2HPacketHandler_8723B(padapter, pbuf, len);
1840                 break;
1841         default:
1842                 break;
1843         }
1844 }
1845
1846 /*  */
1847 /*      Description: */
1848 /*              Query setting of specified variable. */
1849 /*  */
1850 static u8 GetHalDefVar8723BSDIO(
1851         struct adapter *Adapter, enum HAL_DEF_VARIABLE eVariable, void *pValue
1852 )
1853 {
1854         u8      bResult = _SUCCESS;
1855
1856         switch (eVariable) {
1857         case HAL_DEF_IS_SUPPORT_ANT_DIV:
1858                 break;
1859         case HAL_DEF_CURRENT_ANTENNA:
1860                 break;
1861         case HW_VAR_MAX_RX_AMPDU_FACTOR:
1862                 /*  Stanley@BB.SD3 suggests 16K can get stable performance */
1863                 /*  coding by Lucas@20130730 */
1864                 *(u32 *)pValue = MAX_AMPDU_FACTOR_16K;
1865                 break;
1866         default:
1867                 bResult = GetHalDefVar8723B(Adapter, eVariable, pValue);
1868                 break;
1869         }
1870
1871         return bResult;
1872 }
1873
1874 /*  */
1875 /*      Description: */
1876 /*              Change default setting of specified variable. */
1877 /*  */
1878 static u8 SetHalDefVar8723BSDIO(struct adapter *Adapter,
1879                                 enum HAL_DEF_VARIABLE eVariable, void *pValue)
1880 {
1881         return SetHalDefVar8723B(Adapter, eVariable, pValue);
1882 }
1883
1884 void rtl8723bs_set_hal_ops(struct adapter *padapter)
1885 {
1886         struct hal_ops *pHalFunc = &padapter->HalFunc;
1887
1888         rtl8723b_set_hal_ops(pHalFunc);
1889
1890         pHalFunc->hal_init = &rtl8723bs_hal_init;
1891         pHalFunc->hal_deinit = &rtl8723bs_hal_deinit;
1892
1893         pHalFunc->inirp_init = &rtl8723bs_inirp_init;
1894         pHalFunc->inirp_deinit = &rtl8723bs_inirp_deinit;
1895
1896         pHalFunc->init_xmit_priv = &rtl8723bs_init_xmit_priv;
1897         pHalFunc->free_xmit_priv = &rtl8723bs_free_xmit_priv;
1898
1899         pHalFunc->init_recv_priv = &rtl8723bs_init_recv_priv;
1900         pHalFunc->free_recv_priv = &rtl8723bs_free_recv_priv;
1901
1902         pHalFunc->init_default_value = &rtl8723bs_init_default_value;
1903         pHalFunc->intf_chip_configure = &rtl8723bs_interface_configure;
1904         pHalFunc->read_adapter_info = &ReadAdapterInfo8723BS;
1905
1906         pHalFunc->enable_interrupt = &EnableInterrupt8723BSdio;
1907         pHalFunc->disable_interrupt = &DisableInterrupt8723BSdio;
1908         pHalFunc->check_ips_status = &CheckIPSStatus;
1909 #ifdef CONFIG_WOWLAN
1910         pHalFunc->clear_interrupt = &ClearInterrupt8723BSdio;
1911 #endif
1912         pHalFunc->SetHwRegHandler = &SetHwReg8723BS;
1913         pHalFunc->GetHwRegHandler = &GetHwReg8723BS;
1914         pHalFunc->SetHwRegHandlerWithBuf = &SetHwRegWithBuf8723B;
1915         pHalFunc->GetHalDefVarHandler = &GetHalDefVar8723BSDIO;
1916         pHalFunc->SetHalDefVarHandler = &SetHalDefVar8723BSDIO;
1917
1918         pHalFunc->hal_xmit = &rtl8723bs_hal_xmit;
1919         pHalFunc->mgnt_xmit = &rtl8723bs_mgnt_xmit;
1920         pHalFunc->hal_xmitframe_enqueue = &rtl8723bs_hal_xmitframe_enqueue;
1921
1922 #if defined(CONFIG_CHECK_BT_HANG)
1923         pHalFunc->hal_init_checkbthang_workqueue = &rtl8723bs_init_checkbthang_workqueue;
1924         pHalFunc->hal_free_checkbthang_workqueue = &rtl8723bs_free_checkbthang_workqueue;
1925         pHalFunc->hal_cancle_checkbthang_workqueue = &rtl8723bs_cancle_checkbthang_workqueue;
1926         pHalFunc->hal_checke_bt_hang = &rtl8723bs_hal_check_bt_hang;
1927 #endif
1928 }