drivers/staging/rtlwifi/phydm/phydm.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 /* ************************************************************
  16  * include files
  17  * *************************************************************/
  18
  19 #include "mp_precomp.h"
  20 #include "phydm_precomp.h"
  21
  22 static const u16 db_invert_table[12][8] = {
  23         {1, 1, 1, 2, 2, 2, 2, 3},
  24         {3, 3, 4, 4, 4, 5, 6, 6},
  25         {7, 8, 9, 10, 11, 13, 14, 16},
  26         {18, 20, 22, 25, 28, 32, 35, 40},
  27         {45, 50, 56, 63, 71, 79, 89, 100},
  28         {112, 126, 141, 158, 178, 200, 224, 251},
  29         {282, 316, 355, 398, 447, 501, 562, 631},
  30         {708, 794, 891, 1000, 1122, 1259, 1413, 1585},
  31         {1778, 1995, 2239, 2512, 2818, 3162, 3548, 3981},
  32         {4467, 5012, 5623, 6310, 7079, 7943, 8913, 10000},
  33         {11220, 12589, 14125, 15849, 17783, 19953, 22387, 25119},
  34         {28184, 31623, 35481, 39811, 44668, 50119, 56234, 65535},
  35 };
  36
  37 /* ************************************************************
  38  * Local Function predefine.
  39  * *************************************************************/
  40
  41 /* START------------COMMON INFO RELATED--------------- */
  42
  43 static void odm_update_power_training_state(struct phy_dm_struct *dm);
  44
  45 /* ************************************************************
  46  * 3 Export Interface
  47  * *************************************************************/
  48
  49 /*Y = 10*log(X)*/
  50 s32 odm_pwdb_conversion(s32 X, u32 total_bit, u32 decimal_bit)
  51 {
  52         s32 Y, integer = 0, decimal = 0;
  53         u32 i;
  54
  55         if (X == 0)
  56                 X = 1; /* log2(x), x can't be 0 */
  57
  58         for (i = (total_bit - 1); i > 0; i--) {
  59                 if (X & BIT(i)) {
  60                         integer = i;
  61                         if (i > 0) {
  62                                 /* decimal is 0.5dB*3=1.5dB~=2dB */
  63                                 decimal = (X & BIT(i - 1)) ? 2 : 0;
  64                         }
  65                         break;
  66                 }
  67         }
  68
  69         Y = 3 * (integer - decimal_bit) + decimal; /* 10*log(x)=3*log2(x), */
  70
  71         return Y;
  72 }
  73
  74 s32 odm_sign_conversion(s32 value, u32 total_bit)
  75 {
  76         if (value & BIT(total_bit - 1))
  77                 value -= BIT(total_bit);
  78         return value;
  79 }
  80
  81 void phydm_seq_sorting(void *dm_void, u32 *value, u32 *rank_idx, u32 *idx_out,
  82                        u8 seq_length)
  83 {
  84         u8 i = 0, j = 0;
  85         u32 tmp_a, tmp_b;
  86         u32 tmp_idx_a, tmp_idx_b;
  87
  88         for (i = 0; i < seq_length; i++) {
  89                 rank_idx[i] = i;
  90                 /**/
  91         }
  92
  93         for (i = 0; i < (seq_length - 1); i++) {
  94                 for (j = 0; j < (seq_length - 1 - i); j++) {
  95                         tmp_a = value[j];
  96                         tmp_b = value[j + 1];
  97
  98                         tmp_idx_a = rank_idx[j];
  99                         tmp_idx_b = rank_idx[j + 1];
 100
 101                         if (tmp_a < tmp_b) {
 102                                 value[j] = tmp_b;
 103                                 value[j + 1] = tmp_a;
 104
 105                                 rank_idx[j] = tmp_idx_b;
 106                                 rank_idx[j + 1] = tmp_idx_a;
 107                         }
 108                 }
 109         }
 110
 111         for (i = 0; i < seq_length; i++) {
 112                 idx_out[rank_idx[i]] = i + 1;
 113                 /**/
 114         }
 115 }
 116
 117 void odm_init_mp_driver_status(struct phy_dm_struct *dm)
 118 {
 119         dm->mp_mode = false;
 120 }
 121
 122 static void odm_update_mp_driver_status(struct phy_dm_struct *dm)
 123 {
 124         /* Do nothing. */
 125 }
 126
 127 static void phydm_init_trx_antenna_setting(struct phy_dm_struct *dm)
 128 {
 129         /*#if (RTL8814A_SUPPORT == 1)*/
 130
 131         if (dm->support_ic_type & (ODM_RTL8814A)) {
 132                 u8 rx_ant = 0, tx_ant = 0;
 133
 134                 rx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
 135                                             ODM_BIT(BB_RX_PATH, dm));
 136                 tx_ant = (u8)odm_get_bb_reg(dm, ODM_REG(BB_TX_PATH, dm),
 137                                             ODM_BIT(BB_TX_PATH, dm));
 138                 dm->tx_ant_status = (tx_ant & 0xf);
 139                 dm->rx_ant_status = (rx_ant & 0xf);
 140         } else if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8821C |
 141                                           ODM_RTL8710B)) { /* JJ ADD 20161014 */
 142                 dm->tx_ant_status = 0x1;
 143                 dm->rx_ant_status = 0x1;
 144         }
 145         /*#endif*/
 146 }
 147
 148 static void phydm_traffic_load_decision(void *dm_void)
 149 {
 150         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 151
 152         /*---TP & Traffic-load calculation---*/
 153
 154         if (dm->last_tx_ok_cnt > *dm->num_tx_bytes_unicast)
 155                 dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
 156
 157         if (dm->last_rx_ok_cnt > *dm->num_rx_bytes_unicast)
 158                 dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
 159
 160         dm->cur_tx_ok_cnt = *dm->num_tx_bytes_unicast - dm->last_tx_ok_cnt;
 161         dm->cur_rx_ok_cnt = *dm->num_rx_bytes_unicast - dm->last_rx_ok_cnt;
 162         dm->last_tx_ok_cnt = *dm->num_tx_bytes_unicast;
 163         dm->last_rx_ok_cnt = *dm->num_rx_bytes_unicast;
 164
 165         dm->tx_tp = ((dm->tx_tp) >> 1) +
 166                     (u32)(((dm->cur_tx_ok_cnt) >> 18) >>
 167                           1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
 168         dm->rx_tp = ((dm->rx_tp) >> 1) +
 169                     (u32)(((dm->cur_rx_ok_cnt) >> 18) >>
 170                           1); /* <<3(8bit), >>20(10^6,M), >>1(2sec)*/
 171         dm->total_tp = dm->tx_tp + dm->rx_tp;
 172
 173         dm->pre_traffic_load = dm->traffic_load;
 174
 175         if (dm->cur_tx_ok_cnt > 1875000 ||
 176             dm->cur_rx_ok_cnt >
 177                     1875000) { /* ( 1.875M * 8bit ) / 2sec= 7.5M bits /sec )*/
 178
 179                 dm->traffic_load = TRAFFIC_HIGH;
 180                 /**/
 181         } else if (
 182                 dm->cur_tx_ok_cnt > 500000 ||
 183                 dm->cur_rx_ok_cnt >
 184                         500000) { /*( 0.5M * 8bit ) / 2sec =  2M bits /sec )*/
 185
 186                 dm->traffic_load = TRAFFIC_MID;
 187                 /**/
 188         } else if (
 189                 dm->cur_tx_ok_cnt > 100000 ||
 190                 dm->cur_rx_ok_cnt >
 191                         100000) { /*( 0.1M * 8bit ) / 2sec =  0.4M bits /sec )*/
 192
 193                 dm->traffic_load = TRAFFIC_LOW;
 194                 /**/
 195         } else {
 196                 dm->traffic_load = TRAFFIC_ULTRA_LOW;
 197                 /**/
 198         }
 199 }
 200
 201 static void phydm_config_ofdm_tx_path(struct phy_dm_struct *dm, u32 path) {}
 202
 203 void phydm_config_ofdm_rx_path(struct phy_dm_struct *dm, u32 path)
 204 {
 205         u8 ofdm_rx_path = 0;
 206
 207         if (dm->support_ic_type & (ODM_RTL8192E)) {
 208         } else if (dm->support_ic_type & (ODM_RTL8812 | ODM_RTL8822B)) {
 209                 if (path == PHYDM_A) {
 210                         ofdm_rx_path = 1;
 211                         /**/
 212                 } else if (path == PHYDM_B) {
 213                         ofdm_rx_path = 2;
 214                         /**/
 215                 } else if (path == PHYDM_AB) {
 216                         ofdm_rx_path = 3;
 217                         /**/
 218                 }
 219
 220                 odm_set_bb_reg(dm, 0x808, MASKBYTE0,
 221                                ((ofdm_rx_path << 4) | ofdm_rx_path));
 222         }
 223 }
 224
 225 static void phydm_config_cck_rx_antenna_init(struct phy_dm_struct *dm) {}
 226
 227 static void phydm_config_cck_rx_path(struct phy_dm_struct *dm, u8 path,
 228                                      u8 path_div_en)
 229 {
 230 }
 231
 232 void phydm_config_trx_path(void *dm_void, u32 *const dm_value, u32 *_used,
 233                            char *output, u32 *_out_len)
 234 {
 235         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 236         u32 used = *_used;
 237         u32 out_len = *_out_len;
 238
 239         /* CCK */
 240         if (dm_value[0] == 0) {
 241                 if (dm_value[1] == 1) { /*TX*/
 242                         if (dm_value[2] == 1)
 243                                 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x8);
 244                         else if (dm_value[2] == 2)
 245                                 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0x4);
 246                         else if (dm_value[2] == 3)
 247                                 odm_set_bb_reg(dm, 0xa04, 0xf0000000, 0xc);
 248                 } else if (dm_value[1] == 2) { /*RX*/
 249
 250                         phydm_config_cck_rx_antenna_init(dm);
 251
 252                         if (dm_value[2] == 1)
 253                                 phydm_config_cck_rx_path(dm, PHYDM_A,
 254                                                          CCA_PATHDIV_DISABLE);
 255                         else if (dm_value[2] == 2)
 256                                 phydm_config_cck_rx_path(dm, PHYDM_B,
 257                                                          CCA_PATHDIV_DISABLE);
 258                         else if (dm_value[2] == 3 &&
 259                                  dm_value[3] == 1) /*enable path diversity*/
 260                                 phydm_config_cck_rx_path(dm, PHYDM_AB,
 261                                                          CCA_PATHDIV_ENABLE);
 262                         else if (dm_value[2] == 3 && dm_value[3] != 1)
 263                                 phydm_config_cck_rx_path(dm, PHYDM_B,
 264                                                          CCA_PATHDIV_DISABLE);
 265                 }
 266         }
 267         /* OFDM */
 268         else if (dm_value[0] == 1) {
 269                 if (dm_value[1] == 1) { /*TX*/
 270                         phydm_config_ofdm_tx_path(dm, dm_value[2]);
 271                         /**/
 272                 } else if (dm_value[1] == 2) { /*RX*/
 273                         phydm_config_ofdm_rx_path(dm, dm_value[2]);
 274                         /**/
 275                 }
 276         }
 277
 278         PHYDM_SNPRINTF(
 279                 output + used, out_len - used,
 280                 "PHYDM Set path [%s] [%s] = [%s%s%s%s]\n",
 281                 (dm_value[0] == 1) ? "OFDM" : "CCK",
 282                 (dm_value[1] == 1) ? "TX" : "RX",
 283                 (dm_value[2] & 0x1) ? "A" : "", (dm_value[2] & 0x2) ? "B" : "",
 284                 (dm_value[2] & 0x4) ? "C" : "", (dm_value[2] & 0x8) ? "D" : "");
 285 }
 286
 287 static void phydm_init_cck_setting(struct phy_dm_struct *dm)
 288 {
 289         dm->is_cck_high_power = (bool)odm_get_bb_reg(
 290                 dm, ODM_REG(CCK_RPT_FORMAT, dm), ODM_BIT(CCK_RPT_FORMAT, dm));
 291
 292         /* JJ ADD 20161014 */
 293         /* JJ ADD 20161014 */
 294         if (dm->support_ic_type & (ODM_RTL8723D | ODM_RTL8822B | ODM_RTL8197F |
 295                                    ODM_RTL8821C | ODM_RTL8710B))
 296                 dm->cck_new_agc = odm_get_bb_reg(dm, 0xa9c, BIT(17)) ?
 297                                           true :
 298                                           false; /*1: new agc  0: old agc*/
 299         else
 300                 dm->cck_new_agc = false;
 301 }
 302
 303 static void phydm_init_soft_ml_setting(struct phy_dm_struct *dm)
 304 {
 305         if (!dm->mp_mode) {
 306                 if (dm->support_ic_type & ODM_RTL8822B)
 307                         odm_set_bb_reg(dm, 0x19a8, MASKDWORD, 0xc10a0000);
 308         }
 309 }
 310
 311 static void phydm_init_hw_info_by_rfe(struct phy_dm_struct *dm)
 312 {
 313         if (dm->support_ic_type & ODM_RTL8822B)
 314                 phydm_init_hw_info_by_rfe_type_8822b(dm);
 315 }
 316
 317 static void odm_common_info_self_init(struct phy_dm_struct *dm)
 318 {
 319         phydm_init_cck_setting(dm);
 320         dm->rf_path_rx_enable = (u8)odm_get_bb_reg(dm, ODM_REG(BB_RX_PATH, dm),
 321                                                    ODM_BIT(BB_RX_PATH, dm));
 322         odm_init_mp_driver_status(dm);
 323         phydm_init_trx_antenna_setting(dm);
 324         phydm_init_soft_ml_setting(dm);
 325
 326         dm->phydm_period = PHYDM_WATCH_DOG_PERIOD;
 327         dm->phydm_sys_up_time = 0;
 328
 329         if (dm->support_ic_type & ODM_IC_1SS)
 330                 dm->num_rf_path = 1;
 331         else if (dm->support_ic_type & ODM_IC_2SS)
 332                 dm->num_rf_path = 2;
 333         else if (dm->support_ic_type & ODM_IC_3SS)
 334                 dm->num_rf_path = 3;
 335         else if (dm->support_ic_type & ODM_IC_4SS)
 336                 dm->num_rf_path = 4;
 337
 338         dm->tx_rate = 0xFF;
 339
 340         dm->number_linked_client = 0;
 341         dm->pre_number_linked_client = 0;
 342         dm->number_active_client = 0;
 343         dm->pre_number_active_client = 0;
 344
 345         dm->last_tx_ok_cnt = 0;
 346         dm->last_rx_ok_cnt = 0;
 347         dm->tx_tp = 0;
 348         dm->rx_tp = 0;
 349         dm->total_tp = 0;
 350         dm->traffic_load = TRAFFIC_LOW;
 351
 352         dm->nbi_set_result = 0;
 353         dm->is_init_hw_info_by_rfe = false;
 354         dm->pre_dbg_priority = BB_DBGPORT_RELEASE;
 355 }
 356
 357 static void odm_common_info_self_update(struct phy_dm_struct *dm)
 358 {
 359         u8 entry_cnt = 0, num_active_client = 0;
 360         u32 i, one_entry_macid = 0;
 361         struct rtl_sta_info *entry;
 362
 363         /* THis variable cannot be used because it is wrong*/
 364         if (*dm->band_width == ODM_BW40M) {
 365                 if (*dm->sec_ch_offset == 1)
 366                         dm->control_channel = *dm->channel - 2;
 367                 else if (*dm->sec_ch_offset == 2)
 368                         dm->control_channel = *dm->channel + 2;
 369         } else {
 370                 dm->control_channel = *dm->channel;
 371         }
 372
 373         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 374                 entry = dm->odm_sta_info[i];
 375                 if (IS_STA_VALID(entry)) {
 376                         entry_cnt++;
 377                         if (entry_cnt == 1)
 378                                 one_entry_macid = i;
 379                 }
 380         }
 381
 382         if (entry_cnt == 1) {
 383                 dm->is_one_entry_only = true;
 384                 dm->one_entry_macid = one_entry_macid;
 385         } else {
 386                 dm->is_one_entry_only = false;
 387         }
 388
 389         dm->pre_number_linked_client = dm->number_linked_client;
 390         dm->pre_number_active_client = dm->number_active_client;
 391
 392         dm->number_linked_client = entry_cnt;
 393         dm->number_active_client = num_active_client;
 394
 395         /* Update MP driver status*/
 396         odm_update_mp_driver_status(dm);
 397
 398         /*Traffic load information update*/
 399         phydm_traffic_load_decision(dm);
 400
 401         dm->phydm_sys_up_time += dm->phydm_period;
 402 }
 403
 404 static void odm_common_info_self_reset(struct phy_dm_struct *dm)
 405 {
 406         dm->phy_dbg_info.num_qry_beacon_pkt = 0;
 407 }
 408
 409 void *phydm_get_structure(struct phy_dm_struct *dm, u8 structure_type)
 410
 411 {
 412         void *p_struct = NULL;
 413
 414         switch (structure_type) {
 415         case PHYDM_FALSEALMCNT:
 416                 p_struct = &dm->false_alm_cnt;
 417                 break;
 418
 419         case PHYDM_CFOTRACK:
 420                 p_struct = &dm->dm_cfo_track;
 421                 break;
 422
 423         case PHYDM_ADAPTIVITY:
 424                 p_struct = &dm->adaptivity;
 425                 break;
 426
 427         default:
 428                 break;
 429         }
 430
 431         return p_struct;
 432 }
 433
 434 static void odm_hw_setting(struct phy_dm_struct *dm)
 435 {
 436         if (dm->support_ic_type & ODM_RTL8822B)
 437                 phydm_hwsetting_8822b(dm);
 438 }
 439
 440 static void phydm_supportability_init(void *dm_void)
 441 {
 442         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 443         u32 support_ability = 0;
 444
 445         if (dm->support_ic_type != ODM_RTL8821C)
 446                 return;
 447
 448         switch (dm->support_ic_type) {
 449         /*---------------AC Series-------------------*/
 450
 451         case ODM_RTL8822B:
 452                 support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
 453                                    ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
 454                                    ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
 455                                    ODM_RF_TX_PWR_TRACK;
 456                 break;
 457
 458         default:
 459                 support_ability |= ODM_BB_DIG | ODM_BB_FA_CNT | ODM_BB_CCK_PD |
 460                                    ODM_BB_CFO_TRACKING | ODM_BB_RATE_ADAPTIVE |
 461                                    ODM_BB_RSSI_MONITOR | ODM_BB_RA_MASK |
 462                                    ODM_RF_TX_PWR_TRACK;
 463
 464                 ODM_RT_TRACE(dm, ODM_COMP_UNCOND,
 465                              "[Warning] Supportability Init Warning !!!\n");
 466                 break;
 467         }
 468
 469         if (*dm->enable_antdiv)
 470                 support_ability |= ODM_BB_ANT_DIV;
 471
 472         if (*dm->enable_adaptivity) {
 473                 ODM_RT_TRACE(dm, ODM_COMP_INIT,
 474                              "ODM adaptivity is set to Enabled!!!\n");
 475
 476                 support_ability |= ODM_BB_ADAPTIVITY;
 477
 478         } else {
 479                 ODM_RT_TRACE(dm, ODM_COMP_INIT,
 480                              "ODM adaptivity is set to disnabled!!!\n");
 481                 /**/
 482         }
 483
 484         ODM_RT_TRACE(dm, ODM_COMP_INIT, "PHYDM support_ability = ((0x%x))\n",
 485                      support_ability);
 486         odm_cmn_info_init(dm, ODM_CMNINFO_ABILITY, support_ability);
 487 }
 488
 489 /*
 490  * 2011/09/21 MH Add to describe different team necessary resource allocate??
 491  */
 492 void odm_dm_init(struct phy_dm_struct *dm)
 493 {
 494         phydm_supportability_init(dm);
 495         odm_common_info_self_init(dm);
 496         odm_dig_init(dm);
 497         phydm_nhm_counter_statistics_init(dm);
 498         phydm_adaptivity_init(dm);
 499         phydm_ra_info_init(dm);
 500         odm_rate_adaptive_mask_init(dm);
 501         odm_cfo_tracking_init(dm);
 502         odm_edca_turbo_init(dm);
 503         odm_rssi_monitor_init(dm);
 504         phydm_rf_init(dm);
 505         odm_txpowertracking_init(dm);
 506
 507         if (dm->support_ic_type & ODM_RTL8822B)
 508                 phydm_txcurrentcalibration(dm);
 509
 510         odm_antenna_diversity_init(dm);
 511         odm_auto_channel_select_init(dm);
 512         odm_dynamic_tx_power_init(dm);
 513         phydm_init_ra_info(dm);
 514         adc_smp_init(dm);
 515
 516         phydm_beamforming_init(dm);
 517
 518         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 519                 /* 11n series */
 520                 odm_dynamic_bb_power_saving_init(dm);
 521         }
 522
 523         phydm_psd_init(dm);
 524 }
 525
 526 void odm_dm_reset(struct phy_dm_struct *dm)
 527 {
 528         struct dig_thres *dig_tab = &dm->dm_dig_table;
 529
 530         odm_ant_div_reset(dm);
 531         phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);
 532 }
 533
 534 void phydm_support_ability_debug(void *dm_void, u32 *const dm_value, u32 *_used,
 535                                  char *output, u32 *_out_len)
 536 {
 537         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 538         u32 pre_support_ability;
 539         u32 used = *_used;
 540         u32 out_len = *_out_len;
 541
 542         pre_support_ability = dm->support_ability;
 543         PHYDM_SNPRINTF(output + used, out_len - used, "\n%s\n",
 544                        "================================");
 545         if (dm_value[0] == 100) {
 546                 PHYDM_SNPRINTF(output + used, out_len - used,
 547                                "[Supportability] PhyDM Selection\n");
 548                 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
 549                                "================================");
 550                 PHYDM_SNPRINTF(
 551                         output + used, out_len - used, "00. (( %s ))DIG\n",
 552                         ((dm->support_ability & ODM_BB_DIG) ? ("V") : (".")));
 553                 PHYDM_SNPRINTF(
 554                         output + used, out_len - used, "01. (( %s ))RA_MASK\n",
 555                         ((dm->support_ability & ODM_BB_RA_MASK) ? ("V") :
 556                                                                   (".")));
 557                 PHYDM_SNPRINTF(output + used, out_len - used,
 558                                "02. (( %s ))DYNAMIC_TXPWR\n",
 559                                ((dm->support_ability & ODM_BB_DYNAMIC_TXPWR) ?
 560                                         ("V") :
 561                                         (".")));
 562                 PHYDM_SNPRINTF(output + used, out_len - used,
 563                                "03. (( %s ))FA_CNT\n",
 564                                ((dm->support_ability & ODM_BB_FA_CNT) ? ("V") :
 565                                                                         (".")));
 566                 PHYDM_SNPRINTF(output + used, out_len - used,
 567                                "04. (( %s ))RSSI_MONITOR\n",
 568                                ((dm->support_ability & ODM_BB_RSSI_MONITOR) ?
 569                                         ("V") :
 570                                         (".")));
 571                 PHYDM_SNPRINTF(output + used, out_len - used,
 572                                "05. (( %s ))CCK_PD\n",
 573                                ((dm->support_ability & ODM_BB_CCK_PD) ? ("V") :
 574                                                                         (".")));
 575                 PHYDM_SNPRINTF(
 576                         output + used, out_len - used, "06. (( %s ))ANT_DIV\n",
 577                         ((dm->support_ability & ODM_BB_ANT_DIV) ? ("V") :
 578                                                                   (".")));
 579                 PHYDM_SNPRINTF(output + used, out_len - used,
 580                                "08. (( %s ))PWR_TRAIN\n",
 581                                ((dm->support_ability & ODM_BB_PWR_TRAIN) ?
 582                                         ("V") :
 583                                         (".")));
 584                 PHYDM_SNPRINTF(output + used, out_len - used,
 585                                "09. (( %s ))RATE_ADAPTIVE\n",
 586                                ((dm->support_ability & ODM_BB_RATE_ADAPTIVE) ?
 587                                         ("V") :
 588                                         (".")));
 589                 PHYDM_SNPRINTF(
 590                         output + used, out_len - used, "10. (( %s ))PATH_DIV\n",
 591                         ((dm->support_ability & ODM_BB_PATH_DIV) ? ("V") :
 592                                                                    (".")));
 593                 PHYDM_SNPRINTF(output + used, out_len - used,
 594                                "13. (( %s ))ADAPTIVITY\n",
 595                                ((dm->support_ability & ODM_BB_ADAPTIVITY) ?
 596                                         ("V") :
 597                                         (".")));
 598                 PHYDM_SNPRINTF(output + used, out_len - used,
 599                                "14. (( %s ))struct cfo_tracking\n",
 600                                ((dm->support_ability & ODM_BB_CFO_TRACKING) ?
 601                                         ("V") :
 602                                         (".")));
 603                 PHYDM_SNPRINTF(
 604                         output + used, out_len - used, "15. (( %s ))NHM_CNT\n",
 605                         ((dm->support_ability & ODM_BB_NHM_CNT) ? ("V") :
 606                                                                   (".")));
 607                 PHYDM_SNPRINTF(output + used, out_len - used,
 608                                "16. (( %s ))PRIMARY_CCA\n",
 609                                ((dm->support_ability & ODM_BB_PRIMARY_CCA) ?
 610                                         ("V") :
 611                                         (".")));
 612                 PHYDM_SNPRINTF(
 613                         output + used, out_len - used, "17. (( %s ))TXBF\n",
 614                         ((dm->support_ability & ODM_BB_TXBF) ? ("V") : (".")));
 615                 PHYDM_SNPRINTF(output + used, out_len - used,
 616                                "18. (( %s ))DYNAMIC_ARFR\n",
 617                                ((dm->support_ability & ODM_BB_DYNAMIC_ARFR) ?
 618                                         ("V") :
 619                                         (".")));
 620                 PHYDM_SNPRINTF(output + used, out_len - used,
 621                                "20. (( %s ))EDCA_TURBO\n",
 622                                ((dm->support_ability & ODM_MAC_EDCA_TURBO) ?
 623                                         ("V") :
 624                                         (".")));
 625                 PHYDM_SNPRINTF(output + used, out_len - used,
 626                                "21. (( %s ))DYNAMIC_RX_PATH\n",
 627                                ((dm->support_ability & ODM_BB_DYNAMIC_RX_PATH) ?
 628                                         ("V") :
 629                                         (".")));
 630                 PHYDM_SNPRINTF(output + used, out_len - used,
 631                                "24. (( %s ))TX_PWR_TRACK\n",
 632                                ((dm->support_ability & ODM_RF_TX_PWR_TRACK) ?
 633                                         ("V") :
 634                                         (".")));
 635                 PHYDM_SNPRINTF(output + used, out_len - used,
 636                                "25. (( %s ))RX_GAIN_TRACK\n",
 637                                ((dm->support_ability & ODM_RF_RX_GAIN_TRACK) ?
 638                                         ("V") :
 639                                         (".")));
 640                 PHYDM_SNPRINTF(output + used, out_len - used,
 641                                "26. (( %s ))RF_CALIBRATION\n",
 642                                ((dm->support_ability & ODM_RF_CALIBRATION) ?
 643                                         ("V") :
 644                                         (".")));
 645                 PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
 646                                "================================");
 647         } else {
 648                 if (dm_value[1] == 1) { /* enable */
 649                         dm->support_ability |= BIT(dm_value[0]);
 650                 } else if (dm_value[1] == 2) /* disable */
 651                         dm->support_ability &= ~(BIT(dm_value[0]));
 652                 else {
 653                         PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
 654                                        "[Warning!!!]  1:enable,  2:disable");
 655                 }
 656         }
 657         PHYDM_SNPRINTF(output + used, out_len - used,
 658                        "pre-support_ability  =  0x%x\n", pre_support_ability);
 659         PHYDM_SNPRINTF(output + used, out_len - used,
 660                        "Curr-support_ability =  0x%x\n", dm->support_ability);
 661         PHYDM_SNPRINTF(output + used, out_len - used, "%s\n",
 662                        "================================");
 663 }
 664
 665 void phydm_watchdog_mp(struct phy_dm_struct *dm) {}
 666 /*
 667  * 2011/09/20 MH This is the entry pointer for all team to execute HW outsrc DM.
 668  * You can not add any dummy function here, be care, you can only use DM struct
 669  * to perform any new ODM_DM.
 670  */
 671 void odm_dm_watchdog(struct phy_dm_struct *dm)
 672 {
 673         odm_common_info_self_update(dm);
 674         phydm_basic_dbg_message(dm);
 675         odm_hw_setting(dm);
 676
 677         odm_false_alarm_counter_statistics(dm);
 678         phydm_noisy_detection(dm);
 679
 680         odm_rssi_monitor_check(dm);
 681
 682         if (*dm->is_power_saving) {
 683                 odm_dig_by_rssi_lps(dm);
 684                 phydm_adaptivity(dm);
 685                 odm_antenna_diversity(
 686                         dm); /*enable AntDiv in PS mode, request from SD4 Jeff*/
 687                 ODM_RT_TRACE(dm, ODM_COMP_COMMON,
 688                              "DMWatchdog in power saving mode\n");
 689                 return;
 690         }
 691
 692         phydm_check_adaptivity(dm);
 693         odm_update_power_training_state(dm);
 694         odm_DIG(dm);
 695         phydm_adaptivity(dm);
 696         odm_cck_packet_detection_thresh(dm);
 697
 698         phydm_ra_info_watchdog(dm);
 699         odm_edca_turbo_check(dm);
 700         odm_cfo_tracking(dm);
 701         odm_dynamic_tx_power(dm);
 702         odm_antenna_diversity(dm);
 703
 704         phydm_beamforming_watchdog(dm);
 705
 706         phydm_rf_watchdog(dm);
 707
 708         odm_dtc(dm);
 709
 710         odm_common_info_self_reset(dm);
 711 }
 712
 713 /*
 714  * Init /.. Fixed HW value. Only init time.
 715  */
 716 void odm_cmn_info_init(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 717                        u32 value)
 718 {
 719         /* This section is used for init value */
 720         switch (cmn_info) {
 721         /* Fixed ODM value. */
 722         case ODM_CMNINFO_ABILITY:
 723                 dm->support_ability = (u32)value;
 724                 break;
 725
 726         case ODM_CMNINFO_RF_TYPE:
 727                 dm->rf_type = (u8)value;
 728                 break;
 729
 730         case ODM_CMNINFO_PLATFORM:
 731                 dm->support_platform = (u8)value;
 732                 break;
 733
 734         case ODM_CMNINFO_INTERFACE:
 735                 dm->support_interface = (u8)value;
 736                 break;
 737
 738         case ODM_CMNINFO_MP_TEST_CHIP:
 739                 dm->is_mp_chip = (u8)value;
 740                 break;
 741
 742         case ODM_CMNINFO_IC_TYPE:
 743                 dm->support_ic_type = value;
 744                 break;
 745
 746         case ODM_CMNINFO_CUT_VER:
 747                 dm->cut_version = (u8)value;
 748                 break;
 749
 750         case ODM_CMNINFO_FAB_VER:
 751                 dm->fab_version = (u8)value;
 752                 break;
 753
 754         case ODM_CMNINFO_RFE_TYPE:
 755                 dm->rfe_type = (u8)value;
 756                 phydm_init_hw_info_by_rfe(dm);
 757                 break;
 758
 759         case ODM_CMNINFO_RF_ANTENNA_TYPE:
 760                 dm->ant_div_type = (u8)value;
 761                 break;
 762
 763         case ODM_CMNINFO_WITH_EXT_ANTENNA_SWITCH:
 764                 dm->with_extenal_ant_switch = (u8)value;
 765                 break;
 766
 767         case ODM_CMNINFO_BE_FIX_TX_ANT:
 768                 dm->dm_fat_table.b_fix_tx_ant = (u8)value;
 769                 break;
 770
 771         case ODM_CMNINFO_BOARD_TYPE:
 772                 if (!dm->is_init_hw_info_by_rfe)
 773                         dm->board_type = (u8)value;
 774                 break;
 775
 776         case ODM_CMNINFO_PACKAGE_TYPE:
 777                 if (!dm->is_init_hw_info_by_rfe)
 778                         dm->package_type = (u8)value;
 779                 break;
 780
 781         case ODM_CMNINFO_EXT_LNA:
 782                 if (!dm->is_init_hw_info_by_rfe)
 783                         dm->ext_lna = (u8)value;
 784                 break;
 785
 786         case ODM_CMNINFO_5G_EXT_LNA:
 787                 if (!dm->is_init_hw_info_by_rfe)
 788                         dm->ext_lna_5g = (u8)value;
 789                 break;
 790
 791         case ODM_CMNINFO_EXT_PA:
 792                 if (!dm->is_init_hw_info_by_rfe)
 793                         dm->ext_pa = (u8)value;
 794                 break;
 795
 796         case ODM_CMNINFO_5G_EXT_PA:
 797                 if (!dm->is_init_hw_info_by_rfe)
 798                         dm->ext_pa_5g = (u8)value;
 799                 break;
 800
 801         case ODM_CMNINFO_GPA:
 802                 if (!dm->is_init_hw_info_by_rfe)
 803                         dm->type_gpa = (u16)value;
 804                 break;
 805
 806         case ODM_CMNINFO_APA:
 807                 if (!dm->is_init_hw_info_by_rfe)
 808                         dm->type_apa = (u16)value;
 809                 break;
 810
 811         case ODM_CMNINFO_GLNA:
 812                 if (!dm->is_init_hw_info_by_rfe)
 813                         dm->type_glna = (u16)value;
 814                 break;
 815
 816         case ODM_CMNINFO_ALNA:
 817                 if (!dm->is_init_hw_info_by_rfe)
 818                         dm->type_alna = (u16)value;
 819                 break;
 820
 821         case ODM_CMNINFO_EXT_TRSW:
 822                 if (!dm->is_init_hw_info_by_rfe)
 823                         dm->ext_trsw = (u8)value;
 824                 break;
 825         case ODM_CMNINFO_EXT_LNA_GAIN:
 826                 dm->ext_lna_gain = (u8)value;
 827                 break;
 828         case ODM_CMNINFO_PATCH_ID:
 829                 dm->patch_id = (u8)value;
 830                 break;
 831         case ODM_CMNINFO_BINHCT_TEST:
 832                 dm->is_in_hct_test = (bool)value;
 833                 break;
 834         case ODM_CMNINFO_BWIFI_TEST:
 835                 dm->wifi_test = (u8)value;
 836                 break;
 837         case ODM_CMNINFO_SMART_CONCURRENT:
 838                 dm->is_dual_mac_smart_concurrent = (bool)value;
 839                 break;
 840         case ODM_CMNINFO_DOMAIN_CODE_2G:
 841                 dm->odm_regulation_2_4g = (u8)value;
 842                 break;
 843         case ODM_CMNINFO_DOMAIN_CODE_5G:
 844                 dm->odm_regulation_5g = (u8)value;
 845                 break;
 846         case ODM_CMNINFO_CONFIG_BB_RF:
 847                 dm->config_bbrf = (bool)value;
 848                 break;
 849         case ODM_CMNINFO_IQKFWOFFLOAD:
 850                 dm->iqk_fw_offload = (u8)value;
 851                 break;
 852         case ODM_CMNINFO_IQKPAOFF:
 853                 dm->rf_calibrate_info.is_iqk_pa_off = (bool)value;
 854                 break;
 855         case ODM_CMNINFO_REGRFKFREEENABLE:
 856                 dm->rf_calibrate_info.reg_rf_kfree_enable = (u8)value;
 857                 break;
 858         case ODM_CMNINFO_RFKFREEENABLE:
 859                 dm->rf_calibrate_info.rf_kfree_enable = (u8)value;
 860                 break;
 861         case ODM_CMNINFO_NORMAL_RX_PATH_CHANGE:
 862                 dm->normal_rx_path = (u8)value;
 863                 break;
 864         case ODM_CMNINFO_EFUSE0X3D8:
 865                 dm->efuse0x3d8 = (u8)value;
 866                 break;
 867         case ODM_CMNINFO_EFUSE0X3D7:
 868                 dm->efuse0x3d7 = (u8)value;
 869                 break;
 870         /* To remove the compiler warning, must add an empty default statement
 871          * to handle the other values.
 872          */
 873         default:
 874                 /* do nothing */
 875                 break;
 876         }
 877 }
 878
 879 void odm_cmn_info_hook(struct phy_dm_struct *dm, enum odm_cmninfo cmn_info,
 880                        void *value)
 881 {
 882         /*  */
 883         /* Hook call by reference pointer. */
 884         /*  */
 885         switch (cmn_info) {
 886         /*  */
 887         /* Dynamic call by reference pointer. */
 888         /*  */
 889         case ODM_CMNINFO_MAC_PHY_MODE:
 890                 dm->mac_phy_mode = (u8 *)value;
 891                 break;
 892
 893         case ODM_CMNINFO_TX_UNI:
 894                 dm->num_tx_bytes_unicast = (u64 *)value;
 895                 break;
 896
 897         case ODM_CMNINFO_RX_UNI:
 898                 dm->num_rx_bytes_unicast = (u64 *)value;
 899                 break;
 900
 901         case ODM_CMNINFO_WM_MODE:
 902                 dm->wireless_mode = (u8 *)value;
 903                 break;
 904
 905         case ODM_CMNINFO_BAND:
 906                 dm->band_type = (u8 *)value;
 907                 break;
 908
 909         case ODM_CMNINFO_SEC_CHNL_OFFSET:
 910                 dm->sec_ch_offset = (u8 *)value;
 911                 break;
 912
 913         case ODM_CMNINFO_SEC_MODE:
 914                 dm->security = (u8 *)value;
 915                 break;
 916
 917         case ODM_CMNINFO_BW:
 918                 dm->band_width = (u8 *)value;
 919                 break;
 920
 921         case ODM_CMNINFO_CHNL:
 922                 dm->channel = (u8 *)value;
 923                 break;
 924
 925         case ODM_CMNINFO_DMSP_GET_VALUE:
 926                 dm->is_get_value_from_other_mac = (bool *)value;
 927                 break;
 928
 929         case ODM_CMNINFO_BUDDY_ADAPTOR:
 930                 dm->buddy_adapter = (void **)value;
 931                 break;
 932
 933         case ODM_CMNINFO_DMSP_IS_MASTER:
 934                 dm->is_master_of_dmsp = (bool *)value;
 935                 break;
 936
 937         case ODM_CMNINFO_SCAN:
 938                 dm->is_scan_in_process = (bool *)value;
 939                 break;
 940
 941         case ODM_CMNINFO_POWER_SAVING:
 942                 dm->is_power_saving = (bool *)value;
 943                 break;
 944
 945         case ODM_CMNINFO_ONE_PATH_CCA:
 946                 dm->one_path_cca = (u8 *)value;
 947                 break;
 948
 949         case ODM_CMNINFO_DRV_STOP:
 950                 dm->is_driver_stopped = (bool *)value;
 951                 break;
 952
 953         case ODM_CMNINFO_PNP_IN:
 954                 dm->is_driver_is_going_to_pnp_set_power_sleep = (bool *)value;
 955                 break;
 956
 957         case ODM_CMNINFO_INIT_ON:
 958                 dm->pinit_adpt_in_progress = (bool *)value;
 959                 break;
 960
 961         case ODM_CMNINFO_ANT_TEST:
 962                 dm->antenna_test = (u8 *)value;
 963                 break;
 964
 965         case ODM_CMNINFO_NET_CLOSED:
 966                 dm->is_net_closed = (bool *)value;
 967                 break;
 968
 969         case ODM_CMNINFO_FORCED_RATE:
 970                 dm->forced_data_rate = (u16 *)value;
 971                 break;
 972         case ODM_CMNINFO_ANT_DIV:
 973                 dm->enable_antdiv = (u8 *)value;
 974                 break;
 975         case ODM_CMNINFO_ADAPTIVITY:
 976                 dm->enable_adaptivity = (u8 *)value;
 977                 break;
 978         case ODM_CMNINFO_FORCED_IGI_LB:
 979                 dm->pu1_forced_igi_lb = (u8 *)value;
 980                 break;
 981
 982         case ODM_CMNINFO_P2P_LINK:
 983                 dm->dm_dig_table.is_p2p_in_process = (u8 *)value;
 984                 break;
 985
 986         case ODM_CMNINFO_IS1ANTENNA:
 987                 dm->is_1_antenna = (bool *)value;
 988                 break;
 989
 990         case ODM_CMNINFO_RFDEFAULTPATH:
 991                 dm->rf_default_path = (u8 *)value;
 992                 break;
 993
 994         case ODM_CMNINFO_FCS_MODE:
 995                 dm->is_fcs_mode_enable = (bool *)value;
 996                 break;
 997         /*add by YuChen for beamforming PhyDM*/
 998         case ODM_CMNINFO_HUBUSBMODE:
 999                 dm->hub_usb_mode = (u8 *)value;
1000                 break;
1001         case ODM_CMNINFO_FWDWRSVDPAGEINPROGRESS:
1002                 dm->is_fw_dw_rsvd_page_in_progress = (bool *)value;
1003                 break;
1004         case ODM_CMNINFO_TX_TP:
1005                 dm->current_tx_tp = (u32 *)value;
1006                 break;
1007         case ODM_CMNINFO_RX_TP:
1008                 dm->current_rx_tp = (u32 *)value;
1009                 break;
1010         case ODM_CMNINFO_SOUNDING_SEQ:
1011                 dm->sounding_seq = (u8 *)value;
1012                 break;
1013         case ODM_CMNINFO_FORCE_TX_ANT_BY_TXDESC:
1014                 dm->dm_fat_table.p_force_tx_ant_by_desc = (u8 *)value;
1015                 break;
1016         case ODM_CMNINFO_SET_S0S1_DEFAULT_ANTENNA:
1017                 dm->dm_fat_table.p_default_s0_s1 = (u8 *)value;
1018                 break;
1019
1020         default:
1021                 /*do nothing*/
1022                 break;
1023         }
1024 }
1025
1026 void odm_cmn_info_ptr_array_hook(struct phy_dm_struct *dm,
1027                                  enum odm_cmninfo cmn_info, u16 index,
1028                                  void *value)
1029 {
1030         /*Hook call by reference pointer.*/
1031         switch (cmn_info) {
1032         /*Dynamic call by reference pointer.    */
1033         case ODM_CMNINFO_STA_STATUS:
1034                 dm->odm_sta_info[index] = (struct rtl_sta_info *)value;
1035
1036                 if (IS_STA_VALID(dm->odm_sta_info[index]))
1037                         dm->platform2phydm_macid_table[index] = index;
1038
1039                 break;
1040         /* To remove the compiler warning, must add an empty default statement
1041          * to handle the other values.
1042          */
1043         default:
1044                 /* do nothing */
1045                 break;
1046         }
1047 }
1048
1049 /*
1050  * Update band/CHannel/.. The values are dynamic but non-per-packet.
1051  */
1052 void odm_cmn_info_update(struct phy_dm_struct *dm, u32 cmn_info, u64 value)
1053 {
1054         /* This init variable may be changed in run time. */
1055         switch (cmn_info) {
1056         case ODM_CMNINFO_LINK_IN_PROGRESS:
1057                 dm->is_link_in_process = (bool)value;
1058                 break;
1059
1060         case ODM_CMNINFO_ABILITY:
1061                 dm->support_ability = (u32)value;
1062                 break;
1063
1064         case ODM_CMNINFO_RF_TYPE:
1065                 dm->rf_type = (u8)value;
1066                 break;
1067
1068         case ODM_CMNINFO_WIFI_DIRECT:
1069                 dm->is_wifi_direct = (bool)value;
1070                 break;
1071
1072         case ODM_CMNINFO_WIFI_DISPLAY:
1073                 dm->is_wifi_display = (bool)value;
1074                 break;
1075
1076         case ODM_CMNINFO_LINK:
1077                 dm->is_linked = (bool)value;
1078                 break;
1079
1080         case ODM_CMNINFO_CMW500LINK:
1081                 dm->is_linkedcmw500 = (bool)value;
1082                 break;
1083
1084         case ODM_CMNINFO_LPSPG:
1085                 dm->is_in_lps_pg = (bool)value;
1086                 break;
1087
1088         case ODM_CMNINFO_STATION_STATE:
1089                 dm->bsta_state = (bool)value;
1090                 break;
1091
1092         case ODM_CMNINFO_RSSI_MIN:
1093                 dm->rssi_min = (u8)value;
1094                 break;
1095
1096         case ODM_CMNINFO_DBG_COMP:
1097                 dm->debug_components = (u32)value;
1098                 break;
1099
1100         case ODM_CMNINFO_DBG_LEVEL:
1101                 dm->debug_level = (u32)value;
1102                 break;
1103         case ODM_CMNINFO_RA_THRESHOLD_HIGH:
1104                 dm->rate_adaptive.high_rssi_thresh = (u8)value;
1105                 break;
1106
1107         case ODM_CMNINFO_RA_THRESHOLD_LOW:
1108                 dm->rate_adaptive.low_rssi_thresh = (u8)value;
1109                 break;
1110         /* The following is for BT HS mode and BT coexist mechanism. */
1111         case ODM_CMNINFO_BT_ENABLED:
1112                 dm->is_bt_enabled = (bool)value;
1113                 break;
1114
1115         case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1116                 dm->is_bt_connect_process = (bool)value;
1117                 break;
1118
1119         case ODM_CMNINFO_BT_HS_RSSI:
1120                 dm->bt_hs_rssi = (u8)value;
1121                 break;
1122
1123         case ODM_CMNINFO_BT_OPERATION:
1124                 dm->is_bt_hs_operation = (bool)value;
1125                 break;
1126
1127         case ODM_CMNINFO_BT_LIMITED_DIG:
1128                 dm->is_bt_limited_dig = (bool)value;
1129                 break;
1130
1131         case ODM_CMNINFO_BT_DIG:
1132                 dm->bt_hs_dig_val = (u8)value;
1133                 break;
1134
1135         case ODM_CMNINFO_BT_BUSY:
1136                 dm->is_bt_busy = (bool)value;
1137                 break;
1138
1139         case ODM_CMNINFO_BT_DISABLE_EDCA:
1140                 dm->is_bt_disable_edca_turbo = (bool)value;
1141                 break;
1142
1143         case ODM_CMNINFO_AP_TOTAL_NUM:
1144                 dm->ap_total_num = (u8)value;
1145                 break;
1146
1147         case ODM_CMNINFO_POWER_TRAINING:
1148                 dm->is_disable_power_training = (bool)value;
1149                 break;
1150
1151         default:
1152                 /* do nothing */
1153                 break;
1154         }
1155 }
1156
1157 u32 phydm_cmn_info_query(struct phy_dm_struct *dm,
1158                          enum phydm_info_query info_type)
1159 {
1160         struct false_alarm_stat *false_alm_cnt =
1161                 (struct false_alarm_stat *)phydm_get_structure(
1162                         dm, PHYDM_FALSEALMCNT);
1163
1164         switch (info_type) {
1165         case PHYDM_INFO_FA_OFDM:
1166                 return false_alm_cnt->cnt_ofdm_fail;
1167
1168         case PHYDM_INFO_FA_CCK:
1169                 return false_alm_cnt->cnt_cck_fail;
1170
1171         case PHYDM_INFO_FA_TOTAL:
1172                 return false_alm_cnt->cnt_all;
1173
1174         case PHYDM_INFO_CCA_OFDM:
1175                 return false_alm_cnt->cnt_ofdm_cca;
1176
1177         case PHYDM_INFO_CCA_CCK:
1178                 return false_alm_cnt->cnt_cck_cca;
1179
1180         case PHYDM_INFO_CCA_ALL:
1181                 return false_alm_cnt->cnt_cca_all;
1182
1183         case PHYDM_INFO_CRC32_OK_VHT:
1184                 return false_alm_cnt->cnt_vht_crc32_ok;
1185
1186         case PHYDM_INFO_CRC32_OK_HT:
1187                 return false_alm_cnt->cnt_ht_crc32_ok;
1188
1189         case PHYDM_INFO_CRC32_OK_LEGACY:
1190                 return false_alm_cnt->cnt_ofdm_crc32_ok;
1191
1192         case PHYDM_INFO_CRC32_OK_CCK:
1193                 return false_alm_cnt->cnt_cck_crc32_ok;
1194
1195         case PHYDM_INFO_CRC32_ERROR_VHT:
1196                 return false_alm_cnt->cnt_vht_crc32_error;
1197
1198         case PHYDM_INFO_CRC32_ERROR_HT:
1199                 return false_alm_cnt->cnt_ht_crc32_error;
1200
1201         case PHYDM_INFO_CRC32_ERROR_LEGACY:
1202                 return false_alm_cnt->cnt_ofdm_crc32_error;
1203
1204         case PHYDM_INFO_CRC32_ERROR_CCK:
1205                 return false_alm_cnt->cnt_cck_crc32_error;
1206
1207         case PHYDM_INFO_EDCCA_FLAG:
1208                 return false_alm_cnt->edcca_flag;
1209
1210         case PHYDM_INFO_OFDM_ENABLE:
1211                 return false_alm_cnt->ofdm_block_enable;
1212
1213         case PHYDM_INFO_CCK_ENABLE:
1214                 return false_alm_cnt->cck_block_enable;
1215
1216         case PHYDM_INFO_DBG_PORT_0:
1217                 return false_alm_cnt->dbg_port0;
1218
1219         default:
1220                 return 0xffffffff;
1221         }
1222 }
1223
1224 void odm_init_all_timers(struct phy_dm_struct *dm) {}
1225
1226 void odm_cancel_all_timers(struct phy_dm_struct *dm) {}
1227
1228 void odm_release_all_timers(struct phy_dm_struct *dm) {}
1229
1230 /* 3============================================================
1231  * 3 Tx Power Tracking
1232  * 3============================================================
1233  */
1234
1235 /* need to ODM CE Platform
1236  * move to here for ANT detection mechanism using
1237  */
1238
1239 u32 odm_convert_to_db(u32 value)
1240 {
1241         u8 i;
1242         u8 j;
1243         u32 dB;
1244
1245         value = value & 0xFFFF;
1246
1247         for (i = 0; i < 12; i++) {
1248                 if (value <= db_invert_table[i][7])
1249                         break;
1250         }
1251
1252         if (i >= 12)
1253                 return 96; /* maximum 96 dB */
1254
1255         for (j = 0; j < 8; j++) {
1256                 if (value <= db_invert_table[i][j])
1257                         break;
1258         }
1259
1260         dB = (i << 3) + j + 1;
1261
1262         return dB;
1263 }
1264
1265 u32 odm_convert_to_linear(u32 value)
1266 {
1267         u8 i;
1268         u8 j;
1269         u32 linear;
1270
1271         /* 1dB~96dB */
1272
1273         value = value & 0xFF;
1274
1275         i = (u8)((value - 1) >> 3);
1276         j = (u8)(value - 1) - (i << 3);
1277
1278         linear = db_invert_table[i][j];
1279
1280         return linear;
1281 }
1282
1283 /*
1284  * ODM multi-port consideration, added by Roger, 2013.10.01.
1285  */
1286 void odm_asoc_entry_init(struct phy_dm_struct *dm) {}
1287
1288 /* Justin: According to the current RRSI to adjust Response Frame TX power */
1289 void odm_dtc(struct phy_dm_struct *dm) {}
1290
1291 static void odm_update_power_training_state(struct phy_dm_struct *dm)
1292 {
1293         struct false_alarm_stat *false_alm_cnt =
1294                 (struct false_alarm_stat *)phydm_get_structure(
1295                         dm, PHYDM_FALSEALMCNT);
1296         struct dig_thres *dig_tab = &dm->dm_dig_table;
1297         u32 score = 0;
1298
1299         if (!(dm->support_ability & ODM_BB_PWR_TRAIN))
1300                 return;
1301
1302         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s()============>\n", __func__);
1303         dm->is_change_state = false;
1304
1305         /* Debug command */
1306         if (dm->force_power_training_state) {
1307                 if (dm->force_power_training_state == 1 &&
1308                     !dm->is_disable_power_training) {
1309                         dm->is_change_state = true;
1310                         dm->is_disable_power_training = true;
1311                 } else if (dm->force_power_training_state == 2 &&
1312                            dm->is_disable_power_training) {
1313                         dm->is_change_state = true;
1314                         dm->is_disable_power_training = false;
1315                 }
1316
1317                 dm->PT_score = 0;
1318                 dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1319                 dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1320                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1321                              "%s(): force_power_training_state = %d\n",
1322                              __func__, dm->force_power_training_state);
1323                 return;
1324         }
1325
1326         if (!dm->is_linked)
1327                 return;
1328
1329         /* First connect */
1330         if (dm->is_linked && !dig_tab->is_media_connect_0) {
1331                 dm->PT_score = 0;
1332                 dm->is_change_state = true;
1333                 dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1334                 dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1335                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): First Connect\n",
1336                              __func__);
1337                 return;
1338         }
1339
1340         /* Compute score */
1341         if (dm->nhm_cnt_0 >= 215) {
1342                 score = 2;
1343         } else if (dm->nhm_cnt_0 >= 190) {
1344                 score = 1; /* unknown state */
1345         } else {
1346                 u32 rx_pkt_cnt;
1347
1348                 rx_pkt_cnt = (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm) +
1349                              (u32)(dm->phy_dbg_info.num_qry_phy_status_cck);
1350
1351                 if ((false_alm_cnt->cnt_cca_all > 31 && rx_pkt_cnt > 31) &&
1352                     false_alm_cnt->cnt_cca_all >= rx_pkt_cnt) {
1353                         if ((rx_pkt_cnt + (rx_pkt_cnt >> 1)) <=
1354                             false_alm_cnt->cnt_cca_all)
1355                                 score = 0;
1356                         else if ((rx_pkt_cnt + (rx_pkt_cnt >> 2)) <=
1357                                  false_alm_cnt->cnt_cca_all)
1358                                 score = 1;
1359                         else
1360                                 score = 2;
1361                 }
1362                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1363                              "%s(): rx_pkt_cnt = %d, cnt_cca_all = %d\n",
1364                              __func__, rx_pkt_cnt, false_alm_cnt->cnt_cca_all);
1365         }
1366         ODM_RT_TRACE(
1367                 dm, ODM_COMP_RA_MASK,
1368                 "%s(): num_qry_phy_status_ofdm = %d, num_qry_phy_status_cck = %d\n",
1369                 __func__, (u32)(dm->phy_dbg_info.num_qry_phy_status_ofdm),
1370                 (u32)(dm->phy_dbg_info.num_qry_phy_status_cck));
1371         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "%s(): nhm_cnt_0 = %d, score = %d\n",
1372                      __func__, dm->nhm_cnt_0, score);
1373
1374         /* smoothing */
1375         dm->PT_score = (score << 4) + (dm->PT_score >> 1) + (dm->PT_score >> 2);
1376         score = (dm->PT_score + 32) >> 6;
1377         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1378                      "%s(): PT_score = %d, score after smoothing = %d\n",
1379                      __func__, dm->PT_score, score);
1380
1381         /* mode decision */
1382         if (score == 2) {
1383                 if (dm->is_disable_power_training) {
1384                         dm->is_change_state = true;
1385                         dm->is_disable_power_training = false;
1386                         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1387                                      "%s(): Change state\n", __func__);
1388                 }
1389                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1390                              "%s(): Enable Power Training\n", __func__);
1391         } else if (score == 0) {
1392                 if (!dm->is_disable_power_training) {
1393                         dm->is_change_state = true;
1394                         dm->is_disable_power_training = true;
1395                         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1396                                      "%s(): Change state\n", __func__);
1397                 }
1398                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1399                              "%s(): Disable Power Training\n", __func__);
1400         }
1401
1402         dm->phy_dbg_info.num_qry_phy_status_ofdm = 0;
1403         dm->phy_dbg_info.num_qry_phy_status_cck = 0;
1404 }
1405
1406 /*===========================================================*/
1407 /* The following is for compile only*/
1408 /*===========================================================*/
1409 /*#define TARGET_CHNL_NUM_2G_5G 59*/
1410 /*===========================================================*/
1411
1412 void phydm_noisy_detection(struct phy_dm_struct *dm)
1413 {
1414         u32 total_fa_cnt, total_cca_cnt;
1415         u32 score = 0, i, score_smooth;
1416
1417         total_cca_cnt = dm->false_alm_cnt.cnt_cca_all;
1418         total_fa_cnt = dm->false_alm_cnt.cnt_all;
1419
1420         for (i = 0; i <= 16; i++) {
1421                 if (total_fa_cnt * 16 >= total_cca_cnt * (16 - i)) {
1422                         score = 16 - i;
1423                         break;
1424                 }
1425         }
1426
1427         /* noisy_decision_smooth = noisy_decision_smooth>>1 + (score<<3)>>1; */
1428         dm->noisy_decision_smooth =
1429                 (dm->noisy_decision_smooth >> 1) + (score << 2);
1430
1431         /* Round the noisy_decision_smooth: +"3" comes from (2^3)/2-1 */
1432         score_smooth = (total_cca_cnt >= 300) ?
1433                                ((dm->noisy_decision_smooth + 3) >> 3) :
1434                                0;
1435
1436         dm->noisy_decision = (score_smooth >= 3) ? 1 : 0;
1437         ODM_RT_TRACE(
1438                 dm, ODM_COMP_NOISY_DETECT,
1439                 "[NoisyDetection] total_cca_cnt=%d, total_fa_cnt=%d, noisy_decision_smooth=%d, score=%d, score_smooth=%d, dm->noisy_decision=%d\n",
1440                 total_cca_cnt, total_fa_cnt, dm->noisy_decision_smooth, score,
1441                 score_smooth, dm->noisy_decision);
1442 }
1443
1444 void phydm_set_ext_switch(void *dm_void, u32 *const dm_value, u32 *_used,
1445                           char *output, u32 *_out_len)
1446 {
1447         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1448         u32 ext_ant_switch = dm_value[0];
1449
1450         if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
1451                 /*Output Pin Settings*/
1452                 odm_set_mac_reg(dm, 0x4C, BIT(23),
1453                                 0); /*select DPDT_P and DPDT_N as output pin*/
1454                 odm_set_mac_reg(dm, 0x4C, BIT(24), 1); /*by WLAN control*/
1455
1456                 odm_set_bb_reg(dm, 0xCB4, 0xF, 7); /*DPDT_P = 1b'0*/
1457                 odm_set_bb_reg(dm, 0xCB4, 0xF0, 7); /*DPDT_N = 1b'0*/
1458
1459                 if (ext_ant_switch == MAIN_ANT) {
1460                         odm_set_bb_reg(dm, 0xCB4, (BIT(29) | BIT(28)), 1);
1461                         ODM_RT_TRACE(
1462                                 dm, ODM_COMP_API,
1463                                 "***8821A set ant switch = 2b'01 (Main)\n");
1464                 } else if (ext_ant_switch == AUX_ANT) {
1465                         odm_set_bb_reg(dm, 0xCB4, BIT(29) | BIT(28), 2);
1466                         ODM_RT_TRACE(dm, ODM_COMP_API,
1467                                      "***8821A set ant switch = 2b'10 (Aux)\n");
1468                 }
1469         }
1470 }
1471
1472 static void phydm_csi_mask_enable(void *dm_void, u32 enable)
1473 {
1474         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1475         u32 reg_value = 0;
1476
1477         reg_value = (enable == CSI_MASK_ENABLE) ? 1 : 0;
1478
1479         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1480                 odm_set_bb_reg(dm, 0xD2C, BIT(28), reg_value);
1481                 ODM_RT_TRACE(dm, ODM_COMP_API,
1482                              "Enable CSI Mask:  Reg 0xD2C[28] = ((0x%x))\n",
1483                              reg_value);
1484
1485         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1486                 odm_set_bb_reg(dm, 0x874, BIT(0), reg_value);
1487                 ODM_RT_TRACE(dm, ODM_COMP_API,
1488                              "Enable CSI Mask:  Reg 0x874[0] = ((0x%x))\n",
1489                              reg_value);
1490         }
1491 }
1492
1493 static void phydm_clean_all_csi_mask(void *dm_void)
1494 {
1495         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1496
1497         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1498                 odm_set_bb_reg(dm, 0xD40, MASKDWORD, 0);
1499                 odm_set_bb_reg(dm, 0xD44, MASKDWORD, 0);
1500                 odm_set_bb_reg(dm, 0xD48, MASKDWORD, 0);
1501                 odm_set_bb_reg(dm, 0xD4c, MASKDWORD, 0);
1502
1503         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1504                 odm_set_bb_reg(dm, 0x880, MASKDWORD, 0);
1505                 odm_set_bb_reg(dm, 0x884, MASKDWORD, 0);
1506                 odm_set_bb_reg(dm, 0x888, MASKDWORD, 0);
1507                 odm_set_bb_reg(dm, 0x88c, MASKDWORD, 0);
1508                 odm_set_bb_reg(dm, 0x890, MASKDWORD, 0);
1509                 odm_set_bb_reg(dm, 0x894, MASKDWORD, 0);
1510                 odm_set_bb_reg(dm, 0x898, MASKDWORD, 0);
1511                 odm_set_bb_reg(dm, 0x89c, MASKDWORD, 0);
1512         }
1513 }
1514
1515 static void phydm_set_csi_mask_reg(void *dm_void, u32 tone_idx_tmp,
1516                                    u8 tone_direction)
1517 {
1518         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1519         u8 byte_offset, bit_offset;
1520         u32 target_reg;
1521         u8 reg_tmp_value;
1522         u32 tone_num = 64;
1523         u32 tone_num_shift = 0;
1524         u32 csi_mask_reg_p = 0, csi_mask_reg_n = 0;
1525
1526         /* calculate real tone idx*/
1527         if ((tone_idx_tmp % 10) >= 5)
1528                 tone_idx_tmp += 10;
1529
1530         tone_idx_tmp = (tone_idx_tmp / 10);
1531
1532         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1533                 tone_num = 64;
1534                 csi_mask_reg_p = 0xD40;
1535                 csi_mask_reg_n = 0xD48;
1536
1537         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1538                 tone_num = 128;
1539                 csi_mask_reg_p = 0x880;
1540                 csi_mask_reg_n = 0x890;
1541         }
1542
1543         if (tone_direction == FREQ_POSITIVE) {
1544                 if (tone_idx_tmp >= (tone_num - 1))
1545                         tone_idx_tmp = (tone_num - 1);
1546
1547                 byte_offset = (u8)(tone_idx_tmp >> 3);
1548                 bit_offset = (u8)(tone_idx_tmp & 0x7);
1549                 target_reg = csi_mask_reg_p + byte_offset;
1550
1551         } else {
1552                 tone_num_shift = tone_num;
1553
1554                 if (tone_idx_tmp >= tone_num)
1555                         tone_idx_tmp = tone_num;
1556
1557                 tone_idx_tmp = tone_num - tone_idx_tmp;
1558
1559                 byte_offset = (u8)(tone_idx_tmp >> 3);
1560                 bit_offset = (u8)(tone_idx_tmp & 0x7);
1561                 target_reg = csi_mask_reg_n + byte_offset;
1562         }
1563
1564         reg_tmp_value = odm_read_1byte(dm, target_reg);
1565         ODM_RT_TRACE(dm, ODM_COMP_API,
1566                      "Pre Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
1567                      (tone_idx_tmp + tone_num_shift), target_reg,
1568                      reg_tmp_value);
1569         reg_tmp_value |= BIT(bit_offset);
1570         odm_write_1byte(dm, target_reg, reg_tmp_value);
1571         ODM_RT_TRACE(dm, ODM_COMP_API,
1572                      "New Mask tone idx[%d]:  Reg0x%x = ((0x%x))\n",
1573                      (tone_idx_tmp + tone_num_shift), target_reg,
1574                      reg_tmp_value);
1575 }
1576
1577 static void phydm_set_nbi_reg(void *dm_void, u32 tone_idx_tmp, u32 bw)
1578 {
1579         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1580         u32 nbi_table_128[NBI_TABLE_SIZE_128] = {
1581                 25, 55, 85, 115, 135, 155, 185, 205, 225, 245,
1582                 /*1~10*/ /*tone_idx X 10*/
1583                 265, 285, 305, 335, 355, 375, 395, 415, 435, 455, /*11~20*/
1584                 485, 505, 525, 555, 585, 615, 635}; /*21~27*/
1585
1586         u32 nbi_table_256[NBI_TABLE_SIZE_256] = {
1587                 25,   55,   85,   115,  135,  155,  175,  195,  225,
1588                 245, /*1~10*/
1589                 265,  285,  305,  325,  345,  365,  385,  405,  425,
1590                 445, /*11~20*/
1591                 465,  485,  505,  525,  545,  565,  585,  605,  625,
1592                 645, /*21~30*/
1593                 665,  695,  715,  735,  755,  775,  795,  815,  835,
1594                 855, /*31~40*/
1595                 875,  895,  915,  935,  955,  975,  995,  1015, 1035,
1596                 1055, /*41~50*/
1597                 1085, 1105, 1125, 1145, 1175, 1195, 1225, 1255, 1275}; /*51~59*/
1598
1599         u32 reg_idx = 0;
1600         u32 i;
1601         u8 nbi_table_idx = FFT_128_TYPE;
1602
1603         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1604                 nbi_table_idx = FFT_128_TYPE;
1605         } else if (dm->support_ic_type & ODM_IC_11AC_1_SERIES) {
1606                 nbi_table_idx = FFT_256_TYPE;
1607         } else if (dm->support_ic_type & ODM_IC_11AC_2_SERIES) {
1608                 if (bw == 80)
1609                         nbi_table_idx = FFT_256_TYPE;
1610                 else /*20M, 40M*/
1611                         nbi_table_idx = FFT_128_TYPE;
1612         }
1613
1614         if (nbi_table_idx == FFT_128_TYPE) {
1615                 for (i = 0; i < NBI_TABLE_SIZE_128; i++) {
1616                         if (tone_idx_tmp < nbi_table_128[i]) {
1617                                 reg_idx = i + 1;
1618                                 break;
1619                         }
1620                 }
1621
1622         } else if (nbi_table_idx == FFT_256_TYPE) {
1623                 for (i = 0; i < NBI_TABLE_SIZE_256; i++) {
1624                         if (tone_idx_tmp < nbi_table_256[i]) {
1625                                 reg_idx = i + 1;
1626                                 break;
1627                         }
1628                 }
1629         }
1630
1631         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1632                 odm_set_bb_reg(dm, 0xc40, 0x1f000000, reg_idx);
1633                 ODM_RT_TRACE(dm, ODM_COMP_API,
1634                              "Set tone idx:  Reg0xC40[28:24] = ((0x%x))\n",
1635                              reg_idx);
1636                 /**/
1637         } else {
1638                 odm_set_bb_reg(dm, 0x87c, 0xfc000, reg_idx);
1639                 ODM_RT_TRACE(dm, ODM_COMP_API,
1640                              "Set tone idx: Reg0x87C[19:14] = ((0x%x))\n",
1641                              reg_idx);
1642                 /**/
1643         }
1644 }
1645
1646 static void phydm_nbi_enable(void *dm_void, u32 enable)
1647 {
1648         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1649         u32 reg_value = 0;
1650
1651         reg_value = (enable == NBI_ENABLE) ? 1 : 0;
1652
1653         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
1654                 odm_set_bb_reg(dm, 0xc40, BIT(9), reg_value);
1655                 ODM_RT_TRACE(dm, ODM_COMP_API,
1656                              "Enable NBI Reg0xC40[9] = ((0x%x))\n", reg_value);
1657
1658         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
1659                 odm_set_bb_reg(dm, 0x87c, BIT(13), reg_value);
1660                 ODM_RT_TRACE(dm, ODM_COMP_API,
1661                              "Enable NBI Reg0x87C[13] = ((0x%x))\n", reg_value);
1662         }
1663 }
1664
1665 static u8 phydm_calculate_fc(void *dm_void, u32 channel, u32 bw, u32 second_ch,
1666                              u32 *fc_in)
1667 {
1668         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1669         u32 fc = *fc_in;
1670         u32 start_ch_per_40m[NUM_START_CH_40M + 1] = {
1671                 36,  44,  52,  60,  100, 108, 116,     124,
1672                 132, 140, 149, 157, 165, 173, 173 + 8,
1673         };
1674         u32 start_ch_per_80m[NUM_START_CH_80M + 1] = {
1675                 36, 52, 100, 116, 132, 149, 165, 165 + 16,
1676         };
1677         u32 *start_ch = &start_ch_per_40m[0];
1678         u32 num_start_channel = NUM_START_CH_40M;
1679         u32 channel_offset = 0;
1680         u32 i;
1681
1682         /*2.4G*/
1683         if (channel <= 14 && channel > 0) {
1684                 if (bw == 80)
1685                         return SET_ERROR;
1686
1687                 fc = 2412 + (channel - 1) * 5;
1688
1689                 if (bw == 40 && second_ch == PHYDM_ABOVE) {
1690                         if (channel >= 10) {
1691                                 ODM_RT_TRACE(
1692                                         dm, ODM_COMP_API,
1693                                         "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1694                                         channel, second_ch);
1695                                 return SET_ERROR;
1696                         }
1697                         fc += 10;
1698                 } else if (bw == 40 && (second_ch == PHYDM_BELOW)) {
1699                         if (channel <= 2) {
1700                                 ODM_RT_TRACE(
1701                                         dm, ODM_COMP_API,
1702                                         "CH = ((%d)), Scnd_CH = ((%d)) Error setting\n",
1703                                         channel, second_ch);
1704                                 return SET_ERROR;
1705                         }
1706                         fc -= 10;
1707                 }
1708         }
1709         /*5G*/
1710         else if (channel >= 36 && channel <= 177) {
1711                 if (bw == 20) {
1712                         fc = 5180 + (channel - 36) * 5;
1713                         *fc_in = fc;
1714                         return SET_SUCCESS;
1715                 }
1716
1717                 if (bw == 40) {
1718                         num_start_channel = NUM_START_CH_40M;
1719                         start_ch = &start_ch_per_40m[0];
1720                         channel_offset = CH_OFFSET_40M;
1721                 } else if (bw == 80) {
1722                         num_start_channel = NUM_START_CH_80M;
1723                         start_ch = &start_ch_per_80m[0];
1724                         channel_offset = CH_OFFSET_80M;
1725                 }
1726
1727                 for (i = 0; i < num_start_channel; i++) {
1728                         if (channel < start_ch[i + 1]) {
1729                                 channel = start_ch[i] + channel_offset;
1730                                 break;
1731                         }
1732                 }
1733
1734                 ODM_RT_TRACE(dm, ODM_COMP_API, "Mod_CH = ((%d))\n", channel);
1735
1736                 fc = 5180 + (channel - 36) * 5;
1737
1738         } else {
1739                 ODM_RT_TRACE(dm, ODM_COMP_API, "CH = ((%d)) Error setting\n",
1740                              channel);
1741                 return SET_ERROR;
1742         }
1743
1744         *fc_in = fc;
1745
1746         return SET_SUCCESS;
1747 }
1748
1749 static u8 phydm_calculate_intf_distance(void *dm_void, u32 bw, u32 fc,
1750                                         u32 f_interference,
1751                                         u32 *tone_idx_tmp_in)
1752 {
1753         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1754         u32 bw_up, bw_low;
1755         u32 int_distance;
1756         u32 tone_idx_tmp;
1757         u8 set_result = SET_NO_NEED;
1758
1759         bw_up = fc + bw / 2;
1760         bw_low = fc - bw / 2;
1761
1762         ODM_RT_TRACE(dm, ODM_COMP_API,
1763                      "[f_l, fc, fh] = [ %d, %d, %d ], f_int = ((%d))\n", bw_low,
1764                      fc, bw_up, f_interference);
1765
1766         if (f_interference >= bw_low && f_interference <= bw_up) {
1767                 int_distance = (fc >= f_interference) ? (fc - f_interference) :
1768                                                         (f_interference - fc);
1769                 tone_idx_tmp =
1770                         (int_distance << 5); /* =10*(int_distance /0.3125) */
1771                 ODM_RT_TRACE(
1772                         dm, ODM_COMP_API,
1773                         "int_distance = ((%d MHz)) Mhz, tone_idx_tmp = ((%d.%d))\n",
1774                         int_distance, (tone_idx_tmp / 10), (tone_idx_tmp % 10));
1775                 *tone_idx_tmp_in = tone_idx_tmp;
1776                 set_result = SET_SUCCESS;
1777         }
1778
1779         return set_result;
1780 }
1781
1782 static u8 phydm_csi_mask_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
1783                                  u32 f_interference, u32 second_ch)
1784 {
1785         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1786         u32 fc;
1787         u8 tone_direction;
1788         u32 tone_idx_tmp;
1789         u8 set_result = SET_SUCCESS;
1790
1791         if (enable == CSI_MASK_DISABLE) {
1792                 set_result = SET_SUCCESS;
1793                 phydm_clean_all_csi_mask(dm);
1794
1795         } else {
1796                 ODM_RT_TRACE(
1797                         dm, ODM_COMP_API,
1798                         "[Set CSI MASK_] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1799                         channel, bw, f_interference,
1800                         (((bw == 20) || (channel > 14)) ?
1801                                  "Don't care" :
1802                                  (second_ch == PHYDM_ABOVE) ? "H" : "L"));
1803
1804                 /*calculate fc*/
1805                 if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
1806                     SET_ERROR) {
1807                         set_result = SET_ERROR;
1808                 } else {
1809                         /*calculate interference distance*/
1810                         if (phydm_calculate_intf_distance(
1811                                     dm, bw, fc, f_interference,
1812                                     &tone_idx_tmp) == SET_SUCCESS) {
1813                                 tone_direction = (f_interference >= fc) ?
1814                                                          FREQ_POSITIVE :
1815                                                          FREQ_NEGATIVE;
1816                                 phydm_set_csi_mask_reg(dm, tone_idx_tmp,
1817                                                        tone_direction);
1818                                 set_result = SET_SUCCESS;
1819                         } else {
1820                                 set_result = SET_NO_NEED;
1821                         }
1822                 }
1823         }
1824
1825         if (set_result == SET_SUCCESS)
1826                 phydm_csi_mask_enable(dm, enable);
1827         else
1828                 phydm_csi_mask_enable(dm, CSI_MASK_DISABLE);
1829
1830         return set_result;
1831 }
1832
1833 u8 phydm_nbi_setting(void *dm_void, u32 enable, u32 channel, u32 bw,
1834                      u32 f_interference, u32 second_ch)
1835 {
1836         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1837         u32 fc;
1838         u32 tone_idx_tmp;
1839         u8 set_result = SET_SUCCESS;
1840
1841         if (enable == NBI_DISABLE) {
1842                 set_result = SET_SUCCESS;
1843         } else {
1844                 ODM_RT_TRACE(
1845                         dm, ODM_COMP_API,
1846                         "[Set NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1847                         channel, bw, f_interference,
1848                         (((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1849                           (channel > 14)) ?
1850                                  "Don't care" :
1851                                  (second_ch == PHYDM_ABOVE) ? "H" : "L"));
1852
1853                 /*calculate fc*/
1854                 if (phydm_calculate_fc(dm, channel, bw, second_ch, &fc) ==
1855                     SET_ERROR) {
1856                         set_result = SET_ERROR;
1857                 } else {
1858                         /*calculate interference distance*/
1859                         if (phydm_calculate_intf_distance(
1860                                     dm, bw, fc, f_interference,
1861                                     &tone_idx_tmp) == SET_SUCCESS) {
1862                                 phydm_set_nbi_reg(dm, tone_idx_tmp, bw);
1863                                 set_result = SET_SUCCESS;
1864                         } else {
1865                                 set_result = SET_NO_NEED;
1866                         }
1867                 }
1868         }
1869
1870         if (set_result == SET_SUCCESS)
1871                 phydm_nbi_enable(dm, enable);
1872         else
1873                 phydm_nbi_enable(dm, NBI_DISABLE);
1874
1875         return set_result;
1876 }
1877
1878 void phydm_api_debug(void *dm_void, u32 function_map, u32 *const dm_value,
1879                      u32 *_used, char *output, u32 *_out_len)
1880 {
1881         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1882         u32 used = *_used;
1883         u32 out_len = *_out_len;
1884         u32 channel = dm_value[1];
1885         u32 bw = dm_value[2];
1886         u32 f_interference = dm_value[3];
1887         u32 second_ch = dm_value[4];
1888         u8 set_result = 0;
1889
1890         /*PHYDM_API_NBI*/
1891         /*--------------------------------------------------------------------*/
1892         if (function_map == PHYDM_API_NBI) {
1893                 if (dm_value[0] == 100) {
1894                         PHYDM_SNPRINTF(
1895                                 output + used, out_len - used,
1896                                 "[HELP-NBI]  EN(on=1, off=2)   CH   BW(20/40/80)  f_intf(Mhz)    Scnd_CH(L=1, H=2)\n");
1897                         return;
1898
1899                 } else if (dm_value[0] == NBI_ENABLE) {
1900                         PHYDM_SNPRINTF(
1901                                 output + used, out_len - used,
1902                                 "[Enable NBI] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1903                                 channel, bw, f_interference,
1904                                 ((second_ch == PHYDM_DONT_CARE) || (bw == 20) ||
1905                                  (channel > 14)) ?
1906                                         "Don't care" :
1907                                         ((second_ch == PHYDM_ABOVE) ? "H" :
1908                                                                       "L"));
1909                         set_result =
1910                                 phydm_nbi_setting(dm, NBI_ENABLE, channel, bw,
1911                                                   f_interference, second_ch);
1912
1913                 } else if (dm_value[0] == NBI_DISABLE) {
1914                         PHYDM_SNPRINTF(output + used, out_len - used,
1915                                        "[Disable NBI]\n");
1916                         set_result =
1917                                 phydm_nbi_setting(dm, NBI_DISABLE, channel, bw,
1918                                                   f_interference, second_ch);
1919
1920                 } else {
1921                         set_result = SET_ERROR;
1922                 }
1923
1924                 PHYDM_SNPRINTF(
1925                         output + used, out_len - used, "[NBI set result: %s]\n",
1926                         (set_result == SET_SUCCESS) ?
1927                                 "Success" :
1928                                 ((set_result == SET_NO_NEED) ? "No need" :
1929                                                                "Error"));
1930         }
1931
1932         /*PHYDM_CSI_MASK*/
1933         /*--------------------------------------------------------------------*/
1934         else if (function_map == PHYDM_API_CSI_MASK) {
1935                 if (dm_value[0] == 100) {
1936                         PHYDM_SNPRINTF(
1937                                 output + used, out_len - used,
1938                                 "[HELP-CSI MASK]  EN(on=1, off=2)   CH   BW(20/40/80)  f_intf(Mhz)    Scnd_CH(L=1, H=2)\n");
1939                         return;
1940
1941                 } else if (dm_value[0] == CSI_MASK_ENABLE) {
1942                         PHYDM_SNPRINTF(
1943                                 output + used, out_len - used,
1944                                 "[Enable CSI MASK] CH = ((%d)), BW = ((%d)), f_intf = ((%d)), Scnd_CH = ((%s))\n",
1945                                 channel, bw, f_interference,
1946                                 (channel > 14) ?
1947                                         "Don't care" :
1948                                         (((second_ch == PHYDM_DONT_CARE) ||
1949                                           (bw == 20) || (channel > 14)) ?
1950                                                  "H" :
1951                                                  "L"));
1952                         set_result = phydm_csi_mask_setting(
1953                                 dm, CSI_MASK_ENABLE, channel, bw,
1954                                 f_interference, second_ch);
1955
1956                 } else if (dm_value[0] == CSI_MASK_DISABLE) {
1957                         PHYDM_SNPRINTF(output + used, out_len - used,
1958                                        "[Disable CSI MASK]\n");
1959                         set_result = phydm_csi_mask_setting(
1960                                 dm, CSI_MASK_DISABLE, channel, bw,
1961                                 f_interference, second_ch);
1962
1963                 } else {
1964                         set_result = SET_ERROR;
1965                 }
1966
1967                 PHYDM_SNPRINTF(output + used, out_len - used,
1968                                "[CSI MASK set result: %s]\n",
1969                                (set_result == SET_SUCCESS) ?
1970                                        "Success" :
1971                                        ((set_result == SET_NO_NEED) ?
1972                                                 "No need" :
1973                                                 "Error"));
1974         }
1975 }