drivers/staging/rtlwifi/phydm/phydm_adaptivity.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 /* ************************************************************
  16  * include files
  17  * *************************************************************/
  18 #include "mp_precomp.h"
  19 #include "phydm_precomp.h"
  20
  21 void phydm_check_adaptivity(void *dm_void)
  22 {
  23         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  24         struct adaptivity_statistics *adaptivity =
  25                 (struct adaptivity_statistics *)phydm_get_structure(
  26                         dm, PHYDM_ADAPTIVITY);
  27
  28         if (dm->support_ability & ODM_BB_ADAPTIVITY) {
  29                 if (adaptivity->dynamic_link_adaptivity ||
  30                     adaptivity->acs_for_adaptivity) {
  31                         if (dm->is_linked && !adaptivity->is_check) {
  32                                 phydm_nhm_counter_statistics(dm);
  33                                 phydm_check_environment(dm);
  34                         } else if (!dm->is_linked) {
  35                                 adaptivity->is_check = false;
  36                         }
  37                 } else {
  38                         dm->adaptivity_enable = true;
  39
  40                         if (dm->support_ic_type & (ODM_IC_11AC_GAIN_IDX_EDCCA |
  41                                                    ODM_IC_11N_GAIN_IDX_EDCCA))
  42                                 dm->adaptivity_flag = false;
  43                         else
  44                                 dm->adaptivity_flag = true;
  45                 }
  46         } else {
  47                 dm->adaptivity_enable = false;
  48                 dm->adaptivity_flag = false;
  49         }
  50 }
  51
  52 void phydm_nhm_counter_statistics_init(void *dm_void)
  53 {
  54         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  55
  56         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
  57                 /*PHY parameters initialize for n series*/
  58
  59                 /*0x894[31:16]=0x0xC350
  60                  *Time duration for NHM unit: us, 0xc350=200ms
  61                  */
  62                 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11N + 2, 0xC350);
  63                 /*0x890[31:16]=0xffff           th_9, th_10*/
  64                 odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11N + 2, 0xffff);
  65                 /*0x898=0xffffff52              th_3, th_2, th_1, th_0*/
  66                 odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11N, 0xffffff50);
  67                 /*0x89c=0xffffffff              th_7, th_6, th_5, th_4*/
  68                 odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11N, 0xffffffff);
  69                 /*0xe28[7:0]=0xff               th_8*/
  70                 odm_set_bb_reg(dm, ODM_REG_FPGA0_IQK_11N, MASKBYTE0, 0xff);
  71                 /*0x890[10:8]=1         ignoreCCA ignore PHYTXON enable CCX*/
  72                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N,
  73                                BIT(10) | BIT(9) | BIT(8), 0x1);
  74                 /*0xc0c[7]=1                    max power among all RX ants*/
  75                 odm_set_bb_reg(dm, ODM_REG_OFDM_FA_RSTC_11N, BIT(7), 0x1);
  76         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
  77                 /*PHY parameters initialize for ac series*/
  78
  79                 odm_write_2byte(dm, ODM_REG_CCX_PERIOD_11AC + 2, 0xC350);
  80                 /*0x994[31:16]=0xffff           th_9, th_10*/
  81                 odm_write_2byte(dm, ODM_REG_NHM_TH9_TH10_11AC + 2, 0xffff);
  82                 /*0x998=0xffffff52              th_3, th_2, th_1, th_0*/
  83                 odm_write_4byte(dm, ODM_REG_NHM_TH3_TO_TH0_11AC, 0xffffff50);
  84                 /*0x99c=0xffffffff              th_7, th_6, th_5, th_4*/
  85                 odm_write_4byte(dm, ODM_REG_NHM_TH7_TO_TH4_11AC, 0xffffffff);
  86                 /*0x9a0[7:0]=0xff               th_8*/
  87                 odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0, 0xff);
  88                 /*0x994[10:8]=1         ignoreCCA ignore PHYTXON enable CCX*/
  89                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC,
  90                                BIT(8) | BIT(9) | BIT(10), 0x1);
  91                 /*0x9e8[7]=1                    max power among all RX ants*/
  92                 odm_set_bb_reg(dm, ODM_REG_NHM_9E8_11AC, BIT(0), 0x1);
  93         }
  94 }
  95
  96 void phydm_nhm_counter_statistics(void *dm_void)
  97 {
  98         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  99
 100         if (!(dm->support_ability & ODM_BB_NHM_CNT))
 101                 return;
 102
 103         /*Get NHM report*/
 104         phydm_get_nhm_counter_statistics(dm);
 105
 106         /*Reset NHM counter*/
 107         phydm_nhm_counter_statistics_reset(dm);
 108 }
 109
 110 void phydm_get_nhm_counter_statistics(void *dm_void)
 111 {
 112         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 113         u32 value32 = 0;
 114
 115         if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 116                 value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11AC, MASKDWORD);
 117         else if (dm->support_ic_type & ODM_IC_11N_SERIES)
 118                 value32 = odm_get_bb_reg(dm, ODM_REG_NHM_CNT_11N, MASKDWORD);
 119
 120         dm->nhm_cnt_0 = (u8)(value32 & MASKBYTE0);
 121         dm->nhm_cnt_1 = (u8)((value32 & MASKBYTE1) >> 8);
 122 }
 123
 124 void phydm_nhm_counter_statistics_reset(void *dm_void)
 125 {
 126         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 127
 128         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 129                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
 130                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
 131         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 132                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
 133                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
 134         }
 135 }
 136
 137 void phydm_set_edcca_threshold(void *dm_void, s8 H2L, s8 L2H)
 138 {
 139         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 140
 141         if (dm->support_ic_type & ODM_IC_11N_SERIES)
 142                 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
 143                                MASKBYTE2 | MASKBYTE0,
 144                                (u32)((u8)L2H | (u8)H2L << 16));
 145         else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 146                 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
 147                                (u16)((u8)L2H | (u8)H2L << 8));
 148 }
 149
 150 static void phydm_set_lna(void *dm_void, enum phydm_set_lna type)
 151 {
 152         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 153
 154         if (dm->support_ic_type & (ODM_RTL8188E | ODM_RTL8192E)) {
 155                 if (type == phydm_disable_lna) {
 156                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 157                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 158                                        0x18000); /*select Rx mode*/
 159                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 160                                        0x0000f);
 161                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 162                                        0x37f82); /*disable LNA*/
 163                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 164                         if (dm->rf_type > ODM_1T1R) {
 165                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 166                                                0x1);
 167                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
 168                                                0x18000);
 169                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
 170                                                0x0000f);
 171                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
 172                                                0x37f82);
 173                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 174                                                0x0);
 175                         }
 176                 } else if (type == phydm_enable_lna) {
 177                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 178                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 179                                        0x18000); /*select Rx mode*/
 180                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 181                                        0x0000f);
 182                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 183                                        0x77f82); /*back to normal*/
 184                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 185                         if (dm->rf_type > ODM_1T1R) {
 186                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 187                                                0x1);
 188                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
 189                                                0x18000);
 190                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
 191                                                0x0000f);
 192                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
 193                                                0x77f82);
 194                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 195                                                0x0);
 196                         }
 197                 }
 198         } else if (dm->support_ic_type & ODM_RTL8723B) {
 199                 if (type == phydm_disable_lna) {
 200                         /*S0*/
 201                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 202                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 203                                        0x18000); /*select Rx mode*/
 204                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 205                                        0x0001f);
 206                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 207                                        0xe6137); /*disable LNA*/
 208                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 209                         /*S1*/
 210                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
 211                         odm_set_rf_reg(
 212                                 dm, ODM_RF_PATH_A, 0x43, 0xfffff,
 213                                 0x3008d); /*select Rx mode and disable LNA*/
 214                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
 215                 } else if (type == phydm_enable_lna) {
 216                         /*S0*/
 217                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 218                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 219                                        0x18000); /*select Rx mode*/
 220                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 221                                        0x0001f);
 222                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 223                                        0xe6177); /*disable LNA*/
 224                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 225                         /*S1*/
 226                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x1);
 227                         odm_set_rf_reg(
 228                                 dm, ODM_RF_PATH_A, 0x43, 0xfffff,
 229                                 0x300bd); /*select Rx mode and disable LNA*/
 230                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xed, 0x00020, 0x0);
 231                 }
 232
 233         } else if (dm->support_ic_type & ODM_RTL8812) {
 234                 if (type == phydm_disable_lna) {
 235                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 236                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 237                                        0x18000); /*select Rx mode*/
 238                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 239                                        0x3f7ff);
 240                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 241                                        0xc22bf); /*disable LNA*/
 242                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 243                         if (dm->rf_type > ODM_1T1R) {
 244                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 245                                                0x1);
 246                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
 247                                                0x18000); /*select Rx mode*/
 248                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
 249                                                0x3f7ff);
 250                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
 251                                                0xc22bf); /*disable LNA*/
 252                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 253                                                0x0);
 254                         }
 255                 } else if (type == phydm_enable_lna) {
 256                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 257                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 258                                        0x18000); /*select Rx mode*/
 259                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 260                                        0x3f7ff);
 261                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 262                                        0xc26bf); /*disable LNA*/
 263                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 264                         if (dm->rf_type > ODM_1T1R) {
 265                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 266                                                0x1);
 267                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x30, 0xfffff,
 268                                                0x18000); /*select Rx mode*/
 269                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x31, 0xfffff,
 270                                                0x3f7ff);
 271                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0x32, 0xfffff,
 272                                                0xc26bf); /*disable LNA*/
 273                                 odm_set_rf_reg(dm, ODM_RF_PATH_B, 0xef, 0x80000,
 274                                                0x0);
 275                         }
 276                 }
 277         } else if (dm->support_ic_type & (ODM_RTL8821 | ODM_RTL8881A)) {
 278                 if (type == phydm_disable_lna) {
 279                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 280                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 281                                        0x18000); /*select Rx mode*/
 282                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 283                                        0x0002f);
 284                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 285                                        0xfb09b); /*disable LNA*/
 286                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 287                 } else if (type == phydm_enable_lna) {
 288                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x1);
 289                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x30, 0xfffff,
 290                                        0x18000); /*select Rx mode*/
 291                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x31, 0xfffff,
 292                                        0x0002f);
 293                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0x32, 0xfffff,
 294                                        0xfb0bb); /*disable LNA*/
 295                         odm_set_rf_reg(dm, ODM_RF_PATH_A, 0xef, 0x80000, 0x0);
 296                 }
 297         }
 298 }
 299
 300 void phydm_set_trx_mux(void *dm_void, enum phydm_trx_mux_type tx_mode,
 301                        enum phydm_trx_mux_type rx_mode)
 302 {
 303         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 304
 305         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 306                 /*set TXmod to standby mode to remove outside noise affect*/
 307                 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
 308                                BIT(3) | BIT(2) | BIT(1), tx_mode);
 309                 /*set RXmod to standby mode to remove outside noise affect*/
 310                 odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N,
 311                                BIT(22) | BIT(21) | BIT(20), rx_mode);
 312                 if (dm->rf_type > ODM_1T1R) {
 313                         /*set TXmod to standby mode to rm outside noise affect*/
 314                         odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
 315                                        BIT(3) | BIT(2) | BIT(1), tx_mode);
 316                         /*set RXmod to standby mode to rm outside noise affect*/
 317                         odm_set_bb_reg(dm, ODM_REG_CCK_RPT_FORMAT_11N_B,
 318                                        BIT(22) | BIT(21) | BIT(20), rx_mode);
 319                 }
 320         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 321                 /*set TXmod to standby mode to remove outside noise affect*/
 322                 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
 323                                BIT(11) | BIT(10) | BIT(9) | BIT(8), tx_mode);
 324                 /*set RXmod to standby mode to remove outside noise affect*/
 325                 odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC,
 326                                BIT(7) | BIT(6) | BIT(5) | BIT(4), rx_mode);
 327                 if (dm->rf_type > ODM_1T1R) {
 328                         /*set TXmod to standby mode to rm outside noise affect*/
 329                         odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
 330                                        BIT(11) | BIT(10) | BIT(9) | BIT(8),
 331                                        tx_mode);
 332                         /*set RXmod to standby mode to rm outside noise affect*/
 333                         odm_set_bb_reg(dm, ODM_REG_TRMUX_11AC_B,
 334                                        BIT(7) | BIT(6) | BIT(5) | BIT(4),
 335                                        rx_mode);
 336                 }
 337         }
 338 }
 339
 340 void phydm_mac_edcca_state(void *dm_void, enum phydm_mac_edcca_type state)
 341 {
 342         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 343
 344         if (state == phydm_ignore_edcca) {
 345                 /*ignore EDCCA  reg520[15]=1*/
 346                 odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 1);
 347         } else { /*don't set MAC ignore EDCCA signal*/
 348                 /*don't ignore EDCCA     reg520[15]=0*/
 349                 odm_set_mac_reg(dm, REG_TX_PTCL_CTRL, BIT(15), 0);
 350         }
 351         ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "EDCCA enable state = %d\n",
 352                      state);
 353 }
 354
 355 bool phydm_cal_nhm_cnt(void *dm_void)
 356 {
 357         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 358         u16 base = 0;
 359
 360         base = dm->nhm_cnt_0 + dm->nhm_cnt_1;
 361
 362         if (base != 0) {
 363                 dm->nhm_cnt_0 = ((dm->nhm_cnt_0) << 8) / base;
 364                 dm->nhm_cnt_1 = ((dm->nhm_cnt_1) << 8) / base;
 365         }
 366         if ((dm->nhm_cnt_0 - dm->nhm_cnt_1) >= 100)
 367                 return true; /*clean environment*/
 368         else
 369                 return false; /*noisy environment*/
 370 }
 371
 372 void phydm_check_environment(void *dm_void)
 373 {
 374         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 375         struct adaptivity_statistics *adaptivity =
 376                 (struct adaptivity_statistics *)phydm_get_structure(
 377                         dm, PHYDM_ADAPTIVITY);
 378         bool is_clean_environment = false;
 379
 380         if (adaptivity->is_first_link) {
 381                 if (dm->support_ic_type &
 382                     (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
 383                         dm->adaptivity_flag = false;
 384                 else
 385                         dm->adaptivity_flag = true;
 386
 387                 adaptivity->is_first_link = false;
 388                 return;
 389         }
 390
 391         if (adaptivity->nhm_wait < 3) { /*Start enter NHM after 4 nhm_wait*/
 392                 adaptivity->nhm_wait++;
 393                 phydm_nhm_counter_statistics(dm);
 394                 return;
 395         }
 396
 397         phydm_nhm_counter_statistics(dm);
 398         is_clean_environment = phydm_cal_nhm_cnt(dm);
 399
 400         if (is_clean_environment) {
 401                 dm->th_l2h_ini =
 402                         adaptivity->th_l2h_ini_backup; /*adaptivity mode*/
 403                 dm->th_edcca_hl_diff = adaptivity->th_edcca_hl_diff_backup;
 404
 405                 dm->adaptivity_enable = true;
 406
 407                 if (dm->support_ic_type &
 408                     (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))
 409                         dm->adaptivity_flag = false;
 410                 else
 411                         dm->adaptivity_flag = true;
 412         } else {
 413                 if (!adaptivity->acs_for_adaptivity) {
 414                         dm->th_l2h_ini = dm->th_l2h_ini_mode2; /*mode2*/
 415                         dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
 416
 417                         dm->adaptivity_flag = false;
 418                         dm->adaptivity_enable = false;
 419                 }
 420         }
 421
 422         adaptivity->nhm_wait = 0;
 423         adaptivity->is_first_link = true;
 424         adaptivity->is_check = true;
 425 }
 426
 427 void phydm_search_pwdb_lower_bound(void *dm_void)
 428 {
 429         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 430         struct adaptivity_statistics *adaptivity =
 431                 (struct adaptivity_statistics *)phydm_get_structure(
 432                         dm, PHYDM_ADAPTIVITY);
 433         u32 value32 = 0, reg_value32 = 0;
 434         u8 cnt, try_count = 0;
 435         u8 tx_edcca1 = 0, tx_edcca0 = 0;
 436         bool is_adjust = true;
 437         s8 th_l2h_dmc, th_h2l_dmc, igi_target = 0x32;
 438         s8 diff;
 439         u8 IGI = adaptivity->igi_base + 30 + (u8)dm->th_l2h_ini -
 440                  (u8)dm->th_edcca_hl_diff;
 441
 442         if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
 443                                    ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
 444                 phydm_set_lna(dm, phydm_disable_lna);
 445         } else {
 446                 phydm_set_trx_mux(dm, phydm_standby_mode, phydm_standby_mode);
 447                 odm_pause_dig(dm, PHYDM_PAUSE, PHYDM_PAUSE_LEVEL_0, 0x7e);
 448         }
 449
 450         diff = igi_target - (s8)IGI;
 451         th_l2h_dmc = dm->th_l2h_ini + diff;
 452         if (th_l2h_dmc > 10)
 453                 th_l2h_dmc = 10;
 454         th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 455
 456         phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
 457         ODM_delay_ms(30);
 458
 459         while (is_adjust) {
 460                 if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 461                         odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x0);
 462                         reg_value32 =
 463                                 odm_get_bb_reg(dm, ODM_REG_RPT_11N, MASKDWORD);
 464                 } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 465                         odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD,
 466                                        0x0);
 467                         reg_value32 =
 468                                 odm_get_bb_reg(dm, ODM_REG_RPT_11AC, MASKDWORD);
 469                 }
 470                 while (reg_value32 & BIT(3) && try_count < 3) {
 471                         ODM_delay_ms(3);
 472                         try_count = try_count + 1;
 473                         if (dm->support_ic_type & ODM_IC_11N_SERIES)
 474                                 reg_value32 = odm_get_bb_reg(
 475                                         dm, ODM_REG_RPT_11N, MASKDWORD);
 476                         else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 477                                 reg_value32 = odm_get_bb_reg(
 478                                         dm, ODM_REG_RPT_11AC, MASKDWORD);
 479                 }
 480                 try_count = 0;
 481
 482                 for (cnt = 0; cnt < 20; cnt++) {
 483                         if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 484                                 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N,
 485                                                MASKDWORD, 0x208);
 486                                 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11N,
 487                                                          MASKDWORD);
 488                         } else if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 489                                 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC,
 490                                                MASKDWORD, 0x209);
 491                                 value32 = odm_get_bb_reg(dm, ODM_REG_RPT_11AC,
 492                                                          MASKDWORD);
 493                         }
 494                         if (value32 & BIT(30) &&
 495                             (dm->support_ic_type &
 496                              (ODM_RTL8723B | ODM_RTL8188E)))
 497                                 tx_edcca1 = tx_edcca1 + 1;
 498                         else if (value32 & BIT(29))
 499                                 tx_edcca1 = tx_edcca1 + 1;
 500                         else
 501                                 tx_edcca0 = tx_edcca0 + 1;
 502                 }
 503
 504                 if (tx_edcca1 > 1) {
 505                         IGI = IGI - 1;
 506                         th_l2h_dmc = th_l2h_dmc + 1;
 507                         if (th_l2h_dmc > 10)
 508                                 th_l2h_dmc = 10;
 509                         th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 510
 511                         phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
 512                         if (th_l2h_dmc == 10) {
 513                                 is_adjust = false;
 514                                 adaptivity->h2l_lb = th_h2l_dmc;
 515                                 adaptivity->l2h_lb = th_l2h_dmc;
 516                                 dm->adaptivity_igi_upper = IGI;
 517                         }
 518
 519                         tx_edcca1 = 0;
 520                         tx_edcca0 = 0;
 521
 522                 } else {
 523                         is_adjust = false;
 524                         adaptivity->h2l_lb = th_h2l_dmc;
 525                         adaptivity->l2h_lb = th_l2h_dmc;
 526                         dm->adaptivity_igi_upper = IGI;
 527                         tx_edcca1 = 0;
 528                         tx_edcca0 = 0;
 529                 }
 530         }
 531
 532         dm->adaptivity_igi_upper = dm->adaptivity_igi_upper - dm->dc_backoff;
 533         adaptivity->h2l_lb = adaptivity->h2l_lb + dm->dc_backoff;
 534         adaptivity->l2h_lb = adaptivity->l2h_lb + dm->dc_backoff;
 535
 536         if (dm->support_ic_type & (ODM_RTL8723B | ODM_RTL8188E | ODM_RTL8192E |
 537                                    ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)) {
 538                 phydm_set_lna(dm, phydm_enable_lna);
 539         } else {
 540                 phydm_set_trx_mux(dm, phydm_tx_mode, phydm_rx_mode);
 541                 odm_pause_dig(dm, PHYDM_RESUME, PHYDM_PAUSE_LEVEL_0, NONE);
 542         }
 543
 544         phydm_set_edcca_threshold(dm, 0x7f, 0x7f); /*resume to no link state*/
 545 }
 546
 547 static bool phydm_re_search_condition(void *dm_void)
 548 {
 549         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 550         u8 adaptivity_igi_upper;
 551         u8 count = 0;
 552
 553         adaptivity_igi_upper = dm->adaptivity_igi_upper + dm->dc_backoff;
 554
 555         if (adaptivity_igi_upper <= 0x26 && count < 3) {
 556                 count = count + 1;
 557                 return true;
 558         }
 559
 560         return false;
 561 }
 562
 563 void phydm_adaptivity_info_init(void *dm_void, enum phydm_adapinfo cmn_info,
 564                                 u32 value)
 565 {
 566         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 567         struct adaptivity_statistics *adaptivity =
 568                 (struct adaptivity_statistics *)phydm_get_structure(
 569                         dm, PHYDM_ADAPTIVITY);
 570
 571         switch (cmn_info) {
 572         case PHYDM_ADAPINFO_CARRIER_SENSE_ENABLE:
 573                 dm->carrier_sense_enable = (bool)value;
 574                 break;
 575
 576         case PHYDM_ADAPINFO_DCBACKOFF:
 577                 dm->dc_backoff = (u8)value;
 578                 break;
 579
 580         case PHYDM_ADAPINFO_DYNAMICLINKADAPTIVITY:
 581                 adaptivity->dynamic_link_adaptivity = (bool)value;
 582                 break;
 583
 584         case PHYDM_ADAPINFO_TH_L2H_INI:
 585                 dm->th_l2h_ini = (s8)value;
 586                 break;
 587
 588         case PHYDM_ADAPINFO_TH_EDCCA_HL_DIFF:
 589                 dm->th_edcca_hl_diff = (s8)value;
 590                 break;
 591
 592         case PHYDM_ADAPINFO_AP_NUM_TH:
 593                 adaptivity->ap_num_th = (u8)value;
 594                 break;
 595
 596         default:
 597                 break;
 598         }
 599 }
 600
 601 void phydm_adaptivity_init(void *dm_void)
 602 {
 603         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 604         struct adaptivity_statistics *adaptivity =
 605                 (struct adaptivity_statistics *)phydm_get_structure(
 606                         dm, PHYDM_ADAPTIVITY);
 607         s8 igi_target = 0x32;
 608
 609         if (!dm->carrier_sense_enable) {
 610                 if (dm->th_l2h_ini == 0)
 611                         dm->th_l2h_ini = 0xf5;
 612         } else {
 613                 dm->th_l2h_ini = 0xa;
 614         }
 615
 616         if (dm->th_edcca_hl_diff == 0)
 617                 dm->th_edcca_hl_diff = 7;
 618         if (dm->wifi_test || dm->mp_mode) {
 619                 /*even no adaptivity, we still enable EDCCA, AP use mib ctrl*/
 620                 dm->edcca_enable = false;
 621         } else {
 622                 dm->edcca_enable = true;
 623         }
 624
 625         dm->adaptivity_igi_upper = 0;
 626         dm->adaptivity_enable =
 627                 false; /*use this flag to decide enable or disable*/
 628
 629         dm->th_l2h_ini_mode2 = 20;
 630         dm->th_edcca_hl_diff_mode2 = 8;
 631         adaptivity->th_l2h_ini_backup = dm->th_l2h_ini;
 632         adaptivity->th_edcca_hl_diff_backup = dm->th_edcca_hl_diff;
 633
 634         adaptivity->igi_base = 0x32;
 635         adaptivity->igi_target = 0x1c;
 636         adaptivity->h2l_lb = 0;
 637         adaptivity->l2h_lb = 0;
 638         adaptivity->nhm_wait = 0;
 639         adaptivity->is_check = false;
 640         adaptivity->is_first_link = true;
 641         adaptivity->adajust_igi_level = 0;
 642         adaptivity->is_stop_edcca = false;
 643         adaptivity->backup_h2l = 0;
 644         adaptivity->backup_l2h = 0;
 645
 646         phydm_mac_edcca_state(dm, phydm_dont_ignore_edcca);
 647
 648         /*Search pwdB lower bound*/
 649         if (dm->support_ic_type & ODM_IC_11N_SERIES)
 650                 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11N, MASKDWORD, 0x208);
 651         else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 652                 odm_set_bb_reg(dm, ODM_REG_DBG_RPT_11AC, MASKDWORD, 0x209);
 653
 654         if (dm->support_ic_type & ODM_IC_11N_GAIN_IDX_EDCCA) {
 655                 if (dm->support_ic_type & ODM_RTL8197F) {
 656                         /*set to page B1*/
 657                         odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x1);
 658                         /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 659                         odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_97F,
 660                                        BIT(27) | BIT(26), 0x1);
 661                         odm_set_bb_reg(dm, ODM_REG_PAGE_B1_97F, BIT(30), 0x0);
 662                 } else {
 663                         /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 664                         odm_set_bb_reg(dm, ODM_REG_EDCCA_DCNF_11N,
 665                                        BIT(21) | BIT(20), 0x1);
 666                 }
 667         }
 668         /*8814a no need to find pwdB lower bound, maybe*/
 669         if (dm->support_ic_type & ODM_IC_11AC_GAIN_IDX_EDCCA) {
 670                 /*0:rx_dfir, 1: dcnf_out, 2 :rx_iq, 3: rx_nbi_nf_out*/
 671                 odm_set_bb_reg(dm, ODM_REG_ACBB_EDCCA_ENHANCE,
 672                                BIT(29) | BIT(28), 0x1);
 673         }
 674
 675         if (!(dm->support_ic_type &
 676               (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA))) {
 677                 phydm_search_pwdb_lower_bound(dm);
 678                 if (phydm_re_search_condition(dm))
 679                         phydm_search_pwdb_lower_bound(dm);
 680         }
 681
 682         /*we need to consider PwdB upper bound for 8814 later IC*/
 683         adaptivity->adajust_igi_level =
 684                 (u8)((dm->th_l2h_ini + igi_target) - pwdb_upper_bound +
 685                      dfir_loss); /*IGI = L2H - PwdB - dfir_loss*/
 686
 687         ODM_RT_TRACE(
 688                 dm, PHYDM_COMP_ADAPTIVITY,
 689                 "th_l2h_ini = 0x%x, th_edcca_hl_diff = 0x%x, adaptivity->adajust_igi_level = 0x%x\n",
 690                 dm->th_l2h_ini, dm->th_edcca_hl_diff,
 691                 adaptivity->adajust_igi_level);
 692
 693         /*Check this later on Windows*/
 694         /*phydm_set_edcca_threshold_api(dm, dig_tab->cur_ig_value);*/
 695 }
 696
 697 void phydm_adaptivity(void *dm_void)
 698 {
 699         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 700         struct dig_thres *dig_tab = &dm->dm_dig_table;
 701         u8 IGI = dig_tab->cur_ig_value;
 702         s8 th_l2h_dmc, th_h2l_dmc;
 703         s8 diff = 0, igi_target;
 704         struct adaptivity_statistics *adaptivity =
 705                 (struct adaptivity_statistics *)phydm_get_structure(
 706                         dm, PHYDM_ADAPTIVITY);
 707
 708         if (!dm->edcca_enable || adaptivity->is_stop_edcca) {
 709                 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "Disable EDCCA!!!\n");
 710                 return;
 711         }
 712
 713         if (!(dm->support_ability & ODM_BB_ADAPTIVITY)) {
 714                 ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
 715                              "adaptivity disable, enable EDCCA mode!!!\n");
 716                 dm->th_l2h_ini = dm->th_l2h_ini_mode2;
 717                 dm->th_edcca_hl_diff = dm->th_edcca_hl_diff_mode2;
 718         }
 719
 720         ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY, "%s() =====>\n", __func__);
 721         ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
 722                      "igi_base=0x%x, th_l2h_ini = %d, th_edcca_hl_diff = %d\n",
 723                      adaptivity->igi_base, dm->th_l2h_ini,
 724                      dm->th_edcca_hl_diff);
 725         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 726                 /*fix AC series when enable EDCCA hang issue*/
 727                 odm_set_bb_reg(dm, 0x800, BIT(10), 1); /*ADC_mask disable*/
 728                 odm_set_bb_reg(dm, 0x800, BIT(10), 0); /*ADC_mask enable*/
 729         }
 730         if (*dm->band_width == ODM_BW20M) /*CHANNEL_WIDTH_20*/
 731                 igi_target = adaptivity->igi_base;
 732         else if (*dm->band_width == ODM_BW40M)
 733                 igi_target = adaptivity->igi_base + 2;
 734         else if (*dm->band_width == ODM_BW80M)
 735                 igi_target = adaptivity->igi_base + 2;
 736         else
 737                 igi_target = adaptivity->igi_base;
 738         adaptivity->igi_target = (u8)igi_target;
 739
 740         ODM_RT_TRACE(
 741                 dm, PHYDM_COMP_ADAPTIVITY,
 742                 "band_width=%s, igi_target=0x%x, dynamic_link_adaptivity = %d, acs_for_adaptivity = %d\n",
 743                 (*dm->band_width == ODM_BW80M) ?
 744                         "80M" :
 745                         ((*dm->band_width == ODM_BW40M) ? "40M" : "20M"),
 746                 igi_target, adaptivity->dynamic_link_adaptivity,
 747                 adaptivity->acs_for_adaptivity);
 748         ODM_RT_TRACE(
 749                 dm, PHYDM_COMP_ADAPTIVITY,
 750                 "rssi_min = %d, adaptivity->adajust_igi_level= 0x%x, adaptivity_flag = %d, adaptivity_enable = %d\n",
 751                 dm->rssi_min, adaptivity->adajust_igi_level,
 752                 dm->adaptivity_flag, dm->adaptivity_enable);
 753
 754         if (adaptivity->dynamic_link_adaptivity && !dm->is_linked &&
 755             !dm->adaptivity_enable) {
 756                 phydm_set_edcca_threshold(dm, 0x7f, 0x7f);
 757                 ODM_RT_TRACE(
 758                         dm, PHYDM_COMP_ADAPTIVITY,
 759                         "In DynamicLink mode(noisy) and No link, Turn off EDCCA!!\n");
 760                 return;
 761         }
 762
 763         if (dm->support_ic_type &
 764             (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
 765                 if (adaptivity->adajust_igi_level > IGI &&
 766                     dm->adaptivity_enable)
 767                         diff = adaptivity->adajust_igi_level - IGI;
 768
 769                 th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
 770                 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 771         } else {
 772                 diff = igi_target - (s8)IGI;
 773                 th_l2h_dmc = dm->th_l2h_ini + diff;
 774                 if (th_l2h_dmc > 10 && dm->adaptivity_enable)
 775                         th_l2h_dmc = 10;
 776
 777                 th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 778
 779                 /*replace lower bound to prevent EDCCA always equal 1*/
 780                 if (th_h2l_dmc < adaptivity->h2l_lb)
 781                         th_h2l_dmc = adaptivity->h2l_lb;
 782                 if (th_l2h_dmc < adaptivity->l2h_lb)
 783                         th_l2h_dmc = adaptivity->l2h_lb;
 784         }
 785         ODM_RT_TRACE(dm, PHYDM_COMP_ADAPTIVITY,
 786                      "IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n", IGI,
 787                      th_l2h_dmc, th_h2l_dmc);
 788         ODM_RT_TRACE(
 789                 dm, PHYDM_COMP_ADAPTIVITY,
 790                 "adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
 791                 dm->adaptivity_igi_upper, adaptivity->h2l_lb,
 792                 adaptivity->l2h_lb);
 793
 794         phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
 795
 796         if (dm->adaptivity_enable)
 797                 odm_set_mac_reg(dm, REG_RD_CTRL, BIT(11), 1);
 798 }
 799
 800 /*This is for solving USB can't Tx problem due to USB3.0 interference in 2.4G*/
 801 void phydm_pause_edcca(void *dm_void, bool is_pasue_edcca)
 802 {
 803         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 804         struct adaptivity_statistics *adaptivity =
 805                 (struct adaptivity_statistics *)phydm_get_structure(
 806                         dm, PHYDM_ADAPTIVITY);
 807         struct dig_thres *dig_tab = &dm->dm_dig_table;
 808         u8 IGI = dig_tab->cur_ig_value;
 809         s8 diff = 0;
 810
 811         if (is_pasue_edcca) {
 812                 adaptivity->is_stop_edcca = true;
 813
 814                 if (dm->support_ic_type &
 815                     (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
 816                         if (adaptivity->adajust_igi_level > IGI)
 817                                 diff = adaptivity->adajust_igi_level - IGI;
 818
 819                         adaptivity->backup_l2h =
 820                                 dm->th_l2h_ini - diff + adaptivity->igi_target;
 821                         adaptivity->backup_h2l =
 822                                 adaptivity->backup_l2h - dm->th_edcca_hl_diff;
 823                 } else {
 824                         diff = adaptivity->igi_target - (s8)IGI;
 825                         adaptivity->backup_l2h = dm->th_l2h_ini + diff;
 826                         if (adaptivity->backup_l2h > 10)
 827                                 adaptivity->backup_l2h = 10;
 828
 829                         adaptivity->backup_h2l =
 830                                 adaptivity->backup_l2h - dm->th_edcca_hl_diff;
 831
 832                         /*replace lower bound to prevent EDCCA always equal 1*/
 833                         if (adaptivity->backup_h2l < adaptivity->h2l_lb)
 834                                 adaptivity->backup_h2l = adaptivity->h2l_lb;
 835                         if (adaptivity->backup_l2h < adaptivity->l2h_lb)
 836                                 adaptivity->backup_l2h = adaptivity->l2h_lb;
 837                 }
 838                 ODM_RT_TRACE(
 839                         dm, PHYDM_COMP_ADAPTIVITY,
 840                         "pauseEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
 841                         adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
 842
 843                 /*Disable EDCCA*/
 844                 phydm_pause_edcca_work_item_callback(dm);
 845
 846         } else {
 847                 adaptivity->is_stop_edcca = false;
 848                 ODM_RT_TRACE(
 849                         dm, PHYDM_COMP_ADAPTIVITY,
 850                         "resumeEDCCA : L2Hbak = 0x%x, H2Lbak = 0x%x, IGI = 0x%x\n",
 851                         adaptivity->backup_l2h, adaptivity->backup_h2l, IGI);
 852                 /*Resume EDCCA*/
 853                 phydm_resume_edcca_work_item_callback(dm);
 854         }
 855 }
 856
 857 void phydm_pause_edcca_work_item_callback(void *dm_void)
 858 {
 859         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 860
 861         if (dm->support_ic_type & ODM_IC_11N_SERIES)
 862                 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
 863                                MASKBYTE2 | MASKBYTE0, (u32)(0x7f | 0x7f << 16));
 864         else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 865                 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
 866                                (u16)(0x7f | 0x7f << 8));
 867 }
 868
 869 void phydm_resume_edcca_work_item_callback(void *dm_void)
 870 {
 871         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 872         struct adaptivity_statistics *adaptivity =
 873                 (struct adaptivity_statistics *)phydm_get_structure(
 874                         dm, PHYDM_ADAPTIVITY);
 875
 876         if (dm->support_ic_type & ODM_IC_11N_SERIES)
 877                 odm_set_bb_reg(dm, REG_OFDM_0_ECCA_THRESHOLD,
 878                                MASKBYTE2 | MASKBYTE0,
 879                                (u32)((u8)adaptivity->backup_l2h |
 880                                      (u8)adaptivity->backup_h2l << 16));
 881         else if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 882                 odm_set_bb_reg(dm, REG_FPGA0_XB_LSSI_READ_BACK, MASKLWORD,
 883                                (u16)((u8)adaptivity->backup_l2h |
 884                                      (u8)adaptivity->backup_h2l << 8));
 885 }
 886
 887 void phydm_set_edcca_threshold_api(void *dm_void, u8 IGI)
 888 {
 889         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 890         struct adaptivity_statistics *adaptivity =
 891                 (struct adaptivity_statistics *)phydm_get_structure(
 892                         dm, PHYDM_ADAPTIVITY);
 893         s8 th_l2h_dmc, th_h2l_dmc;
 894         s8 diff = 0, igi_target = 0x32;
 895
 896         if (dm->support_ability & ODM_BB_ADAPTIVITY) {
 897                 if (dm->support_ic_type &
 898                     (ODM_IC_11AC_GAIN_IDX_EDCCA | ODM_IC_11N_GAIN_IDX_EDCCA)) {
 899                         if (adaptivity->adajust_igi_level > IGI)
 900                                 diff = adaptivity->adajust_igi_level - IGI;
 901
 902                         th_l2h_dmc = dm->th_l2h_ini - diff + igi_target;
 903                         th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 904                 } else {
 905                         diff = igi_target - (s8)IGI;
 906                         th_l2h_dmc = dm->th_l2h_ini + diff;
 907                         if (th_l2h_dmc > 10)
 908                                 th_l2h_dmc = 10;
 909
 910                         th_h2l_dmc = th_l2h_dmc - dm->th_edcca_hl_diff;
 911
 912                         /*replace lower bound to prevent EDCCA always equal 1*/
 913                         if (th_h2l_dmc < adaptivity->h2l_lb)
 914                                 th_h2l_dmc = adaptivity->h2l_lb;
 915                         if (th_l2h_dmc < adaptivity->l2h_lb)
 916                                 th_l2h_dmc = adaptivity->l2h_lb;
 917                 }
 918                 ODM_RT_TRACE(
 919                         dm, PHYDM_COMP_ADAPTIVITY,
 920                         "API :IGI=0x%x, th_l2h_dmc = %d, th_h2l_dmc = %d\n",
 921                         IGI, th_l2h_dmc, th_h2l_dmc);
 922                 ODM_RT_TRACE(
 923                         dm, PHYDM_COMP_ADAPTIVITY,
 924                         "API :adaptivity_igi_upper=0x%x, h2l_lb = 0x%x, l2h_lb = 0x%x\n",
 925                         dm->adaptivity_igi_upper, adaptivity->h2l_lb,
 926                         adaptivity->l2h_lb);
 927
 928                 phydm_set_edcca_threshold(dm, th_h2l_dmc, th_l2h_dmc);
 929         }
 930 }