drivers/staging/rtlwifi/phydm/phydm_ccx.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25 #include "mp_precomp.h"
  26 #include "phydm_precomp.h"
  27
  28 /*Set NHM period, threshold, disable ignore cca or not,
  29  *disable ignore txon or not
  30  */
  31 void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
  32 {
  33         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  34         struct ccx_info *ccx_info = &dm->dm_ccx_info;
  35
  36         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
  37                 if (nhm_setting == SET_NHM_SETTING) {
  38                         /*Set inexclude_cca, inexclude_txon*/
  39                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
  40                                        ccx_info->nhm_inexclude_cca);
  41                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
  42                                        ccx_info->nhm_inexclude_txon);
  43
  44                         /*Set NHM period*/
  45                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
  46                                        ccx_info->NHM_period);
  47
  48                         /*Set NHM threshold*/
  49                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  50                                        MASKBYTE0, ccx_info->NHM_th[0]);
  51                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  52                                        MASKBYTE1, ccx_info->NHM_th[1]);
  53                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  54                                        MASKBYTE2, ccx_info->NHM_th[2]);
  55                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  56                                        MASKBYTE3, ccx_info->NHM_th[3]);
  57                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  58                                        MASKBYTE0, ccx_info->NHM_th[4]);
  59                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  60                                        MASKBYTE1, ccx_info->NHM_th[5]);
  61                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  62                                        MASKBYTE2, ccx_info->NHM_th[6]);
  63                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  64                                        MASKBYTE3, ccx_info->NHM_th[7]);
  65                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
  66                                        ccx_info->NHM_th[8]);
  67                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
  68                                        ccx_info->NHM_th[9]);
  69                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
  70                                        ccx_info->NHM_th[10]);
  71
  72                         /*CCX EN*/
  73                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
  74                                        CCX_EN);
  75                 } else if (nhm_setting == STORE_NHM_SETTING) {
  76                         /*Store prev. disable_ignore_cca, disable_ignore_txon*/
  77                         ccx_info->NHM_inexclude_cca_restore =
  78                                 (enum nhm_inexclude_cca)odm_get_bb_reg(
  79                                         dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
  80                         ccx_info->NHM_inexclude_txon_restore =
  81                                 (enum nhm_inexclude_txon)odm_get_bb_reg(
  82                                         dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
  83
  84                         /*Store pervious NHM period*/
  85                         ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
  86                                 dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
  87
  88                         /*Store NHM threshold*/
  89                         ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
  90                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
  91                         ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
  92                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
  93                         ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
  94                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
  95                         ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
  96                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
  97                         ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
  98                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
  99                         ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
 100                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
 101                         ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
 102                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
 103                         ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
 104                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
 105                         ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
 106                                 dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
 107                         ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
 108                                 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
 109                         ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
 110                                 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
 111                 } else if (nhm_setting == RESTORE_NHM_SETTING) {
 112                         /*Set disable_ignore_cca, disable_ignore_txon*/
 113                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
 114                                        ccx_info->NHM_inexclude_cca_restore);
 115                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
 116                                        ccx_info->NHM_inexclude_txon_restore);
 117
 118                         /*Set NHM period*/
 119                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
 120                                        ccx_info->NHM_period);
 121
 122                         /*Set NHM threshold*/
 123                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 124                                        MASKBYTE0, ccx_info->NHM_th_restore[0]);
 125                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 126                                        MASKBYTE1, ccx_info->NHM_th_restore[1]);
 127                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 128                                        MASKBYTE2, ccx_info->NHM_th_restore[2]);
 129                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 130                                        MASKBYTE3, ccx_info->NHM_th_restore[3]);
 131                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 132                                        MASKBYTE0, ccx_info->NHM_th_restore[4]);
 133                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 134                                        MASKBYTE1, ccx_info->NHM_th_restore[5]);
 135                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 136                                        MASKBYTE2, ccx_info->NHM_th_restore[6]);
 137                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 138                                        MASKBYTE3, ccx_info->NHM_th_restore[7]);
 139                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
 140                                        ccx_info->NHM_th_restore[8]);
 141                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
 142                                        ccx_info->NHM_th_restore[9]);
 143                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
 144                                        ccx_info->NHM_th_restore[10]);
 145                 } else {
 146                         return;
 147                 }
 148         }
 149
 150         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 151                 if (nhm_setting == SET_NHM_SETTING) {
 152                         /*Set disable_ignore_cca, disable_ignore_txon*/
 153                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
 154                                        ccx_info->nhm_inexclude_cca);
 155                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
 156                                        ccx_info->nhm_inexclude_txon);
 157
 158                         /*Set NHM period*/
 159                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
 160                                        ccx_info->NHM_period);
 161
 162                         /*Set NHM threshold*/
 163                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 164                                        MASKBYTE0, ccx_info->NHM_th[0]);
 165                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 166                                        MASKBYTE1, ccx_info->NHM_th[1]);
 167                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 168                                        MASKBYTE2, ccx_info->NHM_th[2]);
 169                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 170                                        MASKBYTE3, ccx_info->NHM_th[3]);
 171                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 172                                        MASKBYTE0, ccx_info->NHM_th[4]);
 173                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 174                                        MASKBYTE1, ccx_info->NHM_th[5]);
 175                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 176                                        MASKBYTE2, ccx_info->NHM_th[6]);
 177                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 178                                        MASKBYTE3, ccx_info->NHM_th[7]);
 179                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
 180                                        ccx_info->NHM_th[8]);
 181                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
 182                                        ccx_info->NHM_th[9]);
 183                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
 184                                        ccx_info->NHM_th[10]);
 185
 186                         /*CCX EN*/
 187                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
 188                                        CCX_EN);
 189                 } else if (nhm_setting == STORE_NHM_SETTING) {
 190                         /*Store prev. disable_ignore_cca, disable_ignore_txon*/
 191                         ccx_info->NHM_inexclude_cca_restore =
 192                                 (enum nhm_inexclude_cca)odm_get_bb_reg(
 193                                         dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
 194                         ccx_info->NHM_inexclude_txon_restore =
 195                                 (enum nhm_inexclude_txon)odm_get_bb_reg(
 196                                         dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
 197
 198                         /*Store pervious NHM period*/
 199                         ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
 200                                 dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
 201
 202                         /*Store NHM threshold*/
 203                         ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
 204                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
 205                         ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
 206                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
 207                         ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
 208                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
 209                         ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
 210                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
 211                         ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
 212                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
 213                         ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
 214                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
 215                         ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
 216                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
 217                         ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
 218                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
 219                         ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
 220                                 dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
 221                         ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
 222                                 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
 223                         ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
 224                                 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
 225                 } else if (nhm_setting == RESTORE_NHM_SETTING) {
 226                         /*Set disable_ignore_cca, disable_ignore_txon*/
 227                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
 228                                        ccx_info->NHM_inexclude_cca_restore);
 229                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
 230                                        ccx_info->NHM_inexclude_txon_restore);
 231
 232                         /*Set NHM period*/
 233                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
 234                                        ccx_info->NHM_period_restore);
 235
 236                         /*Set NHM threshold*/
 237                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 238                                        MASKBYTE0, ccx_info->NHM_th_restore[0]);
 239                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 240                                        MASKBYTE1, ccx_info->NHM_th_restore[1]);
 241                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 242                                        MASKBYTE2, ccx_info->NHM_th_restore[2]);
 243                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 244                                        MASKBYTE3, ccx_info->NHM_th_restore[3]);
 245                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 246                                        MASKBYTE0, ccx_info->NHM_th_restore[4]);
 247                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 248                                        MASKBYTE1, ccx_info->NHM_th_restore[5]);
 249                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 250                                        MASKBYTE2, ccx_info->NHM_th_restore[6]);
 251                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 252                                        MASKBYTE3, ccx_info->NHM_th_restore[7]);
 253                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
 254                                        ccx_info->NHM_th_restore[8]);
 255                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
 256                                        ccx_info->NHM_th_restore[9]);
 257                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
 258                                        ccx_info->NHM_th_restore[10]);
 259                 } else {
 260                         return;
 261                 }
 262         }
 263 }
 264
 265 void phydm_nhm_trigger(void *dm_void)
 266 {
 267         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 268
 269         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 270                 /*Trigger NHM*/
 271                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
 272                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
 273         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 274                 /*Trigger NHM*/
 275                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
 276                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
 277         }
 278 }
 279
 280 void phydm_get_nhm_result(void *dm_void)
 281 {
 282         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 283         u32 value32;
 284         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 285
 286         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 287                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
 288                 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
 289                 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
 290                 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
 291                 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
 292
 293                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
 294                 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
 295                 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
 296                 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
 297                 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
 298
 299                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
 300                 ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
 301                 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
 302                 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
 303                 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
 304
 305                 /*Get NHM duration*/
 306                 value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
 307                 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
 308         }
 309
 310         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 311                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
 312                 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
 313                 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
 314                 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
 315                 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
 316
 317                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
 318                 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
 319                 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
 320                 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
 321                 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
 322
 323                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
 324                 ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
 325                 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
 326
 327                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
 328                 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
 329                 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
 330
 331                 /*Get NHM duration*/
 332                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
 333                 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
 334         }
 335 }
 336
 337 bool phydm_check_nhm_ready(void *dm_void)
 338 {
 339         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 340         u32 value32 = 0;
 341         u8 i;
 342         bool ret = false;
 343
 344         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 345                 value32 =
 346                         odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
 347
 348                 for (i = 0; i < 200; i++) {
 349                         ODM_delay_ms(1);
 350                         if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
 351                                            BIT(17))) {
 352                                 ret = 1;
 353                                 break;
 354                         }
 355                 }
 356         }
 357
 358         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 359                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
 360
 361                 for (i = 0; i < 200; i++) {
 362                         ODM_delay_ms(1);
 363                         if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
 364                                            BIT(17))) {
 365                                 ret = 1;
 366                                 break;
 367                         }
 368                 }
 369         }
 370         return ret;
 371 }
 372
 373 void phydm_clm_setting(void *dm_void)
 374 {
 375         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 376         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 377
 378         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 379                 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
 380                                ccx_info->CLM_period); /*4us sample 1 time*/
 381                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
 382                                0x1); /*Enable CCX for CLM*/
 383
 384         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 385                 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
 386                                ccx_info->CLM_period); /*4us sample 1 time*/
 387                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
 388                                0x1); /*Enable CCX for CLM*/
 389         }
 390
 391         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
 392                      ccx_info->CLM_period * 4);
 393 }
 394
 395 void phydm_clm_trigger(void *dm_void)
 396 {
 397         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 398
 399         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 400                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
 401                                0x0); /*Trigger CLM*/
 402                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
 403         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 404                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
 405                                0x0); /*Trigger CLM*/
 406                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
 407         }
 408 }
 409
 410 bool phydm_check_cl_mready(void *dm_void)
 411 {
 412         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 413         u32 value32 = 0;
 414         bool ret = false;
 415
 416         if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 417                 value32 = odm_get_bb_reg(
 418                         dm, ODM_REG_CLM_RESULT_11AC,
 419                         MASKDWORD); /*make sure CLM calc is ready*/
 420         else if (dm->support_ic_type & ODM_IC_11N_SERIES)
 421                 value32 = odm_get_bb_reg(
 422                         dm, ODM_REG_CLM_READY_11N,
 423                         MASKDWORD); /*make sure CLM calc is ready*/
 424
 425         if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
 426                 ret = true;
 427         else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
 428                  (value32 & BIT(16)))
 429                 ret = true;
 430         else
 431                 ret = false;
 432
 433         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
 434                      ret);
 435
 436         return ret;
 437 }
 438
 439 void phydm_get_cl_mresult(void *dm_void)
 440 {
 441         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 442         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 443
 444         u32 value32 = 0;
 445
 446         if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 447                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
 448                                          MASKDWORD); /*read CLM calc result*/
 449         else if (dm->support_ic_type & ODM_IC_11N_SERIES)
 450                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
 451                                          MASKDWORD); /*read CLM calc result*/
 452
 453         ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
 454
 455         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
 456                      ccx_info->CLM_result * 4);
 457 }