drivers/staging/rtlwifi/phydm/phydm_ccx.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14 #include "mp_precomp.h"
  15 #include "phydm_precomp.h"
  16
  17 /*Set NHM period, threshold, disable ignore cca or not,
  18  *disable ignore txon or not
  19  */
  20 void phydm_nhm_setting(void *dm_void, u8 nhm_setting)
  21 {
  22         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  23         struct ccx_info *ccx_info = &dm->dm_ccx_info;
  24
  25         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
  26                 if (nhm_setting == SET_NHM_SETTING) {
  27                         /*Set inexclude_cca, inexclude_txon*/
  28                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
  29                                        ccx_info->nhm_inexclude_cca);
  30                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
  31                                        ccx_info->nhm_inexclude_txon);
  32
  33                         /*Set NHM period*/
  34                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
  35                                        ccx_info->NHM_period);
  36
  37                         /*Set NHM threshold*/
  38                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  39                                        MASKBYTE0, ccx_info->NHM_th[0]);
  40                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  41                                        MASKBYTE1, ccx_info->NHM_th[1]);
  42                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  43                                        MASKBYTE2, ccx_info->NHM_th[2]);
  44                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
  45                                        MASKBYTE3, ccx_info->NHM_th[3]);
  46                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  47                                        MASKBYTE0, ccx_info->NHM_th[4]);
  48                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  49                                        MASKBYTE1, ccx_info->NHM_th[5]);
  50                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  51                                        MASKBYTE2, ccx_info->NHM_th[6]);
  52                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
  53                                        MASKBYTE3, ccx_info->NHM_th[7]);
  54                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
  55                                        ccx_info->NHM_th[8]);
  56                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
  57                                        ccx_info->NHM_th[9]);
  58                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
  59                                        ccx_info->NHM_th[10]);
  60
  61                         /*CCX EN*/
  62                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(8),
  63                                        CCX_EN);
  64                 } else if (nhm_setting == STORE_NHM_SETTING) {
  65                         /*Store prev. disable_ignore_cca, disable_ignore_txon*/
  66                         ccx_info->NHM_inexclude_cca_restore =
  67                                 (enum nhm_inexclude_cca)odm_get_bb_reg(
  68                                         dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9));
  69                         ccx_info->NHM_inexclude_txon_restore =
  70                                 (enum nhm_inexclude_txon)odm_get_bb_reg(
  71                                         dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10));
  72
  73                         /*Store pervious NHM period*/
  74                         ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
  75                                 dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD);
  76
  77                         /*Store NHM threshold*/
  78                         ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
  79                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE0);
  80                         ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
  81                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE1);
  82                         ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
  83                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE2);
  84                         ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
  85                                 dm, ODM_REG_NHM_TH3_TO_TH0_11AC, MASKBYTE3);
  86                         ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
  87                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE0);
  88                         ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
  89                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE1);
  90                         ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
  91                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE2);
  92                         ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
  93                                 dm, ODM_REG_NHM_TH7_TO_TH4_11AC, MASKBYTE3);
  94                         ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
  95                                 dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0);
  96                         ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
  97                                 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2);
  98                         ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
  99                                 dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3);
 100                 } else if (nhm_setting == RESTORE_NHM_SETTING) {
 101                         /*Set disable_ignore_cca, disable_ignore_txon*/
 102                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(9),
 103                                        ccx_info->NHM_inexclude_cca_restore);
 104                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(10),
 105                                        ccx_info->NHM_inexclude_txon_restore);
 106
 107                         /*Set NHM period*/
 108                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKHWORD,
 109                                        ccx_info->NHM_period);
 110
 111                         /*Set NHM threshold*/
 112                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 113                                        MASKBYTE0, ccx_info->NHM_th_restore[0]);
 114                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 115                                        MASKBYTE1, ccx_info->NHM_th_restore[1]);
 116                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 117                                        MASKBYTE2, ccx_info->NHM_th_restore[2]);
 118                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11AC,
 119                                        MASKBYTE3, ccx_info->NHM_th_restore[3]);
 120                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 121                                        MASKBYTE0, ccx_info->NHM_th_restore[4]);
 122                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 123                                        MASKBYTE1, ccx_info->NHM_th_restore[5]);
 124                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 125                                        MASKBYTE2, ccx_info->NHM_th_restore[6]);
 126                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11AC,
 127                                        MASKBYTE3, ccx_info->NHM_th_restore[7]);
 128                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11AC, MASKBYTE0,
 129                                        ccx_info->NHM_th_restore[8]);
 130                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE2,
 131                                        ccx_info->NHM_th_restore[9]);
 132                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, MASKBYTE3,
 133                                        ccx_info->NHM_th_restore[10]);
 134                 } else {
 135                         return;
 136                 }
 137         }
 138
 139         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 140                 if (nhm_setting == SET_NHM_SETTING) {
 141                         /*Set disable_ignore_cca, disable_ignore_txon*/
 142                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
 143                                        ccx_info->nhm_inexclude_cca);
 144                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
 145                                        ccx_info->nhm_inexclude_txon);
 146
 147                         /*Set NHM period*/
 148                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
 149                                        ccx_info->NHM_period);
 150
 151                         /*Set NHM threshold*/
 152                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 153                                        MASKBYTE0, ccx_info->NHM_th[0]);
 154                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 155                                        MASKBYTE1, ccx_info->NHM_th[1]);
 156                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 157                                        MASKBYTE2, ccx_info->NHM_th[2]);
 158                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 159                                        MASKBYTE3, ccx_info->NHM_th[3]);
 160                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 161                                        MASKBYTE0, ccx_info->NHM_th[4]);
 162                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 163                                        MASKBYTE1, ccx_info->NHM_th[5]);
 164                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 165                                        MASKBYTE2, ccx_info->NHM_th[6]);
 166                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 167                                        MASKBYTE3, ccx_info->NHM_th[7]);
 168                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
 169                                        ccx_info->NHM_th[8]);
 170                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
 171                                        ccx_info->NHM_th[9]);
 172                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
 173                                        ccx_info->NHM_th[10]);
 174
 175                         /*CCX EN*/
 176                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(8),
 177                                        CCX_EN);
 178                 } else if (nhm_setting == STORE_NHM_SETTING) {
 179                         /*Store prev. disable_ignore_cca, disable_ignore_txon*/
 180                         ccx_info->NHM_inexclude_cca_restore =
 181                                 (enum nhm_inexclude_cca)odm_get_bb_reg(
 182                                         dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9));
 183                         ccx_info->NHM_inexclude_txon_restore =
 184                                 (enum nhm_inexclude_txon)odm_get_bb_reg(
 185                                         dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10));
 186
 187                         /*Store pervious NHM period*/
 188                         ccx_info->NHM_period_restore = (u16)odm_get_bb_reg(
 189                                 dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD);
 190
 191                         /*Store NHM threshold*/
 192                         ccx_info->NHM_th_restore[0] = (u8)odm_get_bb_reg(
 193                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE0);
 194                         ccx_info->NHM_th_restore[1] = (u8)odm_get_bb_reg(
 195                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE1);
 196                         ccx_info->NHM_th_restore[2] = (u8)odm_get_bb_reg(
 197                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE2);
 198                         ccx_info->NHM_th_restore[3] = (u8)odm_get_bb_reg(
 199                                 dm, ODM_REG_NHM_TH3_TO_TH0_11N, MASKBYTE3);
 200                         ccx_info->NHM_th_restore[4] = (u8)odm_get_bb_reg(
 201                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE0);
 202                         ccx_info->NHM_th_restore[5] = (u8)odm_get_bb_reg(
 203                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE1);
 204                         ccx_info->NHM_th_restore[6] = (u8)odm_get_bb_reg(
 205                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE2);
 206                         ccx_info->NHM_th_restore[7] = (u8)odm_get_bb_reg(
 207                                 dm, ODM_REG_NHM_TH7_TO_TH4_11N, MASKBYTE3);
 208                         ccx_info->NHM_th_restore[8] = (u8)odm_get_bb_reg(
 209                                 dm, ODM_REG_NHM_TH8_11N, MASKBYTE0);
 210                         ccx_info->NHM_th_restore[9] = (u8)odm_get_bb_reg(
 211                                 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2);
 212                         ccx_info->NHM_th_restore[10] = (u8)odm_get_bb_reg(
 213                                 dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3);
 214                 } else if (nhm_setting == RESTORE_NHM_SETTING) {
 215                         /*Set disable_ignore_cca, disable_ignore_txon*/
 216                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(9),
 217                                        ccx_info->NHM_inexclude_cca_restore);
 218                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(10),
 219                                        ccx_info->NHM_inexclude_txon_restore);
 220
 221                         /*Set NHM period*/
 222                         odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKHWORD,
 223                                        ccx_info->NHM_period_restore);
 224
 225                         /*Set NHM threshold*/
 226                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 227                                        MASKBYTE0, ccx_info->NHM_th_restore[0]);
 228                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 229                                        MASKBYTE1, ccx_info->NHM_th_restore[1]);
 230                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 231                                        MASKBYTE2, ccx_info->NHM_th_restore[2]);
 232                         odm_set_bb_reg(dm, ODM_REG_NHM_TH3_TO_TH0_11N,
 233                                        MASKBYTE3, ccx_info->NHM_th_restore[3]);
 234                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 235                                        MASKBYTE0, ccx_info->NHM_th_restore[4]);
 236                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 237                                        MASKBYTE1, ccx_info->NHM_th_restore[5]);
 238                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 239                                        MASKBYTE2, ccx_info->NHM_th_restore[6]);
 240                         odm_set_bb_reg(dm, ODM_REG_NHM_TH7_TO_TH4_11N,
 241                                        MASKBYTE3, ccx_info->NHM_th_restore[7]);
 242                         odm_set_bb_reg(dm, ODM_REG_NHM_TH8_11N, MASKBYTE0,
 243                                        ccx_info->NHM_th_restore[8]);
 244                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE2,
 245                                        ccx_info->NHM_th_restore[9]);
 246                         odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, MASKBYTE3,
 247                                        ccx_info->NHM_th_restore[10]);
 248                 } else {
 249                         return;
 250                 }
 251         }
 252 }
 253
 254 void phydm_nhm_trigger(void *dm_void)
 255 {
 256         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 257
 258         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 259                 /*Trigger NHM*/
 260                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 0);
 261                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11AC, BIT(1), 1);
 262         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 263                 /*Trigger NHM*/
 264                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 0);
 265                 odm_set_bb_reg(dm, ODM_REG_NHM_TH9_TH10_11N, BIT(1), 1);
 266         }
 267 }
 268
 269 void phydm_get_nhm_result(void *dm_void)
 270 {
 271         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 272         u32 value32;
 273         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 274
 275         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 276                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11AC);
 277                 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
 278                 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
 279                 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
 280                 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
 281
 282                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11AC);
 283                 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
 284                 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
 285                 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
 286                 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
 287
 288                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT11_TO_CNT8_11AC);
 289                 ccx_info->NHM_result[8] = (u8)(value32 & MASKBYTE0);
 290                 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE1) >> 8);
 291                 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
 292                 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
 293
 294                 /*Get NHM duration*/
 295                 value32 = odm_read_4byte(dm, ODM_REG_NHM_DUR_READY_11AC);
 296                 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
 297         }
 298
 299         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 300                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT_11N);
 301                 ccx_info->NHM_result[0] = (u8)(value32 & MASKBYTE0);
 302                 ccx_info->NHM_result[1] = (u8)((value32 & MASKBYTE1) >> 8);
 303                 ccx_info->NHM_result[2] = (u8)((value32 & MASKBYTE2) >> 16);
 304                 ccx_info->NHM_result[3] = (u8)((value32 & MASKBYTE3) >> 24);
 305
 306                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT7_TO_CNT4_11N);
 307                 ccx_info->NHM_result[4] = (u8)(value32 & MASKBYTE0);
 308                 ccx_info->NHM_result[5] = (u8)((value32 & MASKBYTE1) >> 8);
 309                 ccx_info->NHM_result[6] = (u8)((value32 & MASKBYTE2) >> 16);
 310                 ccx_info->NHM_result[7] = (u8)((value32 & MASKBYTE3) >> 24);
 311
 312                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT9_TO_CNT8_11N);
 313                 ccx_info->NHM_result[8] = (u8)((value32 & MASKBYTE2) >> 16);
 314                 ccx_info->NHM_result[9] = (u8)((value32 & MASKBYTE3) >> 24);
 315
 316                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
 317                 ccx_info->NHM_result[10] = (u8)((value32 & MASKBYTE2) >> 16);
 318                 ccx_info->NHM_result[11] = (u8)((value32 & MASKBYTE3) >> 24);
 319
 320                 /*Get NHM duration*/
 321                 value32 = odm_read_4byte(dm, ODM_REG_NHM_CNT10_TO_CNT11_11N);
 322                 ccx_info->NHM_duration = (u16)(value32 & MASKLWORD);
 323         }
 324 }
 325
 326 bool phydm_check_nhm_ready(void *dm_void)
 327 {
 328         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 329         u32 value32 = 0;
 330         u8 i;
 331         bool ret = false;
 332
 333         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 334                 value32 =
 335                         odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC, MASKDWORD);
 336
 337                 for (i = 0; i < 200; i++) {
 338                         ODM_delay_ms(1);
 339                         if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
 340                                            BIT(17))) {
 341                                 ret = 1;
 342                                 break;
 343                         }
 344                 }
 345         }
 346
 347         else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 348                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_READY_11N, MASKDWORD);
 349
 350                 for (i = 0; i < 200; i++) {
 351                         ODM_delay_ms(1);
 352                         if (odm_get_bb_reg(dm, ODM_REG_NHM_DUR_READY_11AC,
 353                                            BIT(17))) {
 354                                 ret = 1;
 355                                 break;
 356                         }
 357                 }
 358         }
 359         return ret;
 360 }
 361
 362 void phydm_clm_setting(void *dm_void)
 363 {
 364         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 365         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 366
 367         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 368                 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11AC, MASKLWORD,
 369                                ccx_info->CLM_period); /*4us sample 1 time*/
 370                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(8),
 371                                0x1); /*Enable CCX for CLM*/
 372
 373         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 374                 odm_set_bb_reg(dm, ODM_REG_CCX_PERIOD_11N, MASKLWORD,
 375                                ccx_info->CLM_period); /*4us sample 1 time*/
 376                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(8),
 377                                0x1); /*Enable CCX for CLM*/
 378         }
 379
 380         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM period = %dus\n", __func__,
 381                      ccx_info->CLM_period * 4);
 382 }
 383
 384 void phydm_clm_trigger(void *dm_void)
 385 {
 386         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 387
 388         if (dm->support_ic_type & ODM_IC_11AC_SERIES) {
 389                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0),
 390                                0x0); /*Trigger CLM*/
 391                 odm_set_bb_reg(dm, ODM_REG_CLM_11AC, BIT(0), 0x1);
 392         } else if (dm->support_ic_type & ODM_IC_11N_SERIES) {
 393                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0),
 394                                0x0); /*Trigger CLM*/
 395                 odm_set_bb_reg(dm, ODM_REG_CLM_11N, BIT(0), 0x1);
 396         }
 397 }
 398
 399 bool phydm_check_cl_mready(void *dm_void)
 400 {
 401         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 402         u32 value32 = 0;
 403         bool ret = false;
 404
 405         if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 406                 value32 = odm_get_bb_reg(
 407                         dm, ODM_REG_CLM_RESULT_11AC,
 408                         MASKDWORD); /*make sure CLM calc is ready*/
 409         else if (dm->support_ic_type & ODM_IC_11N_SERIES)
 410                 value32 = odm_get_bb_reg(
 411                         dm, ODM_REG_CLM_READY_11N,
 412                         MASKDWORD); /*make sure CLM calc is ready*/
 413
 414         if ((dm->support_ic_type & ODM_IC_11AC_SERIES) && (value32 & BIT(16)))
 415                 ret = true;
 416         else if ((dm->support_ic_type & ODM_IC_11N_SERIES) &&
 417                  (value32 & BIT(16)))
 418                 ret = true;
 419         else
 420                 ret = false;
 421
 422         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM ready = %d\n", __func__,
 423                      ret);
 424
 425         return ret;
 426 }
 427
 428 void phydm_get_cl_mresult(void *dm_void)
 429 {
 430         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 431         struct ccx_info *ccx_info = &dm->dm_ccx_info;
 432
 433         u32 value32 = 0;
 434
 435         if (dm->support_ic_type & ODM_IC_11AC_SERIES)
 436                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11AC,
 437                                          MASKDWORD); /*read CLM calc result*/
 438         else if (dm->support_ic_type & ODM_IC_11N_SERIES)
 439                 value32 = odm_get_bb_reg(dm, ODM_REG_CLM_RESULT_11N,
 440                                          MASKDWORD); /*read CLM calc result*/
 441
 442         ccx_info->CLM_result = (u16)(value32 & MASKLWORD);
 443
 444         ODM_RT_TRACE(dm, ODM_COMP_CCX, "[%s] : CLM result = %dus\n", __func__,
 445                      ccx_info->CLM_result * 4);
 446 }