drivers/staging/rtlwifi/phydm/phydm_dig.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __PHYDMDIG_H__
  27 #define __PHYDMDIG_H__
  28
  29 #define DIG_VERSION "1.32" /* 2016.09.02  YuChen. add CCK PD for 8197F*/
  30
  31 /* Pause DIG & CCKPD */
  32 #define DM_DIG_MAX_PAUSE_TYPE 0x7
  33
  34 enum dig_goupcheck_level {
  35         DIG_GOUPCHECK_LEVEL_0,
  36         DIG_GOUPCHECK_LEVEL_1,
  37         DIG_GOUPCHECK_LEVEL_2
  38
  39 };
  40
  41 struct dig_thres {
  42         bool is_stop_dig; /* for debug */
  43         bool is_ignore_dig;
  44         bool is_psd_in_progress;
  45
  46         u8 dig_enable_flag;
  47         u8 dig_ext_port_stage;
  48
  49         int rssi_low_thresh;
  50         int rssi_high_thresh;
  51
  52         u32 fa_low_thresh;
  53         u32 fa_high_thresh;
  54
  55         u8 cur_sta_connect_state;
  56         u8 pre_sta_connect_state;
  57         u8 cur_multi_sta_connect_state;
  58
  59         u8 pre_ig_value;
  60         u8 cur_ig_value;
  61         u8 backup_ig_value; /* MP DIG */
  62         u8 bt30_cur_igi;
  63         u8 igi_backup;
  64
  65         s8 backoff_val;
  66         s8 backoff_val_range_max;
  67         s8 backoff_val_range_min;
  68         u8 rx_gain_range_max;
  69         u8 rx_gain_range_min;
  70         u8 rssi_val_min;
  71
  72         u8 pre_cck_cca_thres;
  73         u8 cur_cck_cca_thres;
  74         u8 pre_cck_pd_state;
  75         u8 cur_cck_pd_state;
  76         u8 cck_pd_backup;
  77         u8 pause_cckpd_level;
  78         u8 pause_cckpd_value[DM_DIG_MAX_PAUSE_TYPE + 1];
  79
  80         u8 large_fa_hit;
  81         u8 large_fa_timeout; /*if (large_fa_hit), monitor "large_fa_timeout"
  82                               *sec, if timeout, large_fa_hit=0
  83                               */
  84         u8 forbidden_igi;
  85         u32 recover_cnt;
  86
  87         u8 dig_dynamic_min_0;
  88         u8 dig_dynamic_min_1;
  89         bool is_media_connect_0;
  90         bool is_media_connect_1;
  91
  92         u32 ant_div_rssi_max;
  93         u32 rssi_max;
  94
  95         u8 *is_p2p_in_process;
  96
  97         u8 pause_dig_level;
  98         u8 pause_dig_value[DM_DIG_MAX_PAUSE_TYPE + 1];
  99
 100         u32 cck_fa_ma;
 101         enum dig_goupcheck_level dig_go_up_check_level;
 102         u8 aaa_default;
 103
 104         u8 rf_gain_idx;
 105         u8 agc_table_idx;
 106         u8 big_jump_lmt[16];
 107         u8 enable_adjust_big_jump : 1;
 108         u8 big_jump_step1 : 3;
 109         u8 big_jump_step2 : 2;
 110         u8 big_jump_step3 : 2;
 111 };
 112
 113 struct false_alarm_stat {
 114         u32 cnt_parity_fail;
 115         u32 cnt_rate_illegal;
 116         u32 cnt_crc8_fail;
 117         u32 cnt_mcs_fail;
 118         u32 cnt_ofdm_fail;
 119         u32 cnt_ofdm_fail_pre; /* For RTL8881A */
 120         u32 cnt_cck_fail;
 121         u32 cnt_all;
 122         u32 cnt_all_pre;
 123         u32 cnt_fast_fsync;
 124         u32 cnt_sb_search_fail;
 125         u32 cnt_ofdm_cca;
 126         u32 cnt_cck_cca;
 127         u32 cnt_cca_all;
 128         u32 cnt_bw_usc; /* Gary */
 129         u32 cnt_bw_lsc; /* Gary */
 130         u32 cnt_cck_crc32_error;
 131         u32 cnt_cck_crc32_ok;
 132         u32 cnt_ofdm_crc32_error;
 133         u32 cnt_ofdm_crc32_ok;
 134         u32 cnt_ht_crc32_error;
 135         u32 cnt_ht_crc32_ok;
 136         u32 cnt_vht_crc32_error;
 137         u32 cnt_vht_crc32_ok;
 138         u32 cnt_crc32_error_all;
 139         u32 cnt_crc32_ok_all;
 140         bool cck_block_enable;
 141         bool ofdm_block_enable;
 142         u32 dbg_port0;
 143         bool edcca_flag;
 144 };
 145
 146 enum dm_dig_op {
 147         DIG_TYPE_THRESH_HIGH = 0,
 148         DIG_TYPE_THRESH_LOW = 1,
 149         DIG_TYPE_BACKOFF = 2,
 150         DIG_TYPE_RX_GAIN_MIN = 3,
 151         DIG_TYPE_RX_GAIN_MAX = 4,
 152         DIG_TYPE_ENABLE = 5,
 153         DIG_TYPE_DISABLE = 6,
 154         DIG_OP_TYPE_MAX
 155 };
 156
 157 enum phydm_pause_type { PHYDM_PAUSE = BIT(0), PHYDM_RESUME = BIT(1) };
 158
 159 enum phydm_pause_level {
 160         /* number of pause level can't exceed DM_DIG_MAX_PAUSE_TYPE */
 161         PHYDM_PAUSE_LEVEL_0 = 0,
 162         PHYDM_PAUSE_LEVEL_1 = 1,
 163         PHYDM_PAUSE_LEVEL_2 = 2,
 164         PHYDM_PAUSE_LEVEL_3 = 3,
 165         PHYDM_PAUSE_LEVEL_4 = 4,
 166         PHYDM_PAUSE_LEVEL_5 = 5,
 167         PHYDM_PAUSE_LEVEL_6 = 6,
 168         PHYDM_PAUSE_LEVEL_7 = DM_DIG_MAX_PAUSE_TYPE /* maximum level */
 169 };
 170
 171 #define DM_DIG_THRESH_HIGH 40
 172 #define DM_DIG_THRESH_LOW 35
 173
 174 #define DM_FALSEALARM_THRESH_LOW 400
 175 #define DM_FALSEALARM_THRESH_HIGH 1000
 176
 177 #define DM_DIG_MAX_NIC 0x3e
 178 #define DM_DIG_MIN_NIC 0x20
 179 #define DM_DIG_MAX_OF_MIN_NIC 0x3e
 180
 181 #define DM_DIG_MAX_AP 0x3e
 182 #define DM_DIG_MIN_AP 0x20
 183 #define DM_DIG_MAX_OF_MIN 0x2A /* 0x32 */
 184 #define DM_DIG_MIN_AP_DFS 0x20
 185
 186 #define DM_DIG_MAX_NIC_HP 0x46
 187 #define DM_DIG_MIN_NIC_HP 0x2e
 188
 189 #define DM_DIG_MAX_AP_HP 0x42
 190 #define DM_DIG_MIN_AP_HP 0x30
 191
 192 /* vivi 92c&92d has different definition, 20110504
 193  * this is for 92c
 194  */
 195 #define DM_DIG_FA_TH0 0x200 /* 0x20 */
 196
 197 #define DM_DIG_FA_TH1 0x300
 198 #define DM_DIG_FA_TH2 0x400
 199 /* this is for 92d */
 200 #define DM_DIG_FA_TH0_92D 0x100
 201 #define DM_DIG_FA_TH1_92D 0x400
 202 #define DM_DIG_FA_TH2_92D 0x600
 203
 204 #define DM_DIG_BACKOFF_MAX 12
 205 #define DM_DIG_BACKOFF_MIN -4
 206 #define DM_DIG_BACKOFF_DEFAULT 10
 207
 208 #define DM_DIG_FA_TH0_LPS 4 /* -> 4 in lps */
 209 #define DM_DIG_FA_TH1_LPS 15 /* -> 15 lps */
 210 #define DM_DIG_FA_TH2_LPS 30 /* -> 30 lps */
 211 #define RSSI_OFFSET_DIG 0x05
 212 #define LARGE_FA_TIMEOUT 60
 213
 214 void odm_change_dynamic_init_gain_thresh(void *dm_void, u32 dm_type,
 215                                          u32 dm_value);
 216
 217 void odm_write_dig(void *dm_void, u8 current_igi);
 218
 219 void odm_pause_dig(void *dm_void, enum phydm_pause_type pause_type,
 220                    enum phydm_pause_level pause_level, u8 igi_value);
 221
 222 void odm_dig_init(void *dm_void);
 223
 224 void odm_DIG(void *dm_void);
 225
 226 void odm_dig_by_rssi_lps(void *dm_void);
 227
 228 void odm_false_alarm_counter_statistics(void *dm_void);
 229
 230 void odm_pause_cck_packet_detection(void *dm_void,
 231                                     enum phydm_pause_type pause_type,
 232                                     enum phydm_pause_level pause_level,
 233                                     u8 cck_pd_threshold);
 234
 235 void odm_cck_packet_detection_thresh(void *dm_void);
 236
 237 void odm_write_cck_cca_thres(void *dm_void, u8 cur_cck_cca_thres);
 238
 239 bool phydm_dig_go_up_check(void *dm_void);
 240
 241 #endif