1 /******************************************************************************
3 * Copyright(c) 2007 - 2016 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
26 #ifndef __PHYDMPREDEFINE_H__
27 #define __PHYDMPREDEFINE_H__
29 /* 1 ============================================================
31 * 1 ============================================================
34 #define PHYDM_CODE_BASE "PHYDM_TRUNK"
35 #define PHYDM_RELEASE_DATE "00000000"
38 #define MAX_PATH_NUM_8188E 1
39 #define MAX_PATH_NUM_8192E 2
40 #define MAX_PATH_NUM_8723B 1
41 #define MAX_PATH_NUM_8812A 2
42 #define MAX_PATH_NUM_8821A 1
43 #define MAX_PATH_NUM_8814A 4
44 #define MAX_PATH_NUM_8822B 2
45 #define MAX_PATH_NUM_8821B 2
46 #define MAX_PATH_NUM_8703B 1
47 #define MAX_PATH_NUM_8188F 1
48 #define MAX_PATH_NUM_8723D 1
49 #define MAX_PATH_NUM_8197F 2
50 #define MAX_PATH_NUM_8821C 1
52 #define MAX_PATH_NUM_8710B 1
55 #define ODM_RF_PATH_MAX 2
56 #define ODM_RF_PATH_MAX_JAGUAR 4
59 #define PHYDM_A BIT(0)
60 #define PHYDM_B BIT(1)
61 #define PHYDM_C BIT(2)
62 #define PHYDM_D BIT(3)
63 #define PHYDM_AB (BIT(0) | BIT(1))
64 #define PHYDM_AC (BIT(0) | BIT(2))
65 #define PHYDM_AD (BIT(0) | BIT(3))
66 #define PHYDM_BC (BIT(1) | BIT(2))
67 #define PHYDM_BD (BIT(1) | BIT(3))
68 #define PHYDM_CD (BIT(2) | BIT(3))
69 #define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
70 #define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
71 #define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
72 #define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
73 #define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
76 /* defined in wifi.h (32+1) */
77 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
79 #define RX_SMOOTH_FACTOR 20
81 /* -----MGN rate--------------------------------- */
172 #define ODM_MGN_MCS0_SG 0xc0
173 #define ODM_MGN_MCS1_SG 0xc1
174 #define ODM_MGN_MCS2_SG 0xc2
175 #define ODM_MGN_MCS3_SG 0xc3
176 #define ODM_MGN_MCS4_SG 0xc4
177 #define ODM_MGN_MCS5_SG 0xc5
178 #define ODM_MGN_MCS6_SG 0xc6
179 #define ODM_MGN_MCS7_SG 0xc7
180 #define ODM_MGN_MCS8_SG 0xc8
181 #define ODM_MGN_MCS9_SG 0xc9
182 #define ODM_MGN_MCS10_SG 0xca
183 #define ODM_MGN_MCS11_SG 0xcb
184 #define ODM_MGN_MCS12_SG 0xcc
185 #define ODM_MGN_MCS13_SG 0xcd
186 #define ODM_MGN_MCS14_SG 0xce
187 #define ODM_MGN_MCS15_SG 0xcf
189 /* -----DESC rate--------------------------------- */
191 #define ODM_RATEMCS15_SG 0x1c
192 #define ODM_RATEMCS32 0x20
194 /* CCK Rates, TxHT = 0 */
195 #define ODM_RATE1M 0x00
196 #define ODM_RATE2M 0x01
197 #define ODM_RATE5_5M 0x02
198 #define ODM_RATE11M 0x03
199 /* OFDM Rates, TxHT = 0 */
200 #define ODM_RATE6M 0x04
201 #define ODM_RATE9M 0x05
202 #define ODM_RATE12M 0x06
203 #define ODM_RATE18M 0x07
204 #define ODM_RATE24M 0x08
205 #define ODM_RATE36M 0x09
206 #define ODM_RATE48M 0x0A
207 #define ODM_RATE54M 0x0B
208 /* MCS Rates, TxHT = 1 */
209 #define ODM_RATEMCS0 0x0C
210 #define ODM_RATEMCS1 0x0D
211 #define ODM_RATEMCS2 0x0E
212 #define ODM_RATEMCS3 0x0F
213 #define ODM_RATEMCS4 0x10
214 #define ODM_RATEMCS5 0x11
215 #define ODM_RATEMCS6 0x12
216 #define ODM_RATEMCS7 0x13
217 #define ODM_RATEMCS8 0x14
218 #define ODM_RATEMCS9 0x15
219 #define ODM_RATEMCS10 0x16
220 #define ODM_RATEMCS11 0x17
221 #define ODM_RATEMCS12 0x18
222 #define ODM_RATEMCS13 0x19
223 #define ODM_RATEMCS14 0x1A
224 #define ODM_RATEMCS15 0x1B
225 #define ODM_RATEMCS16 0x1C
226 #define ODM_RATEMCS17 0x1D
227 #define ODM_RATEMCS18 0x1E
228 #define ODM_RATEMCS19 0x1F
229 #define ODM_RATEMCS20 0x20
230 #define ODM_RATEMCS21 0x21
231 #define ODM_RATEMCS22 0x22
232 #define ODM_RATEMCS23 0x23
233 #define ODM_RATEMCS24 0x24
234 #define ODM_RATEMCS25 0x25
235 #define ODM_RATEMCS26 0x26
236 #define ODM_RATEMCS27 0x27
237 #define ODM_RATEMCS28 0x28
238 #define ODM_RATEMCS29 0x29
239 #define ODM_RATEMCS30 0x2A
240 #define ODM_RATEMCS31 0x2B
241 #define ODM_RATEVHTSS1MCS0 0x2C
242 #define ODM_RATEVHTSS1MCS1 0x2D
243 #define ODM_RATEVHTSS1MCS2 0x2E
244 #define ODM_RATEVHTSS1MCS3 0x2F
245 #define ODM_RATEVHTSS1MCS4 0x30
246 #define ODM_RATEVHTSS1MCS5 0x31
247 #define ODM_RATEVHTSS1MCS6 0x32
248 #define ODM_RATEVHTSS1MCS7 0x33
249 #define ODM_RATEVHTSS1MCS8 0x34
250 #define ODM_RATEVHTSS1MCS9 0x35
251 #define ODM_RATEVHTSS2MCS0 0x36
252 #define ODM_RATEVHTSS2MCS1 0x37
253 #define ODM_RATEVHTSS2MCS2 0x38
254 #define ODM_RATEVHTSS2MCS3 0x39
255 #define ODM_RATEVHTSS2MCS4 0x3A
256 #define ODM_RATEVHTSS2MCS5 0x3B
257 #define ODM_RATEVHTSS2MCS6 0x3C
258 #define ODM_RATEVHTSS2MCS7 0x3D
259 #define ODM_RATEVHTSS2MCS8 0x3E
260 #define ODM_RATEVHTSS2MCS9 0x3F
261 #define ODM_RATEVHTSS3MCS0 0x40
262 #define ODM_RATEVHTSS3MCS1 0x41
263 #define ODM_RATEVHTSS3MCS2 0x42
264 #define ODM_RATEVHTSS3MCS3 0x43
265 #define ODM_RATEVHTSS3MCS4 0x44
266 #define ODM_RATEVHTSS3MCS5 0x45
267 #define ODM_RATEVHTSS3MCS6 0x46
268 #define ODM_RATEVHTSS3MCS7 0x47
269 #define ODM_RATEVHTSS3MCS8 0x48
270 #define ODM_RATEVHTSS3MCS9 0x49
271 #define ODM_RATEVHTSS4MCS0 0x4A
272 #define ODM_RATEVHTSS4MCS1 0x4B
273 #define ODM_RATEVHTSS4MCS2 0x4C
274 #define ODM_RATEVHTSS4MCS3 0x4D
275 #define ODM_RATEVHTSS4MCS4 0x4E
276 #define ODM_RATEVHTSS4MCS5 0x4F
277 #define ODM_RATEVHTSS4MCS6 0x50
278 #define ODM_RATEVHTSS4MCS7 0x51
279 #define ODM_RATEVHTSS4MCS8 0x52
280 #define ODM_RATEVHTSS4MCS9 0x53
282 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
284 /* 1 ============================================================
286 * 1 ============================================================
289 /* ODM_CMNINFO_INTERFACE */
297 /* ODM_CMNINFO_IC_TYPE */
299 ODM_RTL8188E = BIT(0),
300 ODM_RTL8812 = BIT(1),
301 ODM_RTL8821 = BIT(2),
302 ODM_RTL8192E = BIT(3),
303 ODM_RTL8723B = BIT(4),
304 ODM_RTL8814A = BIT(5),
305 ODM_RTL8881A = BIT(6),
306 ODM_RTL8822B = BIT(7),
307 ODM_RTL8703B = BIT(8),
308 ODM_RTL8195A = BIT(9),
309 ODM_RTL8188F = BIT(10),
310 ODM_RTL8723D = BIT(11),
311 ODM_RTL8197F = BIT(12),
312 ODM_RTL8821C = BIT(13),
313 ODM_RTL8814B = BIT(14),
314 ODM_RTL8198F = BIT(15),
315 /* JJ ADD 20161014 */
316 ODM_RTL8710B = BIT(16),
319 /* JJ ADD 20161014 */
321 (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B | \
322 ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C | \
323 ODM_RTL8195A | ODM_RTL8710B)
324 #define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
325 #define ODM_IC_3SS (ODM_RTL8814A)
326 #define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
328 /* JJ ADD 20161014 */
329 #define ODM_IC_11N_SERIES \
330 (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | \
331 ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
332 #define ODM_IC_11AC_SERIES \
333 (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A | \
334 ODM_RTL8822B | ODM_RTL8821C)
335 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
336 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
337 #define ODM_IC_TXBF_SUPPORT \
338 (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | \
339 ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
340 #define ODM_IC_11N_GAIN_IDX_EDCCA \
341 (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D | \
342 ODM_RTL8197F | ODM_RTL8710B)
343 #define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
344 #define ODM_IC_PHY_STATUE_NEW_TYPE \
345 (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C | \
348 #define PHYDM_IC_8051_SERIES \
349 (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E | \
350 ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
351 #define PHYDM_IC_3081_SERIES \
352 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
354 #define PHYDM_IC_SUPPORT_LA_MODE \
355 (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
357 /* JJ ADD 20161014 */
359 /* ODM_CMNINFO_CUT_VER */
360 enum odm_cut_version {
374 /* ODM_CMNINFO_FAB_VER */
380 /* ODM_CMNINFO_RF_TYPE
382 * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
411 enum odm_mac_phy_mode {
417 enum odm_bt_coexist {
424 /* ODM_CMNINFO_OP_MODE */
425 enum odm_operation_mode {
426 ODM_NO_LINK = BIT(0),
429 ODM_POWERSAVE = BIT(3),
430 ODM_AP_MODE = BIT(4),
431 ODM_CLIENT_MODE = BIT(5),
433 ODM_WIFI_DIRECT = BIT(7),
434 ODM_WIFI_DISPLAY = BIT(8),
437 /* ODM_CMNINFO_WM_MODE */
438 enum odm_wireless_mode {
439 ODM_WM_UNKNOWN = 0x0,
443 ODM_WM_N24G = BIT(3),
445 ODM_WM_AUTO = BIT(5),
449 /* ODM_CMNINFO_BAND */
457 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
458 enum phydm_sec_chnl_offset {
464 /* ODM_CMNINFO_SEC_MODE */
472 ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
487 /* ODM_CMNINFO_CHNL */
489 /* ODM_CMNINFO_BOARD_TYPE */
490 enum odm_board_type {
491 ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
492 ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
493 ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
494 ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
496 BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
498 BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
500 BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
501 ODM_BOARD_EXT_PA_5G =
502 BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
503 ODM_BOARD_EXT_LNA_5G =
504 BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
507 enum odm_package_type {
508 ODM_PACKAGE_DEFAULT = 0,
509 ODM_PACKAGE_QFN68 = BIT(0),
510 ODM_PACKAGE_TFBGA90 = BIT(1),
511 ODM_PACKAGE_TFBGA79 = BIT(2),
563 TYPE_GLNA10 = 0xAAAA,
564 TYPE_GLNA11 = 0xAAFF,
565 TYPE_GLNA12 = 0xFF00,
566 TYPE_GLNA13 = 0xFF55,
567 TYPE_GLNA14 = 0xFFAA,
568 TYPE_GLNA15 = 0xFFFF,
582 TYPE_ALNA10 = 0xAAAA,
583 TYPE_ALNA11 = 0xAAFF,
584 TYPE_ALNA12 = 0xFF00,
585 TYPE_ALNA13 = 0xFF55,
586 TYPE_ALNA14 = 0xFFAA,
587 TYPE_ALNA15 = 0xFFFF,
590 enum odm_rf_radio_path {
591 ODM_RF_PATH_A = 0, /* Radio path A */
592 ODM_RF_PATH_B = 1, /* Radio path B */
593 ODM_RF_PATH_C = 2, /* Radio path C */
594 ODM_RF_PATH_D = 3, /* Radio path D */
605 /* ODM_RF_PATH_MAX, */ /* Max RF number 90 support */
608 enum odm_parameter_init {
610 ODM_POST_SETTING = 1,