drivers/staging/rtlwifi/phydm/phydm_pre_define.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __PHYDMPREDEFINE_H__
  27 #define __PHYDMPREDEFINE_H__
  28
  29 /* 1 ============================================================
  30  * 1  Definition
  31  * 1 ============================================================
  32  */
  33
  34 #define PHYDM_CODE_BASE "PHYDM_TRUNK"
  35 #define PHYDM_RELEASE_DATE "00000000"
  36
  37 /* Max path of IC */
  38 #define MAX_PATH_NUM_8188E 1
  39 #define MAX_PATH_NUM_8192E 2
  40 #define MAX_PATH_NUM_8723B 1
  41 #define MAX_PATH_NUM_8812A 2
  42 #define MAX_PATH_NUM_8821A 1
  43 #define MAX_PATH_NUM_8814A 4
  44 #define MAX_PATH_NUM_8822B 2
  45 #define MAX_PATH_NUM_8821B 2
  46 #define MAX_PATH_NUM_8703B 1
  47 #define MAX_PATH_NUM_8188F 1
  48 #define MAX_PATH_NUM_8723D 1
  49 #define MAX_PATH_NUM_8197F 2
  50 #define MAX_PATH_NUM_8821C 1
  51 /* JJ ADD 20161014 */
  52 #define MAX_PATH_NUM_8710B 1
  53
  54 /* Max RF path */
  55 #define ODM_RF_PATH_MAX 2
  56 #define ODM_RF_PATH_MAX_JAGUAR 4
  57
  58 /*Bit define path*/
  59 #define PHYDM_A BIT(0)
  60 #define PHYDM_B BIT(1)
  61 #define PHYDM_C BIT(2)
  62 #define PHYDM_D BIT(3)
  63 #define PHYDM_AB (BIT(0) | BIT(1))
  64 #define PHYDM_AC (BIT(0) | BIT(2))
  65 #define PHYDM_AD (BIT(0) | BIT(3))
  66 #define PHYDM_BC (BIT(1) | BIT(2))
  67 #define PHYDM_BD (BIT(1) | BIT(3))
  68 #define PHYDM_CD (BIT(2) | BIT(3))
  69 #define PHYDM_ABC (BIT(0) | BIT(1) | BIT(2))
  70 #define PHYDM_ABD (BIT(0) | BIT(1) | BIT(3))
  71 #define PHYDM_ACD (BIT(0) | BIT(2) | BIT(3))
  72 #define PHYDM_BCD (BIT(1) | BIT(2) | BIT(3))
  73 #define PHYDM_ABCD (BIT(0) | BIT(1) | BIT(2) | BIT(3))
  74
  75 /* number of entry */
  76 /* defined in wifi.h (32+1) */
  77 #define ODM_ASSOCIATE_ENTRY_NUM ASSOCIATE_ENTRY_NUM
  78
  79 #define RX_SMOOTH_FACTOR 20
  80
  81 /* -----MGN rate--------------------------------- */
  82
  83 enum ODM_MGN_RATE {
  84         ODM_MGN_1M = 0x02,
  85         ODM_MGN_2M = 0x04,
  86         ODM_MGN_5_5M = 0x0B,
  87         ODM_MGN_6M = 0x0C,
  88         ODM_MGN_9M = 0x12,
  89         ODM_MGN_11M = 0x16,
  90         ODM_MGN_12M = 0x18,
  91         ODM_MGN_18M = 0x24,
  92         ODM_MGN_24M = 0x30,
  93         ODM_MGN_36M = 0x48,
  94         ODM_MGN_48M = 0x60,
  95         ODM_MGN_54M = 0x6C,
  96         ODM_MGN_MCS32 = 0x7F,
  97         ODM_MGN_MCS0,
  98         ODM_MGN_MCS1,
  99         ODM_MGN_MCS2,
 100         ODM_MGN_MCS3,
 101         ODM_MGN_MCS4,
 102         ODM_MGN_MCS5,
 103         ODM_MGN_MCS6,
 104         ODM_MGN_MCS7,
 105         ODM_MGN_MCS8,
 106         ODM_MGN_MCS9,
 107         ODM_MGN_MCS10,
 108         ODM_MGN_MCS11,
 109         ODM_MGN_MCS12,
 110         ODM_MGN_MCS13,
 111         ODM_MGN_MCS14,
 112         ODM_MGN_MCS15,
 113         ODM_MGN_MCS16,
 114         ODM_MGN_MCS17,
 115         ODM_MGN_MCS18,
 116         ODM_MGN_MCS19,
 117         ODM_MGN_MCS20,
 118         ODM_MGN_MCS21,
 119         ODM_MGN_MCS22,
 120         ODM_MGN_MCS23,
 121         ODM_MGN_MCS24,
 122         ODM_MGN_MCS25,
 123         ODM_MGN_MCS26,
 124         ODM_MGN_MCS27,
 125         ODM_MGN_MCS28,
 126         ODM_MGN_MCS29,
 127         ODM_MGN_MCS30,
 128         ODM_MGN_MCS31,
 129         ODM_MGN_VHT1SS_MCS0,
 130         ODM_MGN_VHT1SS_MCS1,
 131         ODM_MGN_VHT1SS_MCS2,
 132         ODM_MGN_VHT1SS_MCS3,
 133         ODM_MGN_VHT1SS_MCS4,
 134         ODM_MGN_VHT1SS_MCS5,
 135         ODM_MGN_VHT1SS_MCS6,
 136         ODM_MGN_VHT1SS_MCS7,
 137         ODM_MGN_VHT1SS_MCS8,
 138         ODM_MGN_VHT1SS_MCS9,
 139         ODM_MGN_VHT2SS_MCS0,
 140         ODM_MGN_VHT2SS_MCS1,
 141         ODM_MGN_VHT2SS_MCS2,
 142         ODM_MGN_VHT2SS_MCS3,
 143         ODM_MGN_VHT2SS_MCS4,
 144         ODM_MGN_VHT2SS_MCS5,
 145         ODM_MGN_VHT2SS_MCS6,
 146         ODM_MGN_VHT2SS_MCS7,
 147         ODM_MGN_VHT2SS_MCS8,
 148         ODM_MGN_VHT2SS_MCS9,
 149         ODM_MGN_VHT3SS_MCS0,
 150         ODM_MGN_VHT3SS_MCS1,
 151         ODM_MGN_VHT3SS_MCS2,
 152         ODM_MGN_VHT3SS_MCS3,
 153         ODM_MGN_VHT3SS_MCS4,
 154         ODM_MGN_VHT3SS_MCS5,
 155         ODM_MGN_VHT3SS_MCS6,
 156         ODM_MGN_VHT3SS_MCS7,
 157         ODM_MGN_VHT3SS_MCS8,
 158         ODM_MGN_VHT3SS_MCS9,
 159         ODM_MGN_VHT4SS_MCS0,
 160         ODM_MGN_VHT4SS_MCS1,
 161         ODM_MGN_VHT4SS_MCS2,
 162         ODM_MGN_VHT4SS_MCS3,
 163         ODM_MGN_VHT4SS_MCS4,
 164         ODM_MGN_VHT4SS_MCS5,
 165         ODM_MGN_VHT4SS_MCS6,
 166         ODM_MGN_VHT4SS_MCS7,
 167         ODM_MGN_VHT4SS_MCS8,
 168         ODM_MGN_VHT4SS_MCS9,
 169         ODM_MGN_UNKNOWN
 170 };
 171
 172 #define ODM_MGN_MCS0_SG 0xc0
 173 #define ODM_MGN_MCS1_SG 0xc1
 174 #define ODM_MGN_MCS2_SG 0xc2
 175 #define ODM_MGN_MCS3_SG 0xc3
 176 #define ODM_MGN_MCS4_SG 0xc4
 177 #define ODM_MGN_MCS5_SG 0xc5
 178 #define ODM_MGN_MCS6_SG 0xc6
 179 #define ODM_MGN_MCS7_SG 0xc7
 180 #define ODM_MGN_MCS8_SG 0xc8
 181 #define ODM_MGN_MCS9_SG 0xc9
 182 #define ODM_MGN_MCS10_SG 0xca
 183 #define ODM_MGN_MCS11_SG 0xcb
 184 #define ODM_MGN_MCS12_SG 0xcc
 185 #define ODM_MGN_MCS13_SG 0xcd
 186 #define ODM_MGN_MCS14_SG 0xce
 187 #define ODM_MGN_MCS15_SG 0xcf
 188
 189 /* -----DESC rate--------------------------------- */
 190
 191 #define ODM_RATEMCS15_SG 0x1c
 192 #define ODM_RATEMCS32 0x20
 193
 194 /* CCK Rates, TxHT = 0 */
 195 #define ODM_RATE1M 0x00
 196 #define ODM_RATE2M 0x01
 197 #define ODM_RATE5_5M 0x02
 198 #define ODM_RATE11M 0x03
 199 /* OFDM Rates, TxHT = 0 */
 200 #define ODM_RATE6M 0x04
 201 #define ODM_RATE9M 0x05
 202 #define ODM_RATE12M 0x06
 203 #define ODM_RATE18M 0x07
 204 #define ODM_RATE24M 0x08
 205 #define ODM_RATE36M 0x09
 206 #define ODM_RATE48M 0x0A
 207 #define ODM_RATE54M 0x0B
 208 /* MCS Rates, TxHT = 1 */
 209 #define ODM_RATEMCS0 0x0C
 210 #define ODM_RATEMCS1 0x0D
 211 #define ODM_RATEMCS2 0x0E
 212 #define ODM_RATEMCS3 0x0F
 213 #define ODM_RATEMCS4 0x10
 214 #define ODM_RATEMCS5 0x11
 215 #define ODM_RATEMCS6 0x12
 216 #define ODM_RATEMCS7 0x13
 217 #define ODM_RATEMCS8 0x14
 218 #define ODM_RATEMCS9 0x15
 219 #define ODM_RATEMCS10 0x16
 220 #define ODM_RATEMCS11 0x17
 221 #define ODM_RATEMCS12 0x18
 222 #define ODM_RATEMCS13 0x19
 223 #define ODM_RATEMCS14 0x1A
 224 #define ODM_RATEMCS15 0x1B
 225 #define ODM_RATEMCS16 0x1C
 226 #define ODM_RATEMCS17 0x1D
 227 #define ODM_RATEMCS18 0x1E
 228 #define ODM_RATEMCS19 0x1F
 229 #define ODM_RATEMCS20 0x20
 230 #define ODM_RATEMCS21 0x21
 231 #define ODM_RATEMCS22 0x22
 232 #define ODM_RATEMCS23 0x23
 233 #define ODM_RATEMCS24 0x24
 234 #define ODM_RATEMCS25 0x25
 235 #define ODM_RATEMCS26 0x26
 236 #define ODM_RATEMCS27 0x27
 237 #define ODM_RATEMCS28 0x28
 238 #define ODM_RATEMCS29 0x29
 239 #define ODM_RATEMCS30 0x2A
 240 #define ODM_RATEMCS31 0x2B
 241 #define ODM_RATEVHTSS1MCS0 0x2C
 242 #define ODM_RATEVHTSS1MCS1 0x2D
 243 #define ODM_RATEVHTSS1MCS2 0x2E
 244 #define ODM_RATEVHTSS1MCS3 0x2F
 245 #define ODM_RATEVHTSS1MCS4 0x30
 246 #define ODM_RATEVHTSS1MCS5 0x31
 247 #define ODM_RATEVHTSS1MCS6 0x32
 248 #define ODM_RATEVHTSS1MCS7 0x33
 249 #define ODM_RATEVHTSS1MCS8 0x34
 250 #define ODM_RATEVHTSS1MCS9 0x35
 251 #define ODM_RATEVHTSS2MCS0 0x36
 252 #define ODM_RATEVHTSS2MCS1 0x37
 253 #define ODM_RATEVHTSS2MCS2 0x38
 254 #define ODM_RATEVHTSS2MCS3 0x39
 255 #define ODM_RATEVHTSS2MCS4 0x3A
 256 #define ODM_RATEVHTSS2MCS5 0x3B
 257 #define ODM_RATEVHTSS2MCS6 0x3C
 258 #define ODM_RATEVHTSS2MCS7 0x3D
 259 #define ODM_RATEVHTSS2MCS8 0x3E
 260 #define ODM_RATEVHTSS2MCS9 0x3F
 261 #define ODM_RATEVHTSS3MCS0 0x40
 262 #define ODM_RATEVHTSS3MCS1 0x41
 263 #define ODM_RATEVHTSS3MCS2 0x42
 264 #define ODM_RATEVHTSS3MCS3 0x43
 265 #define ODM_RATEVHTSS3MCS4 0x44
 266 #define ODM_RATEVHTSS3MCS5 0x45
 267 #define ODM_RATEVHTSS3MCS6 0x46
 268 #define ODM_RATEVHTSS3MCS7 0x47
 269 #define ODM_RATEVHTSS3MCS8 0x48
 270 #define ODM_RATEVHTSS3MCS9 0x49
 271 #define ODM_RATEVHTSS4MCS0 0x4A
 272 #define ODM_RATEVHTSS4MCS1 0x4B
 273 #define ODM_RATEVHTSS4MCS2 0x4C
 274 #define ODM_RATEVHTSS4MCS3 0x4D
 275 #define ODM_RATEVHTSS4MCS4 0x4E
 276 #define ODM_RATEVHTSS4MCS5 0x4F
 277 #define ODM_RATEVHTSS4MCS6 0x50
 278 #define ODM_RATEVHTSS4MCS7 0x51
 279 #define ODM_RATEVHTSS4MCS8 0x52
 280 #define ODM_RATEVHTSS4MCS9 0x53
 281
 282 #define ODM_NUM_RATE_IDX (ODM_RATEVHTSS4MCS9 + 1)
 283
 284 /* 1 ============================================================
 285  * 1  enumeration
 286  * 1 ============================================================
 287  */
 288
 289 /*      ODM_CMNINFO_INTERFACE */
 290 enum odm_interface {
 291         ODM_ITRF_PCIE = 0x1,
 292         ODM_ITRF_USB = 0x2,
 293         ODM_ITRF_SDIO = 0x4,
 294         ODM_ITRF_ALL = 0x7,
 295 };
 296
 297 /* ODM_CMNINFO_IC_TYPE */
 298 enum odm_ic_type {
 299         ODM_RTL8188E = BIT(0),
 300         ODM_RTL8812 = BIT(1),
 301         ODM_RTL8821 = BIT(2),
 302         ODM_RTL8192E = BIT(3),
 303         ODM_RTL8723B = BIT(4),
 304         ODM_RTL8814A = BIT(5),
 305         ODM_RTL8881A = BIT(6),
 306         ODM_RTL8822B = BIT(7),
 307         ODM_RTL8703B = BIT(8),
 308         ODM_RTL8195A = BIT(9),
 309         ODM_RTL8188F = BIT(10),
 310         ODM_RTL8723D = BIT(11),
 311         ODM_RTL8197F = BIT(12),
 312         ODM_RTL8821C = BIT(13),
 313         ODM_RTL8814B = BIT(14),
 314         ODM_RTL8198F = BIT(15),
 315         /* JJ ADD 20161014 */
 316         ODM_RTL8710B = BIT(16),
 317 };
 318
 319 /* JJ ADD 20161014 */
 320 #define ODM_IC_1SS                                                             \
 321         (ODM_RTL8188E | ODM_RTL8188F | ODM_RTL8723B | ODM_RTL8703B |           \
 322          ODM_RTL8723D | ODM_RTL8881A | ODM_RTL8821 | ODM_RTL8821C |            \
 323          ODM_RTL8195A | ODM_RTL8710B)
 324 #define ODM_IC_2SS (ODM_RTL8192E | ODM_RTL8197F | ODM_RTL8812 | ODM_RTL8822B)
 325 #define ODM_IC_3SS (ODM_RTL8814A)
 326 #define ODM_IC_4SS (ODM_RTL8814B | ODM_RTL8198F)
 327
 328 /* JJ ADD 20161014 */
 329 #define ODM_IC_11N_SERIES                                                      \
 330         (ODM_RTL8188E | ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B |           \
 331          ODM_RTL8188F | ODM_RTL8723D | ODM_RTL8197F | ODM_RTL8710B)
 332 #define ODM_IC_11AC_SERIES                                                     \
 333         (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A | ODM_RTL8881A |             \
 334          ODM_RTL8822B | ODM_RTL8821C)
 335 #define ODM_IC_11AC_1_SERIES (ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8881A)
 336 #define ODM_IC_11AC_2_SERIES (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
 337 #define ODM_IC_TXBF_SUPPORT                                                    \
 338         (ODM_RTL8192E | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8814A |             \
 339          ODM_RTL8881A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 340 #define ODM_IC_11N_GAIN_IDX_EDCCA                                              \
 341         (ODM_RTL8195A | ODM_RTL8703B | ODM_RTL8188F | ODM_RTL8723D |           \
 342          ODM_RTL8197F | ODM_RTL8710B)
 343 #define ODM_IC_11AC_GAIN_IDX_EDCCA (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8821C)
 344 #define ODM_IC_PHY_STATUE_NEW_TYPE                                             \
 345         (ODM_RTL8197F | ODM_RTL8822B | ODM_RTL8723D | ODM_RTL8821C |           \
 346          ODM_RTL8710B)
 347
 348 #define PHYDM_IC_8051_SERIES                                                   \
 349         (ODM_RTL8881A | ODM_RTL8812 | ODM_RTL8821 | ODM_RTL8188E |             \
 350          ODM_RTL8192E | ODM_RTL8723B | ODM_RTL8703B | ODM_RTL8188F)
 351 #define PHYDM_IC_3081_SERIES                                                   \
 352         (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 353
 354 #define PHYDM_IC_SUPPORT_LA_MODE                                               \
 355         (ODM_RTL8814A | ODM_RTL8822B | ODM_RTL8197F | ODM_RTL8821C)
 356
 357 /* JJ ADD 20161014 */
 358
 359 /* ODM_CMNINFO_CUT_VER */
 360 enum odm_cut_version {
 361         ODM_CUT_A = 0,
 362         ODM_CUT_B = 1,
 363         ODM_CUT_C = 2,
 364         ODM_CUT_D = 3,
 365         ODM_CUT_E = 4,
 366         ODM_CUT_F = 5,
 367
 368         ODM_CUT_I = 8,
 369         ODM_CUT_J = 9,
 370         ODM_CUT_K = 10,
 371         ODM_CUT_TEST = 15,
 372 };
 373
 374 /* ODM_CMNINFO_FAB_VER */
 375 enum odm_fab {
 376         ODM_TSMC = 0,
 377         ODM_UMC = 1,
 378 };
 379
 380 /* ODM_CMNINFO_RF_TYPE
 381  *
 382  * For example 1T2R (A+AB = BIT(0)|BIT(4)|BIT(5))
 383  */
 384 enum odm_rf_path {
 385         ODM_RF_A = BIT(0),
 386         ODM_RF_B = BIT(1),
 387         ODM_RF_C = BIT(2),
 388         ODM_RF_D = BIT(3),
 389 };
 390
 391 enum odm_rf_tx_num {
 392         ODM_1T = 1,
 393         ODM_2T = 2,
 394         ODM_3T = 3,
 395         ODM_4T = 4,
 396 };
 397
 398 enum odm_rf_type {
 399         ODM_1T1R,
 400         ODM_1T2R,
 401         ODM_2T2R,
 402         ODM_2T2R_GREEN,
 403         ODM_2T3R,
 404         ODM_2T4R,
 405         ODM_3T3R,
 406         ODM_3T4R,
 407         ODM_4T4R,
 408         ODM_XTXR
 409 };
 410
 411 enum odm_mac_phy_mode {
 412         ODM_SMSP = 0,
 413         ODM_DMSP = 1,
 414         ODM_DMDP = 2,
 415 };
 416
 417 enum odm_bt_coexist {
 418         ODM_BT_BUSY = 1,
 419         ODM_BT_ON = 2,
 420         ODM_BT_OFF = 3,
 421         ODM_BT_NONE = 4,
 422 };
 423
 424 /* ODM_CMNINFO_OP_MODE */
 425 enum odm_operation_mode {
 426         ODM_NO_LINK = BIT(0),
 427         ODM_LINK = BIT(1),
 428         ODM_SCAN = BIT(2),
 429         ODM_POWERSAVE = BIT(3),
 430         ODM_AP_MODE = BIT(4),
 431         ODM_CLIENT_MODE = BIT(5),
 432         ODM_AD_HOC = BIT(6),
 433         ODM_WIFI_DIRECT = BIT(7),
 434         ODM_WIFI_DISPLAY = BIT(8),
 435 };
 436
 437 /* ODM_CMNINFO_WM_MODE */
 438 enum odm_wireless_mode {
 439         ODM_WM_UNKNOWN = 0x0,
 440         ODM_WM_B = BIT(0),
 441         ODM_WM_G = BIT(1),
 442         ODM_WM_A = BIT(2),
 443         ODM_WM_N24G = BIT(3),
 444         ODM_WM_N5G = BIT(4),
 445         ODM_WM_AUTO = BIT(5),
 446         ODM_WM_AC = BIT(6),
 447 };
 448
 449 /* ODM_CMNINFO_BAND */
 450 enum odm_band_type {
 451         ODM_BAND_2_4G = 0,
 452         ODM_BAND_5G,
 453         ODM_BAND_ON_BOTH,
 454         ODM_BANDMAX
 455 };
 456
 457 /* ODM_CMNINFO_SEC_CHNL_OFFSET */
 458 enum phydm_sec_chnl_offset {
 459         PHYDM_DONT_CARE = 0,
 460         PHYDM_BELOW = 1,
 461         PHYDM_ABOVE = 2
 462 };
 463
 464 /* ODM_CMNINFO_SEC_MODE */
 465 enum odm_security {
 466         ODM_SEC_OPEN = 0,
 467         ODM_SEC_WEP40 = 1,
 468         ODM_SEC_TKIP = 2,
 469         ODM_SEC_RESERVE = 3,
 470         ODM_SEC_AESCCMP = 4,
 471         ODM_SEC_WEP104 = 5,
 472         ODM_WEP_WPA_MIXED = 6, /* WEP + WPA */
 473         ODM_SEC_SMS4 = 7,
 474 };
 475
 476 /* ODM_CMNINFO_BW */
 477 enum odm_bw {
 478         ODM_BW20M = 0,
 479         ODM_BW40M = 1,
 480         ODM_BW80M = 2,
 481         ODM_BW160M = 3,
 482         ODM_BW5M = 4,
 483         ODM_BW10M = 5,
 484         ODM_BW_MAX = 6
 485 };
 486
 487 /* ODM_CMNINFO_CHNL */
 488
 489 /* ODM_CMNINFO_BOARD_TYPE */
 490 enum odm_board_type {
 491         ODM_BOARD_DEFAULT = 0, /* The DEFAULT case. */
 492         ODM_BOARD_MINICARD = BIT(0), /* 0 = non-mini card, 1= mini card. */
 493         ODM_BOARD_SLIM = BIT(1), /* 0 = non-slim card, 1 = slim card */
 494         ODM_BOARD_BT = BIT(2), /* 0 = without BT card, 1 = with BT */
 495         ODM_BOARD_EXT_PA =
 496                 BIT(3), /* 0 = no 2G ext-PA, 1 = existing 2G ext-PA */
 497         ODM_BOARD_EXT_LNA =
 498                 BIT(4), /* 0 = no 2G ext-LNA, 1 = existing 2G ext-LNA */
 499         ODM_BOARD_EXT_TRSW =
 500                 BIT(5), /* 0 = no ext-TRSW, 1 = existing ext-TRSW */
 501         ODM_BOARD_EXT_PA_5G =
 502                 BIT(6), /* 0 = no 5G ext-PA, 1 = existing 5G ext-PA */
 503         ODM_BOARD_EXT_LNA_5G =
 504                 BIT(7), /* 0 = no 5G ext-LNA, 1 = existing 5G ext-LNA */
 505 };
 506
 507 enum odm_package_type {
 508         ODM_PACKAGE_DEFAULT = 0,
 509         ODM_PACKAGE_QFN68 = BIT(0),
 510         ODM_PACKAGE_TFBGA90 = BIT(1),
 511         ODM_PACKAGE_TFBGA79 = BIT(2),
 512 };
 513
 514 enum odm_type_gpa {
 515         TYPE_GPA0 = 0x0000,
 516         TYPE_GPA1 = 0x0055,
 517         TYPE_GPA2 = 0x00AA,
 518         TYPE_GPA3 = 0x00FF,
 519         TYPE_GPA4 = 0x5500,
 520         TYPE_GPA5 = 0x5555,
 521         TYPE_GPA6 = 0x55AA,
 522         TYPE_GPA7 = 0x55FF,
 523         TYPE_GPA8 = 0xAA00,
 524         TYPE_GPA9 = 0xAA55,
 525         TYPE_GPA10 = 0xAAAA,
 526         TYPE_GPA11 = 0xAAFF,
 527         TYPE_GPA12 = 0xFF00,
 528         TYPE_GPA13 = 0xFF55,
 529         TYPE_GPA14 = 0xFFAA,
 530         TYPE_GPA15 = 0xFFFF,
 531 };
 532
 533 enum odm_type_apa {
 534         TYPE_APA0 = 0x0000,
 535         TYPE_APA1 = 0x0055,
 536         TYPE_APA2 = 0x00AA,
 537         TYPE_APA3 = 0x00FF,
 538         TYPE_APA4 = 0x5500,
 539         TYPE_APA5 = 0x5555,
 540         TYPE_APA6 = 0x55AA,
 541         TYPE_APA7 = 0x55FF,
 542         TYPE_APA8 = 0xAA00,
 543         TYPE_APA9 = 0xAA55,
 544         TYPE_APA10 = 0xAAAA,
 545         TYPE_APA11 = 0xAAFF,
 546         TYPE_APA12 = 0xFF00,
 547         TYPE_APA13 = 0xFF55,
 548         TYPE_APA14 = 0xFFAA,
 549         TYPE_APA15 = 0xFFFF,
 550 };
 551
 552 enum odm_type_glna {
 553         TYPE_GLNA0 = 0x0000,
 554         TYPE_GLNA1 = 0x0055,
 555         TYPE_GLNA2 = 0x00AA,
 556         TYPE_GLNA3 = 0x00FF,
 557         TYPE_GLNA4 = 0x5500,
 558         TYPE_GLNA5 = 0x5555,
 559         TYPE_GLNA6 = 0x55AA,
 560         TYPE_GLNA7 = 0x55FF,
 561         TYPE_GLNA8 = 0xAA00,
 562         TYPE_GLNA9 = 0xAA55,
 563         TYPE_GLNA10 = 0xAAAA,
 564         TYPE_GLNA11 = 0xAAFF,
 565         TYPE_GLNA12 = 0xFF00,
 566         TYPE_GLNA13 = 0xFF55,
 567         TYPE_GLNA14 = 0xFFAA,
 568         TYPE_GLNA15 = 0xFFFF,
 569 };
 570
 571 enum odm_type_alna {
 572         TYPE_ALNA0 = 0x0000,
 573         TYPE_ALNA1 = 0x0055,
 574         TYPE_ALNA2 = 0x00AA,
 575         TYPE_ALNA3 = 0x00FF,
 576         TYPE_ALNA4 = 0x5500,
 577         TYPE_ALNA5 = 0x5555,
 578         TYPE_ALNA6 = 0x55AA,
 579         TYPE_ALNA7 = 0x55FF,
 580         TYPE_ALNA8 = 0xAA00,
 581         TYPE_ALNA9 = 0xAA55,
 582         TYPE_ALNA10 = 0xAAAA,
 583         TYPE_ALNA11 = 0xAAFF,
 584         TYPE_ALNA12 = 0xFF00,
 585         TYPE_ALNA13 = 0xFF55,
 586         TYPE_ALNA14 = 0xFFAA,
 587         TYPE_ALNA15 = 0xFFFF,
 588 };
 589
 590 enum odm_rf_radio_path {
 591         ODM_RF_PATH_A = 0, /* Radio path A */
 592         ODM_RF_PATH_B = 1, /* Radio path B */
 593         ODM_RF_PATH_C = 2, /* Radio path C */
 594         ODM_RF_PATH_D = 3, /* Radio path D */
 595         ODM_RF_PATH_AB,
 596         ODM_RF_PATH_AC,
 597         ODM_RF_PATH_AD,
 598         ODM_RF_PATH_BC,
 599         ODM_RF_PATH_BD,
 600         ODM_RF_PATH_CD,
 601         ODM_RF_PATH_ABC,
 602         ODM_RF_PATH_ACD,
 603         ODM_RF_PATH_BCD,
 604         ODM_RF_PATH_ABCD,
 605         /* ODM_RF_PATH_MAX,    */ /* Max RF number 90 support */
 606 };
 607
 608 enum odm_parameter_init {
 609         ODM_PRE_SETTING = 0,
 610         ODM_POST_SETTING = 1,
 611 };
 612
 613 #endif