drivers/staging/rtlwifi/phydm/phydm_rainfo.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14
  15 /* ************************************************************
  16  * include files
  17  * *************************************************************/
  18 #include "mp_precomp.h"
  19 #include "phydm_precomp.h"
  20
  21 void phydm_h2C_debug(void *dm_void, u32 *const dm_value, u32 *_used,
  22                      char *output, u32 *_out_len)
  23 {
  24         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  25         u8 h2c_parameter[H2C_MAX_LENGTH] = {0};
  26         u8 phydm_h2c_id = (u8)dm_value[0];
  27         u8 i;
  28         u32 used = *_used;
  29         u32 out_len = *_out_len;
  30
  31         PHYDM_SNPRINTF(output + used, out_len - used,
  32                        "Phydm Send H2C_ID (( 0x%x))\n", phydm_h2c_id);
  33         for (i = 0; i < H2C_MAX_LENGTH; i++) {
  34                 h2c_parameter[i] = (u8)dm_value[i + 1];
  35                 PHYDM_SNPRINTF(output + used, out_len - used,
  36                                "H2C: Byte[%d] = ((0x%x))\n", i,
  37                                h2c_parameter[i]);
  38         }
  39
  40         odm_fill_h2c_cmd(dm, phydm_h2c_id, H2C_MAX_LENGTH, h2c_parameter);
  41 }
  42
  43 void phydm_RA_debug_PCR(void *dm_void, u32 *const dm_value, u32 *_used,
  44                         char *output, u32 *_out_len)
  45 {
  46         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  47         struct ra_table *ra_tab = &dm->dm_ra_table;
  48         u32 used = *_used;
  49         u32 out_len = *_out_len;
  50
  51         if (dm_value[0] == 100) {
  52                 PHYDM_SNPRINTF(
  53                         output + used, out_len - used,
  54                         "[Get] PCR RA_threshold_offset = (( %s%d ))\n",
  55                         ((ra_tab->RA_threshold_offset == 0) ?
  56                                  " " :
  57                                  ((ra_tab->RA_offset_direction) ? "+" : "-")),
  58                         ra_tab->RA_threshold_offset);
  59                 /**/
  60         } else if (dm_value[0] == 0) {
  61                 ra_tab->RA_offset_direction = 0;
  62                 ra_tab->RA_threshold_offset = (u8)dm_value[1];
  63                 PHYDM_SNPRINTF(output + used, out_len - used,
  64                                "[Set] PCR RA_threshold_offset = (( -%d ))\n",
  65                                ra_tab->RA_threshold_offset);
  66         } else if (dm_value[0] == 1) {
  67                 ra_tab->RA_offset_direction = 1;
  68                 ra_tab->RA_threshold_offset = (u8)dm_value[1];
  69                 PHYDM_SNPRINTF(output + used, out_len - used,
  70                                "[Set] PCR RA_threshold_offset = (( +%d ))\n",
  71                                ra_tab->RA_threshold_offset);
  72         } else {
  73                 PHYDM_SNPRINTF(output + used, out_len - used, "[Set] Error\n");
  74                 /**/
  75         }
  76 }
  77
  78 void odm_c2h_ra_para_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
  79 {
  80         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
  81
  82         u8 para_idx = cmd_buf[0]; /*Retry Penalty, NH, NL*/
  83         u8 i;
  84
  85         ODM_RT_TRACE(dm, PHYDM_COMP_RA_DBG,
  86                      "[ From FW C2H RA Para ]  cmd_buf[0]= (( %d ))\n",
  87                      cmd_buf[0]);
  88
  89         if (para_idx == RADBG_DEBUG_MONITOR1) {
  90                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
  91                              "-------------------------------\n");
  92                 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
  93                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
  94                                      "RSSI =", cmd_buf[1]);
  95                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
  96                                      "rate =", cmd_buf[2] & 0x7f);
  97                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
  98                                      "SGI =", (cmd_buf[2] & 0x80) >> 7);
  99                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 100                                      "BW =", cmd_buf[3]);
 101                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 102                                      "BW_max =", cmd_buf[4]);
 103                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 104                                      "multi_rate0 =", cmd_buf[5]);
 105                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 106                                      "multi_rate1 =", cmd_buf[6]);
 107                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 108                                      "DISRA =", cmd_buf[7]);
 109                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 110                                      "VHT_EN =", cmd_buf[8]);
 111                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 112                                      "SGI_support =", cmd_buf[9]);
 113                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 114                                      "try_ness =", cmd_buf[10]);
 115                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 116                                      "pre_rate =", cmd_buf[11]);
 117                 } else {
 118                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 119                                      "RSSI =", cmd_buf[1]);
 120                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %x\n",
 121                                      "BW =", cmd_buf[2]);
 122                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 123                                      "DISRA =", cmd_buf[3]);
 124                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 125                                      "VHT_EN =", cmd_buf[4]);
 126                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 127                                      "Hightest rate =", cmd_buf[5]);
 128                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 129                                      "Lowest rate =", cmd_buf[6]);
 130                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 131                                      "SGI_support =", cmd_buf[7]);
 132                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 133                                      "Rate_ID =", cmd_buf[8]);
 134                 }
 135                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 136                              "-------------------------------\n");
 137         } else if (para_idx == RADBG_DEBUG_MONITOR2) {
 138                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 139                              "-------------------------------\n");
 140                 if (dm->support_ic_type & PHYDM_IC_3081_SERIES) {
 141                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 142                                      "rate_id =", cmd_buf[1]);
 143                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 144                                      "highest_rate =", cmd_buf[2]);
 145                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 146                                      "lowest_rate =", cmd_buf[3]);
 147
 148                         for (i = 4; i <= 11; i++)
 149                                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 150                                              "RAMASK =  0x%x\n", cmd_buf[i]);
 151                 } else {
 152                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 153                                      "%5s  %x%x  %x%x  %x%x  %x%x\n",
 154                                      "RA Mask:", cmd_buf[8], cmd_buf[7],
 155                                      cmd_buf[6], cmd_buf[5], cmd_buf[4],
 156                                      cmd_buf[3], cmd_buf[2], cmd_buf[1]);
 157                 }
 158                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 159                              "-------------------------------\n");
 160         } else if (para_idx == RADBG_DEBUG_MONITOR3) {
 161                 for (i = 0; i < (cmd_len - 1); i++)
 162                         ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE,
 163                                      "content[%d] = %d\n", i, cmd_buf[1 + i]);
 164         } else if (para_idx == RADBG_DEBUG_MONITOR4) {
 165                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  {%d.%d}\n",
 166                              "RA version =", cmd_buf[1], cmd_buf[2]);
 167         } else if (para_idx == RADBG_DEBUG_MONITOR5) {
 168                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 169                              "Current rate =", cmd_buf[1]);
 170                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 171                              "Retry ratio =", cmd_buf[2]);
 172                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  %d\n",
 173                              "rate down ratio =", cmd_buf[3]);
 174                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x\n",
 175                              "highest rate =", cmd_buf[4]);
 176                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  {0x%x 0x%x}\n",
 177                              "Muti-try =", cmd_buf[5], cmd_buf[6]);
 178                 ODM_RT_TRACE(dm, ODM_FW_DEBUG_TRACE, "%5s  0x%x%x%x%x%x\n",
 179                              "RA mask =", cmd_buf[11], cmd_buf[10], cmd_buf[9],
 180                              cmd_buf[8], cmd_buf[7]);
 181         }
 182 }
 183
 184 void phydm_ra_dynamic_retry_count(void *dm_void)
 185 {
 186         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 187
 188         if (!(dm->support_ability & ODM_BB_DYNAMIC_ARFR))
 189                 return;
 190
 191         if (dm->pre_b_noisy != dm->noisy_decision) {
 192                 if (dm->noisy_decision) {
 193                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 194                                      "->Noisy Env. RA fallback value\n");
 195                         odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x0);
 196                         odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x04030201);
 197                 } else {
 198                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 199                                      "->Clean Env. RA fallback value\n");
 200                         odm_set_mac_reg(dm, 0x430, MASKDWORD, 0x01000000);
 201                         odm_set_mac_reg(dm, 0x434, MASKDWORD, 0x06050402);
 202                 }
 203                 dm->pre_b_noisy = dm->noisy_decision;
 204         }
 205 }
 206
 207 void phydm_ra_dynamic_retry_limit(void *dm_void) {}
 208
 209 void phydm_print_rate(void *dm_void, u8 rate, u32 dbg_component)
 210 {
 211         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 212         u8 legacy_table[12] = {1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54};
 213         u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 214         u8 vht_en = (rate_idx >= ODM_RATEVHTSS1MCS0) ? 1 : 0;
 215         u8 b_sgi = (rate & 0x80) >> 7;
 216
 217         ODM_RT_TRACE(dm, dbg_component, "( %s%s%s%s%d%s%s)\n",
 218                      ((rate_idx >= ODM_RATEVHTSS1MCS0) &&
 219                       (rate_idx <= ODM_RATEVHTSS1MCS9)) ?
 220                              "VHT 1ss  " :
 221                              "",
 222                      ((rate_idx >= ODM_RATEVHTSS2MCS0) &&
 223                       (rate_idx <= ODM_RATEVHTSS2MCS9)) ?
 224                              "VHT 2ss " :
 225                              "",
 226                      ((rate_idx >= ODM_RATEVHTSS3MCS0) &&
 227                       (rate_idx <= ODM_RATEVHTSS3MCS9)) ?
 228                              "VHT 3ss " :
 229                              "",
 230                      (rate_idx >= ODM_RATEMCS0) ? "MCS " : "",
 231                      (vht_en) ? ((rate_idx - ODM_RATEVHTSS1MCS0) % 10) :
 232                                 ((rate_idx >= ODM_RATEMCS0) ?
 233                                          (rate_idx - ODM_RATEMCS0) :
 234                                          ((rate_idx <= ODM_RATE54M) ?
 235                                                   legacy_table[rate_idx] :
 236                                                   0)),
 237                      (b_sgi) ? "-S" : "  ",
 238                      (rate_idx >= ODM_RATEMCS0) ? "" : "M");
 239 }
 240
 241 void phydm_c2h_ra_report_handler(void *dm_void, u8 *cmd_buf, u8 cmd_len)
 242 {
 243         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 244         struct ra_table *ra_tab = &dm->dm_ra_table;
 245         u8 macid = cmd_buf[1];
 246         u8 rate = cmd_buf[0];
 247         u8 rate_idx = rate & 0x7f; /*remove bit7 SGI*/
 248         u8 rate_order;
 249
 250         if (cmd_len >= 4) {
 251                 if (cmd_buf[3] == 0) {
 252                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 253                                      "TX Init-rate Update[%d]:", macid);
 254                         /**/
 255                 } else if (cmd_buf[3] == 0xff) {
 256                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 257                                      "FW Level: Fix rate[%d]:", macid);
 258                         /**/
 259                 } else if (cmd_buf[3] == 1) {
 260                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 261                                      "Try Success[%d]:", macid);
 262                         /**/
 263                 } else if (cmd_buf[3] == 2) {
 264                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 265                                      "Try Fail & Try Again[%d]:", macid);
 266                         /**/
 267                 } else if (cmd_buf[3] == 3) {
 268                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 269                                      "rate Back[%d]:", macid);
 270                         /**/
 271                 } else if (cmd_buf[3] == 4) {
 272                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 273                                      "start rate by RSSI[%d]:", macid);
 274                         /**/
 275                 } else if (cmd_buf[3] == 5) {
 276                         ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE,
 277                                      "Try rate[%d]:", macid);
 278                         /**/
 279                 }
 280         } else {
 281                 ODM_RT_TRACE(dm, ODM_COMP_RATE_ADAPTIVE, "Tx rate Update[%d]:",
 282                              macid);
 283                 /**/
 284         }
 285
 286         phydm_print_rate(dm, rate, ODM_COMP_RATE_ADAPTIVE);
 287
 288         ra_tab->link_tx_rate[macid] = rate;
 289
 290         /*trigger power training*/
 291
 292         rate_order = phydm_rate_order_compute(dm, rate_idx);
 293
 294         if ((dm->is_one_entry_only) ||
 295             ((rate_order > ra_tab->highest_client_tx_order) &&
 296              (ra_tab->power_tracking_flag == 1))) {
 297                 phydm_update_pwr_track(dm, rate_idx);
 298                 ra_tab->power_tracking_flag = 0;
 299         }
 300
 301         /*trigger dynamic rate ID*/
 302 }
 303
 304 void odm_rssi_monitor_init(void *dm_void)
 305 {
 306         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 307         struct ra_table *ra_tab = &dm->dm_ra_table;
 308
 309         ra_tab->firstconnect = false;
 310 }
 311
 312 void odm_ra_post_action_on_assoc(void *dm_void) {}
 313
 314 void phydm_init_ra_info(void *dm_void)
 315 {
 316         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 317
 318         if (dm->support_ic_type == ODM_RTL8822B) {
 319                 u32 ret_value;
 320
 321                 ret_value = odm_get_bb_reg(dm, 0x4c8, MASKBYTE2);
 322                 odm_set_bb_reg(dm, 0x4cc, MASKBYTE3, (ret_value - 1));
 323         }
 324 }
 325
 326 void phydm_modify_RA_PCR_threshold(void *dm_void, u8 RA_offset_direction,
 327                                    u8 RA_threshold_offset
 328
 329                                    )
 330 {
 331         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 332         struct ra_table *ra_tab = &dm->dm_ra_table;
 333
 334         ra_tab->RA_offset_direction = RA_offset_direction;
 335         ra_tab->RA_threshold_offset = RA_threshold_offset;
 336         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 337                      "Set RA_threshold_offset = (( %s%d ))\n",
 338                      ((RA_threshold_offset == 0) ?
 339                               " " :
 340                               ((RA_offset_direction) ? "+" : "-")),
 341                      RA_threshold_offset);
 342 }
 343
 344 static void odm_rssi_monitor_check_mp(void *dm_void) {}
 345
 346 static void odm_rssi_monitor_check_ce(void *dm_void)
 347 {
 348         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 349         struct ra_table *ra_tab = &dm->dm_ra_table;
 350         struct rtl_priv *rtlpriv = (struct rtl_priv *)dm->adapter;
 351         struct rtl_mac *mac = rtl_mac(rtlpriv);
 352         struct rtl_sta_info *entry;
 353         int i;
 354         int tmp_entry_min_pwdb = 0xff;
 355         unsigned long cur_tx_ok_cnt = 0, cur_rx_ok_cnt = 0;
 356         u8 UL_DL_STATE = 0, STBC_TX = 0, tx_bf_en = 0;
 357         u8 h2c_parameter[H2C_0X42_LENGTH] = {0};
 358         u8 cmdlen = H2C_0X42_LENGTH;
 359         u8 macid = 0;
 360
 361         if (!dm->is_linked)
 362                 return;
 363
 364         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 365                 entry = (struct rtl_sta_info *)dm->odm_sta_info[i];
 366                 if (!IS_STA_VALID(entry))
 367                         continue;
 368
 369                 if (is_multicast_ether_addr(entry->mac_addr) ||
 370                     is_broadcast_ether_addr(entry->mac_addr))
 371                         continue;
 372
 373                 if (entry->rssi_stat.undecorated_smoothed_pwdb == (-1))
 374                         continue;
 375
 376                 /* calculate min_pwdb */
 377                 if (entry->rssi_stat.undecorated_smoothed_pwdb <
 378                     tmp_entry_min_pwdb)
 379                         tmp_entry_min_pwdb =
 380                                 entry->rssi_stat.undecorated_smoothed_pwdb;
 381
 382                 /* report RSSI */
 383                 cur_tx_ok_cnt = rtlpriv->stats.txbytesunicast_inperiod;
 384                 cur_rx_ok_cnt = rtlpriv->stats.rxbytesunicast_inperiod;
 385
 386                 if (cur_rx_ok_cnt > (cur_tx_ok_cnt * 6))
 387                         UL_DL_STATE = 1;
 388                 else
 389                         UL_DL_STATE = 0;
 390
 391                 if (mac->opmode == NL80211_IFTYPE_AP ||
 392                     mac->opmode == NL80211_IFTYPE_ADHOC) {
 393                         struct ieee80211_sta *sta = container_of(
 394                                 (void *)entry, struct ieee80211_sta, drv_priv);
 395                         macid = sta->aid + 1;
 396                 }
 397
 398                 h2c_parameter[0] = macid;
 399                 h2c_parameter[2] =
 400                         entry->rssi_stat.undecorated_smoothed_pwdb & 0x7F;
 401
 402                 if (UL_DL_STATE)
 403                         h2c_parameter[3] |= RAINFO_BE_RX_STATE;
 404
 405                 if (tx_bf_en)
 406                         h2c_parameter[3] |= RAINFO_BF_STATE;
 407                 if (STBC_TX)
 408                         h2c_parameter[3] |= RAINFO_STBC_STATE;
 409                 if (dm->noisy_decision)
 410                         h2c_parameter[3] |= RAINFO_NOISY_STATE;
 411
 412                 if (entry->rssi_stat.is_send_rssi == RA_RSSI_STATE_SEND) {
 413                         h2c_parameter[3] |= RAINFO_INIT_RSSI_RATE_STATE;
 414                         entry->rssi_stat.is_send_rssi = RA_RSSI_STATE_HOLD;
 415                 }
 416
 417                 h2c_parameter[4] = (ra_tab->RA_threshold_offset & 0x7f) |
 418                                    (ra_tab->RA_offset_direction << 7);
 419
 420                 odm_fill_h2c_cmd(dm, ODM_H2C_RSSI_REPORT, cmdlen,
 421                                  h2c_parameter);
 422         }
 423
 424         if (tmp_entry_min_pwdb != 0xff)
 425                 dm->rssi_min = tmp_entry_min_pwdb;
 426 }
 427
 428 static void odm_rssi_monitor_check_ap(void *dm_void) {}
 429
 430 void odm_rssi_monitor_check(void *dm_void)
 431 {
 432         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 433
 434         if (!(dm->support_ability & ODM_BB_RSSI_MONITOR))
 435                 return;
 436
 437         switch (dm->support_platform) {
 438         case ODM_WIN:
 439                 odm_rssi_monitor_check_mp(dm);
 440                 break;
 441
 442         case ODM_CE:
 443                 odm_rssi_monitor_check_ce(dm);
 444                 break;
 445
 446         case ODM_AP:
 447                 odm_rssi_monitor_check_ap(dm);
 448                 break;
 449
 450         default:
 451                 break;
 452         }
 453 }
 454
 455 void odm_rate_adaptive_mask_init(void *dm_void)
 456 {
 457         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 458         struct odm_rate_adaptive *odm_ra = &dm->rate_adaptive;
 459
 460         odm_ra->type = dm_type_by_driver;
 461         if (odm_ra->type == dm_type_by_driver)
 462                 dm->is_use_ra_mask = true;
 463         else
 464                 dm->is_use_ra_mask = false;
 465
 466         odm_ra->ratr_state = DM_RATR_STA_INIT;
 467
 468         odm_ra->ldpc_thres = 35;
 469         odm_ra->is_use_ldpc = false;
 470
 471         odm_ra->high_rssi_thresh = 50;
 472         odm_ra->low_rssi_thresh = 20;
 473 }
 474
 475 /*-----------------------------------------------------------------------------
 476  * Function:    odm_refresh_rate_adaptive_mask()
 477  *
 478  * Overview:    Update rate table mask according to rssi
 479  *
 480  * Input:               NONE
 481  *
 482  * Output:              NONE
 483  *
 484  * Return:              NONE
 485  *
 486  * Revised History:
 487  *      When            Who             Remark
 488  *      05/27/2009      hpfan   Create version 0.
 489  *
 490  *---------------------------------------------------------------------------
 491  */
 492 void odm_refresh_rate_adaptive_mask(void *dm_void)
 493 {
 494         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 495         struct ra_table *ra_tab = &dm->dm_ra_table;
 496
 497         if (!dm->is_linked)
 498                 return;
 499
 500         if (!(dm->support_ability & ODM_BB_RA_MASK)) {
 501                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 502                              "%s(): Return cos not supported\n", __func__);
 503                 return;
 504         }
 505
 506         ra_tab->force_update_ra_mask_count++;
 507         /* 2011/09/29 MH In HW integration first stage, we provide 4 different
 508          * handle to operate at the same time.
 509          * In the stage2/3, we need to prive universal interface and merge all
 510          * HW dynamic mechanism.
 511          */
 512         switch (dm->support_platform) {
 513         case ODM_WIN:
 514                 odm_refresh_rate_adaptive_mask_mp(dm);
 515                 break;
 516
 517         case ODM_CE:
 518                 odm_refresh_rate_adaptive_mask_ce(dm);
 519                 break;
 520
 521         case ODM_AP:
 522                 odm_refresh_rate_adaptive_mask_apadsl(dm);
 523                 break;
 524         }
 525 }
 526
 527 static u8 phydm_trans_platform_bw(void *dm_void, u8 BW)
 528 {
 529         if (BW == HT_CHANNEL_WIDTH_20)
 530                 BW = PHYDM_BW_20;
 531
 532         else if (BW == HT_CHANNEL_WIDTH_20_40)
 533                 BW = PHYDM_BW_40;
 534
 535         else if (BW == HT_CHANNEL_WIDTH_80)
 536                 BW = PHYDM_BW_80;
 537
 538         return BW;
 539 }
 540
 541 static u8 phydm_trans_platform_rf_type(void *dm_void, u8 rf_type)
 542 {
 543         if (rf_type == RF_1T2R)
 544                 rf_type = PHYDM_RF_1T2R;
 545
 546         else if (rf_type == RF_2T4R)
 547                 rf_type = PHYDM_RF_2T4R;
 548
 549         else if (rf_type == RF_2T2R)
 550                 rf_type = PHYDM_RF_2T2R;
 551
 552         else if (rf_type == RF_1T1R)
 553                 rf_type = PHYDM_RF_1T1R;
 554
 555         else if (rf_type == RF_2T2R_GREEN)
 556                 rf_type = PHYDM_RF_2T2R_GREEN;
 557
 558         else if (rf_type == RF_3T3R)
 559                 rf_type = PHYDM_RF_3T3R;
 560
 561         else if (rf_type == RF_4T4R)
 562                 rf_type = PHYDM_RF_4T4R;
 563
 564         else if (rf_type == RF_2T3R)
 565                 rf_type = PHYDM_RF_1T2R;
 566
 567         else if (rf_type == RF_3T4R)
 568                 rf_type = PHYDM_RF_3T4R;
 569
 570         return rf_type;
 571 }
 572
 573 static u32 phydm_trans_platform_wireless_mode(void *dm_void, u32 wireless_mode)
 574 {
 575         return wireless_mode;
 576 }
 577
 578 u8 phydm_vht_en_mapping(void *dm_void, u32 wireless_mode)
 579 {
 580         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 581         u8 vht_en_out = 0;
 582
 583         if ((wireless_mode == PHYDM_WIRELESS_MODE_AC_5G) ||
 584             (wireless_mode == PHYDM_WIRELESS_MODE_AC_24G) ||
 585             (wireless_mode == PHYDM_WIRELESS_MODE_AC_ONLY)) {
 586                 vht_en_out = 1;
 587                 /**/
 588         }
 589
 590         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 591                      "wireless_mode= (( 0x%x )), VHT_EN= (( %d ))\n",
 592                      wireless_mode, vht_en_out);
 593         return vht_en_out;
 594 }
 595
 596 u8 phydm_rate_id_mapping(void *dm_void, u32 wireless_mode, u8 rf_type, u8 bw)
 597 {
 598         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 599         u8 rate_id_idx = 0;
 600         u8 phydm_BW;
 601         u8 phydm_rf_type;
 602
 603         phydm_BW = phydm_trans_platform_bw(dm, bw);
 604         phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
 605         wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
 606
 607         ODM_RT_TRACE(
 608                 dm, ODM_COMP_RA_MASK,
 609                 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x ))\n",
 610                 wireless_mode, phydm_rf_type, phydm_BW);
 611
 612         switch (wireless_mode) {
 613         case PHYDM_WIRELESS_MODE_N_24G: {
 614                 if (phydm_BW == PHYDM_BW_40) {
 615                         if (phydm_rf_type == PHYDM_RF_1T1R)
 616                                 rate_id_idx = PHYDM_BGN_40M_1SS;
 617                         else if (phydm_rf_type == PHYDM_RF_2T2R)
 618                                 rate_id_idx = PHYDM_BGN_40M_2SS;
 619                         else
 620                                 rate_id_idx = PHYDM_ARFR5_N_3SS;
 621
 622                 } else {
 623                         if (phydm_rf_type == PHYDM_RF_1T1R)
 624                                 rate_id_idx = PHYDM_BGN_20M_1SS;
 625                         else if (phydm_rf_type == PHYDM_RF_2T2R)
 626                                 rate_id_idx = PHYDM_BGN_20M_2SS;
 627                         else
 628                                 rate_id_idx = PHYDM_ARFR5_N_3SS;
 629                 }
 630         } break;
 631
 632         case PHYDM_WIRELESS_MODE_N_5G: {
 633                 if (phydm_rf_type == PHYDM_RF_1T1R)
 634                         rate_id_idx = PHYDM_GN_N1SS;
 635                 else if (phydm_rf_type == PHYDM_RF_2T2R)
 636                         rate_id_idx = PHYDM_GN_N2SS;
 637                 else
 638                         rate_id_idx = PHYDM_ARFR5_N_3SS;
 639         }
 640
 641         break;
 642
 643         case PHYDM_WIRELESS_MODE_G:
 644                 rate_id_idx = PHYDM_BG;
 645                 break;
 646
 647         case PHYDM_WIRELESS_MODE_A:
 648                 rate_id_idx = PHYDM_G;
 649                 break;
 650
 651         case PHYDM_WIRELESS_MODE_B:
 652                 rate_id_idx = PHYDM_B_20M;
 653                 break;
 654
 655         case PHYDM_WIRELESS_MODE_AC_5G:
 656         case PHYDM_WIRELESS_MODE_AC_ONLY: {
 657                 if (phydm_rf_type == PHYDM_RF_1T1R)
 658                         rate_id_idx = PHYDM_ARFR1_AC_1SS;
 659                 else if (phydm_rf_type == PHYDM_RF_2T2R)
 660                         rate_id_idx = PHYDM_ARFR0_AC_2SS;
 661                 else
 662                         rate_id_idx = PHYDM_ARFR4_AC_3SS;
 663         } break;
 664
 665         case PHYDM_WIRELESS_MODE_AC_24G: {
 666                 /*Becareful to set "Lowest rate" while using PHYDM_ARFR4_AC_3SS
 667                  *in 2.4G/5G
 668                  */
 669                 if (phydm_BW >= PHYDM_BW_80) {
 670                         if (phydm_rf_type == PHYDM_RF_1T1R)
 671                                 rate_id_idx = PHYDM_ARFR1_AC_1SS;
 672                         else if (phydm_rf_type == PHYDM_RF_2T2R)
 673                                 rate_id_idx = PHYDM_ARFR0_AC_2SS;
 674                         else
 675                                 rate_id_idx = PHYDM_ARFR4_AC_3SS;
 676                 } else {
 677                         if (phydm_rf_type == PHYDM_RF_1T1R)
 678                                 rate_id_idx = PHYDM_ARFR2_AC_2G_1SS;
 679                         else if (phydm_rf_type == PHYDM_RF_2T2R)
 680                                 rate_id_idx = PHYDM_ARFR3_AC_2G_2SS;
 681                         else
 682                                 rate_id_idx = PHYDM_ARFR4_AC_3SS;
 683                 }
 684         } break;
 685
 686         default:
 687                 rate_id_idx = 0;
 688                 break;
 689         }
 690
 691         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK, "RA rate ID = (( 0x%x ))\n",
 692                      rate_id_idx);
 693
 694         return rate_id_idx;
 695 }
 696
 697 void phydm_update_hal_ra_mask(void *dm_void, u32 wireless_mode, u8 rf_type,
 698                               u8 BW, u8 mimo_ps_enable, u8 disable_cck_rate,
 699                               u32 *ratr_bitmap_msb_in, u32 *ratr_bitmap_lsb_in,
 700                               u8 tx_rate_level)
 701 {
 702         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 703         u8 phydm_rf_type;
 704         u8 phydm_BW;
 705         u32 ratr_bitmap = *ratr_bitmap_lsb_in,
 706             ratr_bitmap_msb = *ratr_bitmap_msb_in;
 707
 708         wireless_mode = phydm_trans_platform_wireless_mode(dm, wireless_mode);
 709
 710         phydm_rf_type = phydm_trans_platform_rf_type(dm, rf_type);
 711         phydm_BW = phydm_trans_platform_bw(dm, BW);
 712
 713         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 714                      "Platform original RA Mask = (( 0x %x | %x ))\n",
 715                      ratr_bitmap_msb, ratr_bitmap);
 716
 717         switch (wireless_mode) {
 718         case PHYDM_WIRELESS_MODE_B: {
 719                 ratr_bitmap &= 0x0000000f;
 720         } break;
 721
 722         case PHYDM_WIRELESS_MODE_G: {
 723                 ratr_bitmap &= 0x00000ff5;
 724         } break;
 725
 726         case PHYDM_WIRELESS_MODE_A: {
 727                 ratr_bitmap &= 0x00000ff0;
 728         } break;
 729
 730         case PHYDM_WIRELESS_MODE_N_24G:
 731         case PHYDM_WIRELESS_MODE_N_5G: {
 732                 if (mimo_ps_enable)
 733                         phydm_rf_type = PHYDM_RF_1T1R;
 734
 735                 if (phydm_rf_type == PHYDM_RF_1T1R) {
 736                         if (phydm_BW == PHYDM_BW_40)
 737                                 ratr_bitmap &= 0x000ff015;
 738                         else
 739                                 ratr_bitmap &= 0x000ff005;
 740                 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
 741                            phydm_rf_type == PHYDM_RF_2T4R ||
 742                            phydm_rf_type == PHYDM_RF_2T3R) {
 743                         if (phydm_BW == PHYDM_BW_40)
 744                                 ratr_bitmap &= 0x0ffff015;
 745                         else
 746                                 ratr_bitmap &= 0x0ffff005;
 747                 } else { /*3T*/
 748
 749                         ratr_bitmap &= 0xfffff015;
 750                         ratr_bitmap_msb &= 0xf;
 751                 }
 752         } break;
 753
 754         case PHYDM_WIRELESS_MODE_AC_24G: {
 755                 if (phydm_rf_type == PHYDM_RF_1T1R) {
 756                         ratr_bitmap &= 0x003ff015;
 757                 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
 758                            phydm_rf_type == PHYDM_RF_2T4R ||
 759                            phydm_rf_type == PHYDM_RF_2T3R) {
 760                         ratr_bitmap &= 0xfffff015;
 761                 } else { /*3T*/
 762
 763                         ratr_bitmap &= 0xfffff010;
 764                         ratr_bitmap_msb &= 0x3ff;
 765                 }
 766
 767                 if (phydm_BW ==
 768                     PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
 769                         ratr_bitmap &= 0x7fdfffff;
 770                         ratr_bitmap_msb &= 0x1ff;
 771                 }
 772         } break;
 773
 774         case PHYDM_WIRELESS_MODE_AC_5G: {
 775                 if (phydm_rf_type == PHYDM_RF_1T1R) {
 776                         ratr_bitmap &= 0x003ff010;
 777                 } else if (phydm_rf_type == PHYDM_RF_2T2R ||
 778                            phydm_rf_type == PHYDM_RF_2T4R ||
 779                            phydm_rf_type == PHYDM_RF_2T3R) {
 780                         ratr_bitmap &= 0xfffff010;
 781                 } else { /*3T*/
 782
 783                         ratr_bitmap &= 0xfffff010;
 784                         ratr_bitmap_msb &= 0x3ff;
 785                 }
 786
 787                 if (phydm_BW ==
 788                     PHYDM_BW_20) { /* AC 20MHz doesn't support MCS9 */
 789                         ratr_bitmap &= 0x7fdfffff;
 790                         ratr_bitmap_msb &= 0x1ff;
 791                 }
 792         } break;
 793
 794         default:
 795                 break;
 796         }
 797
 798         if (wireless_mode != PHYDM_WIRELESS_MODE_B) {
 799                 if (tx_rate_level == 0)
 800                         ratr_bitmap &= 0xffffffff;
 801                 else if (tx_rate_level == 1)
 802                         ratr_bitmap &= 0xfffffff0;
 803                 else if (tx_rate_level == 2)
 804                         ratr_bitmap &= 0xffffefe0;
 805                 else if (tx_rate_level == 3)
 806                         ratr_bitmap &= 0xffffcfc0;
 807                 else if (tx_rate_level == 4)
 808                         ratr_bitmap &= 0xffff8f80;
 809                 else if (tx_rate_level >= 5)
 810                         ratr_bitmap &= 0xffff0f00;
 811         }
 812
 813         if (disable_cck_rate)
 814                 ratr_bitmap &= 0xfffffff0;
 815
 816         ODM_RT_TRACE(
 817                 dm, ODM_COMP_RA_MASK,
 818                 "wireless_mode= (( 0x%x )), rf_type = (( 0x%x )), BW = (( 0x%x )), MimoPs_en = (( %d )), tx_rate_level= (( 0x%x ))\n",
 819                 wireless_mode, phydm_rf_type, phydm_BW, mimo_ps_enable,
 820                 tx_rate_level);
 821
 822         *ratr_bitmap_lsb_in = ratr_bitmap;
 823         *ratr_bitmap_msb_in = ratr_bitmap_msb;
 824         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 825                      "Phydm modified RA Mask = (( 0x %x | %x ))\n",
 826                      *ratr_bitmap_msb_in, *ratr_bitmap_lsb_in);
 827 }
 828
 829 u8 phydm_RA_level_decision(void *dm_void, u32 rssi, u8 ratr_state)
 830 {
 831         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 832         u8 ra_rate_floor_table[RA_FLOOR_TABLE_SIZE] = {
 833                 20, 34, 38, 42,
 834                 46, 50, 100}; /*MCS0 ~ MCS4 , VHT1SS MCS0 ~ MCS4 , G 6M~24M*/
 835         u8 new_ratr_state = 0;
 836         u8 i;
 837
 838         ODM_RT_TRACE(
 839                 dm, ODM_COMP_RA_MASK,
 840                 "curr RA level = ((%d)), Rate_floor_table ori [ %d , %d, %d , %d, %d, %d]\n",
 841                 ratr_state, ra_rate_floor_table[0], ra_rate_floor_table[1],
 842                 ra_rate_floor_table[2], ra_rate_floor_table[3],
 843                 ra_rate_floor_table[4], ra_rate_floor_table[5]);
 844
 845         for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
 846                 if (i >= (ratr_state))
 847                         ra_rate_floor_table[i] += RA_FLOOR_UP_GAP;
 848         }
 849
 850         ODM_RT_TRACE(
 851                 dm, ODM_COMP_RA_MASK,
 852                 "RSSI = ((%d)), Rate_floor_table_mod [ %d , %d, %d , %d, %d, %d]\n",
 853                 rssi, ra_rate_floor_table[0], ra_rate_floor_table[1],
 854                 ra_rate_floor_table[2], ra_rate_floor_table[3],
 855                 ra_rate_floor_table[4], ra_rate_floor_table[5]);
 856
 857         for (i = 0; i < RA_FLOOR_TABLE_SIZE; i++) {
 858                 if (rssi < ra_rate_floor_table[i]) {
 859                         new_ratr_state = i;
 860                         break;
 861                 }
 862         }
 863
 864         return new_ratr_state;
 865 }
 866
 867 void odm_refresh_rate_adaptive_mask_mp(void *dm_void) {}
 868
 869 void odm_refresh_rate_adaptive_mask_ce(void *dm_void)
 870 {
 871         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 872         struct ra_table *ra_tab = &dm->dm_ra_table;
 873         void *adapter = dm->adapter;
 874         u32 i;
 875         struct rtl_sta_info *entry;
 876         u8 ratr_state_new;
 877
 878         if (!dm->is_use_ra_mask) {
 879                 ODM_RT_TRACE(
 880                         dm, ODM_COMP_RA_MASK,
 881                         "<---- %s(): driver does not control rate adaptive mask\n",
 882                         __func__);
 883                 return;
 884         }
 885
 886         for (i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++) {
 887                 entry = dm->odm_sta_info[i];
 888
 889                 if (!IS_STA_VALID(entry))
 890                         continue;
 891
 892                 if (is_multicast_ether_addr(entry->mac_addr))
 893                         continue;
 894                 else if (is_broadcast_ether_addr(entry->mac_addr))
 895                         continue;
 896
 897                 ratr_state_new = phydm_RA_level_decision(
 898                         dm, entry->rssi_stat.undecorated_smoothed_pwdb,
 899                         entry->rssi_level);
 900
 901                 if ((entry->rssi_level != ratr_state_new) ||
 902                     (ra_tab->force_update_ra_mask_count >=
 903                      FORCED_UPDATE_RAMASK_PERIOD)) {
 904                         ra_tab->force_update_ra_mask_count = 0;
 905                         ODM_RT_TRACE(
 906                                 dm, ODM_COMP_RA_MASK,
 907                                 "Update Tx RA Level: ((%x)) -> ((%x)),  RSSI = ((%d))\n",
 908                                 entry->rssi_level, ratr_state_new,
 909                                 entry->rssi_stat.undecorated_smoothed_pwdb);
 910
 911                         entry->rssi_level = ratr_state_new;
 912                         rtl_hal_update_ra_mask(adapter, entry,
 913                                                entry->rssi_level);
 914                 } else {
 915                         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
 916                                      "Stay in RA level  = (( %d ))\n\n",
 917                                      ratr_state_new);
 918                         /**/
 919                 }
 920         }
 921 }
 922
 923 void odm_refresh_rate_adaptive_mask_apadsl(void *dm_void) {}
 924
 925 void odm_refresh_basic_rate_mask(void *dm_void) {}
 926
 927 u8 phydm_rate_order_compute(void *dm_void, u8 rate_idx)
 928 {
 929         u8 rate_order = 0;
 930
 931         if (rate_idx >= ODM_RATEVHTSS4MCS0) {
 932                 rate_idx -= ODM_RATEVHTSS4MCS0;
 933                 /**/
 934         } else if (rate_idx >= ODM_RATEVHTSS3MCS0) {
 935                 rate_idx -= ODM_RATEVHTSS3MCS0;
 936                 /**/
 937         } else if (rate_idx >= ODM_RATEVHTSS2MCS0) {
 938                 rate_idx -= ODM_RATEVHTSS2MCS0;
 939                 /**/
 940         } else if (rate_idx >= ODM_RATEVHTSS1MCS0) {
 941                 rate_idx -= ODM_RATEVHTSS1MCS0;
 942                 /**/
 943         } else if (rate_idx >= ODM_RATEMCS24) {
 944                 rate_idx -= ODM_RATEMCS24;
 945                 /**/
 946         } else if (rate_idx >= ODM_RATEMCS16) {
 947                 rate_idx -= ODM_RATEMCS16;
 948                 /**/
 949         } else if (rate_idx >= ODM_RATEMCS8) {
 950                 rate_idx -= ODM_RATEMCS8;
 951                 /**/
 952         }
 953         rate_order = rate_idx;
 954
 955         return rate_order;
 956 }
 957
 958 static void phydm_ra_common_info_update(void *dm_void)
 959 {
 960         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 961         struct ra_table *ra_tab = &dm->dm_ra_table;
 962         u16 macid;
 963         u8 rate_order_tmp;
 964         u8 cnt = 0;
 965
 966         ra_tab->highest_client_tx_order = 0;
 967         ra_tab->power_tracking_flag = 1;
 968
 969         if (dm->number_linked_client != 0) {
 970                 for (macid = 0; macid < ODM_ASSOCIATE_ENTRY_NUM; macid++) {
 971                         rate_order_tmp = phydm_rate_order_compute(
 972                                 dm, ((ra_tab->link_tx_rate[macid]) & 0x7f));
 973
 974                         if (rate_order_tmp >=
 975                             (ra_tab->highest_client_tx_order)) {
 976                                 ra_tab->highest_client_tx_order =
 977                                         rate_order_tmp;
 978                                 ra_tab->highest_client_tx_rate_order = macid;
 979                         }
 980
 981                         cnt++;
 982
 983                         if (cnt == dm->number_linked_client)
 984                                 break;
 985                 }
 986                 ODM_RT_TRACE(
 987                         dm, ODM_COMP_RATE_ADAPTIVE,
 988                         "MACID[%d], Highest Tx order Update for power tracking: %d\n",
 989                         (ra_tab->highest_client_tx_rate_order),
 990                         (ra_tab->highest_client_tx_order));
 991         }
 992 }
 993
 994 void phydm_ra_info_watchdog(void *dm_void)
 995 {
 996         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
 997
 998         phydm_ra_common_info_update(dm);
 999         phydm_ra_dynamic_retry_limit(dm);
1000         phydm_ra_dynamic_retry_count(dm);
1001         odm_refresh_rate_adaptive_mask(dm);
1002         odm_refresh_basic_rate_mask(dm);
1003 }
1004
1005 void phydm_ra_info_init(void *dm_void)
1006 {
1007         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1008         struct ra_table *ra_tab = &dm->dm_ra_table;
1009
1010         ra_tab->highest_client_tx_rate_order = 0;
1011         ra_tab->highest_client_tx_order = 0;
1012         ra_tab->RA_threshold_offset = 0;
1013         ra_tab->RA_offset_direction = 0;
1014 }
1015
1016 u8 odm_find_rts_rate(void *dm_void, u8 tx_rate, bool is_erp_protect)
1017 {
1018         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1019         u8 rts_ini_rate = ODM_RATE6M;
1020
1021         if (is_erp_protect) { /* use CCK rate as RTS*/
1022                 rts_ini_rate = ODM_RATE1M;
1023         } else {
1024                 switch (tx_rate) {
1025                 case ODM_RATEVHTSS3MCS9:
1026                 case ODM_RATEVHTSS3MCS8:
1027                 case ODM_RATEVHTSS3MCS7:
1028                 case ODM_RATEVHTSS3MCS6:
1029                 case ODM_RATEVHTSS3MCS5:
1030                 case ODM_RATEVHTSS3MCS4:
1031                 case ODM_RATEVHTSS3MCS3:
1032                 case ODM_RATEVHTSS2MCS9:
1033                 case ODM_RATEVHTSS2MCS8:
1034                 case ODM_RATEVHTSS2MCS7:
1035                 case ODM_RATEVHTSS2MCS6:
1036                 case ODM_RATEVHTSS2MCS5:
1037                 case ODM_RATEVHTSS2MCS4:
1038                 case ODM_RATEVHTSS2MCS3:
1039                 case ODM_RATEVHTSS1MCS9:
1040                 case ODM_RATEVHTSS1MCS8:
1041                 case ODM_RATEVHTSS1MCS7:
1042                 case ODM_RATEVHTSS1MCS6:
1043                 case ODM_RATEVHTSS1MCS5:
1044                 case ODM_RATEVHTSS1MCS4:
1045                 case ODM_RATEVHTSS1MCS3:
1046                 case ODM_RATEMCS15:
1047                 case ODM_RATEMCS14:
1048                 case ODM_RATEMCS13:
1049                 case ODM_RATEMCS12:
1050                 case ODM_RATEMCS11:
1051                 case ODM_RATEMCS7:
1052                 case ODM_RATEMCS6:
1053                 case ODM_RATEMCS5:
1054                 case ODM_RATEMCS4:
1055                 case ODM_RATEMCS3:
1056                 case ODM_RATE54M:
1057                 case ODM_RATE48M:
1058                 case ODM_RATE36M:
1059                 case ODM_RATE24M:
1060                         rts_ini_rate = ODM_RATE24M;
1061                         break;
1062                 case ODM_RATEVHTSS3MCS2:
1063                 case ODM_RATEVHTSS3MCS1:
1064                 case ODM_RATEVHTSS2MCS2:
1065                 case ODM_RATEVHTSS2MCS1:
1066                 case ODM_RATEVHTSS1MCS2:
1067                 case ODM_RATEVHTSS1MCS1:
1068                 case ODM_RATEMCS10:
1069                 case ODM_RATEMCS9:
1070                 case ODM_RATEMCS2:
1071                 case ODM_RATEMCS1:
1072                 case ODM_RATE18M:
1073                 case ODM_RATE12M:
1074                         rts_ini_rate = ODM_RATE12M;
1075                         break;
1076                 case ODM_RATEVHTSS3MCS0:
1077                 case ODM_RATEVHTSS2MCS0:
1078                 case ODM_RATEVHTSS1MCS0:
1079                 case ODM_RATEMCS8:
1080                 case ODM_RATEMCS0:
1081                 case ODM_RATE9M:
1082                 case ODM_RATE6M:
1083                         rts_ini_rate = ODM_RATE6M;
1084                         break;
1085                 case ODM_RATE11M:
1086                 case ODM_RATE5_5M:
1087                 case ODM_RATE2M:
1088                 case ODM_RATE1M:
1089                         rts_ini_rate = ODM_RATE1M;
1090                         break;
1091                 default:
1092                         rts_ini_rate = ODM_RATE6M;
1093                         break;
1094                 }
1095         }
1096
1097         if (*dm->band_type == 1) {
1098                 if (rts_ini_rate < ODM_RATE6M)
1099                         rts_ini_rate = ODM_RATE6M;
1100         }
1101         return rts_ini_rate;
1102 }
1103
1104 static void odm_set_ra_dm_arfb_by_noisy(struct phy_dm_struct *dm) {}
1105
1106 void odm_update_noisy_state(void *dm_void, bool is_noisy_state_from_c2h)
1107 {
1108         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1109
1110         /* JJ ADD 20161014 */
1111         if (dm->support_ic_type == ODM_RTL8821 ||
1112             dm->support_ic_type == ODM_RTL8812 ||
1113             dm->support_ic_type == ODM_RTL8723B ||
1114             dm->support_ic_type == ODM_RTL8192E ||
1115             dm->support_ic_type == ODM_RTL8188E ||
1116             dm->support_ic_type == ODM_RTL8723D ||
1117             dm->support_ic_type == ODM_RTL8710B)
1118                 dm->is_noisy_state = is_noisy_state_from_c2h;
1119         odm_set_ra_dm_arfb_by_noisy(dm);
1120 };
1121
1122 void phydm_update_pwr_track(void *dm_void, u8 rate)
1123 {
1124         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1125
1126         ODM_RT_TRACE(dm, ODM_COMP_TX_PWR_TRACK, "Pwr Track Get rate=0x%x\n",
1127                      rate);
1128
1129         dm->tx_rate = rate;
1130 }
1131
1132 /* RA_MASK_PHYDMLIZE, will delete it later*/
1133
1134 bool odm_ra_state_check(void *dm_void, s32 rssi, bool is_force_update,
1135                         u8 *ra_tr_state)
1136 {
1137         struct phy_dm_struct *dm = (struct phy_dm_struct *)dm_void;
1138         struct odm_rate_adaptive *ra = &dm->rate_adaptive;
1139         const u8 go_up_gap = 5;
1140         u8 high_rssi_thresh_for_ra = ra->high_rssi_thresh;
1141         u8 low_rssi_thresh_for_ra = ra->low_rssi_thresh;
1142         u8 ratr_state;
1143
1144         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1145                      "RSSI= (( %d )), Current_RSSI_level = (( %d ))\n", rssi,
1146                      *ra_tr_state);
1147         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1148                      "[Ori RA RSSI Thresh]  High= (( %d )), Low = (( %d ))\n",
1149                      high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
1150         /* threshold Adjustment:
1151          * when RSSI state trends to go up one or two levels, make sure RSSI is
1152          * high enough. Here go_up_gap is added to solve the boundary's level
1153          * alternation issue.
1154          */
1155
1156         switch (*ra_tr_state) {
1157         case DM_RATR_STA_INIT:
1158         case DM_RATR_STA_HIGH:
1159                 break;
1160
1161         case DM_RATR_STA_MIDDLE:
1162                 high_rssi_thresh_for_ra += go_up_gap;
1163                 break;
1164
1165         case DM_RATR_STA_LOW:
1166                 high_rssi_thresh_for_ra += go_up_gap;
1167                 low_rssi_thresh_for_ra += go_up_gap;
1168                 break;
1169
1170         default:
1171                 WARN_ONCE(true, "wrong rssi level setting %d !", *ra_tr_state);
1172                 break;
1173         }
1174
1175         /* Decide ratr_state by RSSI.*/
1176         if (rssi > high_rssi_thresh_for_ra)
1177                 ratr_state = DM_RATR_STA_HIGH;
1178         else if (rssi > low_rssi_thresh_for_ra)
1179                 ratr_state = DM_RATR_STA_MIDDLE;
1180
1181         else
1182                 ratr_state = DM_RATR_STA_LOW;
1183         ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1184                      "[Mod RA RSSI Thresh]  High= (( %d )), Low = (( %d ))\n",
1185                      high_rssi_thresh_for_ra, low_rssi_thresh_for_ra);
1186
1187         if (*ra_tr_state != ratr_state || is_force_update) {
1188                 ODM_RT_TRACE(dm, ODM_COMP_RA_MASK,
1189                              "[RSSI Level Update] %d->%d\n", *ra_tr_state,
1190                              ratr_state);
1191                 *ra_tr_state = ratr_state;
1192                 return true;
1193         }
1194
1195         return false;
1196 }