drivers/staging/rtlwifi/phydm/phydm_types.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /******************************************************************************
   3  *
   4  * Copyright(c) 2007 - 2016  Realtek Corporation.
   5  *
   6  * Contact Information:
   7  * wlanfae <wlanfae@realtek.com>
   8  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
   9  * Hsinchu 300, Taiwan.
  10  *
  11  * Larry Finger <Larry.Finger@lwfinger.net>
  12  *
  13  *****************************************************************************/
  14 #ifndef __ODM_TYPES_H__
  15 #define __ODM_TYPES_H__
  16
  17 /*Define Different SW team support*/
  18 #define ODM_AP 0x01 /*BIT0*/
  19 #define ODM_CE 0x04 /*BIT2*/
  20 #define ODM_WIN 0x08 /*BIT3*/
  21 #define ODM_ADSL 0x10 /*BIT4*/
  22 #define ODM_IOT 0x20 /*BIT5*/
  23
  24 /*Deifne HW endian support*/
  25 #define ODM_ENDIAN_BIG 0
  26 #define ODM_ENDIAN_LITTLE 1
  27
  28 #define GET_PDM_ODM(__padapter)                                                \
  29         ((struct phy_dm_struct *)(&(GET_HAL_DATA(__padapter))->odmpriv))
  30
  31 enum hal_status {
  32         HAL_STATUS_SUCCESS,
  33         HAL_STATUS_FAILURE,
  34 };
  35
  36 /*
  37  * Declare for ODM spin lock definition temporarily fro compile pass.
  38  */
  39 enum rt_spinlock_type {
  40         RT_TX_SPINLOCK = 1,
  41         RT_RX_SPINLOCK = 2,
  42         RT_RM_SPINLOCK = 3,
  43         RT_CAM_SPINLOCK = 4,
  44         RT_SCAN_SPINLOCK = 5,
  45         RT_LOG_SPINLOCK = 7,
  46         RT_BW_SPINLOCK = 8,
  47         RT_CHNLOP_SPINLOCK = 9,
  48         RT_RF_OPERATE_SPINLOCK = 10,
  49         RT_INITIAL_SPINLOCK = 11,
  50         RT_RF_STATE_SPINLOCK =
  51                 12, /* For RF state. Added by Bruce, 2007-10-30. */
  52         /* Shall we define Ndis 6.2 SpinLock Here ? */
  53         RT_PORT_SPINLOCK = 16,
  54         RT_VNIC_SPINLOCK = 17,
  55         RT_HVL_SPINLOCK = 18,
  56         RT_H2C_SPINLOCK = 20, /* For H2C cmd. Added by tynli. 2009.11.09. */
  57
  58         rt_bt_data_spinlock = 25,
  59
  60         RT_WAPI_OPTION_SPINLOCK = 26,
  61         RT_WAPI_RX_SPINLOCK = 27,
  62
  63         /* add for 92D CCK control issue */
  64         RT_CCK_PAGEA_SPINLOCK = 28,
  65         RT_BUFFER_SPINLOCK = 29,
  66         RT_CHANNEL_AND_BANDWIDTH_SPINLOCK = 30,
  67         RT_GEN_TEMP_BUF_SPINLOCK = 31,
  68         RT_AWB_SPINLOCK = 32,
  69         RT_FW_PS_SPINLOCK = 33,
  70         RT_HW_TIMER_SPIN_LOCK = 34,
  71         RT_MPT_WI_SPINLOCK = 35,
  72         RT_P2P_SPIN_LOCK = 36, /* Protect P2P context */
  73         RT_DBG_SPIN_LOCK = 37,
  74         RT_IQK_SPINLOCK = 38,
  75         RT_PENDED_OID_SPINLOCK = 39,
  76         RT_CHNLLIST_SPINLOCK = 40,
  77         RT_INDIC_SPINLOCK = 41, /* protect indication */
  78         RT_RFD_SPINLOCK = 42,
  79         RT_SYNC_IO_CNT_SPINLOCK = 43,
  80         RT_LAST_SPINLOCK,
  81 };
  82
  83 #include <asm/byteorder.h>
  84
  85 #if defined(__LITTLE_ENDIAN)
  86 #define ODM_ENDIAN_TYPE ODM_ENDIAN_LITTLE
  87 #elif defined(__BIG_ENDIAN)
  88 #define ODM_ENDIAN_TYPE ODM_ENDIAN_BIG
  89 #else
  90 #error
  91 #endif
  92
  93 #define COND_ELSE 2
  94 #define COND_ENDIF 3
  95
  96 #define MASKBYTE0 0xff
  97 #define MASKBYTE1 0xff00
  98 #define MASKBYTE2 0xff0000
  99 #define MASKBYTE3 0xff000000
 100 #define MASKHWORD 0xffff0000
 101 #define MASKLWORD 0x0000ffff
 102 #define MASKDWORD 0xffffffff
 103 #define MASK7BITS 0x7f
 104 #define MASK12BITS 0xfff
 105 #define MASKH4BITS 0xf0000000
 106 #define MASK20BITS 0xfffff
 107 #define MASKOFDM_D 0xffc00000
 108 #define MASKCCK 0x3f3f3f3f
 109 #define RFREGOFFSETMASK 0xfffff
 110 #define MASKH3BYTES 0xffffff00
 111 #define MASKL3BYTES 0x00ffffff
 112 #define MASKBYTE2HIGHNIBBLE 0x00f00000
 113 #define MASKBYTE3LOWNIBBLE 0x0f000000
 114 #define MASKL3BYTES 0x00ffffff
 115 #define RFREGOFFSETMASK 0xfffff
 116
 117 #include "phydm_features.h"
 118
 119 #endif /* __ODM_TYPES_H__ */