drivers/staging/rtlwifi/phydm/rtl8822b/phydm_regconfig8822b.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2016  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #include "../mp_precomp.h"
  27 #include "../phydm_precomp.h"
  28
  29 void odm_config_rf_reg_8822b(struct phy_dm_struct *dm, u32 addr, u32 data,
  30                              enum odm_rf_radio_path RF_PATH, u32 reg_addr)
  31 {
  32         if (addr == 0xffe) {
  33                 ODM_sleep_ms(50);
  34         } else if (addr == 0xfe) {
  35                 ODM_delay_us(100);
  36         } else {
  37                 odm_set_rf_reg(dm, RF_PATH, reg_addr, RFREGOFFSETMASK, data);
  38
  39                 /* Add 1us delay between BB/RF register setting. */
  40                 ODM_delay_us(1);
  41         }
  42 }
  43
  44 void odm_config_rf_radio_a_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
  45 {
  46         u32 content = 0x1000; /* RF_Content: radioa_txt */
  47         u32 maskfor_phy_set = (u32)(content & 0xE000);
  48
  49         odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_A,
  50                                 addr | maskfor_phy_set);
  51
  52         ODM_RT_TRACE(
  53                 dm, ODM_COMP_INIT,
  54                 "===> odm_config_rf_with_header_file: [RadioA] %08X %08X\n",
  55                 addr, data);
  56 }
  57
  58 void odm_config_rf_radio_b_8822b(struct phy_dm_struct *dm, u32 addr, u32 data)
  59 {
  60         u32 content = 0x1001; /* RF_Content: radiob_txt */
  61         u32 maskfor_phy_set = (u32)(content & 0xE000);
  62
  63         odm_config_rf_reg_8822b(dm, addr, data, ODM_RF_PATH_B,
  64                                 addr | maskfor_phy_set);
  65
  66         ODM_RT_TRACE(
  67                 dm, ODM_COMP_INIT,
  68                 "===> odm_config_rf_with_header_file: [RadioB] %08X %08X\n",
  69                 addr, data);
  70 }
  71
  72 void odm_config_mac_8822b(struct phy_dm_struct *dm, u32 addr, u8 data)
  73 {
  74         odm_write_1byte(dm, addr, data);
  75         ODM_RT_TRACE(
  76                 dm, ODM_COMP_INIT,
  77                 "===> odm_config_mac_with_header_file: [MAC_REG] %08X %08X\n",
  78                 addr, data);
  79 }
  80
  81 void odm_update_agc_big_jump_lmt_8822b(struct phy_dm_struct *dm, u32 addr,
  82                                        u32 data)
  83 {
  84         struct dig_thres *dig_tab = &dm->dm_dig_table;
  85         u8 rf_gain_idx = (u8)((data & 0xFF000000) >> 24);
  86         u8 bb_gain_idx = (u8)((data & 0x00ff0000) >> 16);
  87         u8 agc_table_idx = (u8)((data & 0x00000f00) >> 8);
  88         static bool is_limit;
  89
  90         if (addr != 0x81c)
  91                 return;
  92
  93         if (bb_gain_idx > 0x3c) {
  94                 if ((rf_gain_idx == dig_tab->rf_gain_idx) && !is_limit) {
  95                         is_limit = true;
  96                         dig_tab->big_jump_lmt[agc_table_idx] = bb_gain_idx - 2;
  97                         ODM_RT_TRACE(
  98                                 dm, ODM_COMP_DIG,
  99                                 "===> [AGC_TAB] big_jump_lmt [%d] = 0x%x\n",
 100                                 agc_table_idx,
 101                                 dig_tab->big_jump_lmt[agc_table_idx]);
 102                 }
 103         } else {
 104                 is_limit = false;
 105         }
 106
 107         dig_tab->rf_gain_idx = rf_gain_idx;
 108 }
 109
 110 void odm_config_bb_agc_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
 111                              u32 data)
 112 {
 113         odm_update_agc_big_jump_lmt_8822b(dm, addr, data);
 114
 115         odm_set_bb_reg(dm, addr, bitmask, data);
 116
 117         /* Add 1us delay between BB/RF register setting. */
 118         ODM_delay_us(1);
 119
 120         ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [AGC_TAB] %08X %08X\n",
 121                      __func__, addr, data);
 122 }
 123
 124 void odm_config_bb_phy_reg_pg_8822b(struct phy_dm_struct *dm, u32 band,
 125                                     u32 rf_path, u32 tx_num, u32 addr,
 126                                     u32 bitmask, u32 data)
 127 {
 128         if (addr == 0xfe || addr == 0xffe) {
 129                 ODM_sleep_ms(50);
 130         } else {
 131                 phy_store_tx_power_by_rate(dm->adapter, band, rf_path, tx_num,
 132                                            addr, bitmask, data);
 133         }
 134         ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X %08X\n",
 135                      __func__, addr, bitmask, data);
 136 }
 137
 138 void odm_config_bb_phy_8822b(struct phy_dm_struct *dm, u32 addr, u32 bitmask,
 139                              u32 data)
 140 {
 141         if (addr == 0xfe)
 142                 ODM_sleep_ms(50);
 143         else if (addr == 0xfd)
 144                 ODM_delay_ms(5);
 145         else if (addr == 0xfc)
 146                 ODM_delay_ms(1);
 147         else if (addr == 0xfb)
 148                 ODM_delay_us(50);
 149         else if (addr == 0xfa)
 150                 ODM_delay_us(5);
 151         else if (addr == 0xf9)
 152                 ODM_delay_us(1);
 153         else
 154                 odm_set_bb_reg(dm, addr, bitmask, data);
 155
 156         /* Add 1us delay between BB/RF register setting. */
 157         ODM_delay_us(1);
 158         ODM_RT_TRACE(dm, ODM_COMP_INIT, "===> %s: [PHY_REG] %08X %08X\n",
 159                      __func__, addr, data);
 160 }
 161
 162 void odm_config_bb_txpwr_lmt_8822b(struct phy_dm_struct *dm, u8 *regulation,
 163                                    u8 *band, u8 *bandwidth, u8 *rate_section,
 164                                    u8 *rf_path, u8 *channel, u8 *power_limit)
 165 {
 166         phy_set_tx_power_limit(dm, regulation, band, bandwidth, rate_section,
 167                                rf_path, channel, power_limit);
 168 }