drivers/staging/rts5208/xd.c

   1 /* Driver for Realtek PCI-Express card reader
   2  *
   3  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2, or (at your option) any
   8  * later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along
  16  * with this program; if not, see <http://www.gnu.org/licenses/>.
  17  *
  18  * Author:
  19  *   Wei WANG (wei_wang@realsil.com.cn)
  20  *   Micky Ching (micky_ching@realsil.com.cn)
  21  */
  22
  23 #include <linux/blkdev.h>
  24 #include <linux/kthread.h>
  25 #include <linux/sched.h>
  26 #include <linux/vmalloc.h>
  27
  28 #include "rtsx.h"
  29 #include "rtsx_transport.h"
  30 #include "rtsx_scsi.h"
  31 #include "rtsx_card.h"
  32 #include "xd.h"
  33
  34 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no);
  35 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk, u16 logoff,
  36                         u8 start_page, u8 end_page);
  37
  38 static inline void xd_set_err_code(struct rtsx_chip *chip, u8 err_code)
  39 {
  40         struct xd_info *xd_card = &chip->xd_card;
  41
  42         xd_card->err_code = err_code;
  43 }
  44
  45 static inline int xd_check_err_code(struct rtsx_chip *chip, u8 err_code)
  46 {
  47         struct xd_info *xd_card = &chip->xd_card;
  48
  49         return (xd_card->err_code == err_code);
  50 }
  51
  52 static int xd_set_init_para(struct rtsx_chip *chip)
  53 {
  54         struct xd_info *xd_card = &chip->xd_card;
  55         int retval;
  56
  57         if (chip->asic_code)
  58                 xd_card->xd_clock = 47;
  59         else
  60                 xd_card->xd_clock = CLK_50;
  61
  62         retval = switch_clock(chip, xd_card->xd_clock);
  63         if (retval != STATUS_SUCCESS) {
  64                 rtsx_trace(chip);
  65                 return STATUS_FAIL;
  66         }
  67
  68         return STATUS_SUCCESS;
  69 }
  70
  71 static int xd_switch_clock(struct rtsx_chip *chip)
  72 {
  73         struct xd_info *xd_card = &chip->xd_card;
  74         int retval;
  75
  76         retval = select_card(chip, XD_CARD);
  77         if (retval != STATUS_SUCCESS) {
  78                 rtsx_trace(chip);
  79                 return STATUS_FAIL;
  80         }
  81
  82         retval = switch_clock(chip, xd_card->xd_clock);
  83         if (retval != STATUS_SUCCESS) {
  84                 rtsx_trace(chip);
  85                 return STATUS_FAIL;
  86         }
  87
  88         return STATUS_SUCCESS;
  89 }
  90
  91 static int xd_read_id(struct rtsx_chip *chip, u8 id_cmd, u8 *id_buf, u8 buf_len)
  92 {
  93         int retval, i;
  94         u8 *ptr;
  95
  96         rtsx_init_cmd(chip);
  97
  98         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
  99         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 100                      XD_TRANSFER_START | XD_READ_ID);
 101         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 102                      XD_TRANSFER_END);
 103
 104         for (i = 0; i < 4; i++)
 105                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_ADDRESS1 + i), 0, 0);
 106
 107         retval = rtsx_send_cmd(chip, XD_CARD, 20);
 108         if (retval < 0) {
 109                 rtsx_trace(chip);
 110                 return STATUS_FAIL;
 111         }
 112
 113         ptr = rtsx_get_cmd_data(chip) + 1;
 114         if (id_buf && buf_len) {
 115                 if (buf_len > 4)
 116                         buf_len = 4;
 117                 memcpy(id_buf, ptr, buf_len);
 118         }
 119
 120         return STATUS_SUCCESS;
 121 }
 122
 123 static void xd_assign_phy_addr(struct rtsx_chip *chip, u32 addr, u8 mode)
 124 {
 125         struct xd_info *xd_card = &chip->xd_card;
 126
 127         switch (mode) {
 128         case XD_RW_ADDR:
 129                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
 130                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF, (u8)addr);
 131                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
 132                              0xFF, (u8)(addr >> 8));
 133                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3,
 134                              0xFF, (u8)(addr >> 16));
 135                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 136                              xd_card->addr_cycle |
 137                              XD_CALC_ECC |
 138                              XD_BA_NO_TRANSFORM);
 139                 break;
 140
 141         case XD_ERASE_ADDR:
 142                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, (u8)addr);
 143                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1,
 144                              0xFF, (u8)(addr >> 8));
 145                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2,
 146                              0xFF, (u8)(addr >> 16));
 147                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
 148                              (xd_card->addr_cycle - 1) | XD_CALC_ECC |
 149                         XD_BA_NO_TRANSFORM);
 150                 break;
 151
 152         default:
 153                 break;
 154         }
 155 }
 156
 157 static int xd_read_redundant(struct rtsx_chip *chip, u32 page_addr,
 158                              u8 *buf, int buf_len)
 159 {
 160         int retval, i;
 161
 162         rtsx_init_cmd(chip);
 163
 164         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 165
 166         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
 167                      0xFF, XD_TRANSFER_START | XD_READ_REDUNDANT);
 168         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 169                      XD_TRANSFER_END, XD_TRANSFER_END);
 170
 171         for (i = 0; i < 6; i++)
 172                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_PAGE_STATUS + i),
 173                              0, 0);
 174         for (i = 0; i < 4; i++)
 175                 rtsx_add_cmd(chip, READ_REG_CMD, (u16)(XD_RESERVED0 + i),
 176                              0, 0);
 177         rtsx_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
 178
 179         retval = rtsx_send_cmd(chip, XD_CARD, 500);
 180         if (retval < 0) {
 181                 rtsx_trace(chip);
 182                 return STATUS_FAIL;
 183         }
 184
 185         if (buf && buf_len) {
 186                 u8 *ptr = rtsx_get_cmd_data(chip) + 1;
 187
 188                 if (buf_len > 11)
 189                         buf_len = 11;
 190                 memcpy(buf, ptr, buf_len);
 191         }
 192
 193         return STATUS_SUCCESS;
 194 }
 195
 196 static int xd_read_data_from_ppb(struct rtsx_chip *chip, int offset,
 197                                  u8 *buf, int buf_len)
 198 {
 199         int retval, i;
 200
 201         if (!buf || (buf_len < 0)) {
 202                 rtsx_trace(chip);
 203                 return STATUS_FAIL;
 204         }
 205
 206         rtsx_init_cmd(chip);
 207
 208         for (i = 0; i < buf_len; i++)
 209                 rtsx_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i,
 210                              0, 0);
 211
 212         retval = rtsx_send_cmd(chip, 0, 250);
 213         if (retval < 0) {
 214                 rtsx_clear_xd_error(chip);
 215                 rtsx_trace(chip);
 216                 return STATUS_FAIL;
 217         }
 218
 219         memcpy(buf, rtsx_get_cmd_data(chip), buf_len);
 220
 221         return STATUS_SUCCESS;
 222 }
 223
 224 static int xd_read_cis(struct rtsx_chip *chip, u32 page_addr, u8 *buf,
 225                        int buf_len)
 226 {
 227         int retval;
 228         u8 reg;
 229
 230         if (!buf || (buf_len < 10)) {
 231                 rtsx_trace(chip);
 232                 return STATUS_FAIL;
 233         }
 234
 235         rtsx_init_cmd(chip);
 236
 237         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
 238
 239         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE,
 240                      0x01, PINGPONG_BUFFER);
 241         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
 242         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
 243                      XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
 244
 245         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 246                      XD_TRANSFER_START | XD_READ_PAGES);
 247         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
 248                      XD_TRANSFER_END);
 249
 250         retval = rtsx_send_cmd(chip, XD_CARD, 250);
 251         if (retval == -ETIMEDOUT) {
 252                 rtsx_clear_xd_error(chip);
 253                 rtsx_trace(chip);
 254                 return STATUS_FAIL;
 255         }
 256
 257         retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg);
 258         if (retval) {
 259                 rtsx_trace(chip);
 260                 return retval;
 261         }
 262         if (reg != XD_GPG) {
 263                 rtsx_clear_xd_error(chip);
 264                 rtsx_trace(chip);
 265                 return STATUS_FAIL;
 266         }
 267
 268         retval = rtsx_read_register(chip, XD_CTL, &reg);
 269         if (retval) {
 270                 rtsx_trace(chip);
 271                 return retval;
 272         }
 273         if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
 274                 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
 275                 if (retval != STATUS_SUCCESS) {
 276                         rtsx_trace(chip);
 277                         return STATUS_FAIL;
 278                 }
 279                 if (reg & XD_ECC1_ERROR) {
 280                         u8 ecc_bit, ecc_byte;
 281
 282                         retval = rtsx_read_register(chip, XD_ECC_BIT1,
 283                                                     &ecc_bit);
 284                         if (retval) {
 285                                 rtsx_trace(chip);
 286                                 return retval;
 287                         }
 288                         retval = rtsx_read_register(chip, XD_ECC_BYTE1,
 289                                                     &ecc_byte);
 290                         if (retval) {
 291                                 rtsx_trace(chip);
 292                                 return retval;
 293                         }
 294
 295                         dev_dbg(rtsx_dev(chip), "ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
 296                                 ecc_bit, ecc_byte);
 297                         if (ecc_byte < buf_len) {
 298                                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
 299                                         buf[ecc_byte]);
 300                                 buf[ecc_byte] ^= (1 << ecc_bit);
 301                                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
 302                                         buf[ecc_byte]);
 303                         }
 304                 }
 305         } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
 306                 rtsx_clear_xd_error(chip);
 307
 308                 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
 309                 if (retval != STATUS_SUCCESS) {
 310                         rtsx_trace(chip);
 311                         return STATUS_FAIL;
 312                 }
 313                 if (reg & XD_ECC2_ERROR) {
 314                         u8 ecc_bit, ecc_byte;
 315
 316                         retval = rtsx_read_register(chip, XD_ECC_BIT2,
 317                                                     &ecc_bit);
 318                         if (retval) {
 319                                 rtsx_trace(chip);
 320                                 return retval;
 321                         }
 322                         retval = rtsx_read_register(chip, XD_ECC_BYTE2,
 323                                                     &ecc_byte);
 324                         if (retval) {
 325                                 rtsx_trace(chip);
 326                                 return retval;
 327                         }
 328
 329                         dev_dbg(rtsx_dev(chip), "ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
 330                                 ecc_bit, ecc_byte);
 331                         if (ecc_byte < buf_len) {
 332                                 dev_dbg(rtsx_dev(chip), "Before correct: 0x%x\n",
 333                                         buf[ecc_byte]);
 334                                 buf[ecc_byte] ^= (1 << ecc_bit);
 335                                 dev_dbg(rtsx_dev(chip), "After correct: 0x%x\n",
 336                                         buf[ecc_byte]);
 337                         }
 338                 }
 339         } else {
 340                 rtsx_clear_xd_error(chip);
 341                 rtsx_trace(chip);
 342                 return STATUS_FAIL;
 343         }
 344
 345         return STATUS_SUCCESS;
 346 }
 347
 348 static void xd_fill_pull_ctl_disable(struct rtsx_chip *chip)
 349 {
 350         if (CHECK_PID(chip, 0x5208)) {
 351                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 352                              XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 353                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 354                              XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 355                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 356                              XD_WP_PD | XD_CE_PD | XD_CLE_PD | XD_CD_PU);
 357                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 358                              XD_RDY_PD | XD_WE_PD | XD_RE_PD | XD_ALE_PD);
 359                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 360                              MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 361                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
 362                              MS_D5_PD | MS_D4_PD);
 363         } else if (CHECK_PID(chip, 0x5288)) {
 364                 if (CHECK_BARO_PKG(chip, QFN)) {
 365                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
 366                                      0xFF, 0x55);
 367                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
 368                                      0xFF, 0x55);
 369                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
 370                                      0xFF, 0x4B);
 371                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
 372                                      0xFF, 0x69);
 373                 }
 374         }
 375 }
 376
 377 static void xd_fill_pull_ctl_stage1_barossa(struct rtsx_chip *chip)
 378 {
 379         if (CHECK_BARO_PKG(chip, QFN)) {
 380                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
 381                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
 382                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x4B);
 383                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
 384         }
 385 }
 386
 387 static void xd_fill_pull_ctl_enable(struct rtsx_chip *chip)
 388 {
 389         if (CHECK_PID(chip, 0x5208)) {
 390                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF,
 391                              XD_D3_PD | XD_D2_PD | XD_D1_PD | XD_D0_PD);
 392                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF,
 393                              XD_D7_PD | XD_D6_PD | XD_D5_PD | XD_D4_PD);
 394                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF,
 395                              XD_WP_PD | XD_CE_PU | XD_CLE_PD | XD_CD_PU);
 396                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF,
 397                              XD_RDY_PU | XD_WE_PU | XD_RE_PU | XD_ALE_PD);
 398                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF,
 399                              MS_INS_PU | SD_WP_PD | SD_CD_PU | SD_CMD_PD);
 400                 rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF,
 401                              MS_D5_PD | MS_D4_PD);
 402         } else if (CHECK_PID(chip, 0x5288)) {
 403                 if (CHECK_BARO_PKG(chip, QFN)) {
 404                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1,
 405                                      0xFF, 0x55);
 406                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2,
 407                                      0xFF, 0x55);
 408                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3,
 409                                      0xFF, 0x53);
 410                         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4,
 411                                      0xFF, 0xA9);
 412                 }
 413         }
 414 }
 415
 416 static int xd_pull_ctl_disable(struct rtsx_chip *chip)
 417 {
 418         int retval;
 419
 420         if (CHECK_PID(chip, 0x5208)) {
 421                 retval = rtsx_write_register(chip, CARD_PULL_CTL1, 0xFF,
 422                                              XD_D3_PD |
 423                                              XD_D2_PD |
 424                                              XD_D1_PD |
 425                                              XD_D0_PD);
 426                 if (retval) {
 427                         rtsx_trace(chip);
 428                         return retval;
 429                 }
 430                 retval = rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF,
 431                                              XD_D7_PD |
 432                                              XD_D6_PD |
 433                                              XD_D5_PD |
 434                                              XD_D4_PD);
 435                 if (retval) {
 436                         rtsx_trace(chip);
 437                         return retval;
 438                 }
 439                 retval = rtsx_write_register(chip, CARD_PULL_CTL3, 0xFF,
 440                                              XD_WP_PD |
 441                                              XD_CE_PD |
 442                                              XD_CLE_PD |
 443                                              XD_CD_PU);
 444                 if (retval) {
 445                         rtsx_trace(chip);
 446                         return retval;
 447                 }
 448                 retval = rtsx_write_register(chip, CARD_PULL_CTL4, 0xFF,
 449                                              XD_RDY_PD |
 450                                              XD_WE_PD |
 451                                              XD_RE_PD |
 452                                              XD_ALE_PD);
 453                 if (retval) {
 454                         rtsx_trace(chip);
 455                         return retval;
 456                 }
 457                 retval = rtsx_write_register(chip, CARD_PULL_CTL5, 0xFF,
 458                                              MS_INS_PU |
 459                                              SD_WP_PD |
 460                                              SD_CD_PU |
 461                                              SD_CMD_PD);
 462                 if (retval) {
 463                         rtsx_trace(chip);
 464                         return retval;
 465                 }
 466                 retval = rtsx_write_register(chip, CARD_PULL_CTL6, 0xFF,
 467                                              MS_D5_PD | MS_D4_PD);
 468                 if (retval) {
 469                         rtsx_trace(chip);
 470                         return retval;
 471                 }
 472         } else if (CHECK_PID(chip, 0x5288)) {
 473                 if (CHECK_BARO_PKG(chip, QFN)) {
 474                         retval = rtsx_write_register(chip, CARD_PULL_CTL1,
 475                                                      0xFF, 0x55);
 476                         if (retval) {
 477                                 rtsx_trace(chip);
 478                                 return retval;
 479                         }
 480                         retval = rtsx_write_register(chip, CARD_PULL_CTL2,
 481                                                      0xFF, 0x55);
 482                         if (retval) {
 483                                 rtsx_trace(chip);
 484                                 return retval;
 485                         }
 486                         retval = rtsx_write_register(chip, CARD_PULL_CTL3,
 487                                                      0xFF, 0x4B);
 488                         if (retval) {
 489                                 rtsx_trace(chip);
 490                                 return retval;
 491                         }
 492                         retval = rtsx_write_register(chip, CARD_PULL_CTL4,
 493                                                      0xFF, 0x69);
 494                         if (retval) {
 495                                 rtsx_trace(chip);
 496                                 return retval;
 497                         }
 498                 }
 499         }
 500
 501         return STATUS_SUCCESS;
 502 }
 503
 504 static int reset_xd(struct rtsx_chip *chip)
 505 {
 506         struct xd_info *xd_card = &chip->xd_card;
 507         int retval, i, j;
 508         u8 *ptr, id_buf[4], redunt[11];
 509
 510         retval = select_card(chip, XD_CARD);
 511         if (retval != STATUS_SUCCESS) {
 512                 rtsx_trace(chip);
 513                 return STATUS_FAIL;
 514         }
 515
 516         rtsx_init_cmd(chip);
 517
 518         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
 519                      XD_PGSTS_NOT_FF);
 520         if (chip->asic_code) {
 521                 if (!CHECK_PID(chip, 0x5288))
 522                         xd_fill_pull_ctl_disable(chip);
 523                 else
 524                         xd_fill_pull_ctl_stage1_barossa(chip);
 525         } else {
 526                 rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 527                              (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3) |
 528                              0x20);
 529         }
 530
 531         if (!chip->ft2_fast_mode)
 532                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_INIT,
 533                              XD_NO_AUTO_PWR_OFF, 0);
 534
 535         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
 536
 537         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 538         if (retval < 0) {
 539                 rtsx_trace(chip);
 540                 return STATUS_FAIL;
 541         }
 542
 543         if (!chip->ft2_fast_mode) {
 544                 retval = card_power_off(chip, XD_CARD);
 545                 if (retval != STATUS_SUCCESS) {
 546                         rtsx_trace(chip);
 547                         return STATUS_FAIL;
 548                 }
 549
 550                 wait_timeout(250);
 551
 552                 rtsx_init_cmd(chip);
 553
 554                 if (chip->asic_code) {
 555                         xd_fill_pull_ctl_enable(chip);
 556                 } else {
 557                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 558                                      (FPGA_XD_PULL_CTL_EN1 &
 559                                       FPGA_XD_PULL_CTL_EN2) |
 560                                      0x20);
 561                 }
 562
 563                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 564                 if (retval < 0) {
 565                         rtsx_trace(chip);
 566                         return STATUS_FAIL;
 567                 }
 568
 569                 retval = card_power_on(chip, XD_CARD);
 570                 if (retval != STATUS_SUCCESS) {
 571                         rtsx_trace(chip);
 572                         return STATUS_FAIL;
 573                 }
 574
 575 #ifdef SUPPORT_OCP
 576                 wait_timeout(50);
 577                 if (chip->ocp_stat & (SD_OC_NOW | SD_OC_EVER)) {
 578                         dev_dbg(rtsx_dev(chip), "Over current, OCPSTAT is 0x%x\n",
 579                                 chip->ocp_stat);
 580                         rtsx_trace(chip);
 581                         return STATUS_FAIL;
 582                 }
 583 #endif
 584         }
 585
 586         rtsx_init_cmd(chip);
 587
 588         if (chip->ft2_fast_mode) {
 589                 if (chip->asic_code) {
 590                         xd_fill_pull_ctl_enable(chip);
 591                 } else {
 592                         rtsx_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
 593                                      (FPGA_XD_PULL_CTL_EN1 &
 594                                       FPGA_XD_PULL_CTL_EN2) |
 595                                      0x20);
 596                 }
 597         }
 598
 599         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, XD_OUTPUT_EN);
 600         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
 601
 602         retval = rtsx_send_cmd(chip, XD_CARD, 100);
 603         if (retval < 0) {
 604                 rtsx_trace(chip);
 605                 return STATUS_FAIL;
 606         }
 607
 608         if (!chip->ft2_fast_mode)
 609                 wait_timeout(200);
 610
 611         retval = xd_set_init_para(chip);
 612         if (retval != STATUS_SUCCESS) {
 613                 rtsx_trace(chip);
 614                 return STATUS_FAIL;
 615         }
 616
 617         /* Read ID to check if the timing setting is right */
 618         for (i = 0; i < 4; i++) {
 619                 rtsx_init_cmd(chip);
 620
 621                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
 622                              XD_TIME_SETUP_STEP * 3 +
 623                              XD_TIME_RW_STEP * (2 + i) + XD_TIME_RWN_STEP * i);
 624                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
 625                              XD_TIME_SETUP_STEP * 3 +
 626                              XD_TIME_RW_STEP * (4 + i) +
 627                              XD_TIME_RWN_STEP * (3 + i));
 628
 629                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
 630                              XD_TRANSFER_START | XD_RESET);
 631                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
 632                              XD_TRANSFER_END, XD_TRANSFER_END);
 633
 634                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
 635                 rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
 636
 637                 retval = rtsx_send_cmd(chip, XD_CARD, 100);
 638                 if (retval < 0) {
 639                         rtsx_trace(chip);
 640                         return STATUS_FAIL;
 641                 }
 642
 643                 ptr = rtsx_get_cmd_data(chip) + 1;
 644
 645                 dev_dbg(rtsx_dev(chip), "XD_DAT: 0x%x, XD_CTL: 0x%x\n",
 646                         ptr[0], ptr[1]);
 647
 648                 if (((ptr[0] & READY_FLAG) != READY_STATE) ||
 649                     !(ptr[1] & XD_RDY))
 650                         continue;
 651
 652                 retval = xd_read_id(chip, READ_ID, id_buf, 4);
 653                 if (retval != STATUS_SUCCESS) {
 654                         rtsx_trace(chip);
 655                         return STATUS_FAIL;
 656                 }
 657
 658                 dev_dbg(rtsx_dev(chip), "READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
 659                         id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 660
 661                 xd_card->device_code = id_buf[1];
 662
 663                 /* Check if the xD card is supported */
 664                 switch (xd_card->device_code) {
 665                 case XD_4M_X8_512_1:
 666                 case XD_4M_X8_512_2:
 667                         xd_card->block_shift = 4;
 668                         xd_card->page_off = 0x0F;
 669                         xd_card->addr_cycle = 3;
 670                         xd_card->zone_cnt = 1;
 671                         xd_card->capacity = 8000;
 672                         XD_SET_4MB(xd_card);
 673                         break;
 674                 case XD_8M_X8_512:
 675                         xd_card->block_shift = 4;
 676                         xd_card->page_off = 0x0F;
 677                         xd_card->addr_cycle = 3;
 678                         xd_card->zone_cnt = 1;
 679                         xd_card->capacity = 16000;
 680                         break;
 681                 case XD_16M_X8_512:
 682                         XD_PAGE_512(xd_card);
 683                         xd_card->addr_cycle = 3;
 684                         xd_card->zone_cnt = 1;
 685                         xd_card->capacity = 32000;
 686                         break;
 687                 case XD_32M_X8_512:
 688                         XD_PAGE_512(xd_card);
 689                         xd_card->addr_cycle = 3;
 690                         xd_card->zone_cnt = 2;
 691                         xd_card->capacity = 64000;
 692                         break;
 693                 case XD_64M_X8_512:
 694                         XD_PAGE_512(xd_card);
 695                         xd_card->addr_cycle = 4;
 696                         xd_card->zone_cnt = 4;
 697                         xd_card->capacity = 128000;
 698                         break;
 699                 case XD_128M_X8_512:
 700                         XD_PAGE_512(xd_card);
 701                         xd_card->addr_cycle = 4;
 702                         xd_card->zone_cnt = 8;
 703                         xd_card->capacity = 256000;
 704                         break;
 705                 case XD_256M_X8_512:
 706                         XD_PAGE_512(xd_card);
 707                         xd_card->addr_cycle = 4;
 708                         xd_card->zone_cnt = 16;
 709                         xd_card->capacity = 512000;
 710                         break;
 711                 case XD_512M_X8:
 712                         XD_PAGE_512(xd_card);
 713                         xd_card->addr_cycle = 4;
 714                         xd_card->zone_cnt = 32;
 715                         xd_card->capacity = 1024000;
 716                         break;
 717                 case xD_1G_X8_512:
 718                         XD_PAGE_512(xd_card);
 719                         xd_card->addr_cycle = 4;
 720                         xd_card->zone_cnt = 64;
 721                         xd_card->capacity = 2048000;
 722                         break;
 723                 case xD_2G_X8_512:
 724                         XD_PAGE_512(xd_card);
 725                         xd_card->addr_cycle = 4;
 726                         xd_card->zone_cnt = 128;
 727                         xd_card->capacity = 4096000;
 728                         break;
 729                 default:
 730                         continue;
 731                 }
 732
 733                 /* Confirm timing setting */
 734                 for (j = 0; j < 10; j++) {
 735                         retval = xd_read_id(chip, READ_ID, id_buf, 4);
 736                         if (retval != STATUS_SUCCESS) {
 737                                 rtsx_trace(chip);
 738                                 return STATUS_FAIL;
 739                         }
 740
 741                         if (id_buf[1] != xd_card->device_code)
 742                                 break;
 743                 }
 744
 745                 if (j == 10)
 746                         break;
 747         }
 748
 749         if (i == 4) {
 750                 xd_card->block_shift = 0;
 751                 xd_card->page_off = 0;
 752                 xd_card->addr_cycle = 0;
 753                 xd_card->capacity = 0;
 754
 755                 rtsx_trace(chip);
 756                 return STATUS_FAIL;
 757         }
 758
 759         retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
 760         if (retval != STATUS_SUCCESS) {
 761                 rtsx_trace(chip);
 762                 return STATUS_FAIL;
 763         }
 764         dev_dbg(rtsx_dev(chip), "READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
 765                 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
 766         if (id_buf[2] != XD_ID_CODE) {
 767                 rtsx_trace(chip);
 768                 return STATUS_FAIL;
 769         }
 770
 771         /* Search CIS block */
 772         for (i = 0; i < 24; i++) {
 773                 u32 page_addr;
 774
 775                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
 776                         rtsx_trace(chip);
 777                         return STATUS_FAIL;
 778                 }
 779
 780                 page_addr = (u32)i << xd_card->block_shift;
 781
 782                 for (j = 0; j < 3; j++) {
 783                         retval = xd_read_redundant(chip, page_addr, redunt, 11);
 784                         if (retval == STATUS_SUCCESS)
 785                                 break;
 786                 }
 787                 if (j == 3)
 788                         continue;
 789
 790                 if (redunt[BLOCK_STATUS] != XD_GBLK)
 791                         continue;
 792
 793                 j = 0;
 794                 if (redunt[PAGE_STATUS] != XD_GPG) {
 795                         for (j = 1; j <= 8; j++) {
 796                                 retval = xd_read_redundant(chip, page_addr + j,
 797                                                            redunt, 11);
 798                                 if (retval == STATUS_SUCCESS) {
 799                                         if (redunt[PAGE_STATUS] == XD_GPG)
 800                                                 break;
 801                                 }
 802                         }
 803
 804                         if (j == 9)
 805                                 break;
 806                 }
 807
 808                 /* Check CIS data */
 809                 if ((redunt[BLOCK_STATUS] == XD_GBLK) &&
 810                     (redunt[PARITY] & XD_BA1_ALL0)) {
 811                         u8 buf[10];
 812
 813                         page_addr += j;
 814
 815                         retval = xd_read_cis(chip, page_addr, buf, 10);
 816                         if (retval != STATUS_SUCCESS) {
 817                                 rtsx_trace(chip);
 818                                 return STATUS_FAIL;
 819                         }
 820
 821                         if ((buf[0] == 0x01) && (buf[1] == 0x03) &&
 822                             (buf[2] == 0xD9) &&
 823                             (buf[3] == 0x01) && (buf[4] == 0xFF) &&
 824                             (buf[5] == 0x18) && (buf[6] == 0x02) &&
 825                             (buf[7] == 0xDF) && (buf[8] == 0x01) &&
 826                             (buf[9] == 0x20)) {
 827                                 xd_card->cis_block = (u16)i;
 828                         }
 829                 }
 830
 831                 break;
 832         }
 833
 834         dev_dbg(rtsx_dev(chip), "CIS block: 0x%x\n", xd_card->cis_block);
 835         if (xd_card->cis_block == 0xFFFF) {
 836                 rtsx_trace(chip);
 837                 return STATUS_FAIL;
 838         }
 839
 840         chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
 841
 842         return STATUS_SUCCESS;
 843 }
 844
 845 static int xd_check_data_blank(u8 *redunt)
 846 {
 847         int i;
 848
 849         for (i = 0; i < 6; i++) {
 850                 if (redunt[PAGE_STATUS + i] != 0xFF)
 851                         return 0;
 852         }
 853
 854         if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 855                 != (XD_ECC1_ALL1 | XD_ECC2_ALL1))
 856                 return 0;
 857
 858         for (i = 0; i < 4; i++) {
 859                 if (redunt[RESERVED0 + i] != 0xFF)
 860                         return 0;
 861         }
 862
 863         return 1;
 864 }
 865
 866 static u16 xd_load_log_block_addr(u8 *redunt)
 867 {
 868         u16 addr = 0xFFFF;
 869
 870         if (redunt[PARITY] & XD_BA1_BA2_EQL)
 871                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
 872                         redunt[BLOCK_ADDR1_L];
 873         else if (redunt[PARITY] & XD_BA1_VALID)
 874                 addr = ((u16)redunt[BLOCK_ADDR1_H] << 8) |
 875                         redunt[BLOCK_ADDR1_L];
 876         else if (redunt[PARITY] & XD_BA2_VALID)
 877                 addr = ((u16)redunt[BLOCK_ADDR2_H] << 8) |
 878                         redunt[BLOCK_ADDR2_L];
 879
 880         return addr;
 881 }
 882
 883 static int xd_init_l2p_tbl(struct rtsx_chip *chip)
 884 {
 885         struct xd_info *xd_card = &chip->xd_card;
 886         int size, i;
 887
 888         dev_dbg(rtsx_dev(chip), "%s: zone_cnt = %d\n", __func__,
 889                 xd_card->zone_cnt);
 890
 891         if (xd_card->zone_cnt < 1) {
 892                 rtsx_trace(chip);
 893                 return STATUS_FAIL;
 894         }
 895
 896         size = xd_card->zone_cnt * sizeof(struct zone_entry);
 897         dev_dbg(rtsx_dev(chip), "Buffer size for l2p table is %d\n", size);
 898
 899         xd_card->zone = vmalloc(size);
 900         if (!xd_card->zone) {
 901                 rtsx_trace(chip);
 902                 return STATUS_ERROR;
 903         }
 904
 905         for (i = 0; i < xd_card->zone_cnt; i++) {
 906                 xd_card->zone[i].build_flag = 0;
 907                 xd_card->zone[i].l2p_table = NULL;
 908                 xd_card->zone[i].free_table = NULL;
 909                 xd_card->zone[i].get_index = 0;
 910                 xd_card->zone[i].set_index = 0;
 911                 xd_card->zone[i].unused_blk_cnt = 0;
 912         }
 913
 914         return STATUS_SUCCESS;
 915 }
 916
 917 static inline void free_zone(struct zone_entry *zone)
 918 {
 919         if (!zone)
 920                 return;
 921
 922         zone->build_flag = 0;
 923         zone->set_index = 0;
 924         zone->get_index = 0;
 925         zone->unused_blk_cnt = 0;
 926         vfree(zone->l2p_table);
 927         zone->l2p_table = NULL;
 928         vfree(zone->free_table);
 929         zone->free_table = NULL;
 930 }
 931
 932 static void xd_set_unused_block(struct rtsx_chip *chip, u32 phy_blk)
 933 {
 934         struct xd_info *xd_card = &chip->xd_card;
 935         struct zone_entry *zone;
 936         int zone_no;
 937
 938         zone_no = (int)phy_blk >> 10;
 939         if (zone_no >= xd_card->zone_cnt) {
 940                 dev_dbg(rtsx_dev(chip), "Set unused block to invalid zone (zone_no = %d, zone_cnt = %d)\n",
 941                         zone_no, xd_card->zone_cnt);
 942                 return;
 943         }
 944         zone = &xd_card->zone[zone_no];
 945
 946         if (!zone->free_table) {
 947                 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
 948                         return;
 949         }
 950
 951         if ((zone->set_index >= XD_FREE_TABLE_CNT) ||
 952             (zone->set_index < 0)) {
 953                 free_zone(zone);
 954                 dev_dbg(rtsx_dev(chip), "Set unused block fail, invalid set_index\n");
 955                 return;
 956         }
 957
 958         dev_dbg(rtsx_dev(chip), "Set unused block to index %d\n",
 959                 zone->set_index);
 960
 961         zone->free_table[zone->set_index++] = (u16)(phy_blk & 0x3ff);
 962         if (zone->set_index >= XD_FREE_TABLE_CNT)
 963                 zone->set_index = 0;
 964         zone->unused_blk_cnt++;
 965 }
 966
 967 static u32 xd_get_unused_block(struct rtsx_chip *chip, int zone_no)
 968 {
 969         struct xd_info *xd_card = &chip->xd_card;
 970         struct zone_entry *zone;
 971         u32 phy_blk;
 972
 973         if (zone_no >= xd_card->zone_cnt) {
 974                 dev_dbg(rtsx_dev(chip), "Get unused block from invalid zone (zone_no = %d, zone_cnt = %d)\n",
 975                         zone_no, xd_card->zone_cnt);
 976                 return BLK_NOT_FOUND;
 977         }
 978         zone = &xd_card->zone[zone_no];
 979
 980         if ((zone->unused_blk_cnt == 0) ||
 981             (zone->set_index == zone->get_index)) {
 982                 free_zone(zone);
 983                 dev_dbg(rtsx_dev(chip), "Get unused block fail, no unused block available\n");
 984                 return BLK_NOT_FOUND;
 985         }
 986         if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
 987                 free_zone(zone);
 988                 dev_dbg(rtsx_dev(chip), "Get unused block fail, invalid get_index\n");
 989                 return BLK_NOT_FOUND;
 990         }
 991
 992         dev_dbg(rtsx_dev(chip), "Get unused block from index %d\n",
 993                 zone->get_index);
 994
 995         phy_blk = zone->free_table[zone->get_index];
 996         zone->free_table[zone->get_index++] = 0xFFFF;
 997         if (zone->get_index >= XD_FREE_TABLE_CNT)
 998                 zone->get_index = 0;
 999         zone->unused_blk_cnt--;
1000
1001         phy_blk += ((u32)(zone_no) << 10);
1002         return phy_blk;
1003 }
1004
1005 static void xd_set_l2p_tbl(struct rtsx_chip *chip,
1006                            int zone_no, u16 log_off, u16 phy_off)
1007 {
1008         struct xd_info *xd_card = &chip->xd_card;
1009         struct zone_entry *zone;
1010
1011         zone = &xd_card->zone[zone_no];
1012         zone->l2p_table[log_off] = phy_off;
1013 }
1014
1015 static u32 xd_get_l2p_tbl(struct rtsx_chip *chip, int zone_no, u16 log_off)
1016 {
1017         struct xd_info *xd_card = &chip->xd_card;
1018         struct zone_entry *zone;
1019         int retval;
1020
1021         zone = &xd_card->zone[zone_no];
1022         if (zone->l2p_table[log_off] == 0xFFFF) {
1023                 u32 phy_blk = 0;
1024                 int i;
1025
1026 #ifdef XD_DELAY_WRITE
1027                 retval = xd_delay_write(chip);
1028                 if (retval != STATUS_SUCCESS) {
1029                         dev_dbg(rtsx_dev(chip), "In %s, delay write fail!\n",
1030                                 __func__);
1031                         return BLK_NOT_FOUND;
1032                 }
1033 #endif
1034
1035                 if (zone->unused_blk_cnt <= 0) {
1036                         dev_dbg(rtsx_dev(chip), "No unused block!\n");
1037                         return BLK_NOT_FOUND;
1038                 }
1039
1040                 for (i = 0; i < zone->unused_blk_cnt; i++) {
1041                         phy_blk = xd_get_unused_block(chip, zone_no);
1042                         if (phy_blk == BLK_NOT_FOUND) {
1043                                 dev_dbg(rtsx_dev(chip), "No unused block available!\n");
1044                                 return BLK_NOT_FOUND;
1045                         }
1046
1047                         retval = xd_init_page(chip, phy_blk, log_off,
1048                                               0, xd_card->page_off + 1);
1049                         if (retval == STATUS_SUCCESS)
1050                                 break;
1051                 }
1052                 if (i >= zone->unused_blk_cnt) {
1053                         dev_dbg(rtsx_dev(chip), "No good unused block available!\n");
1054                         return BLK_NOT_FOUND;
1055                 }
1056
1057                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(phy_blk & 0x3FF));
1058                 return phy_blk;
1059         }
1060
1061         return (u32)zone->l2p_table[log_off] + ((u32)(zone_no) << 10);
1062 }
1063
1064 int reset_xd_card(struct rtsx_chip *chip)
1065 {
1066         struct xd_info *xd_card = &chip->xd_card;
1067         int retval;
1068
1069         memset(xd_card, 0, sizeof(struct xd_info));
1070
1071         xd_card->block_shift = 0;
1072         xd_card->page_off = 0;
1073         xd_card->addr_cycle = 0;
1074         xd_card->capacity = 0;
1075         xd_card->zone_cnt = 0;
1076         xd_card->cis_block = 0xFFFF;
1077         xd_card->delay_write.delay_write_flag = 0;
1078
1079         retval = enable_card_clock(chip, XD_CARD);
1080         if (retval != STATUS_SUCCESS) {
1081                 rtsx_trace(chip);
1082                 return STATUS_FAIL;
1083         }
1084
1085         retval = reset_xd(chip);
1086         if (retval != STATUS_SUCCESS) {
1087                 rtsx_trace(chip);
1088                 return STATUS_FAIL;
1089         }
1090
1091         retval = xd_init_l2p_tbl(chip);
1092         if (retval != STATUS_SUCCESS) {
1093                 rtsx_trace(chip);
1094                 return STATUS_FAIL;
1095         }
1096
1097         return STATUS_SUCCESS;
1098 }
1099
1100 static int xd_mark_bad_block(struct rtsx_chip *chip, u32 phy_blk)
1101 {
1102         struct xd_info *xd_card = &chip->xd_card;
1103         int retval;
1104         u32 page_addr;
1105         u8 reg = 0;
1106
1107         dev_dbg(rtsx_dev(chip), "mark block 0x%x as bad block\n", phy_blk);
1108
1109         if (phy_blk == BLK_NOT_FOUND) {
1110                 rtsx_trace(chip);
1111                 return STATUS_FAIL;
1112         }
1113
1114         rtsx_init_cmd(chip);
1115
1116         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1117         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_LATER_BBLK);
1118         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
1119         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
1120         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
1121         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
1122         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
1123         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
1124         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
1125         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
1126
1127         page_addr = phy_blk << xd_card->block_shift;
1128
1129         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1130
1131         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1132                      xd_card->page_off + 1);
1133
1134         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1135                      XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1136         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1137                      XD_TRANSFER_END, XD_TRANSFER_END);
1138
1139         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1140         if (retval < 0) {
1141                 rtsx_clear_xd_error(chip);
1142                 rtsx_read_register(chip, XD_DAT, &reg);
1143                 if (reg & PROGRAM_ERROR)
1144                         xd_set_err_code(chip, XD_PRG_ERROR);
1145                 else
1146                         xd_set_err_code(chip, XD_TO_ERROR);
1147                 rtsx_trace(chip);
1148                 return STATUS_FAIL;
1149         }
1150
1151         return STATUS_SUCCESS;
1152 }
1153
1154 static int xd_init_page(struct rtsx_chip *chip, u32 phy_blk,
1155                         u16 logoff, u8 start_page, u8 end_page)
1156 {
1157         struct xd_info *xd_card = &chip->xd_card;
1158         int retval;
1159         u32 page_addr;
1160         u8 reg = 0;
1161
1162         dev_dbg(rtsx_dev(chip), "Init block 0x%x\n", phy_blk);
1163
1164         if (start_page > end_page) {
1165                 rtsx_trace(chip);
1166                 return STATUS_FAIL;
1167         }
1168         if (phy_blk == BLK_NOT_FOUND) {
1169                 rtsx_trace(chip);
1170                 return STATUS_FAIL;
1171         }
1172
1173         rtsx_init_cmd(chip);
1174
1175         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1176         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1177         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1178                      0xFF, (u8)(logoff >> 8));
1179         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)logoff);
1180
1181         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1182
1183         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1184
1185         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG,
1186                      XD_BA_TRANSFORM, XD_BA_TRANSFORM);
1187
1188         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT,
1189                      0xFF, (end_page - start_page));
1190
1191         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1192                      0xFF, XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1193         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1194                      XD_TRANSFER_END, XD_TRANSFER_END);
1195
1196         retval = rtsx_send_cmd(chip, XD_CARD, 500);
1197         if (retval < 0) {
1198                 rtsx_clear_xd_error(chip);
1199                 rtsx_read_register(chip, XD_DAT, &reg);
1200                 if (reg & PROGRAM_ERROR) {
1201                         xd_mark_bad_block(chip, phy_blk);
1202                         xd_set_err_code(chip, XD_PRG_ERROR);
1203                 } else {
1204                         xd_set_err_code(chip, XD_TO_ERROR);
1205                 }
1206                 rtsx_trace(chip);
1207                 return STATUS_FAIL;
1208         }
1209
1210         return STATUS_SUCCESS;
1211 }
1212
1213 static int xd_copy_page(struct rtsx_chip *chip, u32 old_blk, u32 new_blk,
1214                         u8 start_page, u8 end_page)
1215 {
1216         struct xd_info *xd_card = &chip->xd_card;
1217         u32 old_page, new_page;
1218         u8 i, reg = 0;
1219         int retval;
1220
1221         dev_dbg(rtsx_dev(chip), "Copy page from block 0x%x to block 0x%x\n",
1222                 old_blk, new_blk);
1223
1224         if (start_page > end_page) {
1225                 rtsx_trace(chip);
1226                 return STATUS_FAIL;
1227         }
1228
1229         if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND)) {
1230                 rtsx_trace(chip);
1231                 return STATUS_FAIL;
1232         }
1233
1234         old_page = (old_blk << xd_card->block_shift) + start_page;
1235         new_page = (new_blk << xd_card->block_shift) + start_page;
1236
1237         XD_CLR_BAD_NEWBLK(xd_card);
1238
1239         retval = rtsx_write_register(chip, CARD_DATA_SOURCE, 0x01,
1240                                      PINGPONG_BUFFER);
1241         if (retval) {
1242                 rtsx_trace(chip);
1243                 return retval;
1244         }
1245
1246         for (i = start_page; i < end_page; i++) {
1247                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1248                         rtsx_clear_xd_error(chip);
1249                         xd_set_err_code(chip, XD_NO_CARD);
1250                         rtsx_trace(chip);
1251                         return STATUS_FAIL;
1252                 }
1253
1254                 rtsx_init_cmd(chip);
1255
1256                 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1257
1258                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1259                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1260                              XD_AUTO_CHK_DATA_STATUS, 0);
1261                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1262                              XD_TRANSFER_START | XD_READ_PAGES);
1263                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1264                              XD_TRANSFER_END, XD_TRANSFER_END);
1265
1266                 retval = rtsx_send_cmd(chip, XD_CARD, 500);
1267                 if (retval < 0) {
1268                         rtsx_clear_xd_error(chip);
1269                         reg = 0;
1270                         rtsx_read_register(chip, XD_CTL, &reg);
1271                         if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1272                                 mdelay(100);
1273
1274                                 if (detect_card_cd(chip,
1275                                                    XD_CARD) != STATUS_SUCCESS) {
1276                                         xd_set_err_code(chip, XD_NO_CARD);
1277                                         rtsx_trace(chip);
1278                                         return STATUS_FAIL;
1279                                 }
1280
1281                                 if (((reg & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1282                                                 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1283                                         ((reg & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1284                                                 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1285                                         rtsx_write_register(chip,
1286                                                             XD_PAGE_STATUS,
1287                                                             0xFF,
1288                                                             XD_BPG);
1289                                         rtsx_write_register(chip,
1290                                                             XD_BLOCK_STATUS,
1291                                                             0xFF,
1292                                                             XD_GBLK);
1293                                         XD_SET_BAD_OLDBLK(xd_card);
1294                                         dev_dbg(rtsx_dev(chip), "old block 0x%x ecc error\n",
1295                                                 old_blk);
1296                                 }
1297                         } else {
1298                                 xd_set_err_code(chip, XD_TO_ERROR);
1299                                 rtsx_trace(chip);
1300                                 return STATUS_FAIL;
1301                         }
1302                 }
1303
1304                 if (XD_CHK_BAD_OLDBLK(xd_card))
1305                         rtsx_clear_xd_error(chip);
1306
1307                 rtsx_init_cmd(chip);
1308
1309                 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1310                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1311                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1312                              XD_TRANSFER_START | XD_WRITE_PAGES);
1313                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1314                              XD_TRANSFER_END, XD_TRANSFER_END);
1315
1316                 retval = rtsx_send_cmd(chip, XD_CARD, 300);
1317                 if (retval < 0) {
1318                         rtsx_clear_xd_error(chip);
1319                         reg = 0;
1320                         rtsx_read_register(chip, XD_DAT, &reg);
1321                         if (reg & PROGRAM_ERROR) {
1322                                 xd_mark_bad_block(chip, new_blk);
1323                                 xd_set_err_code(chip, XD_PRG_ERROR);
1324                                 XD_SET_BAD_NEWBLK(xd_card);
1325                         } else {
1326                                 xd_set_err_code(chip, XD_TO_ERROR);
1327                         }
1328                         rtsx_trace(chip);
1329                         return STATUS_FAIL;
1330                 }
1331
1332                 old_page++;
1333                 new_page++;
1334         }
1335
1336         return STATUS_SUCCESS;
1337 }
1338
1339 static int xd_reset_cmd(struct rtsx_chip *chip)
1340 {
1341         int retval;
1342         u8 *ptr;
1343
1344         rtsx_init_cmd(chip);
1345
1346         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1347                      0xFF, XD_TRANSFER_START | XD_RESET);
1348         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1349                      XD_TRANSFER_END, XD_TRANSFER_END);
1350         rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1351         rtsx_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1352
1353         retval = rtsx_send_cmd(chip, XD_CARD, 100);
1354         if (retval < 0) {
1355                 rtsx_trace(chip);
1356                 return STATUS_FAIL;
1357         }
1358
1359         ptr = rtsx_get_cmd_data(chip) + 1;
1360         if (((ptr[0] & READY_FLAG) == READY_STATE) && (ptr[1] & XD_RDY))
1361                 return STATUS_SUCCESS;
1362
1363         rtsx_trace(chip);
1364         return STATUS_FAIL;
1365 }
1366
1367 static int xd_erase_block(struct rtsx_chip *chip, u32 phy_blk)
1368 {
1369         struct xd_info *xd_card = &chip->xd_card;
1370         u32 page_addr;
1371         u8 reg = 0, *ptr;
1372         int i, retval;
1373
1374         if (phy_blk == BLK_NOT_FOUND) {
1375                 rtsx_trace(chip);
1376                 return STATUS_FAIL;
1377         }
1378
1379         page_addr = phy_blk << xd_card->block_shift;
1380
1381         for (i = 0; i < 3; i++) {
1382                 rtsx_init_cmd(chip);
1383
1384                 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1385
1386                 rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1387                              XD_TRANSFER_START | XD_ERASE);
1388                 rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1389                              XD_TRANSFER_END, XD_TRANSFER_END);
1390                 rtsx_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1391
1392                 retval = rtsx_send_cmd(chip, XD_CARD, 250);
1393                 if (retval < 0) {
1394                         rtsx_clear_xd_error(chip);
1395                         rtsx_read_register(chip, XD_DAT, &reg);
1396                         if (reg & PROGRAM_ERROR) {
1397                                 xd_mark_bad_block(chip, phy_blk);
1398                                 xd_set_err_code(chip, XD_PRG_ERROR);
1399                                 rtsx_trace(chip);
1400                                 return STATUS_FAIL;
1401                         }
1402                         xd_set_err_code(chip, XD_ERASE_FAIL);
1403                         retval = xd_reset_cmd(chip);
1404                         if (retval != STATUS_SUCCESS) {
1405                                 rtsx_trace(chip);
1406                                 return STATUS_FAIL;
1407                         }
1408                         continue;
1409                 }
1410
1411                 ptr = rtsx_get_cmd_data(chip) + 1;
1412                 if (*ptr & PROGRAM_ERROR) {
1413                         xd_mark_bad_block(chip, phy_blk);
1414                         xd_set_err_code(chip, XD_PRG_ERROR);
1415                         rtsx_trace(chip);
1416                         return STATUS_FAIL;
1417                 }
1418
1419                 return STATUS_SUCCESS;
1420         }
1421
1422         xd_mark_bad_block(chip, phy_blk);
1423         xd_set_err_code(chip, XD_ERASE_FAIL);
1424         rtsx_trace(chip);
1425         return STATUS_FAIL;
1426 }
1427
1428 static int xd_build_l2p_tbl(struct rtsx_chip *chip, int zone_no)
1429 {
1430         struct xd_info *xd_card = &chip->xd_card;
1431         struct zone_entry *zone;
1432         int retval;
1433         u32 start, end, i;
1434         u16 max_logoff, cur_fst_page_logoff;
1435         u16 cur_lst_page_logoff, ent_lst_page_logoff;
1436         u8 redunt[11];
1437
1438         dev_dbg(rtsx_dev(chip), "%s: %d\n", __func__, zone_no);
1439
1440         if (!xd_card->zone) {
1441                 retval = xd_init_l2p_tbl(chip);
1442                 if (retval != STATUS_SUCCESS)
1443                         return retval;
1444         }
1445
1446         if (xd_card->zone[zone_no].build_flag) {
1447                 dev_dbg(rtsx_dev(chip), "l2p table of zone %d has been built\n",
1448                         zone_no);
1449                 return STATUS_SUCCESS;
1450         }
1451
1452         zone = &xd_card->zone[zone_no];
1453
1454         if (!zone->l2p_table) {
1455                 zone->l2p_table = vmalloc(2000);
1456                 if (!zone->l2p_table) {
1457                         rtsx_trace(chip);
1458                         goto build_fail;
1459                 }
1460         }
1461         memset((u8 *)(zone->l2p_table), 0xff, 2000);
1462
1463         if (!zone->free_table) {
1464                 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1465                 if (!zone->free_table) {
1466                         rtsx_trace(chip);
1467                         goto build_fail;
1468                 }
1469         }
1470         memset((u8 *)(zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1471
1472         if (zone_no == 0) {
1473                 if (xd_card->cis_block == 0xFFFF)
1474                         start = 0;
1475                 else
1476                         start = xd_card->cis_block + 1;
1477                 if (XD_CHK_4MB(xd_card)) {
1478                         end = 0x200;
1479                         max_logoff = 499;
1480                 } else {
1481                         end = 0x400;
1482                         max_logoff = 999;
1483                 }
1484         } else {
1485                 start = (u32)(zone_no) << 10;
1486                 end = (u32)(zone_no + 1) << 10;
1487                 max_logoff = 999;
1488         }
1489
1490         dev_dbg(rtsx_dev(chip), "start block 0x%x, end block 0x%x\n",
1491                 start, end);
1492
1493         zone->set_index = 0;
1494         zone->get_index = 0;
1495         zone->unused_blk_cnt = 0;
1496
1497         for (i = start; i < end; i++) {
1498                 u32 page_addr = i << xd_card->block_shift;
1499                 u32 phy_block;
1500
1501                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1502                 if (retval != STATUS_SUCCESS)
1503                         continue;
1504
1505                 if (redunt[BLOCK_STATUS] != 0xFF) {
1506                         dev_dbg(rtsx_dev(chip), "bad block\n");
1507                         continue;
1508                 }
1509
1510                 if (xd_check_data_blank(redunt)) {
1511                         dev_dbg(rtsx_dev(chip), "blank block\n");
1512                         xd_set_unused_block(chip, i);
1513                         continue;
1514                 }
1515
1516                 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1517                 if ((cur_fst_page_logoff == 0xFFFF) ||
1518                     (cur_fst_page_logoff > max_logoff)) {
1519                         retval = xd_erase_block(chip, i);
1520                         if (retval == STATUS_SUCCESS)
1521                                 xd_set_unused_block(chip, i);
1522                         continue;
1523                 }
1524
1525                 if ((zone_no == 0) && (cur_fst_page_logoff == 0) &&
1526                     (redunt[PAGE_STATUS] != XD_GPG))
1527                         XD_SET_MBR_FAIL(xd_card);
1528
1529                 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1530                         zone->l2p_table[cur_fst_page_logoff] = (u16)(i & 0x3FF);
1531                         continue;
1532                 }
1533
1534                 phy_block = zone->l2p_table[cur_fst_page_logoff] +
1535                         ((u32)((zone_no) << 10));
1536
1537                 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1538
1539                 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1540                 if (retval != STATUS_SUCCESS)
1541                         continue;
1542
1543                 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1544                 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1545                         int m;
1546
1547                         page_addr = ((phy_block + 1) <<
1548                                 xd_card->block_shift) - 1;
1549
1550                         for (m = 0; m < 3; m++) {
1551                                 retval = xd_read_redundant(chip, page_addr,
1552                                                            redunt, 11);
1553                                 if (retval == STATUS_SUCCESS)
1554                                         break;
1555                         }
1556
1557                         if (m == 3) {
1558                                 zone->l2p_table[cur_fst_page_logoff] =
1559                                         (u16)(i & 0x3FF);
1560                                 retval = xd_erase_block(chip, phy_block);
1561                                 if (retval == STATUS_SUCCESS)
1562                                         xd_set_unused_block(chip, phy_block);
1563                                 continue;
1564                         }
1565
1566                         ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1567                         if (ent_lst_page_logoff != cur_fst_page_logoff) {
1568                                 zone->l2p_table[cur_fst_page_logoff] =
1569                                         (u16)(i & 0x3FF);
1570                                 retval = xd_erase_block(chip, phy_block);
1571                                 if (retval == STATUS_SUCCESS)
1572                                         xd_set_unused_block(chip, phy_block);
1573                                 continue;
1574                         } else {
1575                                 retval = xd_erase_block(chip, i);
1576                                 if (retval == STATUS_SUCCESS)
1577                                         xd_set_unused_block(chip, i);
1578                         }
1579                 } else {
1580                         retval = xd_erase_block(chip, i);
1581                         if (retval == STATUS_SUCCESS)
1582                                 xd_set_unused_block(chip, i);
1583                 }
1584         }
1585
1586         if (XD_CHK_4MB(xd_card))
1587                 end = 500;
1588         else
1589                 end = 1000;
1590
1591         i = 0;
1592         for (start = 0; start < end; start++) {
1593                 if (zone->l2p_table[start] == 0xFFFF)
1594                         i++;
1595         }
1596
1597         dev_dbg(rtsx_dev(chip), "Block count %d, invalid L2P entry %d\n",
1598                 end, i);
1599         dev_dbg(rtsx_dev(chip), "Total unused block: %d\n",
1600                 zone->unused_blk_cnt);
1601
1602         if ((zone->unused_blk_cnt - i) < 1)
1603                 chip->card_wp |= XD_CARD;
1604
1605         zone->build_flag = 1;
1606
1607         return STATUS_SUCCESS;
1608
1609 build_fail:
1610         vfree(zone->l2p_table);
1611         zone->l2p_table = NULL;
1612         vfree(zone->free_table);
1613         zone->free_table = NULL;
1614
1615         return STATUS_FAIL;
1616 }
1617
1618 static int xd_send_cmd(struct rtsx_chip *chip, u8 cmd)
1619 {
1620         int retval;
1621
1622         rtsx_init_cmd(chip);
1623
1624         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1625         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1626                      XD_TRANSFER_START | XD_SET_CMD);
1627         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1628                      XD_TRANSFER_END, XD_TRANSFER_END);
1629
1630         retval = rtsx_send_cmd(chip, XD_CARD, 200);
1631         if (retval < 0) {
1632                 rtsx_trace(chip);
1633                 return STATUS_FAIL;
1634         }
1635
1636         return STATUS_SUCCESS;
1637 }
1638
1639 static int xd_read_multiple_pages(struct rtsx_chip *chip, u32 phy_blk,
1640                                   u32 log_blk, u8 start_page, u8 end_page,
1641                                   u8 *buf, unsigned int *index,
1642                                   unsigned int *offset)
1643 {
1644         struct xd_info *xd_card = &chip->xd_card;
1645         u32 page_addr, new_blk;
1646         u16 log_off;
1647         u8 reg_val, page_cnt;
1648         int zone_no, retval, i;
1649
1650         if (start_page > end_page)
1651                 goto status_fail;
1652
1653         page_cnt = end_page - start_page;
1654         zone_no = (int)(log_blk / 1000);
1655         log_off = (u16)(log_blk % 1000);
1656
1657         if ((phy_blk & 0x3FF) == 0x3FF) {
1658                 for (i = 0; i < 256; i++) {
1659                         page_addr = ((u32)i) << xd_card->block_shift;
1660
1661                         retval = xd_read_redundant(chip, page_addr, NULL, 0);
1662                         if (retval == STATUS_SUCCESS)
1663                                 break;
1664
1665                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1666                                 xd_set_err_code(chip, XD_NO_CARD);
1667                                 goto status_fail;
1668                         }
1669                 }
1670         }
1671
1672         page_addr = (phy_blk << xd_card->block_shift) + start_page;
1673
1674         rtsx_init_cmd(chip);
1675
1676         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1677         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE, XD_PPB_TO_SIE);
1678         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1679         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1680         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1681                      XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1682
1683         trans_dma_enable(chip->srb->sc_data_direction, chip,
1684                          page_cnt * 512, DMA_512);
1685
1686         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1687                      XD_TRANSFER_START | XD_READ_PAGES);
1688         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1689                      XD_TRANSFER_END | XD_PPB_EMPTY,
1690                      XD_TRANSFER_END | XD_PPB_EMPTY);
1691
1692         rtsx_send_cmd_no_wait(chip);
1693
1694         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1695                                             scsi_sg_count(chip->srb),
1696                                             index, offset, DMA_FROM_DEVICE,
1697                                             chip->xd_timeout);
1698         if (retval < 0) {
1699                 rtsx_clear_xd_error(chip);
1700
1701                 if (retval == -ETIMEDOUT) {
1702                         xd_set_err_code(chip, XD_TO_ERROR);
1703                         goto status_fail;
1704                 } else {
1705                         rtsx_trace(chip);
1706                         goto fail;
1707                 }
1708         }
1709
1710         return STATUS_SUCCESS;
1711
1712 fail:
1713         retval = rtsx_read_register(chip, XD_PAGE_STATUS, &reg_val);
1714         if (retval) {
1715                 rtsx_trace(chip);
1716                 return retval;
1717         }
1718
1719         if (reg_val !=  XD_GPG)
1720                 xd_set_err_code(chip, XD_PRG_ERROR);
1721
1722         retval = rtsx_read_register(chip, XD_CTL, &reg_val);
1723         if (retval) {
1724                 rtsx_trace(chip);
1725                 return retval;
1726         }
1727
1728         if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ==
1729                                 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE)) ||
1730                 ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE)) ==
1731                         (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1732                 wait_timeout(100);
1733
1734                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
1735                         xd_set_err_code(chip, XD_NO_CARD);
1736                         goto status_fail;
1737                 }
1738
1739                 xd_set_err_code(chip, XD_ECC_ERROR);
1740
1741                 new_blk = xd_get_unused_block(chip, zone_no);
1742                 if (new_blk == NO_NEW_BLK) {
1743                         XD_CLR_BAD_OLDBLK(xd_card);
1744                         goto status_fail;
1745                 }
1746
1747                 retval = xd_copy_page(chip, phy_blk, new_blk, 0,
1748                                       xd_card->page_off + 1);
1749                 if (retval != STATUS_SUCCESS) {
1750                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1751                                 retval = xd_erase_block(chip, new_blk);
1752                                 if (retval == STATUS_SUCCESS)
1753                                         xd_set_unused_block(chip, new_blk);
1754                         } else {
1755                                 XD_CLR_BAD_NEWBLK(xd_card);
1756                         }
1757                         XD_CLR_BAD_OLDBLK(xd_card);
1758                         goto status_fail;
1759                 }
1760                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1761                 xd_erase_block(chip, phy_blk);
1762                 xd_mark_bad_block(chip, phy_blk);
1763                 XD_CLR_BAD_OLDBLK(xd_card);
1764         }
1765
1766 status_fail:
1767         rtsx_trace(chip);
1768         return STATUS_FAIL;
1769 }
1770
1771 static int xd_finish_write(struct rtsx_chip *chip,
1772                            u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1773 {
1774         struct xd_info *xd_card = &chip->xd_card;
1775         int retval, zone_no;
1776         u16 log_off;
1777
1778         dev_dbg(rtsx_dev(chip), "%s ", __func__);
1779         dev_dbg(rtsx_dev(chip), "old_blk = 0x%x, ", old_blk);
1780         dev_dbg(rtsx_dev(chip), "new_blk = 0x%x, ", new_blk);
1781         dev_dbg(rtsx_dev(chip), "log_blk = 0x%x\n", log_blk);
1782
1783         if (page_off > xd_card->page_off) {
1784                 rtsx_trace(chip);
1785                 return STATUS_FAIL;
1786         }
1787
1788         zone_no = (int)(log_blk / 1000);
1789         log_off = (u16)(log_blk % 1000);
1790
1791         if (old_blk == BLK_NOT_FOUND) {
1792                 retval = xd_init_page(chip, new_blk, log_off,
1793                                       page_off, xd_card->page_off + 1);
1794                 if (retval != STATUS_SUCCESS) {
1795                         retval = xd_erase_block(chip, new_blk);
1796                         if (retval == STATUS_SUCCESS)
1797                                 xd_set_unused_block(chip, new_blk);
1798                         rtsx_trace(chip);
1799                         return STATUS_FAIL;
1800                 }
1801         } else {
1802                 retval = xd_copy_page(chip, old_blk, new_blk,
1803                                       page_off, xd_card->page_off + 1);
1804                 if (retval != STATUS_SUCCESS) {
1805                         if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1806                                 retval = xd_erase_block(chip, new_blk);
1807                                 if (retval == STATUS_SUCCESS)
1808                                         xd_set_unused_block(chip, new_blk);
1809                         }
1810                         XD_CLR_BAD_NEWBLK(xd_card);
1811                         rtsx_trace(chip);
1812                         return STATUS_FAIL;
1813                 }
1814
1815                 retval = xd_erase_block(chip, old_blk);
1816                 if (retval == STATUS_SUCCESS) {
1817                         if (XD_CHK_BAD_OLDBLK(xd_card)) {
1818                                 xd_mark_bad_block(chip, old_blk);
1819                                 XD_CLR_BAD_OLDBLK(xd_card);
1820                         } else {
1821                                 xd_set_unused_block(chip, old_blk);
1822                         }
1823                 } else {
1824                         xd_set_err_code(chip, XD_NO_ERROR);
1825                         XD_CLR_BAD_OLDBLK(xd_card);
1826                 }
1827         }
1828
1829         xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1830
1831         return STATUS_SUCCESS;
1832 }
1833
1834 static int xd_prepare_write(struct rtsx_chip *chip,
1835                             u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1836 {
1837         int retval;
1838
1839         dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x, page_off = %d\n",
1840                 __func__, old_blk, new_blk, log_blk, (int)page_off);
1841
1842         if (page_off) {
1843                 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1844                 if (retval != STATUS_SUCCESS) {
1845                         rtsx_trace(chip);
1846                         return STATUS_FAIL;
1847                 }
1848         }
1849
1850         return STATUS_SUCCESS;
1851 }
1852
1853 static int xd_write_multiple_pages(struct rtsx_chip *chip, u32 old_blk,
1854                                    u32 new_blk, u32 log_blk, u8 start_page,
1855                                    u8 end_page, u8 *buf, unsigned int *index,
1856                                    unsigned int *offset)
1857 {
1858         struct xd_info *xd_card = &chip->xd_card;
1859         u32 page_addr;
1860         int zone_no, retval;
1861         u16 log_off;
1862         u8 page_cnt, reg_val;
1863
1864         dev_dbg(rtsx_dev(chip), "%s, old_blk = 0x%x, new_blk = 0x%x, log_blk = 0x%x\n",
1865                 __func__, old_blk, new_blk, log_blk);
1866
1867         if (start_page > end_page)
1868                 goto status_fail;
1869
1870         page_cnt = end_page - start_page;
1871         zone_no = (int)(log_blk / 1000);
1872         log_off = (u16)(log_blk % 1000);
1873
1874         page_addr = (new_blk << xd_card->block_shift) + start_page;
1875
1876         retval = xd_send_cmd(chip, READ1_1);
1877         if (retval != STATUS_SUCCESS)
1878                 goto status_fail;
1879
1880         rtsx_init_cmd(chip);
1881
1882         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H,
1883                      0xFF, (u8)(log_off >> 8));
1884         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, (u8)log_off);
1885         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1886         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1887
1888         xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1889
1890         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1891                      XD_BA_TRANSFORM);
1892         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1893         rtsx_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01, RING_BUFFER);
1894
1895         trans_dma_enable(chip->srb->sc_data_direction, chip,
1896                          page_cnt * 512, DMA_512);
1897
1898         rtsx_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER,
1899                      0xFF, XD_TRANSFER_START | XD_WRITE_PAGES);
1900         rtsx_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1901                      XD_TRANSFER_END, XD_TRANSFER_END);
1902
1903         rtsx_send_cmd_no_wait(chip);
1904
1905         retval = rtsx_transfer_data_partial(chip, XD_CARD, buf, page_cnt * 512,
1906                                             scsi_sg_count(chip->srb),
1907                                             index, offset, DMA_TO_DEVICE, chip->xd_timeout);
1908         if (retval < 0) {
1909                 rtsx_clear_xd_error(chip);
1910
1911                 if (retval == -ETIMEDOUT) {
1912                         xd_set_err_code(chip, XD_TO_ERROR);
1913                         goto status_fail;
1914                 } else {
1915                         rtsx_trace(chip);
1916                         goto fail;
1917                 }
1918         }
1919
1920         if (end_page == (xd_card->page_off + 1)) {
1921                 xd_card->delay_write.delay_write_flag = 0;
1922
1923                 if (old_blk != BLK_NOT_FOUND) {
1924                         retval = xd_erase_block(chip, old_blk);
1925                         if (retval == STATUS_SUCCESS) {
1926                                 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1927                                         xd_mark_bad_block(chip, old_blk);
1928                                         XD_CLR_BAD_OLDBLK(xd_card);
1929                                 } else {
1930                                         xd_set_unused_block(chip, old_blk);
1931                                 }
1932                         } else {
1933                                 xd_set_err_code(chip, XD_NO_ERROR);
1934                                 XD_CLR_BAD_OLDBLK(xd_card);
1935                         }
1936                 }
1937                 xd_set_l2p_tbl(chip, zone_no, log_off, (u16)(new_blk & 0x3FF));
1938         }
1939
1940         return STATUS_SUCCESS;
1941
1942 fail:
1943         retval = rtsx_read_register(chip, XD_DAT, &reg_val);
1944         if (retval) {
1945                 rtsx_trace(chip);
1946                 return retval;
1947         }
1948         if (reg_val & PROGRAM_ERROR) {
1949                 xd_set_err_code(chip, XD_PRG_ERROR);
1950                 xd_mark_bad_block(chip, new_blk);
1951         }
1952
1953 status_fail:
1954         rtsx_trace(chip);
1955         return STATUS_FAIL;
1956 }
1957
1958 #ifdef XD_DELAY_WRITE
1959 int xd_delay_write(struct rtsx_chip *chip)
1960 {
1961         struct xd_info *xd_card = &chip->xd_card;
1962         struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1963         int retval;
1964
1965         if (delay_write->delay_write_flag) {
1966                 dev_dbg(rtsx_dev(chip), "%s\n", __func__);
1967                 retval = xd_switch_clock(chip);
1968                 if (retval != STATUS_SUCCESS) {
1969                         rtsx_trace(chip);
1970                         return STATUS_FAIL;
1971                 }
1972
1973                 delay_write->delay_write_flag = 0;
1974                 retval = xd_finish_write(chip,
1975                                          delay_write->old_phyblock,
1976                                          delay_write->new_phyblock,
1977                                          delay_write->logblock,
1978                                          delay_write->pageoff);
1979                 if (retval != STATUS_SUCCESS) {
1980                         rtsx_trace(chip);
1981                         return STATUS_FAIL;
1982                 }
1983         }
1984
1985         return STATUS_SUCCESS;
1986 }
1987 #endif
1988
1989 int xd_rw(struct scsi_cmnd *srb, struct rtsx_chip *chip,
1990           u32 start_sector, u16 sector_cnt)
1991 {
1992         struct xd_info *xd_card = &chip->xd_card;
1993         unsigned int lun = SCSI_LUN(srb);
1994 #ifdef XD_DELAY_WRITE
1995         struct xd_delay_write_tag *delay_write = &xd_card->delay_write;
1996 #endif
1997         int retval, zone_no;
1998         unsigned int index = 0, offset = 0;
1999         u32 log_blk, old_blk = 0, new_blk = 0;
2000         u16 log_off, total_sec_cnt = sector_cnt;
2001         u8 start_page, end_page = 0, page_cnt;
2002         u8 *ptr;
2003
2004         xd_set_err_code(chip, XD_NO_ERROR);
2005
2006         xd_card->cleanup_counter = 0;
2007
2008         dev_dbg(rtsx_dev(chip), "%s: scsi_sg_count = %d\n", __func__,
2009                 scsi_sg_count(srb));
2010
2011         ptr = (u8 *)scsi_sglist(srb);
2012
2013         retval = xd_switch_clock(chip);
2014         if (retval != STATUS_SUCCESS) {
2015                 rtsx_trace(chip);
2016                 return STATUS_FAIL;
2017         }
2018
2019         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2020                 chip->card_fail |= XD_CARD;
2021                 set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2022                 rtsx_trace(chip);
2023                 return STATUS_FAIL;
2024         }
2025
2026         log_blk = start_sector >> xd_card->block_shift;
2027         start_page = (u8)start_sector & xd_card->page_off;
2028         zone_no = (int)(log_blk / 1000);
2029         log_off = (u16)(log_blk % 1000);
2030
2031         if (xd_card->zone[zone_no].build_flag == 0) {
2032                 retval = xd_build_l2p_tbl(chip, zone_no);
2033                 if (retval != STATUS_SUCCESS) {
2034                         chip->card_fail |= XD_CARD;
2035                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2036                         rtsx_trace(chip);
2037                         return STATUS_FAIL;
2038                 }
2039         }
2040
2041         if (srb->sc_data_direction == DMA_TO_DEVICE) {
2042 #ifdef XD_DELAY_WRITE
2043                 if (delay_write->delay_write_flag &&
2044                     (delay_write->logblock == log_blk) &&
2045                     (start_page > delay_write->pageoff)) {
2046                         delay_write->delay_write_flag = 0;
2047                         if (delay_write->old_phyblock != BLK_NOT_FOUND) {
2048                                 retval = xd_copy_page(chip,
2049                                                       delay_write->old_phyblock,
2050                                                       delay_write->new_phyblock,
2051                                                       delay_write->pageoff,
2052                                                       start_page);
2053                                 if (retval != STATUS_SUCCESS) {
2054                                         set_sense_type(chip, lun,
2055                                                        SENSE_TYPE_MEDIA_WRITE_ERR);
2056                                         rtsx_trace(chip);
2057                                         return STATUS_FAIL;
2058                                 }
2059                         }
2060                         old_blk = delay_write->old_phyblock;
2061                         new_blk = delay_write->new_phyblock;
2062                 } else if (delay_write->delay_write_flag &&
2063                                 (delay_write->logblock == log_blk) &&
2064                                 (start_page == delay_write->pageoff)) {
2065                         delay_write->delay_write_flag = 0;
2066                         old_blk = delay_write->old_phyblock;
2067                         new_blk = delay_write->new_phyblock;
2068                 } else {
2069                         retval = xd_delay_write(chip);
2070                         if (retval != STATUS_SUCCESS) {
2071                                 set_sense_type(chip, lun,
2072                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2073                                 rtsx_trace(chip);
2074                                 return STATUS_FAIL;
2075                         }
2076 #endif
2077                         old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2078                         new_blk  = xd_get_unused_block(chip, zone_no);
2079                         if ((old_blk == BLK_NOT_FOUND) ||
2080                             (new_blk == BLK_NOT_FOUND)) {
2081                                 set_sense_type(chip, lun,
2082                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2083                                 rtsx_trace(chip);
2084                                 return STATUS_FAIL;
2085                         }
2086
2087                         retval = xd_prepare_write(chip, old_blk, new_blk,
2088                                                   log_blk, start_page);
2089                         if (retval != STATUS_SUCCESS) {
2090                                 if (detect_card_cd(chip, XD_CARD) !=
2091                                         STATUS_SUCCESS) {
2092                                         set_sense_type(chip, lun,
2093                                                        SENSE_TYPE_MEDIA_NOT_PRESENT);
2094                                         rtsx_trace(chip);
2095                                         return STATUS_FAIL;
2096                                 }
2097                                 set_sense_type(chip, lun,
2098                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2099                                 rtsx_trace(chip);
2100                                 return STATUS_FAIL;
2101                         }
2102 #ifdef XD_DELAY_WRITE
2103                 }
2104 #endif
2105         } else {
2106 #ifdef XD_DELAY_WRITE
2107                 retval = xd_delay_write(chip);
2108                 if (retval != STATUS_SUCCESS) {
2109                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2110                                 set_sense_type(chip, lun,
2111                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2112                                 rtsx_trace(chip);
2113                                 return STATUS_FAIL;
2114                         }
2115                         set_sense_type(chip, lun,
2116                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2117                         rtsx_trace(chip);
2118                         return STATUS_FAIL;
2119                 }
2120 #endif
2121
2122                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2123                 if (old_blk == BLK_NOT_FOUND) {
2124                         set_sense_type(chip, lun,
2125                                        SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2126                         rtsx_trace(chip);
2127                         return STATUS_FAIL;
2128                 }
2129         }
2130
2131         dev_dbg(rtsx_dev(chip), "old_blk = 0x%x\n", old_blk);
2132
2133         while (total_sec_cnt) {
2134                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2135                         chip->card_fail |= XD_CARD;
2136                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2137                         rtsx_trace(chip);
2138                         return STATUS_FAIL;
2139                 }
2140
2141                 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
2142                         end_page = xd_card->page_off + 1;
2143                 else
2144                         end_page = start_page + (u8)total_sec_cnt;
2145
2146                 page_cnt = end_page - start_page;
2147                 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2148                         retval = xd_read_multiple_pages(chip, old_blk, log_blk,
2149                                                         start_page, end_page,
2150                                                         ptr, &index, &offset);
2151                         if (retval != STATUS_SUCCESS) {
2152                                 set_sense_type(chip, lun,
2153                                                SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2154                                 rtsx_trace(chip);
2155                                 return STATUS_FAIL;
2156                         }
2157                 } else {
2158                         retval = xd_write_multiple_pages(chip, old_blk,
2159                                                          new_blk, log_blk,
2160                                                          start_page, end_page,
2161                                                          ptr, &index, &offset);
2162                         if (retval != STATUS_SUCCESS) {
2163                                 set_sense_type(chip, lun,
2164                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2165                                 rtsx_trace(chip);
2166                                 return STATUS_FAIL;
2167                         }
2168                 }
2169
2170                 total_sec_cnt -= page_cnt;
2171                 if (scsi_sg_count(srb) == 0)
2172                         ptr += page_cnt * 512;
2173
2174                 if (total_sec_cnt == 0)
2175                         break;
2176
2177                 log_blk++;
2178                 zone_no = (int)(log_blk / 1000);
2179                 log_off = (u16)(log_blk % 1000);
2180
2181                 if (xd_card->zone[zone_no].build_flag == 0) {
2182                         retval = xd_build_l2p_tbl(chip, zone_no);
2183                         if (retval != STATUS_SUCCESS) {
2184                                 chip->card_fail |= XD_CARD;
2185                                 set_sense_type(chip, lun,
2186                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2187                                 rtsx_trace(chip);
2188                                 return STATUS_FAIL;
2189                         }
2190                 }
2191
2192                 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2193                 if (old_blk == BLK_NOT_FOUND) {
2194                         if (srb->sc_data_direction == DMA_FROM_DEVICE)
2195                                 set_sense_type(chip, lun,
2196                                                SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2197                         else
2198                                 set_sense_type(chip, lun,
2199                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2200
2201                         rtsx_trace(chip);
2202                         return STATUS_FAIL;
2203                 }
2204
2205                 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2206                         new_blk = xd_get_unused_block(chip, zone_no);
2207                         if (new_blk == BLK_NOT_FOUND) {
2208                                 set_sense_type(chip, lun,
2209                                                SENSE_TYPE_MEDIA_WRITE_ERR);
2210                                 rtsx_trace(chip);
2211                                 return STATUS_FAIL;
2212                         }
2213                 }
2214
2215                 start_page = 0;
2216         }
2217
2218         if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2219             (end_page != (xd_card->page_off + 1))) {
2220 #ifdef XD_DELAY_WRITE
2221                 delay_write->delay_write_flag = 1;
2222                 delay_write->old_phyblock = old_blk;
2223                 delay_write->new_phyblock = new_blk;
2224                 delay_write->logblock = log_blk;
2225                 delay_write->pageoff = end_page;
2226 #else
2227                 if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2228                         chip->card_fail |= XD_CARD;
2229                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
2230                         rtsx_trace(chip);
2231                         return STATUS_FAIL;
2232                 }
2233
2234                 retval = xd_finish_write(chip, old_blk, new_blk,
2235                                          log_blk, end_page);
2236                 if (retval != STATUS_SUCCESS) {
2237                         if (detect_card_cd(chip, XD_CARD) != STATUS_SUCCESS) {
2238                                 set_sense_type(chip, lun,
2239                                                SENSE_TYPE_MEDIA_NOT_PRESENT);
2240                                 rtsx_trace(chip);
2241                                 return STATUS_FAIL;
2242                         }
2243                         set_sense_type(chip, lun, SENSE_TYPE_MEDIA_WRITE_ERR);
2244                         rtsx_trace(chip);
2245                         return STATUS_FAIL;
2246                 }
2247 #endif
2248         }
2249
2250         scsi_set_resid(srb, 0);
2251
2252         return STATUS_SUCCESS;
2253 }
2254
2255 void xd_free_l2p_tbl(struct rtsx_chip *chip)
2256 {
2257         struct xd_info *xd_card = &chip->xd_card;
2258         int i = 0;
2259
2260         if (xd_card->zone) {
2261                 for (i = 0; i < xd_card->zone_cnt; i++) {
2262                         vfree(xd_card->zone[i].l2p_table);
2263                         xd_card->zone[i].l2p_table = NULL;
2264                         vfree(xd_card->zone[i].free_table);
2265                         xd_card->zone[i].free_table = NULL;
2266                 }
2267                 vfree(xd_card->zone);
2268                 xd_card->zone = NULL;
2269         }
2270 }
2271
2272 void xd_cleanup_work(struct rtsx_chip *chip)
2273 {
2274 #ifdef XD_DELAY_WRITE
2275         struct xd_info *xd_card = &chip->xd_card;
2276
2277         if (xd_card->delay_write.delay_write_flag) {
2278                 dev_dbg(rtsx_dev(chip), "xD: delay write\n");
2279                 xd_delay_write(chip);
2280                 xd_card->cleanup_counter = 0;
2281         }
2282 #endif
2283 }
2284
2285 int xd_power_off_card3v3(struct rtsx_chip *chip)
2286 {
2287         int retval;
2288
2289         retval = disable_card_clock(chip, XD_CARD);
2290         if (retval != STATUS_SUCCESS) {
2291                 rtsx_trace(chip);
2292                 return STATUS_FAIL;
2293         }
2294
2295         retval = rtsx_write_register(chip, CARD_OE, XD_OUTPUT_EN, 0);
2296         if (retval) {
2297                 rtsx_trace(chip);
2298                 return retval;
2299         }
2300
2301         if (!chip->ft2_fast_mode) {
2302                 retval = card_power_off(chip, XD_CARD);
2303                 if (retval != STATUS_SUCCESS) {
2304                         rtsx_trace(chip);
2305                         return STATUS_FAIL;
2306                 }
2307
2308                 wait_timeout(50);
2309         }
2310
2311         if (chip->asic_code) {
2312                 retval = xd_pull_ctl_disable(chip);
2313                 if (retval != STATUS_SUCCESS) {
2314                         rtsx_trace(chip);
2315                         return STATUS_FAIL;
2316                 }
2317         } else {
2318                 retval = rtsx_write_register(chip, FPGA_PULL_CTL, 0xFF, 0xDF);
2319                 if (retval) {
2320                         rtsx_trace(chip);
2321                         return retval;
2322                 }
2323         }
2324
2325         return STATUS_SUCCESS;
2326 }
2327
2328 int release_xd_card(struct rtsx_chip *chip)
2329 {
2330         struct xd_info *xd_card = &chip->xd_card;
2331         int retval;
2332
2333         chip->card_ready &= ~XD_CARD;
2334         chip->card_fail &= ~XD_CARD;
2335         chip->card_wp &= ~XD_CARD;
2336
2337         xd_card->delay_write.delay_write_flag = 0;
2338
2339         xd_free_l2p_tbl(chip);
2340
2341         retval = xd_power_off_card3v3(chip);
2342         if (retval != STATUS_SUCCESS) {
2343                 rtsx_trace(chip);
2344                 return STATUS_FAIL;
2345         }
2346
2347         return STATUS_SUCCESS;
2348 }