1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
8 * Purpose: MAC routines
15 * MACbIsRegBitsOn - Test if All test Bits On
16 * MACbIsRegBitsOff - Test if All test Bits Off
17 * MACbIsIntDisable - Test if MAC interrupt disable
18 * MACvSetShortRetryLimit - Set 802.11 Short Retry limit
19 * MACvSetLongRetryLimit - Set 802.11 Long Retry limit
20 * MACvSetLoopbackMode - Set MAC Loopback Mode
21 * MACvSaveContext - Save Context of MAC Registers
22 * MACvRestoreContext - Restore Context of MAC Registers
23 * MACbSoftwareReset - Software Reset MAC
24 * MACbSafeRxOff - Turn Off MAC Rx
25 * MACbSafeTxOff - Turn Off MAC Tx
26 * MACbSafeStop - Stop MAC function
27 * MACbShutdown - Shut down MAC
28 * MACvInitialize - Initialize MAC
29 * MACvSetCurrRxDescAddr - Set Rx Descriptors Address
30 * MACvSetCurrTx0DescAddr - Set Tx0 Descriptors Address
31 * MACvSetCurrTx1DescAddr - Set Tx1 Descriptors Address
32 * MACvTimer0MicroSDelay - Micro Second Delay Loop by MAC
35 * 08-22-2003 Kyle Hsu : Porting MAC functions from sim53
36 * 09-03-2003 Bryan YC Fan : Add MACvClearBusSusInd()&
37 * MACvEnableBusSusEn()
38 * 09-18-2003 Jerry Chen : Add MACvSetKeyEntry & MACvDisableKeyEntry
47 * Test if all test bits on
51 * io_base - Base Address for MAC
52 * byRegOfs - Offset of MAC Register
53 * byTestBits - Test bits
57 * Return Value: true if all test bits On; otherwise false
60 bool MACbIsRegBitsOn(struct vnt_private *priv, unsigned char byRegOfs,
61 unsigned char byTestBits)
63 void __iomem *io_base = priv->PortOffset;
65 return (ioread8(io_base + byRegOfs) & byTestBits) == byTestBits;
70 * Test if all test bits off
74 * io_base - Base Address for MAC
75 * byRegOfs - Offset of MAC Register
76 * byTestBits - Test bits
80 * Return Value: true if all test bits Off; otherwise false
83 bool MACbIsRegBitsOff(struct vnt_private *priv, unsigned char byRegOfs,
84 unsigned char byTestBits)
86 void __iomem *io_base = priv->PortOffset;
88 return !(ioread8(io_base + byRegOfs) & byTestBits);
93 * Test if MAC interrupt disable
97 * io_base - Base Address for MAC
101 * Return Value: true if interrupt is disable; otherwise false
104 bool MACbIsIntDisable(struct vnt_private *priv)
106 void __iomem *io_base = priv->PortOffset;
108 if (ioread32(io_base + MAC_REG_IMR))
116 * Set 802.11 Short Retry Limit
120 * io_base - Base Address for MAC
121 * byRetryLimit- Retry Limit
128 void MACvSetShortRetryLimit(struct vnt_private *priv,
129 unsigned char byRetryLimit)
131 void __iomem *io_base = priv->PortOffset;
133 iowrite8(byRetryLimit, io_base + MAC_REG_SRT);
138 * Set 802.11 Long Retry Limit
142 * io_base - Base Address for MAC
143 * byRetryLimit- Retry Limit
150 void MACvSetLongRetryLimit(struct vnt_private *priv,
151 unsigned char byRetryLimit)
153 void __iomem *io_base = priv->PortOffset;
155 iowrite8(byRetryLimit, io_base + MAC_REG_LRT);
160 * Set MAC Loopback mode
164 * io_base - Base Address for MAC
165 * byLoopbackMode - Loopback Mode
172 void MACvSetLoopbackMode(struct vnt_private *priv, unsigned char byLoopbackMode)
174 void __iomem *io_base = priv->PortOffset;
176 byLoopbackMode <<= 6;
178 iowrite8((ioread8(io_base + MAC_REG_TEST) & 0x3f) | byLoopbackMode,
179 io_base + MAC_REG_TEST);
184 * Save MAC registers to context buffer
188 * io_base - Base Address for MAC
190 * cxt_buf - Context buffer
195 void MACvSaveContext(struct vnt_private *priv, unsigned char *cxt_buf)
197 void __iomem *io_base = priv->PortOffset;
199 /* read page0 register */
200 memcpy_fromio(cxt_buf, io_base, MAC_MAX_CONTEXT_SIZE_PAGE0);
202 MACvSelectPage1(io_base);
204 /* read page1 register */
205 memcpy_fromio(cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0, io_base,
206 MAC_MAX_CONTEXT_SIZE_PAGE1);
208 MACvSelectPage0(io_base);
213 * Restore MAC registers from context buffer
217 * io_base - Base Address for MAC
218 * cxt_buf - Context buffer
225 void MACvRestoreContext(struct vnt_private *priv, unsigned char *cxt_buf)
227 void __iomem *io_base = priv->PortOffset;
229 MACvSelectPage1(io_base);
231 memcpy_toio(io_base, cxt_buf + MAC_MAX_CONTEXT_SIZE_PAGE0,
232 MAC_MAX_CONTEXT_SIZE_PAGE1);
234 MACvSelectPage0(io_base);
236 /* restore RCR,TCR,IMR... */
237 memcpy_toio(io_base + MAC_REG_RCR, cxt_buf + MAC_REG_RCR,
238 MAC_REG_ISR - MAC_REG_RCR);
240 /* restore MAC Config. */
241 memcpy_toio(io_base + MAC_REG_LRT, cxt_buf + MAC_REG_LRT,
242 MAC_REG_PAGE1SEL - MAC_REG_LRT);
244 iowrite8(*(cxt_buf + MAC_REG_CFG), io_base + MAC_REG_CFG);
246 /* restore PS Config. */
247 memcpy_toio(io_base + MAC_REG_PSCFG, cxt_buf + MAC_REG_PSCFG,
248 MAC_REG_BBREGCTL - MAC_REG_PSCFG);
250 /* restore CURR_RX_DESC_ADDR, CURR_TX_DESC_ADDR */
251 iowrite32(*(u32 *)(cxt_buf + MAC_REG_TXDMAPTR0),
252 io_base + MAC_REG_TXDMAPTR0);
253 iowrite32(*(u32 *)(cxt_buf + MAC_REG_AC0DMAPTR),
254 io_base + MAC_REG_AC0DMAPTR);
255 iowrite32(*(u32 *)(cxt_buf + MAC_REG_BCNDMAPTR),
256 io_base + MAC_REG_BCNDMAPTR);
257 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR0),
258 io_base + MAC_REG_RXDMAPTR0);
259 iowrite32(*(u32 *)(cxt_buf + MAC_REG_RXDMAPTR1),
260 io_base + MAC_REG_RXDMAPTR1);
269 * io_base - Base Address for MAC
273 * Return Value: true if Reset Success; otherwise false
276 bool MACbSoftwareReset(struct vnt_private *priv)
278 void __iomem *io_base = priv->PortOffset;
281 /* turn on HOSTCR_SOFTRST, just write 0x01 to reset */
282 iowrite8(0x01, io_base + MAC_REG_HOSTCR);
284 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
285 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_SOFTRST))
288 if (ww == W_MAX_TIMEOUT)
295 * save some important register's value, then do reset, then restore
300 * io_base - Base Address for MAC
304 * Return Value: true if success; otherwise false
307 bool MACbSafeSoftwareReset(struct vnt_private *priv)
309 unsigned char abyTmpRegData[MAC_MAX_CONTEXT_SIZE_PAGE0 + MAC_MAX_CONTEXT_SIZE_PAGE1];
313 * save some important register's value, then do
314 * reset, then restore register's value
316 /* save MAC context */
317 MACvSaveContext(priv, abyTmpRegData);
319 bRetVal = MACbSoftwareReset(priv);
320 /* restore MAC context, except CR0 */
321 MACvRestoreContext(priv, abyTmpRegData);
332 * io_base - Base Address for MAC
336 * Return Value: true if success; otherwise false
339 bool MACbSafeRxOff(struct vnt_private *priv)
341 void __iomem *io_base = priv->PortOffset;
344 /* turn off wow temp for turn off Rx safely */
346 /* Clear RX DMA0,1 */
347 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL0);
348 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_RXDMACTL1);
349 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
350 if (!(ioread32(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
353 if (ww == W_MAX_TIMEOUT) {
354 pr_debug(" DBG_PORT80(0x10)\n");
357 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
358 if (!(ioread32(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
361 if (ww == W_MAX_TIMEOUT) {
362 pr_debug(" DBG_PORT80(0x11)\n");
366 /* try to safe shutdown RX */
367 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_RXON);
368 /* W_MAX_TIMEOUT is the timeout period */
369 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
370 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_RXONST))
373 if (ww == W_MAX_TIMEOUT) {
374 pr_debug(" DBG_PORT80(0x12)\n");
386 * io_base - Base Address for MAC
390 * Return Value: true if success; otherwise false
393 bool MACbSafeTxOff(struct vnt_private *priv)
395 void __iomem *io_base = priv->PortOffset;
400 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_TXDMACTL0);
402 iowrite32(DMACTL_CLRRUN, io_base + MAC_REG_AC0DMACTL);
404 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
405 if (!(ioread32(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
408 if (ww == W_MAX_TIMEOUT) {
409 pr_debug(" DBG_PORT80(0x20)\n");
412 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
413 if (!(ioread32(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
416 if (ww == W_MAX_TIMEOUT) {
417 pr_debug(" DBG_PORT80(0x21)\n");
421 /* try to safe shutdown TX */
422 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_TXON);
424 /* W_MAX_TIMEOUT is the timeout period */
425 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
426 if (!(ioread8(io_base + MAC_REG_HOSTCR) & HOSTCR_TXONST))
429 if (ww == W_MAX_TIMEOUT) {
430 pr_debug(" DBG_PORT80(0x24)\n");
442 * io_base - Base Address for MAC
446 * Return Value: true if success; otherwise false
449 bool MACbSafeStop(struct vnt_private *priv)
451 void __iomem *io_base = priv->PortOffset;
453 MACvRegBitsOff(io_base, MAC_REG_TCR, TCR_AUTOBCNTX);
455 if (!MACbSafeRxOff(priv)) {
456 pr_debug(" MACbSafeRxOff == false)\n");
457 MACbSafeSoftwareReset(priv);
460 if (!MACbSafeTxOff(priv)) {
461 pr_debug(" MACbSafeTxOff == false)\n");
462 MACbSafeSoftwareReset(priv);
466 MACvRegBitsOff(io_base, MAC_REG_HOSTCR, HOSTCR_MACEN);
477 * io_base - Base Address for MAC
481 * Return Value: true if success; otherwise false
484 bool MACbShutdown(struct vnt_private *priv)
486 void __iomem *io_base = priv->PortOffset;
487 /* disable MAC IMR */
488 MACvIntDisable(io_base);
489 MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
490 /* stop the adapter */
491 if (!MACbSafeStop(priv)) {
492 MACvSetLoopbackMode(priv, MAC_LB_NONE);
495 MACvSetLoopbackMode(priv, MAC_LB_NONE);
505 * io_base - Base Address for MAC
512 void MACvInitialize(struct vnt_private *priv)
514 void __iomem *io_base = priv->PortOffset;
515 /* clear sticky bits */
516 MACvClearStckDS(io_base);
517 /* disable force PME-enable */
518 iowrite8(PME_OVR, io_base + MAC_REG_PMC1);
522 MACbSoftwareReset(priv);
524 /* reset TSF counter */
525 iowrite8(TFTCTL_TSFCNTRST, io_base + MAC_REG_TFTCTL);
526 /* enable TSF counter */
527 iowrite8(TFTCTL_TSFCNTREN, io_base + MAC_REG_TFTCTL);
532 * Set the chip with current rx descriptor address
536 * io_base - Base Address for MAC
537 * curr_desc_addr - Descriptor Address
544 void MACvSetCurrRx0DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
546 void __iomem *io_base = priv->PortOffset;
548 unsigned char org_dma_ctl;
550 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL0);
551 if (org_dma_ctl & DMACTL_RUN)
552 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0 + 2);
554 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
555 if (!(ioread8(io_base + MAC_REG_RXDMACTL0) & DMACTL_RUN))
559 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR0);
560 if (org_dma_ctl & DMACTL_RUN)
561 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL0);
566 * Set the chip with current rx descriptor address
570 * io_base - Base Address for MAC
571 * curr_desc_addr - Descriptor Address
578 void MACvSetCurrRx1DescAddr(struct vnt_private *priv, u32 curr_desc_addr)
580 void __iomem *io_base = priv->PortOffset;
582 unsigned char org_dma_ctl;
584 org_dma_ctl = ioread8(io_base + MAC_REG_RXDMACTL1);
585 if (org_dma_ctl & DMACTL_RUN)
586 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1 + 2);
588 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
589 if (!(ioread8(io_base + MAC_REG_RXDMACTL1) & DMACTL_RUN))
593 iowrite32(curr_desc_addr, io_base + MAC_REG_RXDMAPTR1);
594 if (org_dma_ctl & DMACTL_RUN)
595 iowrite8(DMACTL_RUN, io_base + MAC_REG_RXDMACTL1);
601 * Set the chip with current tx0 descriptor address
605 * io_base - Base Address for MAC
606 * curr_desc_addr - Descriptor Address
613 void MACvSetCurrTx0DescAddrEx(struct vnt_private *priv,
616 void __iomem *io_base = priv->PortOffset;
618 unsigned char org_dma_ctl;
620 org_dma_ctl = ioread8(io_base + MAC_REG_TXDMACTL0);
621 if (org_dma_ctl & DMACTL_RUN)
622 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0 + 2);
624 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
625 if (!(ioread8(io_base + MAC_REG_TXDMACTL0) & DMACTL_RUN))
629 iowrite32(curr_desc_addr, io_base + MAC_REG_TXDMAPTR0);
630 if (org_dma_ctl & DMACTL_RUN)
631 iowrite8(DMACTL_RUN, io_base + MAC_REG_TXDMACTL0);
636 * Set the chip with current AC0 descriptor address
640 * io_base - Base Address for MAC
641 * curr_desc_addr - Descriptor Address
648 /* TxDMA1 = AC0DMA */
649 void MACvSetCurrAC0DescAddrEx(struct vnt_private *priv,
652 void __iomem *io_base = priv->PortOffset;
654 unsigned char org_dma_ctl;
656 org_dma_ctl = ioread8(io_base + MAC_REG_AC0DMACTL);
657 if (org_dma_ctl & DMACTL_RUN)
658 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL + 2);
660 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
661 if (!(ioread8(io_base + MAC_REG_AC0DMACTL) & DMACTL_RUN))
664 if (ww == W_MAX_TIMEOUT)
665 pr_debug(" DBG_PORT80(0x26)\n");
666 iowrite32(curr_desc_addr, io_base + MAC_REG_AC0DMAPTR);
667 if (org_dma_ctl & DMACTL_RUN)
668 iowrite8(DMACTL_RUN, io_base + MAC_REG_AC0DMACTL);
671 void MACvSetCurrTXDescAddr(int iTxType, struct vnt_private *priv,
674 if (iTxType == TYPE_AC0DMA)
675 MACvSetCurrAC0DescAddrEx(priv, curr_desc_addr);
676 else if (iTxType == TYPE_TXDMA0)
677 MACvSetCurrTx0DescAddrEx(priv, curr_desc_addr);
682 * Micro Second Delay via MAC
686 * io_base - Base Address for MAC
687 * uDelay - Delay time (timer resolution is 4 us)
694 void MACvTimer0MicroSDelay(struct vnt_private *priv, unsigned int uDelay)
696 void __iomem *io_base = priv->PortOffset;
697 unsigned char byValue;
700 iowrite8(0, io_base + MAC_REG_TMCTL0);
701 iowrite32(uDelay, io_base + MAC_REG_TMDATA0);
702 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL0);
703 for (ii = 0; ii < 66; ii++) { /* assume max PCI clock is 66Mhz */
704 for (uu = 0; uu < uDelay; uu++) {
705 byValue = ioread8(io_base + MAC_REG_TMCTL0);
706 if ((byValue == 0) ||
707 (byValue & TMCTL_TSUSP)) {
708 iowrite8(0, io_base + MAC_REG_TMCTL0);
713 iowrite8(0, io_base + MAC_REG_TMCTL0);
718 * Micro Second One shot timer via MAC
722 * io_base - Base Address for MAC
723 * uDelay - Delay time
730 void MACvOneShotTimer1MicroSec(struct vnt_private *priv,
731 unsigned int uDelayTime)
733 void __iomem *io_base = priv->PortOffset;
735 iowrite8(0, io_base + MAC_REG_TMCTL1);
736 iowrite32(uDelayTime, io_base + MAC_REG_TMDATA1);
737 iowrite8((TMCTL_TMD | TMCTL_TE), io_base + MAC_REG_TMCTL1);
740 void MACvSetMISCFifo(struct vnt_private *priv, unsigned short offset,
743 void __iomem *io_base = priv->PortOffset;
747 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
748 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
749 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
752 bool MACbPSWakeup(struct vnt_private *priv)
754 void __iomem *io_base = priv->PortOffset;
757 if (MACbIsRegBitsOff(priv, MAC_REG_PSCTL, PSCTL_PS))
761 MACvRegBitsOff(io_base, MAC_REG_PSCTL, PSCTL_PSEN);
763 /* Check if SyncFlushOK */
764 for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {
765 if (ioread8(io_base + MAC_REG_PSCTL) & PSCTL_WAKEDONE)
768 if (ww == W_MAX_TIMEOUT) {
769 pr_debug(" DBG_PORT80(0x33)\n");
777 * Set the Key by MISCFIFO
781 * io_base - Base Address for MAC
790 void MACvSetKeyEntry(struct vnt_private *priv, unsigned short wKeyCtl,
791 unsigned int uEntryIdx, unsigned int uKeyIdx,
792 unsigned char *pbyAddr, u32 *pdwKey,
793 unsigned char byLocalID)
795 void __iomem *io_base = priv->PortOffset;
796 unsigned short offset;
803 pr_debug("%s\n", __func__);
804 offset = MISCFIFO_KEYETRY0;
805 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
810 data |= MAKEWORD(*(pbyAddr + 4), *(pbyAddr + 5));
811 pr_debug("1. offset: %d, Data: %X, KeyCtl:%X\n",
812 offset, data, wKeyCtl);
814 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
815 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
816 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
820 data |= *(pbyAddr + 3);
822 data |= *(pbyAddr + 2);
824 data |= *(pbyAddr + 1);
827 pr_debug("2. offset: %d, Data: %X\n", offset, data);
829 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
830 iowrite32(data, io_base + MAC_REG_MISCFFDATA);
831 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
834 offset += (uKeyIdx * 4);
835 for (ii = 0; ii < 4; ii++) {
836 /* always push 128 bits */
837 pr_debug("3.(%d) offset: %d, Data: %X\n",
838 ii, offset + ii, *pdwKey);
839 iowrite16(offset + ii, io_base + MAC_REG_MISCFFNDEX);
840 iowrite32(*pdwKey++, io_base + MAC_REG_MISCFFDATA);
841 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);
847 * Disable the Key Entry by MISCFIFO
851 * io_base - Base Address for MAC
859 void MACvDisableKeyEntry(struct vnt_private *priv, unsigned int uEntryIdx)
861 void __iomem *io_base = priv->PortOffset;
862 unsigned short offset;
864 offset = MISCFIFO_KEYETRY0;
865 offset += (uEntryIdx * MISCFIFO_KEYENTRYSIZE);
867 iowrite16(offset, io_base + MAC_REG_MISCFFNDEX);
868 iowrite32(0, io_base + MAC_REG_MISCFFDATA);
869 iowrite16(MISCFFCTL_WRITE, io_base + MAC_REG_MISCFFCTL);