2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
154 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
155 UPCI_AIOP_INTR_BIT_0,
156 UPCI_AIOP_INTR_BIT_1,
157 UPCI_AIOP_INTR_BIT_2,
162 static Byte_t RData[RDATASIZE] = {
163 0x00, 0x09, 0xf6, 0x82,
164 0x02, 0x09, 0x86, 0xfb,
165 0x04, 0x09, 0x00, 0x0a,
166 0x06, 0x09, 0x01, 0x0a,
167 0x08, 0x09, 0x8a, 0x13,
168 0x0a, 0x09, 0xc5, 0x11,
169 0x0c, 0x09, 0x86, 0x85,
170 0x0e, 0x09, 0x20, 0x0a,
171 0x10, 0x09, 0x21, 0x0a,
172 0x12, 0x09, 0x41, 0xff,
173 0x14, 0x09, 0x82, 0x00,
174 0x16, 0x09, 0x82, 0x7b,
175 0x18, 0x09, 0x8a, 0x7d,
176 0x1a, 0x09, 0x88, 0x81,
177 0x1c, 0x09, 0x86, 0x7a,
178 0x1e, 0x09, 0x84, 0x81,
179 0x20, 0x09, 0x82, 0x7c,
180 0x22, 0x09, 0x0a, 0x0a
183 static Byte_t RRegData[RREGDATASIZE] = {
184 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
185 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
186 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
187 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
188 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
189 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
190 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
191 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
192 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
193 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
194 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
195 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
196 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
199 static CONTROLLER_T sController[CTL_SIZE] = {
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
206 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
207 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
210 static Byte_t sBitMapClrTbl[8] = {
211 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
214 static Byte_t sBitMapSetTbl[8] = {
215 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
218 static int sClockPrescale = 0x14;
221 * Line number is the ttySIx number (x), the Minor number. We
222 * assign them sequentially, starting at zero. The following
223 * array keeps track of the line number assigned to a given board/aiop/channel.
225 static unsigned char lineNumbers[MAX_RP_PORTS];
226 static unsigned long nextLineNumber;
228 /***** RocketPort Static Prototypes *********/
229 static int __init init_ISA(int i);
230 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
231 static void rp_flush_buffer(struct tty_struct *tty);
232 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
233 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
234 static void rp_start(struct tty_struct *tty);
235 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
237 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
238 static void sFlushRxFIFO(CHANNEL_T * ChP);
239 static void sFlushTxFIFO(CHANNEL_T * ChP);
240 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
242 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
244 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
245 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
246 ByteIO_t * AiopIOList, int AiopIOListSize,
247 int IRQNum, Byte_t Frequency, int PeriodicOnly);
248 static int sReadAiopID(ByteIO_t io);
249 static int sReadAiopNumChan(WordIO_t io);
251 MODULE_AUTHOR("Theodore Ts'o");
252 MODULE_DESCRIPTION("Comtrol RocketPort driver");
253 module_param(board1, ulong, 0);
254 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
255 module_param(board2, ulong, 0);
256 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
257 module_param(board3, ulong, 0);
258 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
259 module_param(board4, ulong, 0);
260 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
261 module_param(controller, ulong, 0);
262 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
263 module_param(support_low_speed, bool, 0);
264 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
265 module_param(modem1, ulong, 0);
266 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
267 module_param(modem2, ulong, 0);
268 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
269 module_param(modem3, ulong, 0);
270 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
271 module_param(modem4, ulong, 0);
272 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
273 module_param_array(pc104_1, ulong, NULL, 0);
274 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
275 module_param_array(pc104_2, ulong, NULL, 0);
276 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
277 module_param_array(pc104_3, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
279 module_param_array(pc104_4, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
282 static int __init rp_init(void);
283 static void rp_cleanup_module(void);
285 module_init(rp_init);
286 module_exit(rp_cleanup_module);
289 MODULE_LICENSE("Dual BSD/GPL");
291 /*************************************************************************/
292 /* Module code starts here */
294 static inline int rocket_paranoia_check(struct r_port *info,
297 #ifdef ROCKET_PARANOIA_CHECK
300 if (info->magic != RPORT_MAGIC) {
301 printk(KERN_WARNING "Warning: bad magic number for rocketport "
302 "struct in %s\n", routine);
310 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
311 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
314 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
315 unsigned int ChanStatus)
317 unsigned int CharNStat;
318 int ToRecv, wRecv, space;
321 ToRecv = sGetRxCnt(cp);
322 #ifdef ROCKET_DEBUG_INTR
323 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
329 * if status indicates there are errored characters in the
330 * FIFO, then enter status mode (a word in FIFO holds
331 * character and status).
333 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
334 if (!(ChanStatus & STATMODE)) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Entering STATMODE...\n");
338 ChanStatus |= STATMODE;
344 * if we previously entered status mode, then read down the
345 * FIFO one word at a time, pulling apart the character and
346 * the status. Update error counters depending on status
348 if (ChanStatus & STATMODE) {
349 #ifdef ROCKET_DEBUG_RECEIVE
350 printk(KERN_INFO "Ignore %x, read %x...\n",
351 info->ignore_status_mask, info->read_status_mask);
356 CharNStat = sInW(sGetTxRxDataIO(cp));
357 #ifdef ROCKET_DEBUG_RECEIVE
358 printk(KERN_INFO "%x...\n", CharNStat);
360 if (CharNStat & STMBREAKH)
361 CharNStat &= ~(STMFRAMEH | STMPARITYH);
362 if (CharNStat & info->ignore_status_mask) {
366 CharNStat &= info->read_status_mask;
367 if (CharNStat & STMBREAKH)
369 else if (CharNStat & STMPARITYH)
371 else if (CharNStat & STMFRAMEH)
373 else if (CharNStat & STMRCVROVRH)
377 tty_insert_flip_char(&info->port, CharNStat & 0xff,
383 * after we've emptied the FIFO in status mode, turn
384 * status mode back off
386 if (sGetRxCnt(cp) == 0) {
387 #ifdef ROCKET_DEBUG_RECEIVE
388 printk(KERN_INFO "Status mode off.\n");
390 sDisRxStatusMode(cp);
394 * we aren't in status mode, so read down the FIFO two
395 * characters at time by doing repeated word IO
398 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
399 if (space < ToRecv) {
400 #ifdef ROCKET_DEBUG_RECEIVE
401 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
409 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
411 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
413 /* Push the data up to the tty layer */
414 tty_flip_buffer_push(&info->port);
418 * Serial port transmit data function. Called from the timer polling loop as a
419 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
420 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
421 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
423 static void rp_do_transmit(struct r_port *info)
426 CHANNEL_t *cp = &info->channel;
427 struct tty_struct *tty;
430 #ifdef ROCKET_DEBUG_INTR
431 printk(KERN_DEBUG "%s\n", __func__);
435 tty = tty_port_tty_get(&info->port);
438 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
439 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
443 spin_lock_irqsave(&info->slock, flags);
444 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
446 /* Loop sending data to FIFO until done or FIFO full */
450 c = min(info->xmit_fifo_room, info->xmit_cnt);
451 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
452 if (c <= 0 || info->xmit_fifo_room <= 0)
454 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
456 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
457 info->xmit_tail += c;
458 info->xmit_tail &= XMIT_BUF_SIZE - 1;
460 info->xmit_fifo_room -= c;
461 #ifdef ROCKET_DEBUG_INTR
462 printk(KERN_INFO "tx %d chars...\n", c);
466 if (info->xmit_cnt == 0)
467 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
469 if (info->xmit_cnt < WAKEUP_CHARS) {
471 #ifdef ROCKETPORT_HAVE_POLL_WAIT
472 wake_up_interruptible(&tty->poll_wait);
476 spin_unlock_irqrestore(&info->slock, flags);
479 #ifdef ROCKET_DEBUG_INTR
480 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
481 info->xmit_tail, info->xmit_fifo_room);
486 * Called when a serial port signals it has read data in it's RX FIFO.
487 * It checks what interrupts are pending and services them, including
488 * receiving serial data.
490 static void rp_handle_port(struct r_port *info)
493 unsigned int IntMask, ChanStatus;
498 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
499 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
500 "info->flags & NOT_INIT\n");
506 IntMask = sGetChanIntID(cp) & info->intmask;
507 #ifdef ROCKET_DEBUG_INTR
508 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
510 ChanStatus = sGetChanStatus(cp);
511 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
512 rp_do_receive(info, cp, ChanStatus);
514 if (IntMask & DELTA_CD) { /* CD change */
515 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
516 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
517 (ChanStatus & CD_ACT) ? "on" : "off");
519 if (!(ChanStatus & CD_ACT) && info->cd_status) {
520 #ifdef ROCKET_DEBUG_HANGUP
521 printk(KERN_INFO "CD drop, calling hangup.\n");
523 tty_port_tty_hangup(&info->port, false);
525 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
526 wake_up_interruptible(&info->port.open_wait);
528 #ifdef ROCKET_DEBUG_INTR
529 if (IntMask & DELTA_CTS) { /* CTS change */
530 printk(KERN_INFO "CTS change...\n");
532 if (IntMask & DELTA_DSR) { /* DSR change */
533 printk(KERN_INFO "DSR change...\n");
539 * The top level polling routine. Repeats every 1/100 HZ (10ms).
541 static void rp_do_poll(unsigned long dummy)
544 int ctrl, aiop, ch, line;
545 unsigned int xmitmask, i;
546 unsigned int CtlMask;
547 unsigned char AiopMask;
550 /* Walk through all the boards (ctrl's) */
551 for (ctrl = 0; ctrl < max_board; ctrl++) {
552 if (rcktpt_io_addr[ctrl] <= 0)
555 /* Get a ptr to the board's control struct */
556 ctlp = sCtlNumToCtlPtr(ctrl);
558 /* Get the interrupt status from the board */
560 if (ctlp->BusType == isPCI)
561 CtlMask = sPCIGetControllerIntStatus(ctlp);
564 CtlMask = sGetControllerIntStatus(ctlp);
566 /* Check if any AIOP read bits are set */
567 for (aiop = 0; CtlMask; aiop++) {
568 bit = ctlp->AiopIntrBits[aiop];
571 AiopMask = sGetAiopIntStatus(ctlp, aiop);
573 /* Check if any port read bits are set */
574 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
577 /* Get the line number (/dev/ttyRx number). */
578 /* Read the data from the port. */
579 line = GetLineNumber(ctrl, aiop, ch);
580 rp_handle_port(rp_table[line]);
586 xmitmask = xmit_flags[ctrl];
589 * xmit_flags contains bit-significant flags, indicating there is data
590 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
591 * 1, ... (32 total possible). The variable i has the aiop and ch
592 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
595 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
596 if (xmitmask & (1 << i)) {
597 aiop = (i & 0x18) >> 3;
599 line = GetLineNumber(ctrl, aiop, ch);
600 rp_do_transmit(rp_table[line]);
607 * Reset the timer so we get called at the next clock tick (10ms).
609 if (atomic_read(&rp_num_ports_open))
610 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
614 * Initializes the r_port structure for a port, as well as enabling the port on
616 * Inputs: board, aiop, chan numbers
618 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
625 /* Get the next available line number */
626 line = SetLineNumber(board, aiop, chan);
628 ctlp = sCtlNumToCtlPtr(board);
630 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
631 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
633 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
638 info->magic = RPORT_MAGIC;
644 tty_port_init(&info->port);
645 info->port.ops = &rocket_port_ops;
646 init_completion(&info->close_wait);
647 info->flags &= ~ROCKET_MODE_MASK;
648 if (board < ARRAY_SIZE(pc104) && line < ARRAY_SIZE(pc104_1))
649 switch (pc104[board][line]) {
651 info->flags |= ROCKET_MODE_RS422;
654 info->flags |= ROCKET_MODE_RS485;
658 info->flags |= ROCKET_MODE_RS232;
662 info->flags |= ROCKET_MODE_RS232;
664 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
665 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
666 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
668 tty_port_destroy(&info->port);
673 rocketMode = info->flags & ROCKET_MODE_MASK;
675 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
676 sEnRTSToggle(&info->channel);
678 sDisRTSToggle(&info->channel);
680 if (ctlp->boardType == ROCKET_TYPE_PC104) {
681 switch (rocketMode) {
682 case ROCKET_MODE_RS485:
683 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
685 case ROCKET_MODE_RS422:
686 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
688 case ROCKET_MODE_RS232:
690 if (info->flags & ROCKET_RTS_TOGGLE)
691 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
693 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
697 spin_lock_init(&info->slock);
698 mutex_init(&info->write_mtx);
699 rp_table[line] = info;
700 tty_port_register_device(&info->port, rocket_driver, line,
701 pci_dev ? &pci_dev->dev : NULL);
705 * Configures a rocketport port according to its termio settings. Called from
706 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
708 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
709 struct ktermios *old_termios)
714 int bits, baud, divisor;
716 struct ktermios *t = &tty->termios;
721 /* Byte size and parity */
722 if ((cflag & CSIZE) == CS8) {
729 if (cflag & CSTOPB) {
736 if (cflag & PARENB) {
739 if (cflag & PARODD) {
749 baud = tty_get_baud_rate(tty);
752 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
753 if ((divisor >= 8192 || divisor < 0) && old_termios) {
754 baud = tty_termios_baud_rate(old_termios);
757 divisor = (rp_baud_base[info->board] / baud) - 1;
759 if (divisor >= 8192 || divisor < 0) {
761 divisor = (rp_baud_base[info->board] / baud) - 1;
763 info->cps = baud / bits;
764 sSetBaud(cp, divisor);
766 /* FIXME: Should really back compute a baud rate from the divisor */
767 tty_encode_baud_rate(tty, baud, baud);
769 if (cflag & CRTSCTS) {
770 info->intmask |= DELTA_CTS;
773 info->intmask &= ~DELTA_CTS;
776 if (cflag & CLOCAL) {
777 info->intmask &= ~DELTA_CD;
779 spin_lock_irqsave(&info->slock, flags);
780 if (sGetChanStatus(cp) & CD_ACT)
784 info->intmask |= DELTA_CD;
785 spin_unlock_irqrestore(&info->slock, flags);
789 * Handle software flow control in the board
791 #ifdef ROCKET_SOFT_FLOW
793 sEnTxSoftFlowCtl(cp);
799 sSetTxXONChar(cp, START_CHAR(tty));
800 sSetTxXOFFChar(cp, STOP_CHAR(tty));
802 sDisTxSoftFlowCtl(cp);
809 * Set up ignore/read mask words
811 info->read_status_mask = STMRCVROVRH | 0xFF;
813 info->read_status_mask |= STMFRAMEH | STMPARITYH;
814 if (I_BRKINT(tty) || I_PARMRK(tty))
815 info->read_status_mask |= STMBREAKH;
818 * Characters to ignore
820 info->ignore_status_mask = 0;
822 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
824 info->ignore_status_mask |= STMBREAKH;
826 * If we're ignoring parity and break indicators,
827 * ignore overruns too. (For real raw support).
830 info->ignore_status_mask |= STMRCVROVRH;
833 rocketMode = info->flags & ROCKET_MODE_MASK;
835 if ((info->flags & ROCKET_RTS_TOGGLE)
836 || (rocketMode == ROCKET_MODE_RS485))
841 sSetRTS(&info->channel);
843 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
844 switch (rocketMode) {
845 case ROCKET_MODE_RS485:
846 sSetInterfaceMode(cp, InterfaceModeRS485);
848 case ROCKET_MODE_RS422:
849 sSetInterfaceMode(cp, InterfaceModeRS422);
851 case ROCKET_MODE_RS232:
853 if (info->flags & ROCKET_RTS_TOGGLE)
854 sSetInterfaceMode(cp, InterfaceModeRS232T);
856 sSetInterfaceMode(cp, InterfaceModeRS232);
862 static int carrier_raised(struct tty_port *port)
864 struct r_port *info = container_of(port, struct r_port, port);
865 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
868 static void dtr_rts(struct tty_port *port, int on)
870 struct r_port *info = container_of(port, struct r_port, port);
872 sSetDTR(&info->channel);
873 sSetRTS(&info->channel);
875 sClrDTR(&info->channel);
876 sClrRTS(&info->channel);
881 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
882 * port's r_port struct. Initializes the port hardware.
884 static int rp_open(struct tty_struct *tty, struct file *filp)
887 struct tty_port *port;
892 info = rp_table[tty->index];
897 page = __get_free_page(GFP_KERNEL);
902 * We must not sleep from here until the port is marked fully in use.
907 info->xmit_buf = (unsigned char *) page;
909 tty->driver_data = info;
910 tty_port_tty_set(port, tty);
912 if (port->count++ == 0) {
913 atomic_inc(&rp_num_ports_open);
915 #ifdef ROCKET_DEBUG_OPEN
916 printk(KERN_INFO "rocket mod++ = %d...\n",
917 atomic_read(&rp_num_ports_open));
920 #ifdef ROCKET_DEBUG_OPEN
921 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
925 * Info->count is now 1; so it's safe to sleep now.
927 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
929 sSetRxTrigger(cp, TRIG_1);
930 if (sGetChanStatus(cp) & CD_ACT)
934 sDisRxStatusMode(cp);
938 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
939 sSetRxTrigger(cp, TRIG_1);
942 sDisRxStatusMode(cp);
946 sDisTxSoftFlowCtl(cp);
951 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
954 * Set up the tty->alt_speed kludge
956 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
957 tty->alt_speed = 57600;
958 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
959 tty->alt_speed = 115200;
960 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
961 tty->alt_speed = 230400;
962 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
963 tty->alt_speed = 460800;
965 configure_r_port(tty, info, NULL);
966 if (tty->termios.c_cflag & CBAUD) {
971 /* Starts (or resets) the maint polling loop */
972 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
974 retval = tty_port_block_til_ready(port, tty, filp);
976 #ifdef ROCKET_DEBUG_OPEN
977 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
985 * Exception handler that closes a serial port. info->port.count is considered critical.
987 static void rp_close(struct tty_struct *tty, struct file *filp)
989 struct r_port *info = tty->driver_data;
990 struct tty_port *port = &info->port;
994 if (rocket_paranoia_check(info, "rp_close"))
997 #ifdef ROCKET_DEBUG_OPEN
998 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1001 if (tty_port_close_start(port, tty, filp) == 0)
1004 mutex_lock(&port->mutex);
1005 cp = &info->channel;
1007 * Before we drop DTR, make sure the UART transmitter
1008 * has completely drained; this is especially
1009 * important if there is a transmit FIFO!
1011 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1014 rp_wait_until_sent(tty, timeout);
1015 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1018 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1020 sDisTxSoftFlowCtl(cp);
1028 rp_flush_buffer(tty);
1030 tty_ldisc_flush(tty);
1032 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1034 /* We can't yet use tty_port_close_end as the buffer handling in this
1035 driver is a bit different to the usual */
1037 if (port->blocked_open) {
1038 if (port->close_delay) {
1039 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1041 wake_up_interruptible(&port->open_wait);
1043 if (info->xmit_buf) {
1044 free_page((unsigned long) info->xmit_buf);
1045 info->xmit_buf = NULL;
1048 spin_lock_irq(&port->lock);
1049 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1051 spin_unlock_irq(&port->lock);
1052 mutex_unlock(&port->mutex);
1053 tty_port_tty_set(port, NULL);
1055 complete_all(&info->close_wait);
1056 atomic_dec(&rp_num_ports_open);
1058 #ifdef ROCKET_DEBUG_OPEN
1059 printk(KERN_INFO "rocket mod-- = %d...\n",
1060 atomic_read(&rp_num_ports_open));
1061 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1066 static void rp_set_termios(struct tty_struct *tty,
1067 struct ktermios *old_termios)
1069 struct r_port *info = tty->driver_data;
1073 if (rocket_paranoia_check(info, "rp_set_termios"))
1076 cflag = tty->termios.c_cflag;
1079 * This driver doesn't support CS5 or CS6
1081 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1082 tty->termios.c_cflag =
1083 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1085 tty->termios.c_cflag &= ~CMSPAR;
1087 configure_r_port(tty, info, old_termios);
1089 cp = &info->channel;
1091 /* Handle transition to B0 status */
1092 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1097 /* Handle transition away from B0 status */
1098 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1103 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS))
1107 static int rp_break(struct tty_struct *tty, int break_state)
1109 struct r_port *info = tty->driver_data;
1110 unsigned long flags;
1112 if (rocket_paranoia_check(info, "rp_break"))
1115 spin_lock_irqsave(&info->slock, flags);
1116 if (break_state == -1)
1117 sSendBreak(&info->channel);
1119 sClrBreak(&info->channel);
1120 spin_unlock_irqrestore(&info->slock, flags);
1125 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1126 * the UPCI boards was added, it was decided to make this a function because
1127 * the macro was getting too complicated. All cases except the first one
1128 * (UPCIRingInd) are taken directly from the original macro.
1130 static int sGetChanRI(CHANNEL_T * ChP)
1132 CONTROLLER_t *CtlP = ChP->CtlP;
1133 int ChanNum = ChP->ChanNum;
1136 if (CtlP->UPCIRingInd)
1137 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1138 else if (CtlP->AltChanRingIndicator)
1139 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1140 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1141 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1146 /********************************************************************************************/
1147 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1150 * Returns the state of the serial modem control lines. These next 2 functions
1151 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1153 static int rp_tiocmget(struct tty_struct *tty)
1155 struct r_port *info = tty->driver_data;
1156 unsigned int control, result, ChanStatus;
1158 ChanStatus = sGetChanStatusLo(&info->channel);
1159 control = info->channel.TxControl[3];
1160 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1161 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1162 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1163 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1164 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1165 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1171 * Sets the modem control lines
1173 static int rp_tiocmset(struct tty_struct *tty,
1174 unsigned int set, unsigned int clear)
1176 struct r_port *info = tty->driver_data;
1178 if (set & TIOCM_RTS)
1179 info->channel.TxControl[3] |= SET_RTS;
1180 if (set & TIOCM_DTR)
1181 info->channel.TxControl[3] |= SET_DTR;
1182 if (clear & TIOCM_RTS)
1183 info->channel.TxControl[3] &= ~SET_RTS;
1184 if (clear & TIOCM_DTR)
1185 info->channel.TxControl[3] &= ~SET_DTR;
1187 out32(info->channel.IndexAddr, info->channel.TxControl);
1191 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1193 struct rocket_config tmp;
1197 memset(&tmp, 0, sizeof (tmp));
1198 mutex_lock(&info->port.mutex);
1199 tmp.line = info->line;
1200 tmp.flags = info->flags;
1201 tmp.close_delay = info->port.close_delay;
1202 tmp.closing_wait = info->port.closing_wait;
1203 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1204 mutex_unlock(&info->port.mutex);
1206 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1211 static int set_config(struct tty_struct *tty, struct r_port *info,
1212 struct rocket_config __user *new_info)
1214 struct rocket_config new_serial;
1216 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1219 mutex_lock(&info->port.mutex);
1220 if (!capable(CAP_SYS_ADMIN))
1222 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1223 mutex_unlock(&info->port.mutex);
1226 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1227 configure_r_port(tty, info, NULL);
1228 mutex_unlock(&info->port.mutex);
1232 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1233 info->port.close_delay = new_serial.close_delay;
1234 info->port.closing_wait = new_serial.closing_wait;
1236 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1237 tty->alt_speed = 57600;
1238 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1239 tty->alt_speed = 115200;
1240 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1241 tty->alt_speed = 230400;
1242 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1243 tty->alt_speed = 460800;
1244 mutex_unlock(&info->port.mutex);
1246 configure_r_port(tty, info, NULL);
1251 * This function fills in a rocket_ports struct with information
1252 * about what boards/ports are in the system. This info is passed
1253 * to user space. See setrocket.c where the info is used to create
1254 * the /dev/ttyRx ports.
1256 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1258 struct rocket_ports tmp;
1263 memset(&tmp, 0, sizeof (tmp));
1264 tmp.tty_major = rocket_driver->major;
1266 for (board = 0; board < 4; board++) {
1267 tmp.rocketModel[board].model = rocketModel[board].model;
1268 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1269 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1270 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1271 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1273 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1278 static int reset_rm2(struct r_port *info, void __user *arg)
1282 if (!capable(CAP_SYS_ADMIN))
1285 if (copy_from_user(&reset, arg, sizeof (int)))
1290 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1291 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1294 if (info->ctlp->BusType == isISA)
1295 sModemReset(info->ctlp, info->chan, reset);
1297 sPCIModemReset(info->ctlp, info->chan, reset);
1302 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1304 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1309 /* IOCTL call handler into the driver */
1310 static int rp_ioctl(struct tty_struct *tty,
1311 unsigned int cmd, unsigned long arg)
1313 struct r_port *info = tty->driver_data;
1314 void __user *argp = (void __user *)arg;
1317 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1321 case RCKP_GET_STRUCT:
1322 if (copy_to_user(argp, info, sizeof (struct r_port)))
1325 case RCKP_GET_CONFIG:
1326 ret = get_config(info, argp);
1328 case RCKP_SET_CONFIG:
1329 ret = set_config(tty, info, argp);
1331 case RCKP_GET_PORTS:
1332 ret = get_ports(info, argp);
1334 case RCKP_RESET_RM2:
1335 ret = reset_rm2(info, argp);
1337 case RCKP_GET_VERSION:
1338 ret = get_version(info, argp);
1346 static void rp_send_xchar(struct tty_struct *tty, char ch)
1348 struct r_port *info = tty->driver_data;
1351 if (rocket_paranoia_check(info, "rp_send_xchar"))
1354 cp = &info->channel;
1356 sWriteTxPrioByte(cp, ch);
1358 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1361 static void rp_throttle(struct tty_struct *tty)
1363 struct r_port *info = tty->driver_data;
1365 #ifdef ROCKET_DEBUG_THROTTLE
1366 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1367 tty->ldisc.chars_in_buffer(tty));
1370 if (rocket_paranoia_check(info, "rp_throttle"))
1374 rp_send_xchar(tty, STOP_CHAR(tty));
1376 sClrRTS(&info->channel);
1379 static void rp_unthrottle(struct tty_struct *tty)
1381 struct r_port *info = tty->driver_data;
1382 #ifdef ROCKET_DEBUG_THROTTLE
1383 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1384 tty->ldisc.chars_in_buffer(tty));
1387 if (rocket_paranoia_check(info, "rp_unthrottle"))
1391 rp_send_xchar(tty, START_CHAR(tty));
1393 sSetRTS(&info->channel);
1397 * ------------------------------------------------------------
1398 * rp_stop() and rp_start()
1400 * This routines are called before setting or resetting tty->stopped.
1401 * They enable or disable transmitter interrupts, as necessary.
1402 * ------------------------------------------------------------
1404 static void rp_stop(struct tty_struct *tty)
1406 struct r_port *info = tty->driver_data;
1408 #ifdef ROCKET_DEBUG_FLOW
1409 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1410 info->xmit_cnt, info->xmit_fifo_room);
1413 if (rocket_paranoia_check(info, "rp_stop"))
1416 if (sGetTxCnt(&info->channel))
1417 sDisTransmit(&info->channel);
1420 static void rp_start(struct tty_struct *tty)
1422 struct r_port *info = tty->driver_data;
1424 #ifdef ROCKET_DEBUG_FLOW
1425 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1426 info->xmit_cnt, info->xmit_fifo_room);
1429 if (rocket_paranoia_check(info, "rp_stop"))
1432 sEnTransmit(&info->channel);
1433 set_bit((info->aiop * 8) + info->chan,
1434 (void *) &xmit_flags[info->board]);
1438 * rp_wait_until_sent() --- wait until the transmitter is empty
1440 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1442 struct r_port *info = tty->driver_data;
1444 unsigned long orig_jiffies;
1445 int check_time, exit_time;
1448 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1451 cp = &info->channel;
1453 orig_jiffies = jiffies;
1454 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1455 printk(KERN_INFO "In %s(%d) (jiff=%lu)...\n", __func__, timeout,
1457 printk(KERN_INFO "cps=%d...\n", info->cps);
1460 txcnt = sGetTxCnt(cp);
1462 if (sGetChanStatusLo(cp) & TXSHRMT)
1464 check_time = (HZ / info->cps) / 5;
1466 check_time = HZ * txcnt / info->cps;
1469 exit_time = orig_jiffies + timeout - jiffies;
1472 if (exit_time < check_time)
1473 check_time = exit_time;
1475 if (check_time == 0)
1477 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1478 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1479 jiffies, check_time);
1481 msleep_interruptible(jiffies_to_msecs(check_time));
1482 if (signal_pending(current))
1485 __set_current_state(TASK_RUNNING);
1486 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1487 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1492 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1494 static void rp_hangup(struct tty_struct *tty)
1497 struct r_port *info = tty->driver_data;
1498 unsigned long flags;
1500 if (rocket_paranoia_check(info, "rp_hangup"))
1503 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1504 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1506 rp_flush_buffer(tty);
1507 spin_lock_irqsave(&info->port.lock, flags);
1508 if (info->port.count)
1509 atomic_dec(&rp_num_ports_open);
1510 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1511 spin_unlock_irqrestore(&info->port.lock, flags);
1513 tty_port_hangup(&info->port);
1515 cp = &info->channel;
1518 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1520 sDisTxSoftFlowCtl(cp);
1522 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1524 wake_up_interruptible(&info->port.open_wait);
1528 * Exception handler - write char routine. The RocketPort driver uses a
1529 * double-buffering strategy, with the twist that if the in-memory CPU
1530 * buffer is empty, and there's space in the transmit FIFO, the
1531 * writing routines will write directly to transmit FIFO.
1532 * Write buffer and counters protected by spinlocks
1534 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1536 struct r_port *info = tty->driver_data;
1538 unsigned long flags;
1540 if (rocket_paranoia_check(info, "rp_put_char"))
1544 * Grab the port write mutex, locking out other processes that try to
1545 * write to this port
1547 mutex_lock(&info->write_mtx);
1549 #ifdef ROCKET_DEBUG_WRITE
1550 printk(KERN_INFO "rp_put_char %c...\n", ch);
1553 spin_lock_irqsave(&info->slock, flags);
1554 cp = &info->channel;
1556 if (!tty->stopped && info->xmit_fifo_room == 0)
1557 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1559 if (tty->stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1560 info->xmit_buf[info->xmit_head++] = ch;
1561 info->xmit_head &= XMIT_BUF_SIZE - 1;
1563 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1565 sOutB(sGetTxRxDataIO(cp), ch);
1566 info->xmit_fifo_room--;
1568 spin_unlock_irqrestore(&info->slock, flags);
1569 mutex_unlock(&info->write_mtx);
1574 * Exception handler - write routine, called when user app writes to the device.
1575 * A per port write mutex is used to protect from another process writing to
1576 * this port at the same time. This other process could be running on the other CPU
1577 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1578 * Spinlocks protect the info xmit members.
1580 static int rp_write(struct tty_struct *tty,
1581 const unsigned char *buf, int count)
1583 struct r_port *info = tty->driver_data;
1585 const unsigned char *b;
1587 unsigned long flags;
1589 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1592 if (mutex_lock_interruptible(&info->write_mtx))
1593 return -ERESTARTSYS;
1595 #ifdef ROCKET_DEBUG_WRITE
1596 printk(KERN_INFO "rp_write %d chars...\n", count);
1598 cp = &info->channel;
1600 if (!tty->stopped && info->xmit_fifo_room < count)
1601 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1604 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1605 * into FIFO. Use the write queue for temp storage.
1607 if (!tty->stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1608 c = min(count, info->xmit_fifo_room);
1611 /* Push data into FIFO, 2 bytes at a time */
1612 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1614 /* If there is a byte remaining, write it */
1616 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1622 spin_lock_irqsave(&info->slock, flags);
1623 info->xmit_fifo_room -= c;
1624 spin_unlock_irqrestore(&info->slock, flags);
1627 /* If count is zero, we wrote it all and are done */
1631 /* Write remaining data into the port's xmit_buf */
1634 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1636 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1637 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1642 memcpy(info->xmit_buf + info->xmit_head, b, c);
1644 spin_lock_irqsave(&info->slock, flags);
1646 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1647 info->xmit_cnt += c;
1648 spin_unlock_irqrestore(&info->slock, flags);
1655 if ((retval > 0) && !tty->stopped)
1656 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1659 if (info->xmit_cnt < WAKEUP_CHARS) {
1661 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1662 wake_up_interruptible(&tty->poll_wait);
1665 mutex_unlock(&info->write_mtx);
1670 * Return the number of characters that can be sent. We estimate
1671 * only using the in-memory transmit buffer only, and ignore the
1672 * potential space in the transmit FIFO.
1674 static int rp_write_room(struct tty_struct *tty)
1676 struct r_port *info = tty->driver_data;
1679 if (rocket_paranoia_check(info, "rp_write_room"))
1682 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1685 #ifdef ROCKET_DEBUG_WRITE
1686 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1692 * Return the number of characters in the buffer. Again, this only
1693 * counts those characters in the in-memory transmit buffer.
1695 static int rp_chars_in_buffer(struct tty_struct *tty)
1697 struct r_port *info = tty->driver_data;
1699 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1702 #ifdef ROCKET_DEBUG_WRITE
1703 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1705 return info->xmit_cnt;
1709 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1710 * r_port struct for the port. Note that spinlock are used to protect info members,
1711 * do not call this function if the spinlock is already held.
1713 static void rp_flush_buffer(struct tty_struct *tty)
1715 struct r_port *info = tty->driver_data;
1717 unsigned long flags;
1719 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1722 spin_lock_irqsave(&info->slock, flags);
1723 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1724 spin_unlock_irqrestore(&info->slock, flags);
1726 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1727 wake_up_interruptible(&tty->poll_wait);
1731 cp = &info->channel;
1737 static const struct pci_device_id rocket_pci_ids[] = {
1738 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4QUAD) },
1739 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8OCTA) },
1740 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8OCTA) },
1741 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8INTF) },
1742 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP8INTF) },
1743 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8J) },
1744 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4J) },
1745 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP8SNI) },
1746 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16SNI) },
1747 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP16INTF) },
1748 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP16INTF) },
1749 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_CRP16INTF) },
1750 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP32INTF) },
1751 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_URP32INTF) },
1752 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP4) },
1753 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RPP8) },
1754 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_232) },
1755 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP2_422) },
1756 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP6M) },
1757 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_RP4M) },
1758 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_8PORT) },
1759 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_DEVICE_ID_UPCI_RM3_4PORT) },
1762 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1764 /* Resets the speaker controller on RocketModem II and III devices */
1765 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
1769 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
1770 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
1771 addr = CtlP->AiopIO[0] + 0x4F;
1775 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
1776 if ((model == MODEL_UPCI_RM3_8PORT)
1777 || (model == MODEL_UPCI_RM3_4PORT)) {
1778 addr = CtlP->AiopIO[0] + 0x88;
1783 /***************************************************************************
1784 Function: sPCIInitController
1785 Purpose: Initialization of controller global registers and controller
1787 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
1788 IRQNum,Frequency,PeriodicOnly)
1789 CONTROLLER_T *CtlP; Ptr to controller structure
1790 int CtlNum; Controller number
1791 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
1792 This list must be in the order the AIOPs will be found on the
1793 controller. Once an AIOP in the list is not found, it is
1794 assumed that there are no more AIOPs on the controller.
1795 int AiopIOListSize; Number of addresses in AiopIOList
1796 int IRQNum; Interrupt Request number. Can be any of the following:
1797 0: Disable global interrupts
1806 Byte_t Frequency: A flag identifying the frequency
1807 of the periodic interrupt, can be any one of the following:
1808 FREQ_DIS - periodic interrupt disabled
1809 FREQ_137HZ - 137 Hertz
1810 FREQ_69HZ - 69 Hertz
1811 FREQ_34HZ - 34 Hertz
1812 FREQ_17HZ - 17 Hertz
1815 If IRQNum is set to 0 the Frequency parameter is
1816 overidden, it is forced to a value of FREQ_DIS.
1817 int PeriodicOnly: 1 if all interrupts except the periodic
1818 interrupt are to be blocked.
1819 0 is both the periodic interrupt and
1820 other channel interrupts are allowed.
1821 If IRQNum is set to 0 the PeriodicOnly parameter is
1822 overidden, it is forced to a value of 0.
1823 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
1824 initialization failed.
1827 If periodic interrupts are to be disabled but AIOP interrupts
1828 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
1830 If interrupts are to be completely disabled set IRQNum to 0.
1832 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
1833 invalid combination.
1835 This function performs initialization of global interrupt modes,
1836 but it does not actually enable global interrupts. To enable
1837 and disable global interrupts use functions sEnGlobalInt() and
1838 sDisGlobalInt(). Enabling of global interrupts is normally not
1839 done until all other initializations are complete.
1841 Even if interrupts are globally enabled, they must also be
1842 individually enabled for each channel that is to generate
1845 Warnings: No range checking on any of the parameters is done.
1847 No context switches are allowed while executing this function.
1849 After this function all AIOPs on the controller are disabled,
1850 they can be enabled with sEnAiop().
1852 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
1853 ByteIO_t * AiopIOList, int AiopIOListSize,
1854 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
1855 int PeriodicOnly, int altChanRingIndicator,
1861 CtlP->AltChanRingIndicator = altChanRingIndicator;
1862 CtlP->UPCIRingInd = UPCIRingInd;
1863 CtlP->CtlNum = CtlNum;
1864 CtlP->CtlID = CTLID_0001; /* controller release 1 */
1865 CtlP->BusType = isPCI; /* controller release 1 */
1869 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
1870 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
1871 CtlP->AiopIntrBits = upci_aiop_intr_bits;
1875 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
1876 CtlP->AiopIntrBits = aiop_intr_bits;
1879 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
1882 for (i = 0; i < AiopIOListSize; i++) {
1884 CtlP->AiopIO[i] = (WordIO_t) io;
1885 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
1887 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
1888 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
1889 break; /* done looking for AIOPs */
1891 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
1892 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
1893 sOutB(io + _INDX_DATA, sClockPrescale);
1894 CtlP->NumAiop++; /* bump count of AIOPs */
1897 if (CtlP->NumAiop == 0)
1900 return (CtlP->NumAiop);
1904 * Called when a PCI card is found. Retrieves and stores model information,
1905 * init's aiopic and serial port hardware.
1906 * Inputs: i is the board number (0-n)
1908 static __init int register_PCI(int i, struct pci_dev *dev)
1910 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1911 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1915 int altChanRingIndicator = 0;
1916 int ports_per_aiop = 8;
1917 WordIO_t ConfigIO = 0;
1918 ByteIO_t UPCIRingInd = 0;
1920 if (!dev || !pci_match_id(rocket_pci_ids, dev) ||
1921 pci_enable_device(dev) || i >= NUM_BOARDS)
1924 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1926 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1927 rocketModel[i].loadrm2 = 0;
1928 rocketModel[i].startingPortNumber = nextLineNumber;
1930 /* Depending on the model, set up some config variables */
1931 switch (dev->device) {
1932 case PCI_DEVICE_ID_RP4QUAD:
1935 rocketModel[i].model = MODEL_RP4QUAD;
1936 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1937 rocketModel[i].numPorts = 4;
1939 case PCI_DEVICE_ID_RP8OCTA:
1941 rocketModel[i].model = MODEL_RP8OCTA;
1942 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1943 rocketModel[i].numPorts = 8;
1945 case PCI_DEVICE_ID_URP8OCTA:
1947 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1948 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1949 rocketModel[i].numPorts = 8;
1951 case PCI_DEVICE_ID_RP8INTF:
1953 rocketModel[i].model = MODEL_RP8INTF;
1954 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1955 rocketModel[i].numPorts = 8;
1957 case PCI_DEVICE_ID_URP8INTF:
1959 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1960 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1961 rocketModel[i].numPorts = 8;
1963 case PCI_DEVICE_ID_RP8J:
1965 rocketModel[i].model = MODEL_RP8J;
1966 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1967 rocketModel[i].numPorts = 8;
1969 case PCI_DEVICE_ID_RP4J:
1972 rocketModel[i].model = MODEL_RP4J;
1973 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1974 rocketModel[i].numPorts = 4;
1976 case PCI_DEVICE_ID_RP8SNI:
1978 rocketModel[i].model = MODEL_RP8SNI;
1979 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1980 rocketModel[i].numPorts = 8;
1982 case PCI_DEVICE_ID_RP16SNI:
1984 rocketModel[i].model = MODEL_RP16SNI;
1985 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1986 rocketModel[i].numPorts = 16;
1988 case PCI_DEVICE_ID_RP16INTF:
1990 rocketModel[i].model = MODEL_RP16INTF;
1991 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1992 rocketModel[i].numPorts = 16;
1994 case PCI_DEVICE_ID_URP16INTF:
1996 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1997 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1998 rocketModel[i].numPorts = 16;
2000 case PCI_DEVICE_ID_CRP16INTF:
2002 rocketModel[i].model = MODEL_CPCI_RP16INTF;
2003 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
2004 rocketModel[i].numPorts = 16;
2006 case PCI_DEVICE_ID_RP32INTF:
2008 rocketModel[i].model = MODEL_RP32INTF;
2009 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
2010 rocketModel[i].numPorts = 32;
2012 case PCI_DEVICE_ID_URP32INTF:
2014 rocketModel[i].model = MODEL_UPCI_RP32INTF;
2015 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
2016 rocketModel[i].numPorts = 32;
2018 case PCI_DEVICE_ID_RPP4:
2021 altChanRingIndicator++;
2023 rocketModel[i].model = MODEL_RPP4;
2024 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
2025 rocketModel[i].numPorts = 4;
2027 case PCI_DEVICE_ID_RPP8:
2030 altChanRingIndicator++;
2032 rocketModel[i].model = MODEL_RPP8;
2033 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
2034 rocketModel[i].numPorts = 8;
2036 case PCI_DEVICE_ID_RP2_232:
2039 altChanRingIndicator++;
2041 rocketModel[i].model = MODEL_RP2_232;
2042 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
2043 rocketModel[i].numPorts = 2;
2045 case PCI_DEVICE_ID_RP2_422:
2048 altChanRingIndicator++;
2050 rocketModel[i].model = MODEL_RP2_422;
2051 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
2052 rocketModel[i].numPorts = 2;
2054 case PCI_DEVICE_ID_RP6M:
2059 /* If revision is 1, the rocketmodem flash must be loaded.
2060 * If it is 2 it is a "socketed" version. */
2061 if (dev->revision == 1) {
2062 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2063 rocketModel[i].loadrm2 = 1;
2065 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2068 rocketModel[i].model = MODEL_RP6M;
2069 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2070 rocketModel[i].numPorts = 6;
2072 case PCI_DEVICE_ID_RP4M:
2075 if (dev->revision == 1) {
2076 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2077 rocketModel[i].loadrm2 = 1;
2079 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2082 rocketModel[i].model = MODEL_RP4M;
2083 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2084 rocketModel[i].numPorts = 4;
2092 * Check for UPCI boards.
2095 switch (dev->device) {
2096 case PCI_DEVICE_ID_URP32INTF:
2097 case PCI_DEVICE_ID_URP8INTF:
2098 case PCI_DEVICE_ID_URP16INTF:
2099 case PCI_DEVICE_ID_CRP16INTF:
2100 case PCI_DEVICE_ID_URP8OCTA:
2101 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2102 ConfigIO = pci_resource_start(dev, 1);
2103 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2104 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2107 * Check for octa or quad cable.
2110 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2111 PCI_GPIO_CTRL_8PORT)) {
2113 rocketModel[i].numPorts = 4;
2117 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2119 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2120 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2121 rocketModel[i].numPorts = 8;
2122 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2123 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2124 ConfigIO = pci_resource_start(dev, 1);
2125 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2127 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2129 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2130 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2131 rocketModel[i].numPorts = 4;
2132 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2133 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2134 ConfigIO = pci_resource_start(dev, 1);
2135 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2142 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2143 rp_baud_base[i] = 921600;
2146 * If support_low_speed is set, use the slow clock
2147 * prescale, which supports 50 bps
2149 if (support_low_speed) {
2150 /* mod 9 (divide by 10) prescale */
2151 sClockPrescale = 0x19;
2152 rp_baud_base[i] = 230400;
2154 /* mod 4 (divide by 5) prescale */
2155 sClockPrescale = 0x14;
2156 rp_baud_base[i] = 460800;
2160 for (aiop = 0; aiop < max_num_aiops; aiop++)
2161 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2162 ctlp = sCtlNumToCtlPtr(i);
2163 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2164 for (aiop = 0; aiop < max_num_aiops; aiop++)
2165 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2167 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2168 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2169 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2170 rocketModel[i].startingPortNumber,
2171 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2173 if (num_aiops <= 0) {
2174 rcktpt_io_addr[i] = 0;
2179 /* Reset the AIOPIC, init the serial ports */
2180 for (aiop = 0; aiop < num_aiops; aiop++) {
2181 sResetAiopByNum(ctlp, aiop);
2182 num_chan = ports_per_aiop;
2183 for (chan = 0; chan < num_chan; chan++)
2184 init_r_port(i, aiop, chan, dev);
2187 /* Rocket modems must be reset */
2188 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2189 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2190 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2191 num_chan = ports_per_aiop;
2192 for (chan = 0; chan < num_chan; chan++)
2193 sPCIModemReset(ctlp, chan, 1);
2195 for (chan = 0; chan < num_chan; chan++)
2196 sPCIModemReset(ctlp, chan, 0);
2198 rmSpeakerReset(ctlp, rocketModel[i].model);
2204 * Probes for PCI cards, inits them if found
2205 * Input: board_found = number of ISA boards already found, or the
2206 * starting board number
2207 * Returns: Number of PCI boards found
2209 static int __init init_PCI(int boards_found)
2211 struct pci_dev *dev = NULL;
2214 /* Work through the PCI device list, pulling out ours */
2215 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2216 if (register_PCI(count + boards_found, dev))
2222 #endif /* CONFIG_PCI */
2225 * Probes for ISA cards
2226 * Input: i = the board number to look for
2227 * Returns: 1 if board found, 0 else
2229 static int __init init_ISA(int i)
2231 int num_aiops, num_chan = 0, total_num_chan = 0;
2233 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2237 /* If io_addr is zero, no board configured */
2238 if (rcktpt_io_addr[i] == 0)
2241 /* Reserve the IO region */
2242 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2243 printk(KERN_ERR "Unable to reserve IO region for configured "
2244 "ISA RocketPort at address 0x%lx, board not "
2245 "installed...\n", rcktpt_io_addr[i]);
2246 rcktpt_io_addr[i] = 0;
2250 ctlp = sCtlNumToCtlPtr(i);
2252 ctlp->boardType = rcktpt_type[i];
2254 switch (rcktpt_type[i]) {
2255 case ROCKET_TYPE_PC104:
2256 type_string = "(PC104)";
2258 case ROCKET_TYPE_MODEM:
2259 type_string = "(RocketModem)";
2261 case ROCKET_TYPE_MODEMII:
2262 type_string = "(RocketModem II)";
2270 * If support_low_speed is set, use the slow clock prescale,
2271 * which supports 50 bps
2273 if (support_low_speed) {
2274 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2275 rp_baud_base[i] = 230400;
2277 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2278 rp_baud_base[i] = 460800;
2281 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2282 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2284 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2286 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2287 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2288 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2291 /* If something went wrong initing the AIOP's release the ISA IO memory */
2292 if (num_aiops <= 0) {
2293 release_region(rcktpt_io_addr[i], 64);
2294 rcktpt_io_addr[i] = 0;
2298 rocketModel[i].startingPortNumber = nextLineNumber;
2300 for (aiop = 0; aiop < num_aiops; aiop++) {
2301 sResetAiopByNum(ctlp, aiop);
2302 sEnAiop(ctlp, aiop);
2303 num_chan = sGetAiopNumChan(ctlp, aiop);
2304 total_num_chan += num_chan;
2305 for (chan = 0; chan < num_chan; chan++)
2306 init_r_port(i, aiop, chan, NULL);
2309 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2310 num_chan = sGetAiopNumChan(ctlp, 0);
2311 total_num_chan = num_chan;
2312 for (chan = 0; chan < num_chan; chan++)
2313 sModemReset(ctlp, chan, 1);
2315 for (chan = 0; chan < num_chan; chan++)
2316 sModemReset(ctlp, chan, 0);
2318 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2320 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2322 rocketModel[i].numPorts = total_num_chan;
2323 rocketModel[i].model = MODEL_ISA;
2325 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2326 i, rcktpt_io_addr[i], num_aiops, type_string);
2328 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2329 rocketModel[i].modelString,
2330 rocketModel[i].startingPortNumber,
2331 rocketModel[i].startingPortNumber +
2332 rocketModel[i].numPorts - 1);
2337 static const struct tty_operations rocket_ops = {
2341 .put_char = rp_put_char,
2342 .write_room = rp_write_room,
2343 .chars_in_buffer = rp_chars_in_buffer,
2344 .flush_buffer = rp_flush_buffer,
2346 .throttle = rp_throttle,
2347 .unthrottle = rp_unthrottle,
2348 .set_termios = rp_set_termios,
2351 .hangup = rp_hangup,
2352 .break_ctl = rp_break,
2353 .send_xchar = rp_send_xchar,
2354 .wait_until_sent = rp_wait_until_sent,
2355 .tiocmget = rp_tiocmget,
2356 .tiocmset = rp_tiocmset,
2359 static const struct tty_port_operations rocket_port_ops = {
2360 .carrier_raised = carrier_raised,
2365 * The module "startup" routine; it's run when the module is loaded.
2367 static int __init rp_init(void)
2369 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2371 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2372 ROCKET_VERSION, ROCKET_DATE);
2374 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2379 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2380 * zero, use the default controller IO address of board1 + 0x40.
2383 if (controller == 0)
2384 controller = board1 + 0x40;
2386 controller = 0; /* Used as a flag, meaning no ISA boards */
2389 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2390 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2391 printk(KERN_ERR "Unable to reserve IO region for first "
2392 "configured ISA RocketPort controller 0x%lx. "
2393 "Driver exiting\n", controller);
2398 /* Store ISA variable retrieved from command line or .conf file. */
2399 rcktpt_io_addr[0] = board1;
2400 rcktpt_io_addr[1] = board2;
2401 rcktpt_io_addr[2] = board3;
2402 rcktpt_io_addr[3] = board4;
2404 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2405 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2406 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2407 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2408 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2409 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2410 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2411 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2414 * Set up the tty driver structure and then register this
2415 * driver with the tty layer.
2418 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2419 rocket_driver->name = "ttyR";
2420 rocket_driver->driver_name = "Comtrol RocketPort";
2421 rocket_driver->major = TTY_ROCKET_MAJOR;
2422 rocket_driver->minor_start = 0;
2423 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2424 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2425 rocket_driver->init_termios = tty_std_termios;
2426 rocket_driver->init_termios.c_cflag =
2427 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2428 rocket_driver->init_termios.c_ispeed = 9600;
2429 rocket_driver->init_termios.c_ospeed = 9600;
2430 #ifdef ROCKET_SOFT_FLOW
2431 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2433 tty_set_operations(rocket_driver, &rocket_ops);
2435 ret = tty_register_driver(rocket_driver);
2437 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2438 goto err_controller;
2441 #ifdef ROCKET_DEBUG_OPEN
2442 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2446 * OK, let's probe each of the controllers looking for boards. Any boards found
2447 * will be initialized here.
2449 isa_boards_found = 0;
2450 pci_boards_found = 0;
2452 for (i = 0; i < NUM_BOARDS; i++) {
2458 if (isa_boards_found < NUM_BOARDS)
2459 pci_boards_found = init_PCI(isa_boards_found);
2462 max_board = pci_boards_found + isa_boards_found;
2464 if (max_board == 0) {
2465 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2472 tty_unregister_driver(rocket_driver);
2475 release_region(controller, 4);
2477 put_tty_driver(rocket_driver);
2483 static void rp_cleanup_module(void)
2488 del_timer_sync(&rocket_timer);
2490 retval = tty_unregister_driver(rocket_driver);
2492 printk(KERN_ERR "Error %d while trying to unregister "
2493 "rocketport driver\n", -retval);
2495 for (i = 0; i < MAX_RP_PORTS; i++)
2497 tty_unregister_device(rocket_driver, i);
2498 tty_port_destroy(&rp_table[i]->port);
2502 put_tty_driver(rocket_driver);
2504 for (i = 0; i < NUM_BOARDS; i++) {
2505 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2507 release_region(rcktpt_io_addr[i], 64);
2510 release_region(controller, 4);
2513 /***************************************************************************
2514 Function: sInitController
2515 Purpose: Initialization of controller global registers and controller
2517 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2518 IRQNum,Frequency,PeriodicOnly)
2519 CONTROLLER_T *CtlP; Ptr to controller structure
2520 int CtlNum; Controller number
2521 ByteIO_t MudbacIO; Mudbac base I/O address.
2522 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2523 This list must be in the order the AIOPs will be found on the
2524 controller. Once an AIOP in the list is not found, it is
2525 assumed that there are no more AIOPs on the controller.
2526 int AiopIOListSize; Number of addresses in AiopIOList
2527 int IRQNum; Interrupt Request number. Can be any of the following:
2528 0: Disable global interrupts
2537 Byte_t Frequency: A flag identifying the frequency
2538 of the periodic interrupt, can be any one of the following:
2539 FREQ_DIS - periodic interrupt disabled
2540 FREQ_137HZ - 137 Hertz
2541 FREQ_69HZ - 69 Hertz
2542 FREQ_34HZ - 34 Hertz
2543 FREQ_17HZ - 17 Hertz
2546 If IRQNum is set to 0 the Frequency parameter is
2547 overidden, it is forced to a value of FREQ_DIS.
2548 int PeriodicOnly: 1 if all interrupts except the periodic
2549 interrupt are to be blocked.
2550 0 is both the periodic interrupt and
2551 other channel interrupts are allowed.
2552 If IRQNum is set to 0 the PeriodicOnly parameter is
2553 overidden, it is forced to a value of 0.
2554 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2555 initialization failed.
2558 If periodic interrupts are to be disabled but AIOP interrupts
2559 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2561 If interrupts are to be completely disabled set IRQNum to 0.
2563 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2564 invalid combination.
2566 This function performs initialization of global interrupt modes,
2567 but it does not actually enable global interrupts. To enable
2568 and disable global interrupts use functions sEnGlobalInt() and
2569 sDisGlobalInt(). Enabling of global interrupts is normally not
2570 done until all other initializations are complete.
2572 Even if interrupts are globally enabled, they must also be
2573 individually enabled for each channel that is to generate
2576 Warnings: No range checking on any of the parameters is done.
2578 No context switches are allowed while executing this function.
2580 After this function all AIOPs on the controller are disabled,
2581 they can be enabled with sEnAiop().
2583 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2584 ByteIO_t * AiopIOList, int AiopIOListSize,
2585 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2591 CtlP->AiopIntrBits = aiop_intr_bits;
2592 CtlP->AltChanRingIndicator = 0;
2593 CtlP->CtlNum = CtlNum;
2594 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2595 CtlP->BusType = isISA;
2596 CtlP->MBaseIO = MudbacIO;
2597 CtlP->MReg1IO = MudbacIO + 1;
2598 CtlP->MReg2IO = MudbacIO + 2;
2599 CtlP->MReg3IO = MudbacIO + 3;
2601 CtlP->MReg2 = 0; /* interrupt disable */
2602 CtlP->MReg3 = 0; /* no periodic interrupts */
2604 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2605 CtlP->MReg2 = 0; /* interrupt disable */
2606 CtlP->MReg3 = 0; /* no periodic interrupts */
2608 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2609 CtlP->MReg3 = Frequency; /* set frequency */
2610 if (PeriodicOnly) { /* periodic interrupt only */
2611 CtlP->MReg3 |= PERIODIC_ONLY;
2615 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2616 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2617 sControllerEOI(CtlP); /* clear EOI if warm init */
2620 for (i = done = 0; i < AiopIOListSize; i++) {
2622 CtlP->AiopIO[i] = (WordIO_t) io;
2623 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2624 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2625 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2628 sEnAiop(CtlP, i); /* enable the AIOP */
2629 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2630 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2631 done = 1; /* done looking for AIOPs */
2633 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2634 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2635 sOutB(io + _INDX_DATA, sClockPrescale);
2636 CtlP->NumAiop++; /* bump count of AIOPs */
2638 sDisAiop(CtlP, i); /* disable AIOP */
2641 if (CtlP->NumAiop == 0)
2644 return (CtlP->NumAiop);
2647 /***************************************************************************
2648 Function: sReadAiopID
2649 Purpose: Read the AIOP idenfication number directly from an AIOP.
2650 Call: sReadAiopID(io)
2651 ByteIO_t io: AIOP base I/O address
2652 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2653 is replace by an identifying number.
2654 Flag AIOPID_NULL if no valid AIOP is found
2655 Warnings: No context switches are allowed while executing this function.
2658 static int sReadAiopID(ByteIO_t io)
2660 Byte_t AiopID; /* ID byte from AIOP */
2662 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2663 sOutB(io + _CMD_REG, 0x0);
2664 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2667 else /* AIOP does not exist */
2671 /***************************************************************************
2672 Function: sReadAiopNumChan
2673 Purpose: Read the number of channels available in an AIOP directly from
2675 Call: sReadAiopNumChan(io)
2676 WordIO_t io: AIOP base I/O address
2677 Return: int: The number of channels available
2678 Comments: The number of channels is determined by write/reads from identical
2679 offsets within the SRAM address spaces for channels 0 and 4.
2680 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2681 AIOP, otherwise it is an 8 channel.
2682 Warnings: No context switches are allowed while executing this function.
2684 static int sReadAiopNumChan(WordIO_t io)
2687 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2689 /* write to chan 0 SRAM */
2690 out32((DWordIO_t) io + _INDX_ADDR, R);
2691 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2692 x = sInW(io + _INDX_DATA);
2693 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2694 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2700 /***************************************************************************
2702 Purpose: Initialization of a channel and channel structure
2703 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2704 CONTROLLER_T *CtlP; Ptr to controller structure
2705 CHANNEL_T *ChP; Ptr to channel structure
2706 int AiopNum; AIOP number within controller
2707 int ChanNum; Channel number within AIOP
2708 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2709 number exceeds number of channels available in AIOP.
2710 Comments: This function must be called before a channel can be used.
2711 Warnings: No range checking on any of the parameters is done.
2713 No context switches are allowed while executing this function.
2715 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2726 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2727 return 0; /* exceeds num chans in AIOP */
2729 /* Channel, AIOP, and controller identifiers */
2731 ChP->ChanID = CtlP->AiopID[AiopNum];
2732 ChP->AiopNum = AiopNum;
2733 ChP->ChanNum = ChanNum;
2735 /* Global direct addresses */
2736 AiopIO = CtlP->AiopIO[AiopNum];
2737 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2738 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2739 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2740 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2741 ChP->IndexData = AiopIO + _INDX_DATA;
2743 /* Channel direct addresses */
2744 ChIOOff = AiopIO + ChP->ChanNum * 2;
2745 ChP->TxRxData = ChIOOff + _TD0;
2746 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2747 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2748 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2750 /* Initialize the channel from the RData array */
2751 for (i = 0; i < RDATASIZE; i += 4) {
2753 R[1] = RData[i + 1] + 0x10 * ChanNum;
2754 R[2] = RData[i + 2];
2755 R[3] = RData[i + 3];
2756 out32(ChP->IndexAddr, R);
2760 for (i = 0; i < RREGDATASIZE; i += 4) {
2761 ChR[i] = RRegData[i];
2762 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2763 ChR[i + 2] = RRegData[i + 2];
2764 ChR[i + 3] = RRegData[i + 3];
2767 /* Indexed registers */
2768 ChOff = (Word_t) ChanNum *0x1000;
2770 if (sClockPrescale == 0x14)
2775 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2776 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2777 ChP->BaudDiv[2] = (Byte_t) brd9600;
2778 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2779 out32(ChP->IndexAddr, ChP->BaudDiv);
2781 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2782 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2783 ChP->TxControl[2] = 0;
2784 ChP->TxControl[3] = 0;
2785 out32(ChP->IndexAddr, ChP->TxControl);
2787 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2788 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2789 ChP->RxControl[2] = 0;
2790 ChP->RxControl[3] = 0;
2791 out32(ChP->IndexAddr, ChP->RxControl);
2793 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2794 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2795 ChP->TxEnables[2] = 0;
2796 ChP->TxEnables[3] = 0;
2797 out32(ChP->IndexAddr, ChP->TxEnables);
2799 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2800 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2801 ChP->TxCompare[2] = 0;
2802 ChP->TxCompare[3] = 0;
2803 out32(ChP->IndexAddr, ChP->TxCompare);
2805 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2806 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2807 ChP->TxReplace1[2] = 0;
2808 ChP->TxReplace1[3] = 0;
2809 out32(ChP->IndexAddr, ChP->TxReplace1);
2811 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2812 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2813 ChP->TxReplace2[2] = 0;
2814 ChP->TxReplace2[3] = 0;
2815 out32(ChP->IndexAddr, ChP->TxReplace2);
2817 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2818 ChP->TxFIFO = ChOff + _TX_FIFO;
2820 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2821 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2822 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2823 sOutW(ChP->IndexData, 0);
2824 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2825 ChP->RxFIFO = ChOff + _RX_FIFO;
2827 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2828 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2829 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2830 sOutW(ChP->IndexData, 0);
2831 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2832 sOutW(ChP->IndexData, 0);
2833 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2834 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2835 sOutB(ChP->IndexData, 0);
2836 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2837 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2838 sOutB(ChP->IndexData, 0);
2839 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2840 sEnRxProcessor(ChP); /* start the Rx processor */
2845 /***************************************************************************
2846 Function: sStopRxProcessor
2847 Purpose: Stop the receive processor from processing a channel.
2848 Call: sStopRxProcessor(ChP)
2849 CHANNEL_T *ChP; Ptr to channel structure
2851 Comments: The receive processor can be started again with sStartRxProcessor().
2852 This function causes the receive processor to skip over the
2853 stopped channel. It does not stop it from processing other channels.
2855 Warnings: No context switches are allowed while executing this function.
2857 Do not leave the receive processor stopped for more than one
2860 After calling this function a delay of 4 uS is required to ensure
2861 that the receive processor is no longer processing this channel.
2863 static void sStopRxProcessor(CHANNEL_T * ChP)
2871 out32(ChP->IndexAddr, R);
2874 /***************************************************************************
2875 Function: sFlushRxFIFO
2876 Purpose: Flush the Rx FIFO
2877 Call: sFlushRxFIFO(ChP)
2878 CHANNEL_T *ChP; Ptr to channel structure
2880 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2881 while it is being flushed the receive processor is stopped
2882 and the transmitter is disabled. After these operations a
2883 4 uS delay is done before clearing the pointers to allow
2884 the receive processor to stop. These items are handled inside
2886 Warnings: No context switches are allowed while executing this function.
2888 static void sFlushRxFIFO(CHANNEL_T * ChP)
2891 Byte_t Ch; /* channel number within AIOP */
2892 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2894 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2895 return; /* don't need to flush */
2898 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2900 sDisRxFIFO(ChP); /* disable it */
2901 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2902 sInB(ChP->IntChan); /* depends on bus i/o timing */
2904 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2905 Ch = (Byte_t) sGetChanNum(ChP);
2906 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2907 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2908 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2909 sOutW(ChP->IndexData, 0);
2910 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2911 sOutW(ChP->IndexData, 0);
2913 sEnRxFIFO(ChP); /* enable Rx FIFO */
2916 /***************************************************************************
2917 Function: sFlushTxFIFO
2918 Purpose: Flush the Tx FIFO
2919 Call: sFlushTxFIFO(ChP)
2920 CHANNEL_T *ChP; Ptr to channel structure
2922 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2923 while it is being flushed the receive processor is stopped
2924 and the transmitter is disabled. After these operations a
2925 4 uS delay is done before clearing the pointers to allow
2926 the receive processor to stop. These items are handled inside
2928 Warnings: No context switches are allowed while executing this function.
2930 static void sFlushTxFIFO(CHANNEL_T * ChP)
2933 Byte_t Ch; /* channel number within AIOP */
2934 int TxEnabled; /* 1 if transmitter enabled */
2936 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2937 return; /* don't need to flush */
2940 if (ChP->TxControl[3] & TX_ENABLE) {
2942 sDisTransmit(ChP); /* disable transmitter */
2944 sStopRxProcessor(ChP); /* stop Rx processor */
2945 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2946 sInB(ChP->IntChan); /* depends on bus i/o timing */
2947 Ch = (Byte_t) sGetChanNum(ChP);
2948 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2949 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2950 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2951 sOutW(ChP->IndexData, 0);
2953 sEnTransmit(ChP); /* enable transmitter */
2954 sStartRxProcessor(ChP); /* restart Rx processor */
2957 /***************************************************************************
2958 Function: sWriteTxPrioByte
2959 Purpose: Write a byte of priority transmit data to a channel
2960 Call: sWriteTxPrioByte(ChP,Data)
2961 CHANNEL_T *ChP; Ptr to channel structure
2962 Byte_t Data; The transmit data byte
2964 Return: int: 1 if the bytes is successfully written, otherwise 0.
2966 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2968 Warnings: No context switches are allowed while executing this function.
2970 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2972 Byte_t DWBuf[4]; /* buffer for double word writes */
2973 Word_t *WordPtr; /* must be far because Win SS != DS */
2974 register DWordIO_t IndexAddr;
2976 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2977 IndexAddr = ChP->IndexAddr;
2978 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2979 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2980 return (0); /* nothing sent */
2982 WordPtr = (Word_t *) (&DWBuf[0]);
2983 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2985 DWBuf[2] = Data; /* data byte value */
2986 out32(IndexAddr, DWBuf); /* write it out */
2988 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2990 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2991 DWBuf[3] = 0; /* priority buffer pointer */
2992 out32(IndexAddr, DWBuf); /* write it out */
2993 } else { /* write it to Tx FIFO */
2995 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2997 return (1); /* 1 byte sent */
3000 /***************************************************************************
3001 Function: sEnInterrupts
3002 Purpose: Enable one or more interrupts for a channel
3003 Call: sEnInterrupts(ChP,Flags)
3004 CHANNEL_T *ChP; Ptr to channel structure
3005 Word_t Flags: Interrupt enable flags, can be any combination
3006 of the following flags:
3007 TXINT_EN: Interrupt on Tx FIFO empty
3008 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3010 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3011 MCINT_EN: Interrupt on modem input change
3012 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3013 Interrupt Channel Register.
3015 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3016 enabled. If an interrupt enable flag is not set in Flags, that
3017 interrupt will not be changed. Interrupts can be disabled with
3018 function sDisInterrupts().
3020 This function sets the appropriate bit for the channel in the AIOP's
3021 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3022 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3024 Interrupts must also be globally enabled before channel interrupts
3025 will be passed on to the host. This is done with function
3028 In some cases it may be desirable to disable interrupts globally but
3029 enable channel interrupts. This would allow the global interrupt
3030 status register to be used to determine which AIOPs need service.
3032 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3034 Byte_t Mask; /* Interrupt Mask Register */
3036 ChP->RxControl[2] |=
3037 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3039 out32(ChP->IndexAddr, ChP->RxControl);
3041 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3043 out32(ChP->IndexAddr, ChP->TxControl);
3045 if (Flags & CHANINT_EN) {
3046 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3047 sOutB(ChP->IntMask, Mask);
3051 /***************************************************************************
3052 Function: sDisInterrupts
3053 Purpose: Disable one or more interrupts for a channel
3054 Call: sDisInterrupts(ChP,Flags)
3055 CHANNEL_T *ChP; Ptr to channel structure
3056 Word_t Flags: Interrupt flags, can be any combination
3057 of the following flags:
3058 TXINT_EN: Interrupt on Tx FIFO empty
3059 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3061 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3062 MCINT_EN: Interrupt on modem input change
3063 CHANINT_EN: Disable channel interrupt signal to the
3064 AIOP's Interrupt Channel Register.
3066 Comments: If an interrupt flag is set in Flags, that interrupt will be
3067 disabled. If an interrupt flag is not set in Flags, that
3068 interrupt will not be changed. Interrupts can be enabled with
3069 function sEnInterrupts().
3071 This function clears the appropriate bit for the channel in the AIOP's
3072 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3073 this channel's bit from being set in the AIOP's Interrupt Channel
3076 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3078 Byte_t Mask; /* Interrupt Mask Register */
3080 ChP->RxControl[2] &=
3081 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3082 out32(ChP->IndexAddr, ChP->RxControl);
3083 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3084 out32(ChP->IndexAddr, ChP->TxControl);
3086 if (Flags & CHANINT_EN) {
3087 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3088 sOutB(ChP->IntMask, Mask);
3092 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3094 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3098 * Not an official SSCI function, but how to reset RocketModems.
3101 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3106 addr = CtlP->AiopIO[0] + 0x400;
3107 val = sInB(CtlP->MReg3IO);
3108 /* if AIOP[1] is not enabled, enable it */
3109 if ((val & 2) == 0) {
3110 val = sInB(CtlP->MReg2IO);
3111 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3112 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3118 sOutB(addr + chan, 0); /* apply or remove reset */
3123 * Not an official SSCI function, but how to reset RocketModems.
3126 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3130 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3133 sOutB(addr + chan, 0); /* apply or remove reset */
3136 /* Returns the line number given the controller (board), aiop and channel number */
3137 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3139 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3143 * Stores the line number associated with a given controller (board), aiop
3144 * and channel number.
3145 * Returns: The line number assigned
3147 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3149 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3150 return (nextLineNumber - 1);