drivers/tty/serial/8250/8250_exar.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *  Probe module for 8250/16550-type Exar chips PCI serial ports.
   4  *
   5  *  Based on drivers/tty/serial/8250/8250_pci.c,
   6  *
   7  *  Copyright (C) 2017 Sudip Mukherjee, All Rights Reserved.
   8  */
   9 #include <linux/acpi.h>
  10 #include <linux/dmi.h>
  11 #include <linux/io.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/pci.h>
  15 #include <linux/property.h>
  16 #include <linux/serial_core.h>
  17 #include <linux/serial_reg.h>
  18 #include <linux/slab.h>
  19 #include <linux/string.h>
  20 #include <linux/tty.h>
  21 #include <linux/8250_pci.h>
  22
  23 #include <asm/byteorder.h>
  24
  25 #include "8250.h"
  26
  27 #define PCI_DEVICE_ID_ACCES_COM_2S              0x1052
  28 #define PCI_DEVICE_ID_ACCES_COM_4S              0x105d
  29 #define PCI_DEVICE_ID_ACCES_COM_8S              0x106c
  30 #define PCI_DEVICE_ID_ACCES_COM232_8            0x10a8
  31 #define PCI_DEVICE_ID_ACCES_COM_2SM             0x10d2
  32 #define PCI_DEVICE_ID_ACCES_COM_4SM             0x10db
  33 #define PCI_DEVICE_ID_ACCES_COM_8SM             0x10ea
  34
  35 #define PCI_DEVICE_ID_COMMTECH_4224PCI335       0x0002
  36 #define PCI_DEVICE_ID_COMMTECH_4222PCI335       0x0004
  37 #define PCI_DEVICE_ID_COMMTECH_2324PCI335       0x000a
  38 #define PCI_DEVICE_ID_COMMTECH_2328PCI335       0x000b
  39 #define PCI_DEVICE_ID_COMMTECH_4224PCIE         0x0020
  40 #define PCI_DEVICE_ID_COMMTECH_4228PCIE         0x0021
  41 #define PCI_DEVICE_ID_COMMTECH_4222PCIE         0x0022
  42 #define PCI_DEVICE_ID_EXAR_XR17V4358            0x4358
  43 #define PCI_DEVICE_ID_EXAR_XR17V8358            0x8358
  44
  45 #define UART_EXAR_INT0          0x80
  46 #define UART_EXAR_8XMODE        0x88    /* 8X sampling rate select */
  47
  48 #define UART_EXAR_FCTR          0x08    /* Feature Control Register */
  49 #define UART_FCTR_EXAR_IRDA     0x10    /* IrDa data encode select */
  50 #define UART_FCTR_EXAR_485      0x20    /* Auto 485 half duplex dir ctl */
  51 #define UART_FCTR_EXAR_TRGA     0x00    /* FIFO trigger table A */
  52 #define UART_FCTR_EXAR_TRGB     0x60    /* FIFO trigger table B */
  53 #define UART_FCTR_EXAR_TRGC     0x80    /* FIFO trigger table C */
  54 #define UART_FCTR_EXAR_TRGD     0xc0    /* FIFO trigger table D programmable */
  55
  56 #define UART_EXAR_TXTRG         0x0a    /* Tx FIFO trigger level write-only */
  57 #define UART_EXAR_RXTRG         0x0b    /* Rx FIFO trigger level write-only */
  58
  59 #define UART_EXAR_MPIOINT_7_0   0x8f    /* MPIOINT[7:0] */
  60 #define UART_EXAR_MPIOLVL_7_0   0x90    /* MPIOLVL[7:0] */
  61 #define UART_EXAR_MPIO3T_7_0    0x91    /* MPIO3T[7:0] */
  62 #define UART_EXAR_MPIOINV_7_0   0x92    /* MPIOINV[7:0] */
  63 #define UART_EXAR_MPIOSEL_7_0   0x93    /* MPIOSEL[7:0] */
  64 #define UART_EXAR_MPIOOD_7_0    0x94    /* MPIOOD[7:0] */
  65 #define UART_EXAR_MPIOINT_15_8  0x95    /* MPIOINT[15:8] */
  66 #define UART_EXAR_MPIOLVL_15_8  0x96    /* MPIOLVL[15:8] */
  67 #define UART_EXAR_MPIO3T_15_8   0x97    /* MPIO3T[15:8] */
  68 #define UART_EXAR_MPIOINV_15_8  0x98    /* MPIOINV[15:8] */
  69 #define UART_EXAR_MPIOSEL_15_8  0x99    /* MPIOSEL[15:8] */
  70 #define UART_EXAR_MPIOOD_15_8   0x9a    /* MPIOOD[15:8] */
  71
  72 #define UART_EXAR_RS485_DLY(x)  ((x) << 4)
  73
  74 /*
  75  * IOT2040 MPIO wiring semantics:
  76  *
  77  * MPIO         Port    Function
  78  * ----         ----    --------
  79  * 0            2       Mode bit 0
  80  * 1            2       Mode bit 1
  81  * 2            2       Terminate bus
  82  * 3            -       <reserved>
  83  * 4            3       Mode bit 0
  84  * 5            3       Mode bit 1
  85  * 6            3       Terminate bus
  86  * 7            -       <reserved>
  87  * 8            2       Enable
  88  * 9            3       Enable
  89  * 10           -       Red LED
  90  * 11..15       -       <unused>
  91  */
  92
  93 /* IOT2040 MPIOs 0..7 */
  94 #define IOT2040_UART_MODE_RS232         0x01
  95 #define IOT2040_UART_MODE_RS485         0x02
  96 #define IOT2040_UART_MODE_RS422         0x03
  97 #define IOT2040_UART_TERMINATE_BUS      0x04
  98
  99 #define IOT2040_UART1_MASK              0x0f
 100 #define IOT2040_UART2_SHIFT             4
 101
 102 #define IOT2040_UARTS_DEFAULT_MODE      0x11    /* both RS232 */
 103 #define IOT2040_UARTS_GPIO_LO_MODE      0x88    /* reserved pins as input */
 104
 105 /* IOT2040 MPIOs 8..15 */
 106 #define IOT2040_UARTS_ENABLE            0x03
 107 #define IOT2040_UARTS_GPIO_HI_MODE      0xF8    /* enable & LED as outputs */
 108
 109 struct exar8250;
 110
 111 struct exar8250_platform {
 112         int (*rs485_config)(struct uart_port *, struct serial_rs485 *);
 113         int (*register_gpio)(struct pci_dev *, struct uart_8250_port *);
 114 };
 115
 116 /**
 117  * struct exar8250_board - board information
 118  * @num_ports: number of serial ports
 119  * @reg_shift: describes UART register mapping in PCI memory
 120  * @setup: quirk run at ->probe() stage
 121  * @exit: quirk run at ->remove() stage
 122  */
 123 struct exar8250_board {
 124         unsigned int num_ports;
 125         unsigned int reg_shift;
 126         int     (*setup)(struct exar8250 *, struct pci_dev *,
 127                          struct uart_8250_port *, int);
 128         void    (*exit)(struct pci_dev *pcidev);
 129 };
 130
 131 struct exar8250 {
 132         unsigned int            nr;
 133         struct exar8250_board   *board;
 134         void __iomem            *virt;
 135         int                     line[0];
 136 };
 137
 138 static int default_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 139                          int idx, unsigned int offset,
 140                          struct uart_8250_port *port)
 141 {
 142         const struct exar8250_board *board = priv->board;
 143         unsigned int bar = 0;
 144
 145         port->port.iotype = UPIO_MEM;
 146         port->port.mapbase = pci_resource_start(pcidev, bar) + offset;
 147         port->port.membase = priv->virt + offset;
 148         port->port.regshift = board->reg_shift;
 149
 150         return 0;
 151 }
 152
 153 static int
 154 pci_fastcom335_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 155                      struct uart_8250_port *port, int idx)
 156 {
 157         unsigned int offset = idx * 0x200;
 158         unsigned int baud = 1843200;
 159         u8 __iomem *p;
 160         int err;
 161
 162         port->port.uartclk = baud * 16;
 163
 164         err = default_setup(priv, pcidev, idx, offset, port);
 165         if (err)
 166                 return err;
 167
 168         p = port->port.membase;
 169
 170         writeb(0x00, p + UART_EXAR_8XMODE);
 171         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 172         writeb(32, p + UART_EXAR_TXTRG);
 173         writeb(32, p + UART_EXAR_RXTRG);
 174
 175         /*
 176          * Setup Multipurpose Input/Output pins.
 177          */
 178         if (idx == 0) {
 179                 switch (pcidev->device) {
 180                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
 181                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
 182                         writeb(0x78, p + UART_EXAR_MPIOLVL_7_0);
 183                         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 184                         writeb(0x00, p + UART_EXAR_MPIOSEL_7_0);
 185                         break;
 186                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
 187                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
 188                         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 189                         writeb(0xc0, p + UART_EXAR_MPIOINV_7_0);
 190                         writeb(0xc0, p + UART_EXAR_MPIOSEL_7_0);
 191                         break;
 192                 }
 193                 writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 194                 writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 195                 writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 196         }
 197
 198         return 0;
 199 }
 200
 201 static int
 202 pci_connect_tech_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 203                        struct uart_8250_port *port, int idx)
 204 {
 205         unsigned int offset = idx * 0x200;
 206         unsigned int baud = 1843200;
 207
 208         port->port.uartclk = baud * 16;
 209         return default_setup(priv, pcidev, idx, offset, port);
 210 }
 211
 212 static int
 213 pci_xr17c154_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 214                    struct uart_8250_port *port, int idx)
 215 {
 216         unsigned int offset = idx * 0x200;
 217         unsigned int baud = 921600;
 218
 219         port->port.uartclk = baud * 16;
 220         return default_setup(priv, pcidev, idx, offset, port);
 221 }
 222
 223 static void setup_gpio(struct pci_dev *pcidev, u8 __iomem *p)
 224 {
 225         /*
 226          * The Commtech adapters required the MPIOs to be driven low. The Exar
 227          * devices will export them as GPIOs, so we pre-configure them safely
 228          * as inputs.
 229          */
 230
 231         u8 dir = 0x00;
 232
 233         if  ((pcidev->vendor == PCI_VENDOR_ID_EXAR) &&
 234                 (pcidev->subsystem_vendor != PCI_VENDOR_ID_SEALEVEL)) {
 235                 // Configure GPIO as inputs for Commtech adapters
 236                 dir = 0xff;
 237         } else {
 238                 // Configure GPIO as outputs for SeaLevel adapters
 239                 dir = 0x00;
 240         }
 241
 242         writeb(0x00, p + UART_EXAR_MPIOINT_7_0);
 243         writeb(0x00, p + UART_EXAR_MPIOLVL_7_0);
 244         writeb(0x00, p + UART_EXAR_MPIO3T_7_0);
 245         writeb(0x00, p + UART_EXAR_MPIOINV_7_0);
 246         writeb(dir,  p + UART_EXAR_MPIOSEL_7_0);
 247         writeb(0x00, p + UART_EXAR_MPIOOD_7_0);
 248         writeb(0x00, p + UART_EXAR_MPIOINT_15_8);
 249         writeb(0x00, p + UART_EXAR_MPIOLVL_15_8);
 250         writeb(0x00, p + UART_EXAR_MPIO3T_15_8);
 251         writeb(0x00, p + UART_EXAR_MPIOINV_15_8);
 252         writeb(dir,  p + UART_EXAR_MPIOSEL_15_8);
 253         writeb(0x00, p + UART_EXAR_MPIOOD_15_8);
 254 }
 255
 256 static void *
 257 __xr17v35x_register_gpio(struct pci_dev *pcidev,
 258                          const struct property_entry *properties)
 259 {
 260         struct platform_device *pdev;
 261
 262         pdev = platform_device_alloc("gpio_exar", PLATFORM_DEVID_AUTO);
 263         if (!pdev)
 264                 return NULL;
 265
 266         pdev->dev.parent = &pcidev->dev;
 267         ACPI_COMPANION_SET(&pdev->dev, ACPI_COMPANION(&pcidev->dev));
 268
 269         if (platform_device_add_properties(pdev, properties) < 0 ||
 270             platform_device_add(pdev) < 0) {
 271                 platform_device_put(pdev);
 272                 return NULL;
 273         }
 274
 275         return pdev;
 276 }
 277
 278 static const struct property_entry exar_gpio_properties[] = {
 279         PROPERTY_ENTRY_U32("exar,first-pin", 0),
 280         PROPERTY_ENTRY_U32("ngpios", 16),
 281         { }
 282 };
 283
 284 static int xr17v35x_register_gpio(struct pci_dev *pcidev,
 285                                   struct uart_8250_port *port)
 286 {
 287         if (pcidev->vendor == PCI_VENDOR_ID_EXAR)
 288                 port->port.private_data =
 289                         __xr17v35x_register_gpio(pcidev, exar_gpio_properties);
 290
 291         return 0;
 292 }
 293
 294 static int generic_rs485_config(struct uart_port *port,
 295                                 struct serial_rs485 *rs485)
 296 {
 297         bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
 298         u8 __iomem *p = port->membase;
 299         u8 value;
 300
 301         value = readb(p + UART_EXAR_FCTR);
 302         if (is_rs485)
 303                 value |= UART_FCTR_EXAR_485;
 304         else
 305                 value &= ~UART_FCTR_EXAR_485;
 306
 307         writeb(value, p + UART_EXAR_FCTR);
 308
 309         if (is_rs485)
 310                 writeb(UART_EXAR_RS485_DLY(4), p + UART_MSR);
 311
 312         port->rs485 = *rs485;
 313
 314         return 0;
 315 }
 316
 317 static const struct exar8250_platform exar8250_default_platform = {
 318         .register_gpio = xr17v35x_register_gpio,
 319         .rs485_config = generic_rs485_config,
 320 };
 321
 322 static int iot2040_rs485_config(struct uart_port *port,
 323                                 struct serial_rs485 *rs485)
 324 {
 325         bool is_rs485 = !!(rs485->flags & SER_RS485_ENABLED);
 326         u8 __iomem *p = port->membase;
 327         u8 mask = IOT2040_UART1_MASK;
 328         u8 mode, value;
 329
 330         if (is_rs485) {
 331                 if (rs485->flags & SER_RS485_RX_DURING_TX)
 332                         mode = IOT2040_UART_MODE_RS422;
 333                 else
 334                         mode = IOT2040_UART_MODE_RS485;
 335
 336                 if (rs485->flags & SER_RS485_TERMINATE_BUS)
 337                         mode |= IOT2040_UART_TERMINATE_BUS;
 338         } else {
 339                 mode = IOT2040_UART_MODE_RS232;
 340         }
 341
 342         if (port->line == 3) {
 343                 mask <<= IOT2040_UART2_SHIFT;
 344                 mode <<= IOT2040_UART2_SHIFT;
 345         }
 346
 347         value = readb(p + UART_EXAR_MPIOLVL_7_0);
 348         value &= ~mask;
 349         value |= mode;
 350         writeb(value, p + UART_EXAR_MPIOLVL_7_0);
 351
 352         return generic_rs485_config(port, rs485);
 353 }
 354
 355 static const struct property_entry iot2040_gpio_properties[] = {
 356         PROPERTY_ENTRY_U32("exar,first-pin", 10),
 357         PROPERTY_ENTRY_U32("ngpios", 1),
 358         { }
 359 };
 360
 361 static int iot2040_register_gpio(struct pci_dev *pcidev,
 362                               struct uart_8250_port *port)
 363 {
 364         u8 __iomem *p = port->port.membase;
 365
 366         writeb(IOT2040_UARTS_DEFAULT_MODE, p + UART_EXAR_MPIOLVL_7_0);
 367         writeb(IOT2040_UARTS_GPIO_LO_MODE, p + UART_EXAR_MPIOSEL_7_0);
 368         writeb(IOT2040_UARTS_ENABLE, p + UART_EXAR_MPIOLVL_15_8);
 369         writeb(IOT2040_UARTS_GPIO_HI_MODE, p + UART_EXAR_MPIOSEL_15_8);
 370
 371         port->port.private_data =
 372                 __xr17v35x_register_gpio(pcidev, iot2040_gpio_properties);
 373
 374         return 0;
 375 }
 376
 377 static const struct exar8250_platform iot2040_platform = {
 378         .rs485_config = iot2040_rs485_config,
 379         .register_gpio = iot2040_register_gpio,
 380 };
 381
 382 static const struct dmi_system_id exar_platforms[] = {
 383         {
 384                 .matches = {
 385                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "SIMATIC IOT2000"),
 386                         DMI_EXACT_MATCH(DMI_BOARD_ASSET_TAG,
 387                                         "6ES7647-0AA00-1YA2"),
 388                 },
 389                 .driver_data = (void *)&iot2040_platform,
 390         },
 391         {}
 392 };
 393
 394 static int
 395 pci_xr17v35x_setup(struct exar8250 *priv, struct pci_dev *pcidev,
 396                    struct uart_8250_port *port, int idx)
 397 {
 398         const struct exar8250_platform *platform;
 399         const struct dmi_system_id *dmi_match;
 400         unsigned int offset = idx * 0x400;
 401         unsigned int baud = 7812500;
 402         u8 __iomem *p;
 403         int ret;
 404
 405         dmi_match = dmi_first_match(exar_platforms);
 406         if (dmi_match)
 407                 platform = dmi_match->driver_data;
 408         else
 409                 platform = &exar8250_default_platform;
 410
 411         port->port.uartclk = baud * 16;
 412         port->port.rs485_config = platform->rs485_config;
 413
 414         /*
 415          * Setup the UART clock for the devices on expansion slot to
 416          * half the clock speed of the main chip (which is 125MHz)
 417          */
 418         if (idx >= 8)
 419                 port->port.uartclk /= 2;
 420
 421         ret = default_setup(priv, pcidev, idx, offset, port);
 422         if (ret)
 423                 return ret;
 424
 425         p = port->port.membase;
 426
 427         writeb(0x00, p + UART_EXAR_8XMODE);
 428         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
 429         writeb(128, p + UART_EXAR_TXTRG);
 430         writeb(128, p + UART_EXAR_RXTRG);
 431
 432         if (idx == 0) {
 433                 /* Setup Multipurpose Input/Output pins. */
 434                 setup_gpio(pcidev, p);
 435
 436                 ret = platform->register_gpio(pcidev, port);
 437         }
 438
 439         return ret;
 440 }
 441
 442 static void pci_xr17v35x_exit(struct pci_dev *pcidev)
 443 {
 444         struct exar8250 *priv = pci_get_drvdata(pcidev);
 445         struct uart_8250_port *port = serial8250_get_port(priv->line[0]);
 446         struct platform_device *pdev = port->port.private_data;
 447
 448         platform_device_unregister(pdev);
 449         port->port.private_data = NULL;
 450 }
 451
 452 /*
 453  * These Exar UARTs have an extra interrupt indicator that could fire for a
 454  * few interrupts that are not presented/cleared through IIR.  One of which is
 455  * a wakeup interrupt when coming out of sleep.  These interrupts are only
 456  * cleared by reading global INT0 or INT1 registers as interrupts are
 457  * associated with channel 0. The INT[3:0] registers _are_ accessible from each
 458  * channel's address space, but for the sake of bus efficiency we register a
 459  * dedicated handler at the PCI device level to handle them.
 460  */
 461 static irqreturn_t exar_misc_handler(int irq, void *data)
 462 {
 463         struct exar8250 *priv = data;
 464
 465         /* Clear all PCI interrupts by reading INT0. No effect on IIR */
 466         readb(priv->virt + UART_EXAR_INT0);
 467
 468         /* Clear INT0 for Expansion Interface slave ports, too */
 469         if (priv->board->num_ports > 8)
 470                 readb(priv->virt + 0x2000 + UART_EXAR_INT0);
 471
 472         return IRQ_HANDLED;
 473 }
 474
 475 static int
 476 exar_pci_probe(struct pci_dev *pcidev, const struct pci_device_id *ent)
 477 {
 478         unsigned int nr_ports, i, bar = 0, maxnr;
 479         struct exar8250_board *board;
 480         struct uart_8250_port uart;
 481         struct exar8250 *priv;
 482         int rc;
 483
 484         board = (struct exar8250_board *)ent->driver_data;
 485         if (!board)
 486                 return -EINVAL;
 487
 488         rc = pcim_enable_device(pcidev);
 489         if (rc)
 490                 return rc;
 491
 492         maxnr = pci_resource_len(pcidev, bar) >> (board->reg_shift + 3);
 493
 494         nr_ports = board->num_ports ? board->num_ports : pcidev->device & 0x0f;
 495
 496         priv = devm_kzalloc(&pcidev->dev, sizeof(*priv) +
 497                             sizeof(unsigned int) * nr_ports,
 498                             GFP_KERNEL);
 499         if (!priv)
 500                 return -ENOMEM;
 501
 502         priv->board = board;
 503         priv->virt = pcim_iomap(pcidev, bar, 0);
 504         if (!priv->virt)
 505                 return -ENOMEM;
 506
 507         pci_set_master(pcidev);
 508
 509         rc = pci_alloc_irq_vectors(pcidev, 1, 1, PCI_IRQ_ALL_TYPES);
 510         if (rc < 0)
 511                 return rc;
 512
 513         memset(&uart, 0, sizeof(uart));
 514         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ
 515                           | UPF_EXAR_EFR;
 516         uart.port.irq = pci_irq_vector(pcidev, 0);
 517         uart.port.dev = &pcidev->dev;
 518
 519         rc = devm_request_irq(&pcidev->dev, uart.port.irq, exar_misc_handler,
 520                          IRQF_SHARED, "exar_uart", priv);
 521         if (rc)
 522                 return rc;
 523
 524         for (i = 0; i < nr_ports && i < maxnr; i++) {
 525                 rc = board->setup(priv, pcidev, &uart, i);
 526                 if (rc) {
 527                         dev_err(&pcidev->dev, "Failed to setup port %u\n", i);
 528                         break;
 529                 }
 530
 531                 dev_dbg(&pcidev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
 532                         uart.port.iobase, uart.port.irq, uart.port.iotype);
 533
 534                 priv->line[i] = serial8250_register_8250_port(&uart);
 535                 if (priv->line[i] < 0) {
 536                         dev_err(&pcidev->dev,
 537                                 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
 538                                 uart.port.iobase, uart.port.irq,
 539                                 uart.port.iotype, priv->line[i]);
 540                         break;
 541                 }
 542         }
 543         priv->nr = i;
 544         pci_set_drvdata(pcidev, priv);
 545         return 0;
 546 }
 547
 548 static void exar_pci_remove(struct pci_dev *pcidev)
 549 {
 550         struct exar8250 *priv = pci_get_drvdata(pcidev);
 551         unsigned int i;
 552
 553         for (i = 0; i < priv->nr; i++)
 554                 serial8250_unregister_port(priv->line[i]);
 555
 556         if (priv->board->exit)
 557                 priv->board->exit(pcidev);
 558 }
 559
 560 static int __maybe_unused exar_suspend(struct device *dev)
 561 {
 562         struct pci_dev *pcidev = to_pci_dev(dev);
 563         struct exar8250 *priv = pci_get_drvdata(pcidev);
 564         unsigned int i;
 565
 566         for (i = 0; i < priv->nr; i++)
 567                 if (priv->line[i] >= 0)
 568                         serial8250_suspend_port(priv->line[i]);
 569
 570         /* Ensure that every init quirk is properly torn down */
 571         if (priv->board->exit)
 572                 priv->board->exit(pcidev);
 573
 574         return 0;
 575 }
 576
 577 static int __maybe_unused exar_resume(struct device *dev)
 578 {
 579         struct pci_dev *pcidev = to_pci_dev(dev);
 580         struct exar8250 *priv = pci_get_drvdata(pcidev);
 581         unsigned int i;
 582
 583         for (i = 0; i < priv->nr; i++)
 584                 if (priv->line[i] >= 0)
 585                         serial8250_resume_port(priv->line[i]);
 586
 587         return 0;
 588 }
 589
 590 static SIMPLE_DEV_PM_OPS(exar_pci_pm, exar_suspend, exar_resume);
 591
 592 static const struct exar8250_board acces_com_2x = {
 593         .num_ports      = 2,
 594         .setup          = pci_xr17c154_setup,
 595 };
 596
 597 static const struct exar8250_board acces_com_4x = {
 598         .num_ports      = 4,
 599         .setup          = pci_xr17c154_setup,
 600 };
 601
 602 static const struct exar8250_board acces_com_8x = {
 603         .num_ports      = 8,
 604         .setup          = pci_xr17c154_setup,
 605 };
 606
 607
 608 static const struct exar8250_board pbn_fastcom335_2 = {
 609         .num_ports      = 2,
 610         .setup          = pci_fastcom335_setup,
 611 };
 612
 613 static const struct exar8250_board pbn_fastcom335_4 = {
 614         .num_ports      = 4,
 615         .setup          = pci_fastcom335_setup,
 616 };
 617
 618 static const struct exar8250_board pbn_fastcom335_8 = {
 619         .num_ports      = 8,
 620         .setup          = pci_fastcom335_setup,
 621 };
 622
 623 static const struct exar8250_board pbn_connect = {
 624         .setup          = pci_connect_tech_setup,
 625 };
 626
 627 static const struct exar8250_board pbn_exar_ibm_saturn = {
 628         .num_ports      = 1,
 629         .setup          = pci_xr17c154_setup,
 630 };
 631
 632 static const struct exar8250_board pbn_exar_XR17C15x = {
 633         .setup          = pci_xr17c154_setup,
 634 };
 635
 636 static const struct exar8250_board pbn_exar_XR17V35x = {
 637         .setup          = pci_xr17v35x_setup,
 638         .exit           = pci_xr17v35x_exit,
 639 };
 640
 641 static const struct exar8250_board pbn_fastcom35x_2 = {
 642         .num_ports      = 2,
 643         .setup          = pci_xr17v35x_setup,
 644         .exit           = pci_xr17v35x_exit,
 645 };
 646
 647 static const struct exar8250_board pbn_fastcom35x_4 = {
 648         .num_ports      = 4,
 649         .setup          = pci_xr17v35x_setup,
 650         .exit           = pci_xr17v35x_exit,
 651 };
 652
 653 static const struct exar8250_board pbn_fastcom35x_8 = {
 654         .num_ports      = 8,
 655         .setup          = pci_xr17v35x_setup,
 656         .exit           = pci_xr17v35x_exit,
 657 };
 658
 659 static const struct exar8250_board pbn_exar_XR17V4358 = {
 660         .num_ports      = 12,
 661         .setup          = pci_xr17v35x_setup,
 662         .exit           = pci_xr17v35x_exit,
 663 };
 664
 665 static const struct exar8250_board pbn_exar_XR17V8358 = {
 666         .num_ports      = 16,
 667         .setup          = pci_xr17v35x_setup,
 668         .exit           = pci_xr17v35x_exit,
 669 };
 670
 671 #define CONNECT_DEVICE(devid, sdevid, bd) {                             \
 672         PCI_DEVICE_SUB(                                                 \
 673                 PCI_VENDOR_ID_EXAR,                                     \
 674                 PCI_DEVICE_ID_EXAR_##devid,                             \
 675                 PCI_SUBVENDOR_ID_CONNECT_TECH,                          \
 676                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_##sdevid), 0, 0,      \
 677                 (kernel_ulong_t)&bd                                     \
 678         }
 679
 680 #define EXAR_DEVICE(vend, devid, bd) {                                  \
 681         PCI_VDEVICE(vend, PCI_DEVICE_ID_##devid), (kernel_ulong_t)&bd   \
 682         }
 683
 684 #define IBM_DEVICE(devid, sdevid, bd) {                 \
 685         PCI_DEVICE_SUB(                                 \
 686                 PCI_VENDOR_ID_EXAR,                     \
 687                 PCI_DEVICE_ID_EXAR_##devid,             \
 688                 PCI_VENDOR_ID_IBM,                      \
 689                 PCI_SUBDEVICE_ID_IBM_##sdevid), 0, 0,   \
 690                 (kernel_ulong_t)&bd                     \
 691         }
 692
 693 static const struct pci_device_id exar_pci_tbl[] = {
 694         EXAR_DEVICE(ACCESSIO, ACCES_COM_2S, acces_com_2x),
 695         EXAR_DEVICE(ACCESSIO, ACCES_COM_4S, acces_com_4x),
 696         EXAR_DEVICE(ACCESSIO, ACCES_COM_8S, acces_com_8x),
 697         EXAR_DEVICE(ACCESSIO, ACCES_COM232_8, acces_com_8x),
 698         EXAR_DEVICE(ACCESSIO, ACCES_COM_2SM, acces_com_2x),
 699         EXAR_DEVICE(ACCESSIO, ACCES_COM_4SM, acces_com_4x),
 700         EXAR_DEVICE(ACCESSIO, ACCES_COM_8SM, acces_com_8x),
 701
 702
 703         CONNECT_DEVICE(XR17C152, UART_2_232, pbn_connect),
 704         CONNECT_DEVICE(XR17C154, UART_4_232, pbn_connect),
 705         CONNECT_DEVICE(XR17C158, UART_8_232, pbn_connect),
 706         CONNECT_DEVICE(XR17C152, UART_1_1, pbn_connect),
 707         CONNECT_DEVICE(XR17C154, UART_2_2, pbn_connect),
 708         CONNECT_DEVICE(XR17C158, UART_4_4, pbn_connect),
 709         CONNECT_DEVICE(XR17C152, UART_2, pbn_connect),
 710         CONNECT_DEVICE(XR17C154, UART_4, pbn_connect),
 711         CONNECT_DEVICE(XR17C158, UART_8, pbn_connect),
 712         CONNECT_DEVICE(XR17C152, UART_2_485, pbn_connect),
 713         CONNECT_DEVICE(XR17C154, UART_4_485, pbn_connect),
 714         CONNECT_DEVICE(XR17C158, UART_8_485, pbn_connect),
 715
 716         IBM_DEVICE(XR17C152, SATURN_SERIAL_ONE_PORT, pbn_exar_ibm_saturn),
 717
 718         /* Exar Corp. XR17C15[248] Dual/Quad/Octal UART */
 719         EXAR_DEVICE(EXAR, EXAR_XR17C152, pbn_exar_XR17C15x),
 720         EXAR_DEVICE(EXAR, EXAR_XR17C154, pbn_exar_XR17C15x),
 721         EXAR_DEVICE(EXAR, EXAR_XR17C158, pbn_exar_XR17C15x),
 722
 723         /* Exar Corp. XR17V[48]35[248] Dual/Quad/Octal/Hexa PCIe UARTs */
 724         EXAR_DEVICE(EXAR, EXAR_XR17V352, pbn_exar_XR17V35x),
 725         EXAR_DEVICE(EXAR, EXAR_XR17V354, pbn_exar_XR17V35x),
 726         EXAR_DEVICE(EXAR, EXAR_XR17V358, pbn_exar_XR17V35x),
 727         EXAR_DEVICE(EXAR, EXAR_XR17V4358, pbn_exar_XR17V4358),
 728         EXAR_DEVICE(EXAR, EXAR_XR17V8358, pbn_exar_XR17V8358),
 729         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCIE, pbn_fastcom35x_2),
 730         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCIE, pbn_fastcom35x_4),
 731         EXAR_DEVICE(COMMTECH, COMMTECH_4228PCIE, pbn_fastcom35x_8),
 732
 733         EXAR_DEVICE(COMMTECH, COMMTECH_4222PCI335, pbn_fastcom335_2),
 734         EXAR_DEVICE(COMMTECH, COMMTECH_4224PCI335, pbn_fastcom335_4),
 735         EXAR_DEVICE(COMMTECH, COMMTECH_2324PCI335, pbn_fastcom335_4),
 736         EXAR_DEVICE(COMMTECH, COMMTECH_2328PCI335, pbn_fastcom335_8),
 737         { 0, }
 738 };
 739 MODULE_DEVICE_TABLE(pci, exar_pci_tbl);
 740
 741 static struct pci_driver exar_pci_driver = {
 742         .name           = "exar_serial",
 743         .probe          = exar_pci_probe,
 744         .remove         = exar_pci_remove,
 745         .driver         = {
 746                 .pm     = &exar_pci_pm,
 747         },
 748         .id_table       = exar_pci_tbl,
 749 };
 750 module_pci_driver(exar_pci_driver);
 751
 752 MODULE_LICENSE("GPL");
 753 MODULE_DESCRIPTION("Exar Serial Driver");
 754 MODULE_AUTHOR("Sudip Mukherjee <sudip.mukherjee@codethink.co.uk>");