1 // SPDX-License-Identifier: GPL-2.0
3 * Probe for F81216A LPC to 4 UART
5 * Copyright (C) 2014-2016 Ricardo Ribalda, Qtechnology A/S
7 #include <linux/module.h>
10 #include <linux/kernel.h>
11 #include <linux/serial_core.h>
12 #include <linux/irq.h>
20 #define CHIP_ID_F81865 0x0407
21 #define CHIP_ID_F81866 0x1010
22 #define CHIP_ID_F81216AD 0x1602
23 #define CHIP_ID_F81216H 0x0501
24 #define CHIP_ID_F81216 0x0802
25 #define VENDOR_ID1 0x23
26 #define VENDOR_ID1_VAL 0x19
27 #define VENDOR_ID2 0x24
28 #define VENDOR_ID2_VAL 0x34
33 #define FINTEK_IRQ_MODE 0x70
34 #define IRQ_SHARE BIT(4)
35 #define IRQ_MODE_MASK (BIT(6) | BIT(5))
36 #define IRQ_LEVEL_LOW 0
37 #define IRQ_EDGE_HIGH BIT(5)
40 * F81216H clock source register, the value and mask is the same with F81866,
43 * Clock speeds for UART (register F0h)
50 #define RTS_INVERT BIT(5)
51 #define RS485_URA BIT(4)
52 #define RXW4C_IRA BIT(3)
53 #define TXW4C_IRA BIT(2)
55 #define FIFO_CTRL 0xF6
56 #define FIFO_MODE_MASK (BIT(1) | BIT(0))
57 #define FIFO_MODE_128 (BIT(1) | BIT(0))
58 #define RXFTHR_MODE_MASK (BIT(5) | BIT(4))
59 #define RXFTHR_MODE_4X BIT(5)
61 #define F81216_LDN_LOW 0x0
62 #define F81216_LDN_HIGH 0x4
67 * The IRQ setting mode of F81866 is not the same with F81216 series.
68 * Level/Low: IRQ_MODE0:0, IRQ_MODE1:0
69 * Edge/High: IRQ_MODE0:1, IRQ_MODE1:0
71 * Clock speeds for UART (register F2h)
77 #define F81866_IRQ_MODE 0xf0
78 #define F81866_IRQ_SHARE BIT(0)
79 #define F81866_IRQ_MODE0 BIT(1)
81 #define F81866_FIFO_CTRL FIFO_CTRL
82 #define F81866_IRQ_MODE1 BIT(3)
84 #define F81866_LDN_LOW 0x10
85 #define F81866_LDN_HIGH 0x16
87 #define F81866_UART_CLK 0xF2
88 #define F81866_UART_CLK_MASK (BIT(1) | BIT(0))
89 #define F81866_UART_CLK_1_8432MHZ 0
90 #define F81866_UART_CLK_14_769MHZ (BIT(1) | BIT(0))
91 #define F81866_UART_CLK_18_432MHZ BIT(0)
92 #define F81866_UART_CLK_24MHZ BIT(1)
101 static u8 sio_read_reg(struct fintek_8250 *pdata, u8 reg)
103 outb(reg, pdata->base_port + ADDR_PORT);
104 return inb(pdata->base_port + DATA_PORT);
107 static void sio_write_reg(struct fintek_8250 *pdata, u8 reg, u8 data)
109 outb(reg, pdata->base_port + ADDR_PORT);
110 outb(data, pdata->base_port + DATA_PORT);
113 static void sio_write_mask_reg(struct fintek_8250 *pdata, u8 reg, u8 mask,
118 tmp = (sio_read_reg(pdata, reg) & ~mask) | (mask & data);
119 sio_write_reg(pdata, reg, tmp);
122 static int fintek_8250_enter_key(u16 base_port, u8 key)
124 if (!request_muxed_region(base_port, 2, "8250_fintek"))
127 /* Force to deactive all SuperIO in this base_port */
128 outb(EXIT_KEY, base_port + ADDR_PORT);
130 outb(key, base_port + ADDR_PORT);
131 outb(key, base_port + ADDR_PORT);
135 static void fintek_8250_exit_key(u16 base_port)
138 outb(EXIT_KEY, base_port + ADDR_PORT);
139 release_region(base_port + ADDR_PORT, 2);
142 static int fintek_8250_check_id(struct fintek_8250 *pdata)
146 if (sio_read_reg(pdata, VENDOR_ID1) != VENDOR_ID1_VAL)
149 if (sio_read_reg(pdata, VENDOR_ID2) != VENDOR_ID2_VAL)
152 chip = sio_read_reg(pdata, CHIP_ID1);
153 chip |= sio_read_reg(pdata, CHIP_ID2) << 8;
158 case CHIP_ID_F81216AD:
159 case CHIP_ID_F81216H:
170 static int fintek_8250_get_ldn_range(struct fintek_8250 *pdata, int *min,
173 switch (pdata->pid) {
176 *min = F81866_LDN_LOW;
177 *max = F81866_LDN_HIGH;
180 case CHIP_ID_F81216AD:
181 case CHIP_ID_F81216H:
183 *min = F81216_LDN_LOW;
184 *max = F81216_LDN_HIGH;
191 static int fintek_8250_rs485_config(struct uart_port *port,
192 struct serial_rs485 *rs485)
195 struct fintek_8250 *pdata = port->private_data;
201 if (rs485->flags & SER_RS485_ENABLED) {
202 /* Hardware do not support same RTS level on send and receive */
203 if (!(rs485->flags & SER_RS485_RTS_ON_SEND) ==
204 !(rs485->flags & SER_RS485_RTS_AFTER_SEND))
206 memset(rs485->padding, 0, sizeof(rs485->padding));
209 memset(rs485, 0, sizeof(*rs485));
212 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
213 SER_RS485_RTS_AFTER_SEND;
215 /* Only the first port supports delays */
217 rs485->delay_rts_before_send = 0;
218 rs485->delay_rts_after_send = 0;
221 if (rs485->delay_rts_before_send) {
222 rs485->delay_rts_before_send = 1;
226 if (rs485->delay_rts_after_send) {
227 rs485->delay_rts_after_send = 1;
231 if (rs485->flags & SER_RS485_RTS_ON_SEND)
232 config |= RTS_INVERT;
234 if (fintek_8250_enter_key(pdata->base_port, pdata->key))
237 sio_write_reg(pdata, LDN, pdata->index);
238 sio_write_reg(pdata, RS485, config);
239 fintek_8250_exit_key(pdata->base_port);
241 port->rs485 = *rs485;
246 static void fintek_8250_set_irq_mode(struct fintek_8250 *pdata, bool is_level)
248 sio_write_reg(pdata, LDN, pdata->index);
250 switch (pdata->pid) {
252 sio_write_mask_reg(pdata, F81866_FIFO_CTRL, F81866_IRQ_MODE1,
256 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_SHARE,
258 sio_write_mask_reg(pdata, F81866_IRQ_MODE, F81866_IRQ_MODE0,
259 is_level ? 0 : F81866_IRQ_MODE0);
262 case CHIP_ID_F81216AD:
263 case CHIP_ID_F81216H:
265 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_SHARE,
267 sio_write_mask_reg(pdata, FINTEK_IRQ_MODE, IRQ_MODE_MASK,
268 is_level ? IRQ_LEVEL_LOW : IRQ_EDGE_HIGH);
273 static void fintek_8250_set_max_fifo(struct fintek_8250 *pdata)
275 switch (pdata->pid) {
276 case CHIP_ID_F81216H: /* 128Bytes FIFO */
278 sio_write_mask_reg(pdata, FIFO_CTRL,
279 FIFO_MODE_MASK | RXFTHR_MODE_MASK,
280 FIFO_MODE_128 | RXFTHR_MODE_4X);
283 default: /* Default 16Bytes FIFO */
288 static void fintek_8250_goto_highspeed(struct uart_8250_port *uart,
289 struct fintek_8250 *pdata)
291 sio_write_reg(pdata, LDN, pdata->index);
293 switch (pdata->pid) {
294 case CHIP_ID_F81866: /* set uart clock for high speed serial mode */
295 sio_write_mask_reg(pdata, F81866_UART_CLK,
296 F81866_UART_CLK_MASK,
297 F81866_UART_CLK_14_769MHZ);
299 uart->port.uartclk = 921600 * 16;
301 default: /* leave clock speed untouched */
306 void fintek_8250_set_termios(struct uart_port *port, struct ktermios *termios,
307 struct ktermios *old)
309 struct fintek_8250 *pdata = port->private_data;
310 unsigned int baud = tty_termios_baud_rate(termios);
313 static u32 baudrate_table[] = {115200, 921600, 1152000, 1500000};
314 static u8 clock_table[] = { F81866_UART_CLK_1_8432MHZ,
315 F81866_UART_CLK_14_769MHZ, F81866_UART_CLK_18_432MHZ,
316 F81866_UART_CLK_24MHZ };
319 * We'll use serial8250_do_set_termios() for baud = 0, otherwise It'll
320 * crash on baudrate_table[i] % baud with "division by zero".
325 switch (pdata->pid) {
326 case CHIP_ID_F81216H:
330 reg = F81866_UART_CLK;
333 /* Don't change clocksource with unknown PID */
335 "%s: pid: %x Not support. use default set_termios.\n",
336 __func__, pdata->pid);
340 for (i = 0; i < ARRAY_SIZE(baudrate_table); ++i) {
341 if (baud > baudrate_table[i] || baudrate_table[i] % baud != 0)
344 if (port->uartclk == baudrate_table[i] * 16)
347 if (fintek_8250_enter_key(pdata->base_port, pdata->key))
350 port->uartclk = baudrate_table[i] * 16;
352 sio_write_reg(pdata, LDN, pdata->index);
353 sio_write_mask_reg(pdata, reg, F81866_UART_CLK_MASK,
356 fintek_8250_exit_key(pdata->base_port);
360 if (i == ARRAY_SIZE(baudrate_table)) {
361 baud = tty_termios_baud_rate(old);
362 tty_termios_encode_baud_rate(termios, baud, baud);
366 serial8250_do_set_termios(port, termios, old);
369 static void fintek_8250_set_termios_handler(struct uart_8250_port *uart)
371 struct fintek_8250 *pdata = uart->port.private_data;
373 switch (pdata->pid) {
374 case CHIP_ID_F81216H:
376 uart->port.set_termios = fintek_8250_set_termios;
384 static int probe_setup_port(struct fintek_8250 *pdata,
385 struct uart_8250_port *uart)
387 static const u16 addr[] = {0x4e, 0x2e};
388 static const u8 keys[] = {0x77, 0xa0, 0x87, 0x67};
389 struct irq_data *irq_data;
390 bool level_mode = false;
391 int i, j, k, min, max;
393 for (i = 0; i < ARRAY_SIZE(addr); i++) {
394 for (j = 0; j < ARRAY_SIZE(keys); j++) {
395 pdata->base_port = addr[i];
396 pdata->key = keys[j];
398 if (fintek_8250_enter_key(addr[i], keys[j]))
400 if (fintek_8250_check_id(pdata) ||
401 fintek_8250_get_ldn_range(pdata, &min, &max)) {
402 fintek_8250_exit_key(addr[i]);
406 for (k = min; k < max; k++) {
409 sio_write_reg(pdata, LDN, k);
410 aux = sio_read_reg(pdata, IO_ADDR1);
411 aux |= sio_read_reg(pdata, IO_ADDR2) << 8;
412 if (aux != uart->port.iobase)
417 irq_data = irq_get_irq_data(uart->port.irq);
420 irqd_is_level_type(irq_data);
422 fintek_8250_set_irq_mode(pdata, level_mode);
423 fintek_8250_set_max_fifo(pdata);
424 fintek_8250_goto_highspeed(uart, pdata);
426 fintek_8250_exit_key(addr[i]);
431 fintek_8250_exit_key(addr[i]);
438 static void fintek_8250_set_rs485_handler(struct uart_8250_port *uart)
440 struct fintek_8250 *pdata = uart->port.private_data;
442 switch (pdata->pid) {
443 case CHIP_ID_F81216AD:
444 case CHIP_ID_F81216H:
447 uart->port.rs485_config = fintek_8250_rs485_config;
450 default: /* No RS485 Auto direction functional */
455 int fintek_8250_probe(struct uart_8250_port *uart)
457 struct fintek_8250 *pdata;
458 struct fintek_8250 probe_data;
460 if (probe_setup_port(&probe_data, uart))
463 pdata = devm_kzalloc(uart->port.dev, sizeof(*pdata), GFP_KERNEL);
467 memcpy(pdata, &probe_data, sizeof(probe_data));
468 uart->port.private_data = pdata;
469 fintek_8250_set_rs485_handler(uart);
470 fintek_8250_set_termios_handler(uart);