1 // SPDX-License-Identifier: GPL-2.0
3 * 8250-core based driver for the OMAP internal UART
5 * based on omap-serial.c, Copyright (C) 2010 Texas Instruments.
7 * Copyright (C) 2014 Sebastian Andrzej Siewior
11 #include <linux/device.h>
13 #include <linux/module.h>
14 #include <linux/serial_8250.h>
15 #include <linux/serial_reg.h>
16 #include <linux/tty_flip.h>
17 #include <linux/platform_device.h>
18 #include <linux/slab.h>
20 #include <linux/of_device.h>
21 #include <linux/of_gpio.h>
22 #include <linux/of_irq.h>
23 #include <linux/delay.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/console.h>
26 #include <linux/pm_qos.h>
27 #include <linux/pm_wakeirq.h>
28 #include <linux/dma-mapping.h>
32 #define DEFAULT_CLK_SPEED 48000000
34 #define UART_ERRATA_i202_MDR1_ACCESS (1 << 0)
35 #define OMAP_UART_WER_HAS_TX_WAKEUP (1 << 1)
36 #define OMAP_DMA_TX_KICK (1 << 2)
38 * See Advisory 21 in AM437x errata SPRZ408B, updated April 2015.
39 * The same errata is applicable to AM335x and DRA7x processors too.
41 #define UART_ERRATA_CLOCK_DISABLE (1 << 3)
43 #define OMAP_UART_FCR_RX_TRIG 6
44 #define OMAP_UART_FCR_TX_TRIG 4
46 /* SCR register bitmasks */
47 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
48 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
49 #define OMAP_UART_SCR_TX_EMPTY (1 << 3)
50 #define OMAP_UART_SCR_DMAMODE_MASK (3 << 1)
51 #define OMAP_UART_SCR_DMAMODE_1 (1 << 1)
52 #define OMAP_UART_SCR_DMAMODE_CTL (1 << 0)
54 /* MVR register bitmasks */
55 #define OMAP_UART_MVR_SCHEME_SHIFT 30
56 #define OMAP_UART_LEGACY_MVR_MAJ_MASK 0xf0
57 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT 4
58 #define OMAP_UART_LEGACY_MVR_MIN_MASK 0x0f
59 #define OMAP_UART_MVR_MAJ_MASK 0x700
60 #define OMAP_UART_MVR_MAJ_SHIFT 8
61 #define OMAP_UART_MVR_MIN_MASK 0x3f
63 /* SYSC register bitmasks */
64 #define OMAP_UART_SYSC_SOFTRESET (1 << 1)
66 /* SYSS register bitmasks */
67 #define OMAP_UART_SYSS_RESETDONE (1 << 0)
69 #define UART_TI752_TLR_TX 0
70 #define UART_TI752_TLR_RX 4
72 #define TRIGGER_TLR_MASK(x) ((x & 0x3c) >> 2)
73 #define TRIGGER_FCR_MASK(x) (x & 3)
75 /* Enable XON/XOFF flow control on output */
76 #define OMAP_UART_SW_TX 0x08
77 /* Enable XON/XOFF flow control on input */
78 #define OMAP_UART_SW_RX 0x02
80 #define OMAP_UART_WER_MOD_WKUP 0x7f
81 #define OMAP_UART_TX_WAKEUP_EN (1 << 7)
86 #define OMAP_UART_TCR_RESTORE(x) ((x / 4) << 4)
87 #define OMAP_UART_TCR_HALT(x) ((x / 4) << 0)
89 #define UART_BUILD_REVISION(x, y) (((x) << 8) | (y))
91 #define OMAP_UART_REV_46 0x0406
92 #define OMAP_UART_REV_52 0x0502
93 #define OMAP_UART_REV_63 0x0603
95 struct omap8250_priv {
112 struct pm_qos_request pm_qos_request;
113 struct work_struct qos_work;
114 struct uart_8250_dma omap8250_dma;
115 spinlock_t rx_dma_lock;
120 #ifdef CONFIG_SERIAL_8250_DMA
121 static void omap_8250_rx_dma_flush(struct uart_8250_port *p);
123 static inline void omap_8250_rx_dma_flush(struct uart_8250_port *p) { }
126 static u32 uart_read(struct uart_8250_port *up, u32 reg)
128 return readl(up->port.membase + (reg << up->port.regshift));
131 static void omap8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
133 struct uart_8250_port *up = up_to_u8250p(port);
134 struct omap8250_priv *priv = up->port.private_data;
137 serial8250_do_set_mctrl(port, mctrl);
140 * Turn off autoRTS if RTS is lowered and restore autoRTS setting
143 lcr = serial_in(up, UART_LCR);
144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
145 if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
146 priv->efr |= UART_EFR_RTS;
148 priv->efr &= ~UART_EFR_RTS;
149 serial_out(up, UART_EFR, priv->efr);
150 serial_out(up, UART_LCR, lcr);
154 * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
155 * The access to uart register after MDR1 Access
156 * causes UART to corrupt data.
159 * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
160 * give 10 times as much
162 static void omap_8250_mdr1_errataset(struct uart_8250_port *up,
163 struct omap8250_priv *priv)
167 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
169 serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
170 UART_FCR_CLEAR_RCVR);
172 * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
173 * TX_FIFO_E bit is 1.
175 while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
176 (UART_LSR_THRE | UART_LSR_DR))) {
179 /* Should *never* happen. we warn and carry on */
180 dev_crit(up->port.dev, "Errata i202: timedout %x\n",
181 serial_in(up, UART_LSR));
188 static void omap_8250_get_divisor(struct uart_port *port, unsigned int baud,
189 struct omap8250_priv *priv)
191 unsigned int uartclk = port->uartclk;
192 unsigned int div_13, div_16;
193 unsigned int abs_d13, abs_d16;
196 * Old custom speed handling.
198 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST) {
199 priv->quot = port->custom_divisor & UART_DIV_MAX;
201 * I assume that nobody is using this. But hey, if somebody
202 * would like to specify the divisor _and_ the mode then the
203 * driver is ready and waiting for it.
205 if (port->custom_divisor & (1 << 16))
206 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
208 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
211 div_13 = DIV_ROUND_CLOSEST(uartclk, 13 * baud);
212 div_16 = DIV_ROUND_CLOSEST(uartclk, 16 * baud);
219 abs_d13 = abs(baud - uartclk / 13 / div_13);
220 abs_d16 = abs(baud - uartclk / 16 / div_16);
222 if (abs_d13 >= abs_d16) {
223 priv->mdr1 = UART_OMAP_MDR1_16X_MODE;
226 priv->mdr1 = UART_OMAP_MDR1_13X_MODE;
231 static void omap8250_update_scr(struct uart_8250_port *up,
232 struct omap8250_priv *priv)
236 old_scr = serial_in(up, UART_OMAP_SCR);
237 if (old_scr == priv->scr)
241 * The manual recommends not to enable the DMA mode selector in the SCR
242 * (instead of the FCR) register _and_ selecting the DMA mode as one
243 * register write because this may lead to malfunction.
245 if (priv->scr & OMAP_UART_SCR_DMAMODE_MASK)
246 serial_out(up, UART_OMAP_SCR,
247 priv->scr & ~OMAP_UART_SCR_DMAMODE_MASK);
248 serial_out(up, UART_OMAP_SCR, priv->scr);
251 static void omap8250_update_mdr1(struct uart_8250_port *up,
252 struct omap8250_priv *priv)
254 if (priv->habit & UART_ERRATA_i202_MDR1_ACCESS)
255 omap_8250_mdr1_errataset(up, priv);
257 serial_out(up, UART_OMAP_MDR1, priv->mdr1);
260 static void omap8250_restore_regs(struct uart_8250_port *up)
262 struct omap8250_priv *priv = up->port.private_data;
263 struct uart_8250_dma *dma = up->dma;
265 if (dma && dma->tx_running) {
267 * TCSANOW requests the change to occur immediately however if
268 * we have a TX-DMA operation in progress then it has been
269 * observed that it might stall and never complete. Therefore we
270 * delay DMA completes to prevent this hang from happen.
272 priv->delayed_restore = 1;
276 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
277 serial_out(up, UART_EFR, UART_EFR_ECB);
279 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
280 serial8250_out_MCR(up, UART_MCR_TCRTLR);
281 serial_out(up, UART_FCR, up->fcr);
283 omap8250_update_scr(up, priv);
285 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
287 serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_RESTORE(16) |
288 OMAP_UART_TCR_HALT(52));
289 serial_out(up, UART_TI752_TLR,
290 TRIGGER_TLR_MASK(TX_TRIGGER) << UART_TI752_TLR_TX |
291 TRIGGER_TLR_MASK(RX_TRIGGER) << UART_TI752_TLR_RX);
293 serial_out(up, UART_LCR, 0);
295 /* drop TCR + TLR access, we setup XON/XOFF later */
296 serial8250_out_MCR(up, up->mcr);
297 serial_out(up, UART_IER, up->ier);
299 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
300 serial_dl_write(up, priv->quot);
302 serial_out(up, UART_EFR, priv->efr);
304 /* Configure flow control */
305 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
306 serial_out(up, UART_XON1, priv->xon);
307 serial_out(up, UART_XOFF1, priv->xoff);
309 serial_out(up, UART_LCR, up->lcr);
311 omap8250_update_mdr1(up, priv);
313 up->port.ops->set_mctrl(&up->port, up->port.mctrl);
317 * OMAP can use "CLK / (16 or 13) / div" for baud rate. And then we have have
318 * some differences in how we want to handle flow control.
320 static void omap_8250_set_termios(struct uart_port *port,
321 struct ktermios *termios,
322 struct ktermios *old)
324 struct uart_8250_port *up = up_to_u8250p(port);
325 struct omap8250_priv *priv = up->port.private_data;
326 unsigned char cval = 0;
329 switch (termios->c_cflag & CSIZE) {
331 cval = UART_LCR_WLEN5;
334 cval = UART_LCR_WLEN6;
337 cval = UART_LCR_WLEN7;
341 cval = UART_LCR_WLEN8;
345 if (termios->c_cflag & CSTOPB)
346 cval |= UART_LCR_STOP;
347 if (termios->c_cflag & PARENB)
348 cval |= UART_LCR_PARITY;
349 if (!(termios->c_cflag & PARODD))
350 cval |= UART_LCR_EPAR;
351 if (termios->c_cflag & CMSPAR)
352 cval |= UART_LCR_SPAR;
355 * Ask the core to calculate the divisor for us.
357 baud = uart_get_baud_rate(port, termios, old,
358 port->uartclk / 16 / UART_DIV_MAX,
360 omap_8250_get_divisor(port, baud, priv);
363 * Ok, we're now changing the port state. Do it with
364 * interrupts disabled.
366 pm_runtime_get_sync(port->dev);
367 spin_lock_irq(&port->lock);
370 * Update the per-port timeout.
372 uart_update_timeout(port, termios->c_cflag, baud);
374 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
375 if (termios->c_iflag & INPCK)
376 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
377 if (termios->c_iflag & (IGNBRK | PARMRK))
378 up->port.read_status_mask |= UART_LSR_BI;
381 * Characters to ignore
383 up->port.ignore_status_mask = 0;
384 if (termios->c_iflag & IGNPAR)
385 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
386 if (termios->c_iflag & IGNBRK) {
387 up->port.ignore_status_mask |= UART_LSR_BI;
389 * If we're ignoring parity and break indicators,
390 * ignore overruns too (for real raw support).
392 if (termios->c_iflag & IGNPAR)
393 up->port.ignore_status_mask |= UART_LSR_OE;
397 * ignore all characters if CREAD is not set
399 if ((termios->c_cflag & CREAD) == 0)
400 up->port.ignore_status_mask |= UART_LSR_DR;
403 * Modem status interrupts
405 up->ier &= ~UART_IER_MSI;
406 if (UART_ENABLE_MS(&up->port, termios->c_cflag))
407 up->ier |= UART_IER_MSI;
410 /* Up to here it was mostly serial8250_do_set_termios() */
413 * We enable TRIG_GRANU for RX and TX and additionally we set
414 * SCR_TX_EMPTY bit. The result is the following:
415 * - RX_TRIGGER amount of bytes in the FIFO will cause an interrupt.
416 * - less than RX_TRIGGER number of bytes will also cause an interrupt
417 * once the UART decides that there no new bytes arriving.
418 * - Once THRE is enabled, the interrupt will be fired once the FIFO is
419 * empty - the trigger level is ignored here.
421 * Once DMA is enabled:
422 * - UART will assert the TX DMA line once there is room for TX_TRIGGER
423 * bytes in the TX FIFO. On each assert the DMA engine will move
424 * TX_TRIGGER bytes into the FIFO.
425 * - UART will assert the RX DMA line once there are RX_TRIGGER bytes in
426 * the FIFO and move RX_TRIGGER bytes.
427 * This is because threshold and trigger values are the same.
429 up->fcr = UART_FCR_ENABLE_FIFO;
430 up->fcr |= TRIGGER_FCR_MASK(TX_TRIGGER) << OMAP_UART_FCR_TX_TRIG;
431 up->fcr |= TRIGGER_FCR_MASK(RX_TRIGGER) << OMAP_UART_FCR_RX_TRIG;
433 priv->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK | OMAP_UART_SCR_TX_EMPTY |
434 OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
437 priv->scr |= OMAP_UART_SCR_DMAMODE_1 |
438 OMAP_UART_SCR_DMAMODE_CTL;
440 priv->xon = termios->c_cc[VSTART];
441 priv->xoff = termios->c_cc[VSTOP];
444 up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
446 if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
447 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
448 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
449 priv->efr |= UART_EFR_CTS;
450 } else if (up->port.flags & UPF_SOFT_FLOW) {
452 * OMAP rx s/w flow control is borked; the transmitter remains
453 * stuck off even if rx flow control is subsequently disabled
458 * Enable XON/XOFF flow control on output.
459 * Transmit XON1, XOFF1
461 if (termios->c_iflag & IXOFF) {
462 up->port.status |= UPSTAT_AUTOXOFF;
463 priv->efr |= OMAP_UART_SW_TX;
466 omap8250_restore_regs(up);
468 spin_unlock_irq(&up->port.lock);
469 pm_runtime_mark_last_busy(port->dev);
470 pm_runtime_put_autosuspend(port->dev);
472 /* calculate wakeup latency constraint */
473 priv->calc_latency = USEC_PER_SEC * 64 * 8 / baud;
474 priv->latency = priv->calc_latency;
476 schedule_work(&priv->qos_work);
478 /* Don't rewrite B0 */
479 if (tty_termios_baud_rate(termios))
480 tty_termios_encode_baud_rate(termios, baud, baud);
483 /* same as 8250 except that we may have extra flow bits set in EFR */
484 static void omap_8250_pm(struct uart_port *port, unsigned int state,
485 unsigned int oldstate)
487 struct uart_8250_port *up = up_to_u8250p(port);
490 pm_runtime_get_sync(port->dev);
491 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
492 efr = serial_in(up, UART_EFR);
493 serial_out(up, UART_EFR, efr | UART_EFR_ECB);
494 serial_out(up, UART_LCR, 0);
496 serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
497 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
498 serial_out(up, UART_EFR, efr);
499 serial_out(up, UART_LCR, 0);
501 pm_runtime_mark_last_busy(port->dev);
502 pm_runtime_put_autosuspend(port->dev);
505 static void omap_serial_fill_features_erratas(struct uart_8250_port *up,
506 struct omap8250_priv *priv)
509 u16 revision, major, minor;
511 mvr = uart_read(up, UART_OMAP_MVER);
513 /* Check revision register scheme */
514 scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
517 case 0: /* Legacy Scheme: OMAP2/3 */
518 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
519 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
520 OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
521 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
524 /* New Scheme: OMAP4+ */
525 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
526 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
527 OMAP_UART_MVR_MAJ_SHIFT;
528 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
531 dev_warn(up->port.dev,
532 "Unknown revision, defaulting to highest\n");
533 /* highest possible revision */
537 /* normalize revision for the driver */
538 revision = UART_BUILD_REVISION(major, minor);
541 case OMAP_UART_REV_46:
542 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS;
544 case OMAP_UART_REV_52:
545 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
546 OMAP_UART_WER_HAS_TX_WAKEUP;
548 case OMAP_UART_REV_63:
549 priv->habit |= UART_ERRATA_i202_MDR1_ACCESS |
550 OMAP_UART_WER_HAS_TX_WAKEUP;
557 static void omap8250_uart_qos_work(struct work_struct *work)
559 struct omap8250_priv *priv;
561 priv = container_of(work, struct omap8250_priv, qos_work);
562 pm_qos_update_request(&priv->pm_qos_request, priv->latency);
565 #ifdef CONFIG_SERIAL_8250_DMA
566 static int omap_8250_dma_handle_irq(struct uart_port *port);
569 static irqreturn_t omap8250_irq(int irq, void *dev_id)
571 struct uart_port *port = dev_id;
572 struct uart_8250_port *up = up_to_u8250p(port);
576 #ifdef CONFIG_SERIAL_8250_DMA
578 ret = omap_8250_dma_handle_irq(port);
579 return IRQ_RETVAL(ret);
583 serial8250_rpm_get(up);
584 iir = serial_port_in(port, UART_IIR);
585 ret = serial8250_handle_irq(port, iir);
586 serial8250_rpm_put(up);
588 return IRQ_RETVAL(ret);
591 static int omap_8250_startup(struct uart_port *port)
593 struct uart_8250_port *up = up_to_u8250p(port);
594 struct omap8250_priv *priv = port->private_data;
598 ret = dev_pm_set_dedicated_wake_irq(port->dev, priv->wakeirq);
603 pm_runtime_get_sync(port->dev);
606 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
608 serial_out(up, UART_LCR, UART_LCR_WLEN8);
610 up->lsr_saved_flags = 0;
611 up->msr_saved_flags = 0;
613 /* Disable DMA for console UART */
614 if (uart_console(port))
618 ret = serial8250_request_dma(up);
620 dev_warn_ratelimited(port->dev,
621 "failed to request DMA\n");
626 ret = request_irq(port->irq, omap8250_irq, IRQF_SHARED,
627 dev_name(port->dev), port);
631 up->ier = UART_IER_RLSI | UART_IER_RDI;
632 serial_out(up, UART_IER, up->ier);
635 up->capabilities |= UART_CAP_RPM;
638 /* Enable module level wake up */
639 priv->wer = OMAP_UART_WER_MOD_WKUP;
640 if (priv->habit & OMAP_UART_WER_HAS_TX_WAKEUP)
641 priv->wer |= OMAP_UART_TX_WAKEUP_EN;
642 serial_out(up, UART_OMAP_WER, priv->wer);
647 pm_runtime_mark_last_busy(port->dev);
648 pm_runtime_put_autosuspend(port->dev);
651 pm_runtime_mark_last_busy(port->dev);
652 pm_runtime_put_autosuspend(port->dev);
653 dev_pm_clear_wake_irq(port->dev);
657 static void omap_8250_shutdown(struct uart_port *port)
659 struct uart_8250_port *up = up_to_u8250p(port);
660 struct omap8250_priv *priv = port->private_data;
662 flush_work(&priv->qos_work);
664 omap_8250_rx_dma_flush(up);
666 pm_runtime_get_sync(port->dev);
668 serial_out(up, UART_OMAP_WER, 0);
671 serial_out(up, UART_IER, 0);
674 serial8250_release_dma(up);
677 * Disable break condition and FIFOs
679 if (up->lcr & UART_LCR_SBC)
680 serial_out(up, UART_LCR, up->lcr & ~UART_LCR_SBC);
681 serial_out(up, UART_FCR, UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
683 pm_runtime_mark_last_busy(port->dev);
684 pm_runtime_put_autosuspend(port->dev);
685 free_irq(port->irq, port);
686 dev_pm_clear_wake_irq(port->dev);
689 static void omap_8250_throttle(struct uart_port *port)
691 struct omap8250_priv *priv = port->private_data;
692 struct uart_8250_port *up = up_to_u8250p(port);
695 pm_runtime_get_sync(port->dev);
697 spin_lock_irqsave(&port->lock, flags);
698 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
699 serial_out(up, UART_IER, up->ier);
700 priv->throttled = true;
701 spin_unlock_irqrestore(&port->lock, flags);
703 pm_runtime_mark_last_busy(port->dev);
704 pm_runtime_put_autosuspend(port->dev);
707 static int omap_8250_rs485_config(struct uart_port *port,
708 struct serial_rs485 *rs485)
710 struct uart_8250_port *up = up_to_u8250p(port);
712 /* Clamp the delays to [0, 100ms] */
713 rs485->delay_rts_before_send = min(rs485->delay_rts_before_send, 100U);
714 rs485->delay_rts_after_send = min(rs485->delay_rts_after_send, 100U);
716 port->rs485 = *rs485;
719 * Both serial8250_em485_init and serial8250_em485_destroy
722 if (rs485->flags & SER_RS485_ENABLED) {
723 int ret = serial8250_em485_init(up);
726 rs485->flags &= ~SER_RS485_ENABLED;
727 port->rs485.flags &= ~SER_RS485_ENABLED;
732 serial8250_em485_destroy(up);
737 static void omap_8250_unthrottle(struct uart_port *port)
739 struct omap8250_priv *priv = port->private_data;
740 struct uart_8250_port *up = up_to_u8250p(port);
743 pm_runtime_get_sync(port->dev);
745 spin_lock_irqsave(&port->lock, flags);
746 priv->throttled = false;
749 up->ier |= UART_IER_RLSI | UART_IER_RDI;
750 serial_out(up, UART_IER, up->ier);
751 spin_unlock_irqrestore(&port->lock, flags);
753 pm_runtime_mark_last_busy(port->dev);
754 pm_runtime_put_autosuspend(port->dev);
757 #ifdef CONFIG_SERIAL_8250_DMA
758 static int omap_8250_rx_dma(struct uart_8250_port *p);
760 static void __dma_rx_do_complete(struct uart_8250_port *p)
762 struct omap8250_priv *priv = p->port.private_data;
763 struct uart_8250_dma *dma = p->dma;
764 struct tty_port *tty_port = &p->port.state->port;
765 struct dma_tx_state state;
770 spin_lock_irqsave(&priv->rx_dma_lock, flags);
772 if (!dma->rx_running)
776 dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
778 count = dma->rx_size - state.residue;
779 if (count < dma->rx_size)
780 dmaengine_terminate_async(dma->rxchan);
783 ret = tty_insert_flip_string(tty_port, dma->rx_buf, count);
785 p->port.icount.rx += ret;
786 p->port.icount.buf_overrun += count - ret;
788 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
790 tty_flip_buffer_push(tty_port);
793 static void __dma_rx_complete(void *param)
795 struct uart_8250_port *p = param;
796 struct omap8250_priv *priv = p->port.private_data;
797 struct uart_8250_dma *dma = p->dma;
798 struct dma_tx_state state;
801 spin_lock_irqsave(&p->port.lock, flags);
804 * If the tx status is not DMA_COMPLETE, then this is a delayed
805 * completion callback. A previous RX timeout flush would have
806 * already pushed the data, so exit.
808 if (dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state) !=
810 spin_unlock_irqrestore(&p->port.lock, flags);
813 __dma_rx_do_complete(p);
814 if (!priv->throttled)
817 spin_unlock_irqrestore(&p->port.lock, flags);
820 static void omap_8250_rx_dma_flush(struct uart_8250_port *p)
822 struct omap8250_priv *priv = p->port.private_data;
823 struct uart_8250_dma *dma = p->dma;
824 struct dma_tx_state state;
828 spin_lock_irqsave(&priv->rx_dma_lock, flags);
830 if (!dma->rx_running) {
831 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
835 ret = dmaengine_tx_status(dma->rxchan, dma->rx_cookie, &state);
836 if (ret == DMA_IN_PROGRESS) {
837 ret = dmaengine_pause(dma->rxchan);
838 if (WARN_ON_ONCE(ret))
839 priv->rx_dma_broken = true;
841 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
843 __dma_rx_do_complete(p);
846 static int omap_8250_rx_dma(struct uart_8250_port *p)
848 struct omap8250_priv *priv = p->port.private_data;
849 struct uart_8250_dma *dma = p->dma;
851 struct dma_async_tx_descriptor *desc;
854 if (priv->rx_dma_broken)
857 spin_lock_irqsave(&priv->rx_dma_lock, flags);
862 desc = dmaengine_prep_slave_single(dma->rxchan, dma->rx_addr,
863 dma->rx_size, DMA_DEV_TO_MEM,
864 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
871 desc->callback = __dma_rx_complete;
872 desc->callback_param = p;
874 dma->rx_cookie = dmaengine_submit(desc);
876 dma_async_issue_pending(dma->rxchan);
878 spin_unlock_irqrestore(&priv->rx_dma_lock, flags);
882 static int omap_8250_tx_dma(struct uart_8250_port *p);
884 static void omap_8250_dma_tx_complete(void *param)
886 struct uart_8250_port *p = param;
887 struct uart_8250_dma *dma = p->dma;
888 struct circ_buf *xmit = &p->port.state->xmit;
890 bool en_thri = false;
891 struct omap8250_priv *priv = p->port.private_data;
893 dma_sync_single_for_cpu(dma->txchan->device->dev, dma->tx_addr,
894 UART_XMIT_SIZE, DMA_TO_DEVICE);
896 spin_lock_irqsave(&p->port.lock, flags);
900 xmit->tail += dma->tx_size;
901 xmit->tail &= UART_XMIT_SIZE - 1;
902 p->port.icount.tx += dma->tx_size;
904 if (priv->delayed_restore) {
905 priv->delayed_restore = 0;
906 omap8250_restore_regs(p);
909 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
910 uart_write_wakeup(&p->port);
912 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&p->port)) {
915 ret = omap_8250_tx_dma(p);
919 } else if (p->capabilities & UART_CAP_RPM) {
925 p->ier |= UART_IER_THRI;
926 serial_port_out(&p->port, UART_IER, p->ier);
929 spin_unlock_irqrestore(&p->port.lock, flags);
932 static int omap_8250_tx_dma(struct uart_8250_port *p)
934 struct uart_8250_dma *dma = p->dma;
935 struct omap8250_priv *priv = p->port.private_data;
936 struct circ_buf *xmit = &p->port.state->xmit;
937 struct dma_async_tx_descriptor *desc;
938 unsigned int skip_byte = 0;
943 if (uart_tx_stopped(&p->port) || uart_circ_empty(xmit)) {
946 * Even if no data, we need to return an error for the two cases
947 * below so serial8250_tx_chars() is invoked and properly clears
948 * THRI and/or runtime suspend.
950 if (dma->tx_err || p->capabilities & UART_CAP_RPM) {
954 if (p->ier & UART_IER_THRI) {
955 p->ier &= ~UART_IER_THRI;
956 serial_out(p, UART_IER, p->ier);
961 dma->tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
962 if (priv->habit & OMAP_DMA_TX_KICK) {
966 * We need to put the first byte into the FIFO in order to start
967 * the DMA transfer. For transfers smaller than four bytes we
968 * don't bother doing DMA at all. It seem not matter if there
969 * are still bytes in the FIFO from the last transfer (in case
970 * we got here directly from omap_8250_dma_tx_complete()). Bytes
971 * leaving the FIFO seem not to trigger the DMA transfer. It is
972 * really the byte that we put into the FIFO.
973 * If the FIFO is already full then we most likely got here from
974 * omap_8250_dma_tx_complete(). And this means the DMA engine
975 * just completed its work. We don't have to wait the complete
976 * 86us at 115200,8n1 but around 60us (not to mention lower
977 * baudrates). So in that case we take the interrupt and try
978 * again with an empty FIFO.
980 tx_lvl = serial_in(p, UART_OMAP_TX_LVL);
981 if (tx_lvl == p->tx_loadsz) {
985 if (dma->tx_size < 4) {
992 desc = dmaengine_prep_slave_single(dma->txchan,
993 dma->tx_addr + xmit->tail + skip_byte,
994 dma->tx_size - skip_byte, DMA_MEM_TO_DEV,
995 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1001 dma->tx_running = 1;
1003 desc->callback = omap_8250_dma_tx_complete;
1004 desc->callback_param = p;
1006 dma->tx_cookie = dmaengine_submit(desc);
1008 dma_sync_single_for_device(dma->txchan->device->dev, dma->tx_addr,
1009 UART_XMIT_SIZE, DMA_TO_DEVICE);
1011 dma_async_issue_pending(dma->txchan);
1015 if (p->ier & UART_IER_THRI) {
1016 p->ier &= ~UART_IER_THRI;
1017 serial_out(p, UART_IER, p->ier);
1020 serial_out(p, UART_TX, xmit->buf[xmit->tail]);
1027 static bool handle_rx_dma(struct uart_8250_port *up, unsigned int iir)
1029 switch (iir & 0x3f) {
1031 case UART_IIR_RX_TIMEOUT:
1033 omap_8250_rx_dma_flush(up);
1036 return omap_8250_rx_dma(up);
1040 * This is mostly serial8250_handle_irq(). We have a slightly different DMA
1041 * hoook for RX/TX and need different logic for them in the ISR. Therefore we
1042 * use the default routine in the non-DMA case and this one for with DMA.
1044 static int omap_8250_dma_handle_irq(struct uart_port *port)
1046 struct uart_8250_port *up = up_to_u8250p(port);
1047 unsigned char status;
1048 unsigned long flags;
1051 serial8250_rpm_get(up);
1053 iir = serial_port_in(port, UART_IIR);
1054 if (iir & UART_IIR_NO_INT) {
1055 serial8250_rpm_put(up);
1059 spin_lock_irqsave(&port->lock, flags);
1061 status = serial_port_in(port, UART_LSR);
1063 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1064 if (handle_rx_dma(up, iir)) {
1065 status = serial8250_rx_chars(up, status);
1066 omap_8250_rx_dma(up);
1069 serial8250_modem_status(up);
1070 if (status & UART_LSR_THRE && up->dma->tx_err) {
1071 if (uart_tx_stopped(&up->port) ||
1072 uart_circ_empty(&up->port.state->xmit)) {
1073 up->dma->tx_err = 0;
1074 serial8250_tx_chars(up);
1077 * try again due to an earlier failer which
1078 * might have been resolved by now.
1080 if (omap_8250_tx_dma(up))
1081 serial8250_tx_chars(up);
1085 spin_unlock_irqrestore(&port->lock, flags);
1086 serial8250_rpm_put(up);
1090 static bool the_no_dma_filter_fn(struct dma_chan *chan, void *param)
1097 static inline int omap_8250_rx_dma(struct uart_8250_port *p)
1103 static int omap8250_no_handle_irq(struct uart_port *port)
1105 /* IRQ has not been requested but handling irq? */
1106 WARN_ONCE(1, "Unexpected irq handling before port startup\n");
1110 static const u8 omap4_habit = UART_ERRATA_CLOCK_DISABLE;
1111 static const u8 am3352_habit = OMAP_DMA_TX_KICK | UART_ERRATA_CLOCK_DISABLE;
1112 static const u8 dra742_habit = UART_ERRATA_CLOCK_DISABLE;
1114 static const struct of_device_id omap8250_dt_ids[] = {
1115 { .compatible = "ti,am654-uart" },
1116 { .compatible = "ti,omap2-uart" },
1117 { .compatible = "ti,omap3-uart" },
1118 { .compatible = "ti,omap4-uart", .data = &omap4_habit, },
1119 { .compatible = "ti,am3352-uart", .data = &am3352_habit, },
1120 { .compatible = "ti,am4372-uart", .data = &am3352_habit, },
1121 { .compatible = "ti,dra742-uart", .data = &dra742_habit, },
1124 MODULE_DEVICE_TABLE(of, omap8250_dt_ids);
1126 static int omap8250_probe(struct platform_device *pdev)
1128 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1129 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1130 struct omap8250_priv *priv;
1131 struct uart_8250_port up;
1133 void __iomem *membase;
1135 if (!regs || !irq) {
1136 dev_err(&pdev->dev, "missing registers or irq\n");
1140 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1144 membase = devm_ioremap_nocache(&pdev->dev, regs->start,
1145 resource_size(regs));
1149 memset(&up, 0, sizeof(up));
1150 up.port.dev = &pdev->dev;
1151 up.port.mapbase = regs->start;
1152 up.port.membase = membase;
1153 up.port.irq = irq->start;
1155 * It claims to be 16C750 compatible however it is a little different.
1156 * It has EFR and has no FCR7_64byte bit. The AFE (which it claims to
1157 * have) is enabled via EFR instead of MCR. The type is set here 8250
1158 * just to get things going. UNKNOWN does not work for a few reasons and
1159 * we don't need our own type since we don't use 8250's set_termios()
1162 up.port.type = PORT_8250;
1163 up.port.iotype = UPIO_MEM;
1164 up.port.flags = UPF_FIXED_PORT | UPF_FIXED_TYPE | UPF_SOFT_FLOW |
1166 up.port.private_data = priv;
1168 up.port.regshift = 2;
1169 up.port.fifosize = 64;
1171 up.capabilities = UART_CAP_FIFO;
1174 * Runtime PM is mostly transparent. However to do it right we need to a
1175 * TX empty interrupt before we can put the device to auto idle. So if
1176 * PM is not enabled we don't add that flag and can spare that one extra
1177 * interrupt in the TX path.
1179 up.capabilities |= UART_CAP_RPM;
1181 up.port.set_termios = omap_8250_set_termios;
1182 up.port.set_mctrl = omap8250_set_mctrl;
1183 up.port.pm = omap_8250_pm;
1184 up.port.startup = omap_8250_startup;
1185 up.port.shutdown = omap_8250_shutdown;
1186 up.port.throttle = omap_8250_throttle;
1187 up.port.unthrottle = omap_8250_unthrottle;
1188 up.port.rs485_config = omap_8250_rs485_config;
1190 if (pdev->dev.of_node) {
1191 const struct of_device_id *id;
1193 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1195 of_property_read_u32(pdev->dev.of_node, "clock-frequency",
1197 priv->wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1199 id = of_match_device(of_match_ptr(omap8250_dt_ids), &pdev->dev);
1201 priv->habit |= *(u8 *)id->data;
1206 dev_err(&pdev->dev, "failed to get alias/pdev id\n");
1211 if (!up.port.uartclk) {
1212 up.port.uartclk = DEFAULT_CLK_SPEED;
1213 dev_warn(&pdev->dev,
1214 "No clock speed specified: using default: %d\n",
1218 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1219 priv->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1220 pm_qos_add_request(&priv->pm_qos_request, PM_QOS_CPU_DMA_LATENCY,
1222 INIT_WORK(&priv->qos_work, omap8250_uart_qos_work);
1224 spin_lock_init(&priv->rx_dma_lock);
1226 device_init_wakeup(&pdev->dev, true);
1227 pm_runtime_enable(&pdev->dev);
1228 pm_runtime_use_autosuspend(&pdev->dev);
1229 pm_runtime_set_autosuspend_delay(&pdev->dev, -1);
1231 pm_runtime_irq_safe(&pdev->dev);
1233 pm_runtime_get_sync(&pdev->dev);
1235 omap_serial_fill_features_erratas(&up, priv);
1236 up.port.handle_irq = omap8250_no_handle_irq;
1237 #ifdef CONFIG_SERIAL_8250_DMA
1238 if (pdev->dev.of_node) {
1240 * Oh DMA support. If there are no DMA properties in the DT then
1241 * we will fall back to a generic DMA channel which does not
1242 * really work here. To ensure that we do not get a generic DMA
1243 * channel assigned, we have the the_no_dma_filter_fn() here.
1244 * To avoid "failed to request DMA" messages we check for DMA
1247 ret = of_property_count_strings(pdev->dev.of_node, "dma-names");
1249 up.dma = &priv->omap8250_dma;
1250 priv->omap8250_dma.fn = the_no_dma_filter_fn;
1251 priv->omap8250_dma.tx_dma = omap_8250_tx_dma;
1252 priv->omap8250_dma.rx_dma = omap_8250_rx_dma;
1253 priv->omap8250_dma.rx_size = RX_TRIGGER;
1254 priv->omap8250_dma.rxconf.src_maxburst = RX_TRIGGER;
1255 priv->omap8250_dma.txconf.dst_maxburst = TX_TRIGGER;
1259 ret = serial8250_register_8250_port(&up);
1261 dev_err(&pdev->dev, "unable to register 8250 port\n");
1265 platform_set_drvdata(pdev, priv);
1266 pm_runtime_mark_last_busy(&pdev->dev);
1267 pm_runtime_put_autosuspend(&pdev->dev);
1270 pm_runtime_dont_use_autosuspend(&pdev->dev);
1271 pm_runtime_put_sync(&pdev->dev);
1272 pm_runtime_disable(&pdev->dev);
1276 static int omap8250_remove(struct platform_device *pdev)
1278 struct omap8250_priv *priv = platform_get_drvdata(pdev);
1280 pm_runtime_dont_use_autosuspend(&pdev->dev);
1281 pm_runtime_put_sync(&pdev->dev);
1282 pm_runtime_disable(&pdev->dev);
1283 serial8250_unregister_port(priv->line);
1284 pm_qos_remove_request(&priv->pm_qos_request);
1285 device_init_wakeup(&pdev->dev, false);
1289 #ifdef CONFIG_PM_SLEEP
1290 static int omap8250_prepare(struct device *dev)
1292 struct omap8250_priv *priv = dev_get_drvdata(dev);
1296 priv->is_suspending = true;
1300 static void omap8250_complete(struct device *dev)
1302 struct omap8250_priv *priv = dev_get_drvdata(dev);
1306 priv->is_suspending = false;
1309 static int omap8250_suspend(struct device *dev)
1311 struct omap8250_priv *priv = dev_get_drvdata(dev);
1312 struct uart_8250_port *up = serial8250_get_port(priv->line);
1314 serial8250_suspend_port(priv->line);
1316 pm_runtime_get_sync(dev);
1317 if (!device_may_wakeup(dev))
1319 serial_out(up, UART_OMAP_WER, priv->wer);
1320 pm_runtime_mark_last_busy(dev);
1321 pm_runtime_put_autosuspend(dev);
1323 flush_work(&priv->qos_work);
1327 static int omap8250_resume(struct device *dev)
1329 struct omap8250_priv *priv = dev_get_drvdata(dev);
1331 serial8250_resume_port(priv->line);
1335 #define omap8250_prepare NULL
1336 #define omap8250_complete NULL
1340 static int omap8250_lost_context(struct uart_8250_port *up)
1344 val = serial_in(up, UART_OMAP_SCR);
1346 * If we lose context, then SCR is set to its reset value of zero.
1347 * After set_termios() we set bit 3 of SCR (TX_EMPTY_CTL_IT) to 1,
1348 * among other bits, to never set the register back to zero again.
1355 /* TODO: in future, this should happen via API in drivers/reset/ */
1356 static int omap8250_soft_reset(struct device *dev)
1358 struct omap8250_priv *priv = dev_get_drvdata(dev);
1359 struct uart_8250_port *up = serial8250_get_port(priv->line);
1365 * At least on omap4, unused uarts may not idle after reset without
1366 * a basic scr dma configuration even with no dma in use. The
1367 * module clkctrl status bits will be 1 instead of 3 blocking idle
1368 * for the whole clockdomain. The softreset below will clear scr,
1369 * and we restore it on resume so this is safe to do on all SoCs
1370 * needing omap8250_soft_reset() quirk. Do it in two writes as
1371 * recommended in the comment for omap8250_update_scr().
1373 serial_out(up, UART_OMAP_SCR, OMAP_UART_SCR_DMAMODE_1);
1374 serial_out(up, UART_OMAP_SCR,
1375 OMAP_UART_SCR_DMAMODE_1 | OMAP_UART_SCR_DMAMODE_CTL);
1377 sysc = serial_in(up, UART_OMAP_SYSC);
1379 /* softreset the UART */
1380 sysc |= OMAP_UART_SYSC_SOFTRESET;
1381 serial_out(up, UART_OMAP_SYSC, sysc);
1383 /* By experiments, 1us enough for reset complete on AM335x */
1386 syss = serial_in(up, UART_OMAP_SYSS);
1387 } while (--timeout && !(syss & OMAP_UART_SYSS_RESETDONE));
1390 dev_err(dev, "timed out waiting for reset done\n");
1397 static int omap8250_runtime_suspend(struct device *dev)
1399 struct omap8250_priv *priv = dev_get_drvdata(dev);
1400 struct uart_8250_port *up;
1402 /* In case runtime-pm tries this before we are setup */
1406 up = serial8250_get_port(priv->line);
1408 * When using 'no_console_suspend', the console UART must not be
1409 * suspended. Since driver suspend is managed by runtime suspend,
1410 * preventing runtime suspend (by returning error) will keep device
1411 * active during suspend.
1413 if (priv->is_suspending && !console_suspend_enabled) {
1414 if (uart_console(&up->port))
1418 if (priv->habit & UART_ERRATA_CLOCK_DISABLE) {
1421 ret = omap8250_soft_reset(dev);
1425 /* Restore to UART mode after reset (for wakeup) */
1426 omap8250_update_mdr1(up, priv);
1427 /* Restore wakeup enable register */
1428 serial_out(up, UART_OMAP_WER, priv->wer);
1431 if (up->dma && up->dma->rxchan)
1432 omap_8250_rx_dma_flush(up);
1434 priv->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
1435 schedule_work(&priv->qos_work);
1440 static int omap8250_runtime_resume(struct device *dev)
1442 struct omap8250_priv *priv = dev_get_drvdata(dev);
1443 struct uart_8250_port *up;
1445 /* In case runtime-pm tries this before we are setup */
1449 up = serial8250_get_port(priv->line);
1451 if (omap8250_lost_context(up))
1452 omap8250_restore_regs(up);
1454 if (up->dma && up->dma->rxchan)
1455 omap_8250_rx_dma(up);
1457 priv->latency = priv->calc_latency;
1458 schedule_work(&priv->qos_work);
1463 #ifdef CONFIG_SERIAL_8250_OMAP_TTYO_FIXUP
1464 static int __init omap8250_console_fixup(void)
1470 if (strstr(boot_command_line, "console=ttyS"))
1471 /* user set a ttyS based name for the console */
1474 omap_str = strstr(boot_command_line, "console=ttyO");
1476 /* user did not set ttyO based console, so we don't care */
1480 if ('0' <= *omap_str && *omap_str <= '9')
1481 idx = *omap_str - '0';
1486 if (omap_str[0] == ',') {
1493 add_preferred_console("ttyS", idx, options);
1494 pr_err("WARNING: Your 'console=ttyO%d' has been replaced by 'ttyS%d'\n",
1496 pr_err("This ensures that you still see kernel messages. Please\n");
1497 pr_err("update your kernel commandline.\n");
1500 console_initcall(omap8250_console_fixup);
1503 static const struct dev_pm_ops omap8250_dev_pm_ops = {
1504 SET_SYSTEM_SLEEP_PM_OPS(omap8250_suspend, omap8250_resume)
1505 SET_RUNTIME_PM_OPS(omap8250_runtime_suspend,
1506 omap8250_runtime_resume, NULL)
1507 .prepare = omap8250_prepare,
1508 .complete = omap8250_complete,
1511 static struct platform_driver omap8250_platform_driver = {
1514 .pm = &omap8250_dev_pm_ops,
1515 .of_match_table = omap8250_dt_ids,
1517 .probe = omap8250_probe,
1518 .remove = omap8250_remove,
1520 module_platform_driver(omap8250_platform_driver);
1522 MODULE_AUTHOR("Sebastian Andrzej Siewior");
1523 MODULE_DESCRIPTION("OMAP 8250 Driver");
1524 MODULE_LICENSE("GPL v2");