2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
61 #include <linux/acpi.h>
63 #include "amba-pl011.h"
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
71 #define AMBA_ISR_PASS_LIMIT 256
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_FR] = UART01x_FR,
79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
92 /* There is by now at least one vendor with differing details, so handle it */
94 const u16 *reg_offset;
103 bool cts_event_workaround;
107 unsigned int (*get_fifosize)(struct amba_device *dev);
110 static unsigned int get_fifosize_arm(struct amba_device *dev)
112 return amba_rev(dev) < 3 ? 16 : 32;
115 static struct vendor_data vendor_arm = {
116 .reg_offset = pl011_std_offsets,
117 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
118 .fr_busy = UART01x_FR_BUSY,
119 .fr_dsr = UART01x_FR_DSR,
120 .fr_cts = UART01x_FR_CTS,
121 .fr_ri = UART011_FR_RI,
122 .oversampling = false,
123 .dma_threshold = false,
124 .cts_event_workaround = false,
125 .always_enabled = false,
126 .fixed_options = false,
127 .get_fifosize = get_fifosize_arm,
130 static struct vendor_data vendor_sbsa = {
131 .reg_offset = pl011_std_offsets,
132 .fr_busy = UART01x_FR_BUSY,
133 .fr_dsr = UART01x_FR_DSR,
134 .fr_cts = UART01x_FR_CTS,
135 .fr_ri = UART011_FR_RI,
137 .oversampling = false,
138 .dma_threshold = false,
139 .cts_event_workaround = false,
140 .always_enabled = true,
141 .fixed_options = true,
144 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
145 [REG_DR] = UART01x_DR,
146 [REG_ST_DMAWM] = ST_UART011_DMAWM,
147 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
148 [REG_FR] = UART01x_FR,
149 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
150 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
151 [REG_IBRD] = UART011_IBRD,
152 [REG_FBRD] = UART011_FBRD,
153 [REG_CR] = UART011_CR,
154 [REG_IFLS] = UART011_IFLS,
155 [REG_IMSC] = UART011_IMSC,
156 [REG_RIS] = UART011_RIS,
157 [REG_MIS] = UART011_MIS,
158 [REG_ICR] = UART011_ICR,
159 [REG_DMACR] = UART011_DMACR,
160 [REG_ST_XFCR] = ST_UART011_XFCR,
161 [REG_ST_XON1] = ST_UART011_XON1,
162 [REG_ST_XON2] = ST_UART011_XON2,
163 [REG_ST_XOFF1] = ST_UART011_XOFF1,
164 [REG_ST_XOFF2] = ST_UART011_XOFF2,
165 [REG_ST_ITCR] = ST_UART011_ITCR,
166 [REG_ST_ITIP] = ST_UART011_ITIP,
167 [REG_ST_ABCR] = ST_UART011_ABCR,
168 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
171 static unsigned int get_fifosize_st(struct amba_device *dev)
176 static struct vendor_data vendor_st = {
177 .reg_offset = pl011_st_offsets,
178 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
179 .fr_busy = UART01x_FR_BUSY,
180 .fr_dsr = UART01x_FR_DSR,
181 .fr_cts = UART01x_FR_CTS,
182 .fr_ri = UART011_FR_RI,
183 .oversampling = true,
184 .dma_threshold = true,
185 .cts_event_workaround = true,
186 .always_enabled = false,
187 .fixed_options = false,
188 .get_fifosize = get_fifosize_st,
191 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
192 [REG_DR] = ZX_UART011_DR,
193 [REG_FR] = ZX_UART011_FR,
194 [REG_LCRH_RX] = ZX_UART011_LCRH,
195 [REG_LCRH_TX] = ZX_UART011_LCRH,
196 [REG_IBRD] = ZX_UART011_IBRD,
197 [REG_FBRD] = ZX_UART011_FBRD,
198 [REG_CR] = ZX_UART011_CR,
199 [REG_IFLS] = ZX_UART011_IFLS,
200 [REG_IMSC] = ZX_UART011_IMSC,
201 [REG_RIS] = ZX_UART011_RIS,
202 [REG_MIS] = ZX_UART011_MIS,
203 [REG_ICR] = ZX_UART011_ICR,
204 [REG_DMACR] = ZX_UART011_DMACR,
207 static unsigned int get_fifosize_zte(struct amba_device *dev)
212 static struct vendor_data vendor_zte = {
213 .reg_offset = pl011_zte_offsets,
215 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
216 .fr_busy = ZX_UART01x_FR_BUSY,
217 .fr_dsr = ZX_UART01x_FR_DSR,
218 .fr_cts = ZX_UART01x_FR_CTS,
219 .fr_ri = ZX_UART011_FR_RI,
220 .get_fifosize = get_fifosize_zte,
223 /* Deals with DMA transactions */
226 struct scatterlist sg;
230 struct pl011_dmarx_data {
231 struct dma_chan *chan;
232 struct completion complete;
234 struct pl011_sgbuf sgbuf_a;
235 struct pl011_sgbuf sgbuf_b;
238 struct timer_list timer;
239 unsigned int last_residue;
240 unsigned long last_jiffies;
242 unsigned int poll_rate;
243 unsigned int poll_timeout;
246 struct pl011_dmatx_data {
247 struct dma_chan *chan;
248 struct scatterlist sg;
254 * We wrap our port structure around the generic uart_port.
256 struct uart_amba_port {
257 struct uart_port port;
258 const u16 *reg_offset;
260 const struct vendor_data *vendor;
261 unsigned int dmacr; /* dma control reg */
262 unsigned int im; /* interrupt mask */
263 unsigned int old_status;
264 unsigned int fifosize; /* vendor-specific */
265 unsigned int old_cr; /* state during shutdown */
267 unsigned int fixed_baud; /* vendor-set fixed baud rate */
269 #ifdef CONFIG_DMA_ENGINE
273 struct pl011_dmarx_data dmarx;
274 struct pl011_dmatx_data dmatx;
279 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
282 return uap->reg_offset[reg];
285 static unsigned int pl011_read(const struct uart_amba_port *uap,
288 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
290 return (uap->port.iotype == UPIO_MEM32) ?
291 readl_relaxed(addr) : readw_relaxed(addr);
294 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
297 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
299 if (uap->port.iotype == UPIO_MEM32)
300 writel_relaxed(val, addr);
302 writew_relaxed(val, addr);
306 * Reads up to 256 characters from the FIFO or until it's empty and
307 * inserts them into the TTY layer. Returns the number of characters
308 * read from the FIFO.
310 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
313 unsigned int ch, flag, max_count = 256;
316 while (max_count--) {
317 status = pl011_read(uap, REG_FR);
318 if (status & UART01x_FR_RXFE)
321 /* Take chars from the FIFO and update status */
322 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
324 uap->port.icount.rx++;
327 if (unlikely(ch & UART_DR_ERROR)) {
328 if (ch & UART011_DR_BE) {
329 ch &= ~(UART011_DR_FE | UART011_DR_PE);
330 uap->port.icount.brk++;
331 if (uart_handle_break(&uap->port))
333 } else if (ch & UART011_DR_PE)
334 uap->port.icount.parity++;
335 else if (ch & UART011_DR_FE)
336 uap->port.icount.frame++;
337 if (ch & UART011_DR_OE)
338 uap->port.icount.overrun++;
340 ch &= uap->port.read_status_mask;
342 if (ch & UART011_DR_BE)
344 else if (ch & UART011_DR_PE)
346 else if (ch & UART011_DR_FE)
350 if (uart_handle_sysrq_char(&uap->port, ch & 255))
353 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
361 * All the DMA operation mode stuff goes inside this ifdef.
362 * This assumes that you have a generic DMA device interface,
363 * no custom DMA interfaces are supported.
365 #ifdef CONFIG_DMA_ENGINE
367 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
369 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
370 enum dma_data_direction dir)
374 sg->buf = dma_alloc_coherent(chan->device->dev,
375 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
379 sg_init_table(&sg->sg, 1);
380 sg_set_page(&sg->sg, phys_to_page(dma_addr),
381 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
382 sg_dma_address(&sg->sg) = dma_addr;
383 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
388 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
389 enum dma_data_direction dir)
392 dma_free_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, sg->buf,
394 sg_dma_address(&sg->sg));
398 static void pl011_dma_probe(struct uart_amba_port *uap)
400 /* DMA is the sole user of the platform data right now */
401 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
402 struct device *dev = uap->port.dev;
403 struct dma_slave_config tx_conf = {
404 .dst_addr = uap->port.mapbase +
405 pl011_reg_to_offset(uap, REG_DR),
406 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
407 .direction = DMA_MEM_TO_DEV,
408 .dst_maxburst = uap->fifosize >> 1,
411 struct dma_chan *chan;
414 uap->dma_probed = true;
415 chan = dma_request_slave_channel_reason(dev, "tx");
417 if (PTR_ERR(chan) == -EPROBE_DEFER) {
418 uap->dma_probed = false;
422 /* We need platform data */
423 if (!plat || !plat->dma_filter) {
424 dev_info(uap->port.dev, "no DMA platform data\n");
428 /* Try to acquire a generic DMA engine slave TX channel */
430 dma_cap_set(DMA_SLAVE, mask);
432 chan = dma_request_channel(mask, plat->dma_filter,
435 dev_err(uap->port.dev, "no TX DMA channel!\n");
440 dmaengine_slave_config(chan, &tx_conf);
441 uap->dmatx.chan = chan;
443 dev_info(uap->port.dev, "DMA channel TX %s\n",
444 dma_chan_name(uap->dmatx.chan));
446 /* Optionally make use of an RX channel as well */
447 chan = dma_request_slave_channel(dev, "rx");
449 if (!chan && plat && plat->dma_rx_param) {
450 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
453 dev_err(uap->port.dev, "no RX DMA channel!\n");
459 struct dma_slave_config rx_conf = {
460 .src_addr = uap->port.mapbase +
461 pl011_reg_to_offset(uap, REG_DR),
462 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
463 .direction = DMA_DEV_TO_MEM,
464 .src_maxburst = uap->fifosize >> 2,
467 struct dma_slave_caps caps;
470 * Some DMA controllers provide information on their capabilities.
471 * If the controller does, check for suitable residue processing
472 * otherwise assime all is well.
474 if (0 == dma_get_slave_caps(chan, &caps)) {
475 if (caps.residue_granularity ==
476 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
477 dma_release_channel(chan);
478 dev_info(uap->port.dev,
479 "RX DMA disabled - no residue processing\n");
483 dmaengine_slave_config(chan, &rx_conf);
484 uap->dmarx.chan = chan;
486 uap->dmarx.auto_poll_rate = false;
487 if (plat && plat->dma_rx_poll_enable) {
488 /* Set poll rate if specified. */
489 if (plat->dma_rx_poll_rate) {
490 uap->dmarx.auto_poll_rate = false;
491 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
494 * 100 ms defaults to poll rate if not
495 * specified. This will be adjusted with
496 * the baud rate at set_termios.
498 uap->dmarx.auto_poll_rate = true;
499 uap->dmarx.poll_rate = 100;
501 /* 3 secs defaults poll_timeout if not specified. */
502 if (plat->dma_rx_poll_timeout)
503 uap->dmarx.poll_timeout =
504 plat->dma_rx_poll_timeout;
506 uap->dmarx.poll_timeout = 3000;
507 } else if (!plat && dev->of_node) {
508 uap->dmarx.auto_poll_rate = of_property_read_bool(
509 dev->of_node, "auto-poll");
510 if (uap->dmarx.auto_poll_rate) {
513 if (0 == of_property_read_u32(dev->of_node,
515 uap->dmarx.poll_rate = x;
517 uap->dmarx.poll_rate = 100;
518 if (0 == of_property_read_u32(dev->of_node,
519 "poll-timeout-ms", &x))
520 uap->dmarx.poll_timeout = x;
522 uap->dmarx.poll_timeout = 3000;
525 dev_info(uap->port.dev, "DMA channel RX %s\n",
526 dma_chan_name(uap->dmarx.chan));
530 static void pl011_dma_remove(struct uart_amba_port *uap)
533 dma_release_channel(uap->dmatx.chan);
535 dma_release_channel(uap->dmarx.chan);
538 /* Forward declare these for the refill routine */
539 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
540 static void pl011_start_tx_pio(struct uart_amba_port *uap);
543 * The current DMA TX buffer has been sent.
544 * Try to queue up another DMA buffer.
546 static void pl011_dma_tx_callback(void *data)
548 struct uart_amba_port *uap = data;
549 struct pl011_dmatx_data *dmatx = &uap->dmatx;
553 spin_lock_irqsave(&uap->port.lock, flags);
554 if (uap->dmatx.queued)
555 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
559 uap->dmacr = dmacr & ~UART011_TXDMAE;
560 pl011_write(uap->dmacr, uap, REG_DMACR);
563 * If TX DMA was disabled, it means that we've stopped the DMA for
564 * some reason (eg, XOFF received, or we want to send an X-char.)
566 * Note: we need to be careful here of a potential race between DMA
567 * and the rest of the driver - if the driver disables TX DMA while
568 * a TX buffer completing, we must update the tx queued status to
569 * get further refills (hence we check dmacr).
571 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
572 uart_circ_empty(&uap->port.state->xmit)) {
573 uap->dmatx.queued = false;
574 spin_unlock_irqrestore(&uap->port.lock, flags);
578 if (pl011_dma_tx_refill(uap) <= 0)
580 * We didn't queue a DMA buffer for some reason, but we
581 * have data pending to be sent. Re-enable the TX IRQ.
583 pl011_start_tx_pio(uap);
585 spin_unlock_irqrestore(&uap->port.lock, flags);
589 * Try to refill the TX DMA buffer.
590 * Locking: called with port lock held and IRQs disabled.
592 * 1 if we queued up a TX DMA buffer.
593 * 0 if we didn't want to handle this by DMA
596 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
598 struct pl011_dmatx_data *dmatx = &uap->dmatx;
599 struct dma_chan *chan = dmatx->chan;
600 struct dma_device *dma_dev = chan->device;
601 struct dma_async_tx_descriptor *desc;
602 struct circ_buf *xmit = &uap->port.state->xmit;
606 * Try to avoid the overhead involved in using DMA if the
607 * transaction fits in the first half of the FIFO, by using
608 * the standard interrupt handling. This ensures that we
609 * issue a uart_write_wakeup() at the appropriate time.
611 count = uart_circ_chars_pending(xmit);
612 if (count < (uap->fifosize >> 1)) {
613 uap->dmatx.queued = false;
618 * Bodge: don't send the last character by DMA, as this
619 * will prevent XON from notifying us to restart DMA.
623 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
624 if (count > PL011_DMA_BUFFER_SIZE)
625 count = PL011_DMA_BUFFER_SIZE;
627 if (xmit->tail < xmit->head)
628 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
630 size_t first = UART_XMIT_SIZE - xmit->tail;
635 second = count - first;
637 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
639 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
642 dmatx->sg.length = count;
644 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
645 uap->dmatx.queued = false;
646 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
650 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
651 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
653 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
654 uap->dmatx.queued = false;
656 * If DMA cannot be used right now, we complete this
657 * transaction via IRQ and let the TTY layer retry.
659 dev_dbg(uap->port.dev, "TX DMA busy\n");
663 /* Some data to go along to the callback */
664 desc->callback = pl011_dma_tx_callback;
665 desc->callback_param = uap;
667 /* All errors should happen at prepare time */
668 dmaengine_submit(desc);
670 /* Fire the DMA transaction */
671 dma_dev->device_issue_pending(chan);
673 uap->dmacr |= UART011_TXDMAE;
674 pl011_write(uap->dmacr, uap, REG_DMACR);
675 uap->dmatx.queued = true;
678 * Now we know that DMA will fire, so advance the ring buffer
679 * with the stuff we just dispatched.
681 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
682 uap->port.icount.tx += count;
684 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
685 uart_write_wakeup(&uap->port);
691 * We received a transmit interrupt without a pending X-char but with
692 * pending characters.
693 * Locking: called with port lock held and IRQs disabled.
695 * false if we want to use PIO to transmit
696 * true if we queued a DMA buffer
698 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
700 if (!uap->using_tx_dma)
704 * If we already have a TX buffer queued, but received a
705 * TX interrupt, it will be because we've just sent an X-char.
706 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
708 if (uap->dmatx.queued) {
709 uap->dmacr |= UART011_TXDMAE;
710 pl011_write(uap->dmacr, uap, REG_DMACR);
711 uap->im &= ~UART011_TXIM;
712 pl011_write(uap->im, uap, REG_IMSC);
717 * We don't have a TX buffer queued, so try to queue one.
718 * If we successfully queued a buffer, mask the TX IRQ.
720 if (pl011_dma_tx_refill(uap) > 0) {
721 uap->im &= ~UART011_TXIM;
722 pl011_write(uap->im, uap, REG_IMSC);
729 * Stop the DMA transmit (eg, due to received XOFF).
730 * Locking: called with port lock held and IRQs disabled.
732 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
734 if (uap->dmatx.queued) {
735 uap->dmacr &= ~UART011_TXDMAE;
736 pl011_write(uap->dmacr, uap, REG_DMACR);
741 * Try to start a DMA transmit, or in the case of an XON/OFF
742 * character queued for send, try to get that character out ASAP.
743 * Locking: called with port lock held and IRQs disabled.
745 * false if we want the TX IRQ to be enabled
746 * true if we have a buffer queued
748 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
752 if (!uap->using_tx_dma)
755 if (!uap->port.x_char) {
756 /* no X-char, try to push chars out in DMA mode */
759 if (!uap->dmatx.queued) {
760 if (pl011_dma_tx_refill(uap) > 0) {
761 uap->im &= ~UART011_TXIM;
762 pl011_write(uap->im, uap, REG_IMSC);
765 } else if (!(uap->dmacr & UART011_TXDMAE)) {
766 uap->dmacr |= UART011_TXDMAE;
767 pl011_write(uap->dmacr, uap, REG_DMACR);
773 * We have an X-char to send. Disable DMA to prevent it loading
774 * the TX fifo, and then see if we can stuff it into the FIFO.
777 uap->dmacr &= ~UART011_TXDMAE;
778 pl011_write(uap->dmacr, uap, REG_DMACR);
780 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
782 * No space in the FIFO, so enable the transmit interrupt
783 * so we know when there is space. Note that once we've
784 * loaded the character, we should just re-enable DMA.
789 pl011_write(uap->port.x_char, uap, REG_DR);
790 uap->port.icount.tx++;
791 uap->port.x_char = 0;
793 /* Success - restore the DMA state */
795 pl011_write(dmacr, uap, REG_DMACR);
801 * Flush the transmit buffer.
802 * Locking: called with port lock held and IRQs disabled.
804 static void pl011_dma_flush_buffer(struct uart_port *port)
805 __releases(&uap->port.lock)
806 __acquires(&uap->port.lock)
808 struct uart_amba_port *uap =
809 container_of(port, struct uart_amba_port, port);
811 if (!uap->using_tx_dma)
814 dmaengine_terminate_async(uap->dmatx.chan);
816 if (uap->dmatx.queued) {
817 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
819 uap->dmatx.queued = false;
820 uap->dmacr &= ~UART011_TXDMAE;
821 pl011_write(uap->dmacr, uap, REG_DMACR);
825 static void pl011_dma_rx_callback(void *data);
827 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
829 struct dma_chan *rxchan = uap->dmarx.chan;
830 struct pl011_dmarx_data *dmarx = &uap->dmarx;
831 struct dma_async_tx_descriptor *desc;
832 struct pl011_sgbuf *sgbuf;
837 /* Start the RX DMA job */
838 sgbuf = uap->dmarx.use_buf_b ?
839 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
840 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
842 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
844 * If the DMA engine is busy and cannot prepare a
845 * channel, no big deal, the driver will fall back
846 * to interrupt mode as a result of this error code.
849 uap->dmarx.running = false;
850 dmaengine_terminate_all(rxchan);
854 /* Some data to go along to the callback */
855 desc->callback = pl011_dma_rx_callback;
856 desc->callback_param = uap;
857 dmarx->cookie = dmaengine_submit(desc);
858 dma_async_issue_pending(rxchan);
860 uap->dmacr |= UART011_RXDMAE;
861 pl011_write(uap->dmacr, uap, REG_DMACR);
862 uap->dmarx.running = true;
864 uap->im &= ~UART011_RXIM;
865 pl011_write(uap->im, uap, REG_IMSC);
871 * This is called when either the DMA job is complete, or
872 * the FIFO timeout interrupt occurred. This must be called
873 * with the port spinlock uap->port.lock held.
875 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
876 u32 pending, bool use_buf_b,
879 struct tty_port *port = &uap->port.state->port;
880 struct pl011_sgbuf *sgbuf = use_buf_b ?
881 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
883 u32 fifotaken = 0; /* only used for vdbg() */
885 struct pl011_dmarx_data *dmarx = &uap->dmarx;
888 if (uap->dmarx.poll_rate) {
889 /* The data can be taken by polling */
890 dmataken = sgbuf->sg.length - dmarx->last_residue;
891 /* Recalculate the pending size */
892 if (pending >= dmataken)
896 /* Pick the remain data from the DMA */
900 * First take all chars in the DMA pipe, then look in the FIFO.
901 * Note that tty_insert_flip_buf() tries to take as many chars
904 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
907 uap->port.icount.rx += dma_count;
908 if (dma_count < pending)
909 dev_warn(uap->port.dev,
910 "couldn't insert all characters (TTY is full?)\n");
913 /* Reset the last_residue for Rx DMA poll */
914 if (uap->dmarx.poll_rate)
915 dmarx->last_residue = sgbuf->sg.length;
918 * Only continue with trying to read the FIFO if all DMA chars have
921 if (dma_count == pending && readfifo) {
922 /* Clear any error flags */
923 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
924 UART011_FEIS, uap, REG_ICR);
927 * If we read all the DMA'd characters, and we had an
928 * incomplete buffer, that could be due to an rx error, or
929 * maybe we just timed out. Read any pending chars and check
932 * Error conditions will only occur in the FIFO, these will
933 * trigger an immediate interrupt and stop the DMA job, so we
934 * will always find the error in the FIFO, never in the DMA
937 fifotaken = pl011_fifo_to_tty(uap);
940 spin_unlock(&uap->port.lock);
941 dev_vdbg(uap->port.dev,
942 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
943 dma_count, fifotaken);
944 tty_flip_buffer_push(port);
945 spin_lock(&uap->port.lock);
948 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
950 struct pl011_dmarx_data *dmarx = &uap->dmarx;
951 struct dma_chan *rxchan = dmarx->chan;
952 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
953 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
955 struct dma_tx_state state;
956 enum dma_status dmastat;
959 * Pause the transfer so we can trust the current counter,
960 * do this before we pause the PL011 block, else we may
963 if (dmaengine_pause(rxchan))
964 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
965 dmastat = rxchan->device->device_tx_status(rxchan,
966 dmarx->cookie, &state);
967 if (dmastat != DMA_PAUSED)
968 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
970 /* Disable RX DMA - incoming data will wait in the FIFO */
971 uap->dmacr &= ~UART011_RXDMAE;
972 pl011_write(uap->dmacr, uap, REG_DMACR);
973 uap->dmarx.running = false;
975 pending = sgbuf->sg.length - state.residue;
976 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
977 /* Then we terminate the transfer - we now know our residue */
978 dmaengine_terminate_all(rxchan);
981 * This will take the chars we have so far and insert
982 * into the framework.
984 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
986 /* Switch buffer & re-trigger DMA job */
987 dmarx->use_buf_b = !dmarx->use_buf_b;
988 if (pl011_dma_rx_trigger_dma(uap)) {
989 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
990 "fall back to interrupt mode\n");
991 uap->im |= UART011_RXIM;
992 pl011_write(uap->im, uap, REG_IMSC);
996 static void pl011_dma_rx_callback(void *data)
998 struct uart_amba_port *uap = data;
999 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1000 struct dma_chan *rxchan = dmarx->chan;
1001 bool lastbuf = dmarx->use_buf_b;
1002 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1003 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1005 struct dma_tx_state state;
1009 * This completion interrupt occurs typically when the
1010 * RX buffer is totally stuffed but no timeout has yet
1011 * occurred. When that happens, we just want the RX
1012 * routine to flush out the secondary DMA buffer while
1013 * we immediately trigger the next DMA job.
1015 spin_lock_irq(&uap->port.lock);
1017 * Rx data can be taken by the UART interrupts during
1018 * the DMA irq handler. So we check the residue here.
1020 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1021 pending = sgbuf->sg.length - state.residue;
1022 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1023 /* Then we terminate the transfer - we now know our residue */
1024 dmaengine_terminate_all(rxchan);
1026 uap->dmarx.running = false;
1027 dmarx->use_buf_b = !lastbuf;
1028 ret = pl011_dma_rx_trigger_dma(uap);
1030 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1031 spin_unlock_irq(&uap->port.lock);
1033 * Do this check after we picked the DMA chars so we don't
1034 * get some IRQ immediately from RX.
1037 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1038 "fall back to interrupt mode\n");
1039 uap->im |= UART011_RXIM;
1040 pl011_write(uap->im, uap, REG_IMSC);
1045 * Stop accepting received characters, when we're shutting down or
1046 * suspending this port.
1047 * Locking: called with port lock held and IRQs disabled.
1049 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1051 if (!uap->using_rx_dma)
1054 /* FIXME. Just disable the DMA enable */
1055 uap->dmacr &= ~UART011_RXDMAE;
1056 pl011_write(uap->dmacr, uap, REG_DMACR);
1060 * Timer handler for Rx DMA polling.
1061 * Every polling, It checks the residue in the dma buffer and transfer
1062 * data to the tty. Also, last_residue is updated for the next polling.
1064 static void pl011_dma_rx_poll(unsigned long args)
1066 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1067 struct tty_port *port = &uap->port.state->port;
1068 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1069 struct dma_chan *rxchan = uap->dmarx.chan;
1070 unsigned long flags = 0;
1071 unsigned int dmataken = 0;
1072 unsigned int size = 0;
1073 struct pl011_sgbuf *sgbuf;
1075 struct dma_tx_state state;
1077 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1078 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1079 if (likely(state.residue < dmarx->last_residue)) {
1080 dmataken = sgbuf->sg.length - dmarx->last_residue;
1081 size = dmarx->last_residue - state.residue;
1082 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1084 if (dma_count == size)
1085 dmarx->last_residue = state.residue;
1086 dmarx->last_jiffies = jiffies;
1088 tty_flip_buffer_push(port);
1091 * If no data is received in poll_timeout, the driver will fall back
1092 * to interrupt mode. We will retrigger DMA at the first interrupt.
1094 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1095 > uap->dmarx.poll_timeout) {
1097 spin_lock_irqsave(&uap->port.lock, flags);
1098 pl011_dma_rx_stop(uap);
1099 uap->im |= UART011_RXIM;
1100 pl011_write(uap->im, uap, REG_IMSC);
1101 spin_unlock_irqrestore(&uap->port.lock, flags);
1103 uap->dmarx.running = false;
1104 dmaengine_terminate_all(rxchan);
1105 del_timer(&uap->dmarx.timer);
1107 mod_timer(&uap->dmarx.timer,
1108 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1112 static void pl011_dma_startup(struct uart_amba_port *uap)
1116 if (!uap->dma_probed)
1117 pl011_dma_probe(uap);
1119 if (!uap->dmatx.chan)
1122 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1123 if (!uap->dmatx.buf) {
1124 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1125 uap->port.fifosize = uap->fifosize;
1129 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1131 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1132 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1133 uap->using_tx_dma = true;
1135 if (!uap->dmarx.chan)
1138 /* Allocate and map DMA RX buffers */
1139 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1142 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1143 "RX buffer A", ret);
1147 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1150 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1151 "RX buffer B", ret);
1152 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1157 uap->using_rx_dma = true;
1160 /* Turn on DMA error (RX/TX will be enabled on demand) */
1161 uap->dmacr |= UART011_DMAONERR;
1162 pl011_write(uap->dmacr, uap, REG_DMACR);
1165 * ST Micro variants has some specific dma burst threshold
1166 * compensation. Set this to 16 bytes, so burst will only
1167 * be issued above/below 16 bytes.
1169 if (uap->vendor->dma_threshold)
1170 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1173 if (uap->using_rx_dma) {
1174 if (pl011_dma_rx_trigger_dma(uap))
1175 dev_dbg(uap->port.dev, "could not trigger initial "
1176 "RX DMA job, fall back to interrupt mode\n");
1177 if (uap->dmarx.poll_rate) {
1178 init_timer(&(uap->dmarx.timer));
1179 uap->dmarx.timer.function = pl011_dma_rx_poll;
1180 uap->dmarx.timer.data = (unsigned long)uap;
1181 mod_timer(&uap->dmarx.timer,
1183 msecs_to_jiffies(uap->dmarx.poll_rate));
1184 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1185 uap->dmarx.last_jiffies = jiffies;
1190 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1192 if (!(uap->using_tx_dma || uap->using_rx_dma))
1195 /* Disable RX and TX DMA */
1196 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1199 spin_lock_irq(&uap->port.lock);
1200 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1201 pl011_write(uap->dmacr, uap, REG_DMACR);
1202 spin_unlock_irq(&uap->port.lock);
1204 if (uap->using_tx_dma) {
1205 /* In theory, this should already be done by pl011_dma_flush_buffer */
1206 dmaengine_terminate_all(uap->dmatx.chan);
1207 if (uap->dmatx.queued) {
1208 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1210 uap->dmatx.queued = false;
1213 kfree(uap->dmatx.buf);
1214 uap->using_tx_dma = false;
1217 if (uap->using_rx_dma) {
1218 dmaengine_terminate_all(uap->dmarx.chan);
1219 /* Clean up the RX DMA */
1220 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1221 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1222 if (uap->dmarx.poll_rate)
1223 del_timer_sync(&uap->dmarx.timer);
1224 uap->using_rx_dma = false;
1228 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1230 return uap->using_rx_dma;
1233 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1235 return uap->using_rx_dma && uap->dmarx.running;
1239 /* Blank functions if the DMA engine is not available */
1240 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1244 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1248 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1252 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1256 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1261 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1265 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1270 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1274 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1278 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1283 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1288 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1293 #define pl011_dma_flush_buffer NULL
1296 static void pl011_stop_tx(struct uart_port *port)
1298 struct uart_amba_port *uap =
1299 container_of(port, struct uart_amba_port, port);
1301 uap->im &= ~UART011_TXIM;
1302 pl011_write(uap->im, uap, REG_IMSC);
1303 pl011_dma_tx_stop(uap);
1306 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1308 /* Start TX with programmed I/O only (no DMA) */
1309 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1311 if (pl011_tx_chars(uap, false)) {
1312 uap->im |= UART011_TXIM;
1313 pl011_write(uap->im, uap, REG_IMSC);
1317 static void pl011_start_tx(struct uart_port *port)
1319 struct uart_amba_port *uap =
1320 container_of(port, struct uart_amba_port, port);
1322 if (!pl011_dma_tx_start(uap))
1323 pl011_start_tx_pio(uap);
1326 static void pl011_stop_rx(struct uart_port *port)
1328 struct uart_amba_port *uap =
1329 container_of(port, struct uart_amba_port, port);
1331 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1332 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1333 pl011_write(uap->im, uap, REG_IMSC);
1335 pl011_dma_rx_stop(uap);
1338 static void pl011_enable_ms(struct uart_port *port)
1340 struct uart_amba_port *uap =
1341 container_of(port, struct uart_amba_port, port);
1343 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1344 pl011_write(uap->im, uap, REG_IMSC);
1347 static void pl011_rx_chars(struct uart_amba_port *uap)
1348 __releases(&uap->port.lock)
1349 __acquires(&uap->port.lock)
1351 pl011_fifo_to_tty(uap);
1353 spin_unlock(&uap->port.lock);
1354 tty_flip_buffer_push(&uap->port.state->port);
1356 * If we were temporarily out of DMA mode for a while,
1357 * attempt to switch back to DMA mode again.
1359 if (pl011_dma_rx_available(uap)) {
1360 if (pl011_dma_rx_trigger_dma(uap)) {
1361 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1362 "fall back to interrupt mode again\n");
1363 uap->im |= UART011_RXIM;
1364 pl011_write(uap->im, uap, REG_IMSC);
1366 #ifdef CONFIG_DMA_ENGINE
1367 /* Start Rx DMA poll */
1368 if (uap->dmarx.poll_rate) {
1369 uap->dmarx.last_jiffies = jiffies;
1370 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1371 mod_timer(&uap->dmarx.timer,
1373 msecs_to_jiffies(uap->dmarx.poll_rate));
1378 spin_lock(&uap->port.lock);
1381 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1384 if (unlikely(!from_irq) &&
1385 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1386 return false; /* unable to transmit character */
1388 pl011_write(c, uap, REG_DR);
1389 uap->port.icount.tx++;
1394 /* Returns true if tx interrupts have to be (kept) enabled */
1395 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1397 struct circ_buf *xmit = &uap->port.state->xmit;
1398 int count = uap->fifosize >> 1;
1400 if (uap->port.x_char) {
1401 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1403 uap->port.x_char = 0;
1406 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1407 pl011_stop_tx(&uap->port);
1411 /* If we are using DMA mode, try to send some characters. */
1412 if (pl011_dma_tx_irq(uap))
1416 if (likely(from_irq) && count-- == 0)
1419 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1422 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1423 } while (!uart_circ_empty(xmit));
1425 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1426 uart_write_wakeup(&uap->port);
1428 if (uart_circ_empty(xmit)) {
1429 pl011_stop_tx(&uap->port);
1435 static void pl011_modem_status(struct uart_amba_port *uap)
1437 unsigned int status, delta;
1439 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1441 delta = status ^ uap->old_status;
1442 uap->old_status = status;
1447 if (delta & UART01x_FR_DCD)
1448 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1450 if (delta & uap->vendor->fr_dsr)
1451 uap->port.icount.dsr++;
1453 if (delta & uap->vendor->fr_cts)
1454 uart_handle_cts_change(&uap->port,
1455 status & uap->vendor->fr_cts);
1457 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1460 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1462 unsigned int dummy_read;
1464 if (!uap->vendor->cts_event_workaround)
1467 /* workaround to make sure that all bits are unlocked.. */
1468 pl011_write(0x00, uap, REG_ICR);
1471 * WA: introduce 26ns(1 uart clk) delay before W1C;
1472 * single apb access will incur 2 pclk(133.12Mhz) delay,
1473 * so add 2 dummy reads
1475 dummy_read = pl011_read(uap, REG_ICR);
1476 dummy_read = pl011_read(uap, REG_ICR);
1479 static irqreturn_t pl011_int(int irq, void *dev_id)
1481 struct uart_amba_port *uap = dev_id;
1482 unsigned long flags;
1483 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1487 spin_lock_irqsave(&uap->port.lock, flags);
1488 imsc = pl011_read(uap, REG_IMSC);
1489 status = pl011_read(uap, REG_RIS) & imsc;
1492 check_apply_cts_event_workaround(uap);
1494 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1498 if (status & (UART011_RTIS|UART011_RXIS)) {
1499 if (pl011_dma_rx_running(uap))
1500 pl011_dma_rx_irq(uap);
1502 pl011_rx_chars(uap);
1504 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1505 UART011_CTSMIS|UART011_RIMIS))
1506 pl011_modem_status(uap);
1507 if (status & UART011_TXIS)
1508 pl011_tx_chars(uap, true);
1510 if (pass_counter-- == 0)
1513 status = pl011_read(uap, REG_RIS) & imsc;
1514 } while (status != 0);
1518 spin_unlock_irqrestore(&uap->port.lock, flags);
1520 return IRQ_RETVAL(handled);
1523 static unsigned int pl011_tx_empty(struct uart_port *port)
1525 struct uart_amba_port *uap =
1526 container_of(port, struct uart_amba_port, port);
1527 unsigned int status = pl011_read(uap, REG_FR);
1528 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1532 static unsigned int pl011_get_mctrl(struct uart_port *port)
1534 struct uart_amba_port *uap =
1535 container_of(port, struct uart_amba_port, port);
1536 unsigned int result = 0;
1537 unsigned int status = pl011_read(uap, REG_FR);
1539 #define TIOCMBIT(uartbit, tiocmbit) \
1540 if (status & uartbit) \
1543 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1544 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1545 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1546 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1551 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1553 struct uart_amba_port *uap =
1554 container_of(port, struct uart_amba_port, port);
1557 cr = pl011_read(uap, REG_CR);
1559 #define TIOCMBIT(tiocmbit, uartbit) \
1560 if (mctrl & tiocmbit) \
1565 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1566 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1567 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1568 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1569 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1572 /* We need to disable auto-RTS if we want to turn RTS off */
1573 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1577 pl011_write(cr, uap, REG_CR);
1580 static void pl011_break_ctl(struct uart_port *port, int break_state)
1582 struct uart_amba_port *uap =
1583 container_of(port, struct uart_amba_port, port);
1584 unsigned long flags;
1587 spin_lock_irqsave(&uap->port.lock, flags);
1588 lcr_h = pl011_read(uap, REG_LCRH_TX);
1589 if (break_state == -1)
1590 lcr_h |= UART01x_LCRH_BRK;
1592 lcr_h &= ~UART01x_LCRH_BRK;
1593 pl011_write(lcr_h, uap, REG_LCRH_TX);
1594 spin_unlock_irqrestore(&uap->port.lock, flags);
1597 #ifdef CONFIG_CONSOLE_POLL
1599 static void pl011_quiesce_irqs(struct uart_port *port)
1601 struct uart_amba_port *uap =
1602 container_of(port, struct uart_amba_port, port);
1604 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1606 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1607 * we simply mask it. start_tx() will unmask it.
1609 * Note we can race with start_tx(), and if the race happens, the
1610 * polling user might get another interrupt just after we clear it.
1611 * But it should be OK and can happen even w/o the race, e.g.
1612 * controller immediately got some new data and raised the IRQ.
1614 * And whoever uses polling routines assumes that it manages the device
1615 * (including tx queue), so we're also fine with start_tx()'s caller
1618 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1622 static int pl011_get_poll_char(struct uart_port *port)
1624 struct uart_amba_port *uap =
1625 container_of(port, struct uart_amba_port, port);
1626 unsigned int status;
1629 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1632 pl011_quiesce_irqs(port);
1634 status = pl011_read(uap, REG_FR);
1635 if (status & UART01x_FR_RXFE)
1636 return NO_POLL_CHAR;
1638 return pl011_read(uap, REG_DR);
1641 static void pl011_put_poll_char(struct uart_port *port,
1644 struct uart_amba_port *uap =
1645 container_of(port, struct uart_amba_port, port);
1647 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1650 pl011_write(ch, uap, REG_DR);
1653 #endif /* CONFIG_CONSOLE_POLL */
1655 static int pl011_hwinit(struct uart_port *port)
1657 struct uart_amba_port *uap =
1658 container_of(port, struct uart_amba_port, port);
1661 /* Optionaly enable pins to be muxed in and configured */
1662 pinctrl_pm_select_default_state(port->dev);
1665 * Try to enable the clock producer.
1667 retval = clk_prepare_enable(uap->clk);
1671 uap->port.uartclk = clk_get_rate(uap->clk);
1673 /* Clear pending error and receive interrupts */
1674 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1675 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1679 * Save interrupts enable mask, and enable RX interrupts in case if
1680 * the interrupt is used for NMI entry.
1682 uap->im = pl011_read(uap, REG_IMSC);
1683 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1685 if (dev_get_platdata(uap->port.dev)) {
1686 struct amba_pl011_data *plat;
1688 plat = dev_get_platdata(uap->port.dev);
1695 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1697 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1698 pl011_reg_to_offset(uap, REG_LCRH_TX);
1701 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1703 pl011_write(lcr_h, uap, REG_LCRH_RX);
1704 if (pl011_split_lcrh(uap)) {
1707 * Wait 10 PCLKs before writing LCRH_TX register,
1708 * to get this delay write read only register 10 times
1710 for (i = 0; i < 10; ++i)
1711 pl011_write(0xff, uap, REG_MIS);
1712 pl011_write(lcr_h, uap, REG_LCRH_TX);
1716 static int pl011_allocate_irq(struct uart_amba_port *uap)
1718 pl011_write(uap->im, uap, REG_IMSC);
1720 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1724 * Enable interrupts, only timeouts when using DMA
1725 * if initial RX DMA job failed, start in interrupt mode
1728 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1732 spin_lock_irq(&uap->port.lock);
1734 /* Clear out any spuriously appearing RX interrupts */
1735 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1738 * RXIS is asserted only when the RX FIFO transitions from below
1739 * to above the trigger threshold. If the RX FIFO is already
1740 * full to the threshold this can't happen and RXIS will now be
1741 * stuck off. Drain the RX FIFO explicitly to fix this:
1743 for (i = 0; i < uap->fifosize * 2; ++i) {
1744 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1747 pl011_read(uap, REG_DR);
1750 uap->im = UART011_RTIM;
1751 if (!pl011_dma_rx_running(uap))
1752 uap->im |= UART011_RXIM;
1753 pl011_write(uap->im, uap, REG_IMSC);
1754 spin_unlock_irq(&uap->port.lock);
1757 static int pl011_startup(struct uart_port *port)
1759 struct uart_amba_port *uap =
1760 container_of(port, struct uart_amba_port, port);
1764 retval = pl011_hwinit(port);
1768 retval = pl011_allocate_irq(uap);
1772 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1774 spin_lock_irq(&uap->port.lock);
1776 /* restore RTS and DTR */
1777 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1778 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1779 pl011_write(cr, uap, REG_CR);
1781 spin_unlock_irq(&uap->port.lock);
1784 * initialise the old status of the modem signals
1786 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1789 pl011_dma_startup(uap);
1791 pl011_enable_interrupts(uap);
1796 clk_disable_unprepare(uap->clk);
1800 static int sbsa_uart_startup(struct uart_port *port)
1802 struct uart_amba_port *uap =
1803 container_of(port, struct uart_amba_port, port);
1806 retval = pl011_hwinit(port);
1810 retval = pl011_allocate_irq(uap);
1814 /* The SBSA UART does not support any modem status lines. */
1815 uap->old_status = 0;
1817 pl011_enable_interrupts(uap);
1822 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1827 val = pl011_read(uap, lcrh);
1828 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1829 pl011_write(val, uap, lcrh);
1833 * disable the port. It should not disable RTS and DTR.
1834 * Also RTS and DTR state should be preserved to restore
1835 * it during startup().
1837 static void pl011_disable_uart(struct uart_amba_port *uap)
1841 uap->autorts = false;
1842 spin_lock_irq(&uap->port.lock);
1843 cr = pl011_read(uap, REG_CR);
1845 cr &= UART011_CR_RTS | UART011_CR_DTR;
1846 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1847 pl011_write(cr, uap, REG_CR);
1848 spin_unlock_irq(&uap->port.lock);
1851 * disable break condition and fifos
1853 pl011_shutdown_channel(uap, REG_LCRH_RX);
1854 if (pl011_split_lcrh(uap))
1855 pl011_shutdown_channel(uap, REG_LCRH_TX);
1858 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1860 spin_lock_irq(&uap->port.lock);
1862 /* mask all interrupts and clear all pending ones */
1864 pl011_write(uap->im, uap, REG_IMSC);
1865 pl011_write(0xffff, uap, REG_ICR);
1867 spin_unlock_irq(&uap->port.lock);
1870 static void pl011_shutdown(struct uart_port *port)
1872 struct uart_amba_port *uap =
1873 container_of(port, struct uart_amba_port, port);
1875 pl011_disable_interrupts(uap);
1877 pl011_dma_shutdown(uap);
1879 free_irq(uap->port.irq, uap);
1881 pl011_disable_uart(uap);
1884 * Shut down the clock producer
1886 clk_disable_unprepare(uap->clk);
1887 /* Optionally let pins go into sleep states */
1888 pinctrl_pm_select_sleep_state(port->dev);
1890 if (dev_get_platdata(uap->port.dev)) {
1891 struct amba_pl011_data *plat;
1893 plat = dev_get_platdata(uap->port.dev);
1898 if (uap->port.ops->flush_buffer)
1899 uap->port.ops->flush_buffer(port);
1902 static void sbsa_uart_shutdown(struct uart_port *port)
1904 struct uart_amba_port *uap =
1905 container_of(port, struct uart_amba_port, port);
1907 pl011_disable_interrupts(uap);
1909 free_irq(uap->port.irq, uap);
1911 if (uap->port.ops->flush_buffer)
1912 uap->port.ops->flush_buffer(port);
1916 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1918 port->read_status_mask = UART011_DR_OE | 255;
1919 if (termios->c_iflag & INPCK)
1920 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1921 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1922 port->read_status_mask |= UART011_DR_BE;
1925 * Characters to ignore
1927 port->ignore_status_mask = 0;
1928 if (termios->c_iflag & IGNPAR)
1929 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1930 if (termios->c_iflag & IGNBRK) {
1931 port->ignore_status_mask |= UART011_DR_BE;
1933 * If we're ignoring parity and break indicators,
1934 * ignore overruns too (for real raw support).
1936 if (termios->c_iflag & IGNPAR)
1937 port->ignore_status_mask |= UART011_DR_OE;
1941 * Ignore all characters if CREAD is not set.
1943 if ((termios->c_cflag & CREAD) == 0)
1944 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1948 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1949 struct ktermios *old)
1951 struct uart_amba_port *uap =
1952 container_of(port, struct uart_amba_port, port);
1953 unsigned int lcr_h, old_cr;
1954 unsigned long flags;
1955 unsigned int baud, quot, clkdiv;
1957 if (uap->vendor->oversampling)
1963 * Ask the core to calculate the divisor for us.
1965 baud = uart_get_baud_rate(port, termios, old, 0,
1966 port->uartclk / clkdiv);
1967 #ifdef CONFIG_DMA_ENGINE
1969 * Adjust RX DMA polling rate with baud rate if not specified.
1971 if (uap->dmarx.auto_poll_rate)
1972 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1975 if (baud > port->uartclk/16)
1976 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1978 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1980 switch (termios->c_cflag & CSIZE) {
1982 lcr_h = UART01x_LCRH_WLEN_5;
1985 lcr_h = UART01x_LCRH_WLEN_6;
1988 lcr_h = UART01x_LCRH_WLEN_7;
1991 lcr_h = UART01x_LCRH_WLEN_8;
1994 if (termios->c_cflag & CSTOPB)
1995 lcr_h |= UART01x_LCRH_STP2;
1996 if (termios->c_cflag & PARENB) {
1997 lcr_h |= UART01x_LCRH_PEN;
1998 if (!(termios->c_cflag & PARODD))
1999 lcr_h |= UART01x_LCRH_EPS;
2000 if (termios->c_cflag & CMSPAR)
2001 lcr_h |= UART011_LCRH_SPS;
2003 if (uap->fifosize > 1)
2004 lcr_h |= UART01x_LCRH_FEN;
2006 spin_lock_irqsave(&port->lock, flags);
2009 * Update the per-port timeout.
2011 uart_update_timeout(port, termios->c_cflag, baud);
2013 pl011_setup_status_masks(port, termios);
2015 if (UART_ENABLE_MS(port, termios->c_cflag))
2016 pl011_enable_ms(port);
2018 /* first, disable everything */
2019 old_cr = pl011_read(uap, REG_CR);
2020 pl011_write(0, uap, REG_CR);
2022 if (termios->c_cflag & CRTSCTS) {
2023 if (old_cr & UART011_CR_RTS)
2024 old_cr |= UART011_CR_RTSEN;
2026 old_cr |= UART011_CR_CTSEN;
2027 uap->autorts = true;
2029 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2030 uap->autorts = false;
2033 if (uap->vendor->oversampling) {
2034 if (baud > port->uartclk / 16)
2035 old_cr |= ST_UART011_CR_OVSFACT;
2037 old_cr &= ~ST_UART011_CR_OVSFACT;
2041 * Workaround for the ST Micro oversampling variants to
2042 * increase the bitrate slightly, by lowering the divisor,
2043 * to avoid delayed sampling of start bit at high speeds,
2044 * else we see data corruption.
2046 if (uap->vendor->oversampling) {
2047 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2049 else if ((baud > 3250000) && (quot > 2))
2053 pl011_write(quot & 0x3f, uap, REG_FBRD);
2054 pl011_write(quot >> 6, uap, REG_IBRD);
2057 * ----------v----------v----------v----------v-----
2058 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2059 * REG_FBRD & REG_IBRD.
2060 * ----------^----------^----------^----------^-----
2062 pl011_write_lcr_h(uap, lcr_h);
2063 pl011_write(old_cr, uap, REG_CR);
2065 spin_unlock_irqrestore(&port->lock, flags);
2069 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2070 struct ktermios *old)
2072 struct uart_amba_port *uap =
2073 container_of(port, struct uart_amba_port, port);
2074 unsigned long flags;
2076 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2078 /* The SBSA UART only supports 8n1 without hardware flow control. */
2079 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2080 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2081 termios->c_cflag |= CS8 | CLOCAL;
2083 spin_lock_irqsave(&port->lock, flags);
2084 uart_update_timeout(port, CS8, uap->fixed_baud);
2085 pl011_setup_status_masks(port, termios);
2086 spin_unlock_irqrestore(&port->lock, flags);
2089 static const char *pl011_type(struct uart_port *port)
2091 struct uart_amba_port *uap =
2092 container_of(port, struct uart_amba_port, port);
2093 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2097 * Configure/autoconfigure the port.
2099 static void pl011_config_port(struct uart_port *port, int flags)
2101 if (flags & UART_CONFIG_TYPE)
2102 port->type = PORT_AMBA;
2106 * verify the new serial_struct (for TIOCSSERIAL).
2108 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2111 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2113 if (ser->irq < 0 || ser->irq >= nr_irqs)
2115 if (ser->baud_base < 9600)
2117 if (port->mapbase != (unsigned long) ser->iomem_base)
2122 static struct uart_ops amba_pl011_pops = {
2123 .tx_empty = pl011_tx_empty,
2124 .set_mctrl = pl011_set_mctrl,
2125 .get_mctrl = pl011_get_mctrl,
2126 .stop_tx = pl011_stop_tx,
2127 .start_tx = pl011_start_tx,
2128 .stop_rx = pl011_stop_rx,
2129 .enable_ms = pl011_enable_ms,
2130 .break_ctl = pl011_break_ctl,
2131 .startup = pl011_startup,
2132 .shutdown = pl011_shutdown,
2133 .flush_buffer = pl011_dma_flush_buffer,
2134 .set_termios = pl011_set_termios,
2136 .config_port = pl011_config_port,
2137 .verify_port = pl011_verify_port,
2138 #ifdef CONFIG_CONSOLE_POLL
2139 .poll_init = pl011_hwinit,
2140 .poll_get_char = pl011_get_poll_char,
2141 .poll_put_char = pl011_put_poll_char,
2145 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2149 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2154 static const struct uart_ops sbsa_uart_pops = {
2155 .tx_empty = pl011_tx_empty,
2156 .set_mctrl = sbsa_uart_set_mctrl,
2157 .get_mctrl = sbsa_uart_get_mctrl,
2158 .stop_tx = pl011_stop_tx,
2159 .start_tx = pl011_start_tx,
2160 .stop_rx = pl011_stop_rx,
2161 .startup = sbsa_uart_startup,
2162 .shutdown = sbsa_uart_shutdown,
2163 .set_termios = sbsa_uart_set_termios,
2165 .config_port = pl011_config_port,
2166 .verify_port = pl011_verify_port,
2167 #ifdef CONFIG_CONSOLE_POLL
2168 .poll_init = pl011_hwinit,
2169 .poll_get_char = pl011_get_poll_char,
2170 .poll_put_char = pl011_put_poll_char,
2174 static struct uart_amba_port *amba_ports[UART_NR];
2176 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2178 static void pl011_console_putchar(struct uart_port *port, int ch)
2180 struct uart_amba_port *uap =
2181 container_of(port, struct uart_amba_port, port);
2183 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2185 pl011_write(ch, uap, REG_DR);
2189 pl011_console_write(struct console *co, const char *s, unsigned int count)
2191 struct uart_amba_port *uap = amba_ports[co->index];
2192 unsigned int old_cr = 0, new_cr;
2193 unsigned long flags;
2196 clk_enable(uap->clk);
2198 local_irq_save(flags);
2199 if (uap->port.sysrq)
2201 else if (oops_in_progress)
2202 locked = spin_trylock(&uap->port.lock);
2204 spin_lock(&uap->port.lock);
2207 * First save the CR then disable the interrupts
2209 if (!uap->vendor->always_enabled) {
2210 old_cr = pl011_read(uap, REG_CR);
2211 new_cr = old_cr & ~UART011_CR_CTSEN;
2212 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2213 pl011_write(new_cr, uap, REG_CR);
2216 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2219 * Finally, wait for transmitter to become empty
2220 * and restore the TCR
2222 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
2224 if (!uap->vendor->always_enabled)
2225 pl011_write(old_cr, uap, REG_CR);
2228 spin_unlock(&uap->port.lock);
2229 local_irq_restore(flags);
2231 clk_disable(uap->clk);
2234 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2235 int *parity, int *bits)
2237 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2238 unsigned int lcr_h, ibrd, fbrd;
2240 lcr_h = pl011_read(uap, REG_LCRH_TX);
2243 if (lcr_h & UART01x_LCRH_PEN) {
2244 if (lcr_h & UART01x_LCRH_EPS)
2250 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2255 ibrd = pl011_read(uap, REG_IBRD);
2256 fbrd = pl011_read(uap, REG_FBRD);
2258 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2260 if (uap->vendor->oversampling) {
2261 if (pl011_read(uap, REG_CR)
2262 & ST_UART011_CR_OVSFACT)
2268 static int pl011_console_setup(struct console *co, char *options)
2270 struct uart_amba_port *uap;
2278 * Check whether an invalid uart number has been specified, and
2279 * if so, search for the first available port that does have
2282 if (co->index >= UART_NR)
2284 uap = amba_ports[co->index];
2288 /* Allow pins to be muxed in and configured */
2289 pinctrl_pm_select_default_state(uap->port.dev);
2291 ret = clk_prepare(uap->clk);
2295 if (dev_get_platdata(uap->port.dev)) {
2296 struct amba_pl011_data *plat;
2298 plat = dev_get_platdata(uap->port.dev);
2303 uap->port.uartclk = clk_get_rate(uap->clk);
2305 if (uap->vendor->fixed_options) {
2306 baud = uap->fixed_baud;
2309 uart_parse_options(options,
2310 &baud, &parity, &bits, &flow);
2312 pl011_console_get_options(uap, &baud, &parity, &bits);
2315 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2319 * pl011_console_match - non-standard console matching
2320 * @co: registering console
2321 * @name: name from console command line
2322 * @idx: index from console command line
2323 * @options: ptr to option string from console command line
2325 * Only attempts to match console command lines of the form:
2326 * console=pl011,mmio|mmio32,<addr>[,<options>]
2327 * console=pl011,0x<addr>[,<options>]
2328 * This form is used to register an initial earlycon boot console and
2329 * replace it with the amba_console at pl011 driver init.
2331 * Performs console setup for a match (as required by interface)
2332 * If no <options> are specified, then assume the h/w is already setup.
2334 * Returns 0 if console matches; otherwise non-zero to use default matching
2336 static int pl011_console_match(struct console *co, char *name, int idx,
2339 unsigned char iotype;
2340 resource_size_t addr;
2343 if (strcmp(name, "pl011") != 0)
2346 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2349 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2352 /* try to match the port specified on the command line */
2353 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2354 struct uart_port *port;
2359 port = &amba_ports[i]->port;
2361 if (port->mapbase != addr)
2366 return pl011_console_setup(co, options);
2372 static struct uart_driver amba_reg;
2373 static struct console amba_console = {
2375 .write = pl011_console_write,
2376 .device = uart_console_device,
2377 .setup = pl011_console_setup,
2378 .match = pl011_console_match,
2379 .flags = CON_PRINTBUFFER,
2384 #define AMBA_CONSOLE (&amba_console)
2386 static void pl011_putc(struct uart_port *port, int c)
2388 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2390 if (port->iotype == UPIO_MEM32)
2391 writel(c, port->membase + UART01x_DR);
2393 writeb(c, port->membase + UART01x_DR);
2394 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2398 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2400 struct earlycon_device *dev = con->data;
2402 uart_console_write(&dev->port, s, n, pl011_putc);
2405 static int __init pl011_early_console_setup(struct earlycon_device *device,
2408 if (!device->port.membase)
2411 device->con->write = pl011_early_write;
2414 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2417 #define AMBA_CONSOLE NULL
2420 static struct uart_driver amba_reg = {
2421 .owner = THIS_MODULE,
2422 .driver_name = "ttyAMA",
2423 .dev_name = "ttyAMA",
2424 .major = SERIAL_AMBA_MAJOR,
2425 .minor = SERIAL_AMBA_MINOR,
2427 .cons = AMBA_CONSOLE,
2430 static int pl011_probe_dt_alias(int index, struct device *dev)
2432 struct device_node *np;
2433 static bool seen_dev_with_alias = false;
2434 static bool seen_dev_without_alias = false;
2437 if (!IS_ENABLED(CONFIG_OF))
2444 ret = of_alias_get_id(np, "serial");
2446 seen_dev_without_alias = true;
2449 seen_dev_with_alias = true;
2450 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2451 dev_warn(dev, "requested serial port %d not available.\n", ret);
2456 if (seen_dev_with_alias && seen_dev_without_alias)
2457 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2462 /* unregisters the driver also if no more ports are left */
2463 static void pl011_unregister_port(struct uart_amba_port *uap)
2468 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2469 if (amba_ports[i] == uap)
2470 amba_ports[i] = NULL;
2471 else if (amba_ports[i])
2474 pl011_dma_remove(uap);
2476 uart_unregister_driver(&amba_reg);
2479 static int pl011_find_free_port(void)
2483 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2484 if (amba_ports[i] == NULL)
2490 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2491 struct resource *mmiobase, int index)
2495 base = devm_ioremap_resource(dev, mmiobase);
2497 return PTR_ERR(base);
2499 index = pl011_probe_dt_alias(index, dev);
2502 uap->port.dev = dev;
2503 uap->port.mapbase = mmiobase->start;
2504 uap->port.membase = base;
2505 uap->port.fifosize = uap->fifosize;
2506 uap->port.flags = UPF_BOOT_AUTOCONF;
2507 uap->port.line = index;
2508 spin_lock_init(&uap->port.lock);
2510 amba_ports[index] = uap;
2515 static int pl011_register_port(struct uart_amba_port *uap)
2519 /* Ensure interrupts from this UART are masked and cleared */
2520 pl011_write(0, uap, REG_IMSC);
2521 pl011_write(0xffff, uap, REG_ICR);
2523 if (!amba_reg.state) {
2524 ret = uart_register_driver(&amba_reg);
2526 dev_err(uap->port.dev,
2527 "Failed to register AMBA-PL011 driver\n");
2528 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2529 if (amba_ports[i] == uap)
2530 amba_ports[i] = NULL;
2535 ret = uart_add_one_port(&amba_reg, &uap->port);
2537 pl011_unregister_port(uap);
2542 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2544 struct uart_amba_port *uap;
2545 struct vendor_data *vendor = id->data;
2548 portnr = pl011_find_free_port();
2552 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2557 uap->clk = devm_clk_get(&dev->dev, NULL);
2558 if (IS_ERR(uap->clk))
2559 return PTR_ERR(uap->clk);
2561 uap->reg_offset = vendor->reg_offset;
2562 uap->vendor = vendor;
2563 uap->fifosize = vendor->get_fifosize(dev);
2564 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2565 uap->port.irq = dev->irq[0];
2566 uap->port.ops = &amba_pl011_pops;
2568 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2570 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2574 amba_set_drvdata(dev, uap);
2576 return pl011_register_port(uap);
2579 static int pl011_remove(struct amba_device *dev)
2581 struct uart_amba_port *uap = amba_get_drvdata(dev);
2583 uart_remove_one_port(&amba_reg, &uap->port);
2584 pl011_unregister_port(uap);
2588 #ifdef CONFIG_PM_SLEEP
2589 static int pl011_suspend(struct device *dev)
2591 struct uart_amba_port *uap = dev_get_drvdata(dev);
2596 return uart_suspend_port(&amba_reg, &uap->port);
2599 static int pl011_resume(struct device *dev)
2601 struct uart_amba_port *uap = dev_get_drvdata(dev);
2606 return uart_resume_port(&amba_reg, &uap->port);
2610 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2612 static int sbsa_uart_probe(struct platform_device *pdev)
2614 struct uart_amba_port *uap;
2620 * Check the mandatory baud rate parameter in the DT node early
2621 * so that we can easily exit with the error.
2623 if (pdev->dev.of_node) {
2624 struct device_node *np = pdev->dev.of_node;
2626 ret = of_property_read_u32(np, "current-speed", &baudrate);
2633 portnr = pl011_find_free_port();
2637 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2642 ret = platform_get_irq(pdev, 0);
2644 if (ret != -EPROBE_DEFER)
2645 dev_err(&pdev->dev, "cannot obtain irq\n");
2648 uap->port.irq = ret;
2650 uap->reg_offset = vendor_sbsa.reg_offset;
2651 uap->vendor = &vendor_sbsa;
2653 uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
2654 uap->port.ops = &sbsa_uart_pops;
2655 uap->fixed_baud = baudrate;
2657 snprintf(uap->type, sizeof(uap->type), "SBSA");
2659 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2661 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2665 platform_set_drvdata(pdev, uap);
2667 return pl011_register_port(uap);
2670 static int sbsa_uart_remove(struct platform_device *pdev)
2672 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2674 uart_remove_one_port(&amba_reg, &uap->port);
2675 pl011_unregister_port(uap);
2679 static const struct of_device_id sbsa_uart_of_match[] = {
2680 { .compatible = "arm,sbsa-uart", },
2683 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2685 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2690 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2692 static struct platform_driver arm_sbsa_uart_platform_driver = {
2693 .probe = sbsa_uart_probe,
2694 .remove = sbsa_uart_remove,
2696 .name = "sbsa-uart",
2697 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2698 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2699 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2703 static struct amba_id pl011_ids[] = {
2707 .data = &vendor_arm,
2715 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2717 .data = &vendor_zte,
2722 MODULE_DEVICE_TABLE(amba, pl011_ids);
2724 static struct amba_driver pl011_driver = {
2726 .name = "uart-pl011",
2727 .pm = &pl011_dev_pm_ops,
2728 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2730 .id_table = pl011_ids,
2731 .probe = pl011_probe,
2732 .remove = pl011_remove,
2735 static int __init pl011_init(void)
2737 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2739 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2740 pr_warn("could not register SBSA UART platform driver\n");
2741 return amba_driver_register(&pl011_driver);
2744 static void __exit pl011_exit(void)
2746 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2747 amba_driver_unregister(&pl011_driver);
2751 * While this can be a module, if builtin it's most likely the console
2752 * So let's leave module_exit but move module_init to an earlier place
2754 arch_initcall(pl011_init);
2755 module_exit(pl011_exit);
2757 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2758 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2759 MODULE_LICENSE("GPL");