2 * Driver for AMBA serial ports
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 * Copyright 1999 ARM Limited
7 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * Copyright (C) 2010 ST-Ericsson SA
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 * This is a generic driver for ARM AMBA-type serial ports. They
25 * have a lot of 16550-like features, but are not register compatible.
26 * Note that although they do have CTS, DCD and DSR inputs, they do
27 * not have an RI input, nor do they have DTR or RTS outputs. If
28 * required, these have to be supplied via some other means (eg, GPIO)
29 * and hooked into this driver.
33 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
37 #include <linux/module.h>
38 #include <linux/ioport.h>
39 #include <linux/init.h>
40 #include <linux/console.h>
41 #include <linux/sysrq.h>
42 #include <linux/device.h>
43 #include <linux/tty.h>
44 #include <linux/tty_flip.h>
45 #include <linux/serial_core.h>
46 #include <linux/serial.h>
47 #include <linux/amba/bus.h>
48 #include <linux/amba/serial.h>
49 #include <linux/clk.h>
50 #include <linux/slab.h>
51 #include <linux/dmaengine.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/scatterlist.h>
54 #include <linux/delay.h>
55 #include <linux/types.h>
57 #include <linux/of_device.h>
58 #include <linux/pinctrl/consumer.h>
59 #include <linux/sizes.h>
61 #include <linux/acpi.h>
63 #include "amba-pl011.h"
67 #define SERIAL_AMBA_MAJOR 204
68 #define SERIAL_AMBA_MINOR 64
69 #define SERIAL_AMBA_NR UART_NR
71 #define AMBA_ISR_PASS_LIMIT 256
73 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
74 #define UART_DUMMY_DR_RX (1 << 16)
76 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
77 [REG_DR] = UART01x_DR,
78 [REG_FR] = UART01x_FR,
79 [REG_LCRH_RX] = UART011_LCRH,
80 [REG_LCRH_TX] = UART011_LCRH,
81 [REG_IBRD] = UART011_IBRD,
82 [REG_FBRD] = UART011_FBRD,
83 [REG_CR] = UART011_CR,
84 [REG_IFLS] = UART011_IFLS,
85 [REG_IMSC] = UART011_IMSC,
86 [REG_RIS] = UART011_RIS,
87 [REG_MIS] = UART011_MIS,
88 [REG_ICR] = UART011_ICR,
89 [REG_DMACR] = UART011_DMACR,
92 /* There is by now at least one vendor with differing details, so handle it */
94 const u16 *reg_offset;
104 bool cts_event_workaround;
108 unsigned int (*get_fifosize)(struct amba_device *dev);
111 static unsigned int get_fifosize_arm(struct amba_device *dev)
113 return amba_rev(dev) < 3 ? 16 : 32;
116 static struct vendor_data vendor_arm = {
117 .reg_offset = pl011_std_offsets,
118 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
119 .fr_busy = UART01x_FR_BUSY,
120 .fr_dsr = UART01x_FR_DSR,
121 .fr_cts = UART01x_FR_CTS,
122 .fr_ri = UART011_FR_RI,
123 .oversampling = false,
124 .dma_threshold = false,
125 .cts_event_workaround = false,
126 .always_enabled = false,
127 .fixed_options = false,
128 .get_fifosize = get_fifosize_arm,
131 static const struct vendor_data vendor_sbsa = {
132 .reg_offset = pl011_std_offsets,
133 .fr_busy = UART01x_FR_BUSY,
134 .fr_dsr = UART01x_FR_DSR,
135 .fr_cts = UART01x_FR_CTS,
136 .fr_ri = UART011_FR_RI,
138 .oversampling = false,
139 .dma_threshold = false,
140 .cts_event_workaround = false,
141 .always_enabled = true,
142 .fixed_options = true,
145 #ifdef CONFIG_ACPI_SPCR_TABLE
146 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
147 .reg_offset = pl011_std_offsets,
148 .fr_busy = UART011_FR_TXFE,
149 .fr_dsr = UART01x_FR_DSR,
150 .fr_cts = UART01x_FR_CTS,
151 .fr_ri = UART011_FR_RI,
152 .inv_fr = UART011_FR_TXFE,
154 .oversampling = false,
155 .dma_threshold = false,
156 .cts_event_workaround = false,
157 .always_enabled = true,
158 .fixed_options = true,
162 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
163 [REG_DR] = UART01x_DR,
164 [REG_ST_DMAWM] = ST_UART011_DMAWM,
165 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
166 [REG_FR] = UART01x_FR,
167 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
168 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
169 [REG_IBRD] = UART011_IBRD,
170 [REG_FBRD] = UART011_FBRD,
171 [REG_CR] = UART011_CR,
172 [REG_IFLS] = UART011_IFLS,
173 [REG_IMSC] = UART011_IMSC,
174 [REG_RIS] = UART011_RIS,
175 [REG_MIS] = UART011_MIS,
176 [REG_ICR] = UART011_ICR,
177 [REG_DMACR] = UART011_DMACR,
178 [REG_ST_XFCR] = ST_UART011_XFCR,
179 [REG_ST_XON1] = ST_UART011_XON1,
180 [REG_ST_XON2] = ST_UART011_XON2,
181 [REG_ST_XOFF1] = ST_UART011_XOFF1,
182 [REG_ST_XOFF2] = ST_UART011_XOFF2,
183 [REG_ST_ITCR] = ST_UART011_ITCR,
184 [REG_ST_ITIP] = ST_UART011_ITIP,
185 [REG_ST_ABCR] = ST_UART011_ABCR,
186 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
189 static unsigned int get_fifosize_st(struct amba_device *dev)
194 static struct vendor_data vendor_st = {
195 .reg_offset = pl011_st_offsets,
196 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
197 .fr_busy = UART01x_FR_BUSY,
198 .fr_dsr = UART01x_FR_DSR,
199 .fr_cts = UART01x_FR_CTS,
200 .fr_ri = UART011_FR_RI,
201 .oversampling = true,
202 .dma_threshold = true,
203 .cts_event_workaround = true,
204 .always_enabled = false,
205 .fixed_options = false,
206 .get_fifosize = get_fifosize_st,
209 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
210 [REG_DR] = ZX_UART011_DR,
211 [REG_FR] = ZX_UART011_FR,
212 [REG_LCRH_RX] = ZX_UART011_LCRH,
213 [REG_LCRH_TX] = ZX_UART011_LCRH,
214 [REG_IBRD] = ZX_UART011_IBRD,
215 [REG_FBRD] = ZX_UART011_FBRD,
216 [REG_CR] = ZX_UART011_CR,
217 [REG_IFLS] = ZX_UART011_IFLS,
218 [REG_IMSC] = ZX_UART011_IMSC,
219 [REG_RIS] = ZX_UART011_RIS,
220 [REG_MIS] = ZX_UART011_MIS,
221 [REG_ICR] = ZX_UART011_ICR,
222 [REG_DMACR] = ZX_UART011_DMACR,
225 static unsigned int get_fifosize_zte(struct amba_device *dev)
230 static struct vendor_data vendor_zte = {
231 .reg_offset = pl011_zte_offsets,
233 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
234 .fr_busy = ZX_UART01x_FR_BUSY,
235 .fr_dsr = ZX_UART01x_FR_DSR,
236 .fr_cts = ZX_UART01x_FR_CTS,
237 .fr_ri = ZX_UART011_FR_RI,
238 .get_fifosize = get_fifosize_zte,
241 /* Deals with DMA transactions */
244 struct scatterlist sg;
248 struct pl011_dmarx_data {
249 struct dma_chan *chan;
250 struct completion complete;
252 struct pl011_sgbuf sgbuf_a;
253 struct pl011_sgbuf sgbuf_b;
256 struct timer_list timer;
257 unsigned int last_residue;
258 unsigned long last_jiffies;
260 unsigned int poll_rate;
261 unsigned int poll_timeout;
264 struct pl011_dmatx_data {
265 struct dma_chan *chan;
266 struct scatterlist sg;
272 * We wrap our port structure around the generic uart_port.
274 struct uart_amba_port {
275 struct uart_port port;
276 const u16 *reg_offset;
278 const struct vendor_data *vendor;
279 unsigned int dmacr; /* dma control reg */
280 unsigned int im; /* interrupt mask */
281 unsigned int old_status;
282 unsigned int fifosize; /* vendor-specific */
283 unsigned int old_cr; /* state during shutdown */
285 unsigned int fixed_baud; /* vendor-set fixed baud rate */
287 #ifdef CONFIG_DMA_ENGINE
291 struct pl011_dmarx_data dmarx;
292 struct pl011_dmatx_data dmatx;
297 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
300 return uap->reg_offset[reg];
303 static unsigned int pl011_read(const struct uart_amba_port *uap,
306 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
308 return (uap->port.iotype == UPIO_MEM32) ?
309 readl_relaxed(addr) : readw_relaxed(addr);
312 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
315 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
317 if (uap->port.iotype == UPIO_MEM32)
318 writel_relaxed(val, addr);
320 writew_relaxed(val, addr);
324 * Reads up to 256 characters from the FIFO or until it's empty and
325 * inserts them into the TTY layer. Returns the number of characters
326 * read from the FIFO.
328 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
331 unsigned int ch, flag, max_count = 256;
334 while (max_count--) {
335 status = pl011_read(uap, REG_FR);
336 if (status & UART01x_FR_RXFE)
339 /* Take chars from the FIFO and update status */
340 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
342 uap->port.icount.rx++;
345 if (unlikely(ch & UART_DR_ERROR)) {
346 if (ch & UART011_DR_BE) {
347 ch &= ~(UART011_DR_FE | UART011_DR_PE);
348 uap->port.icount.brk++;
349 if (uart_handle_break(&uap->port))
351 } else if (ch & UART011_DR_PE)
352 uap->port.icount.parity++;
353 else if (ch & UART011_DR_FE)
354 uap->port.icount.frame++;
355 if (ch & UART011_DR_OE)
356 uap->port.icount.overrun++;
358 ch &= uap->port.read_status_mask;
360 if (ch & UART011_DR_BE)
362 else if (ch & UART011_DR_PE)
364 else if (ch & UART011_DR_FE)
368 if (uart_handle_sysrq_char(&uap->port, ch & 255))
371 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
379 * All the DMA operation mode stuff goes inside this ifdef.
380 * This assumes that you have a generic DMA device interface,
381 * no custom DMA interfaces are supported.
383 #ifdef CONFIG_DMA_ENGINE
385 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
387 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
388 enum dma_data_direction dir)
392 sg->buf = dma_alloc_coherent(chan->device->dev,
393 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
397 sg_init_table(&sg->sg, 1);
398 sg_set_page(&sg->sg, phys_to_page(dma_addr),
399 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
400 sg_dma_address(&sg->sg) = dma_addr;
401 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
406 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
407 enum dma_data_direction dir)
410 dma_free_coherent(chan->device->dev,
411 PL011_DMA_BUFFER_SIZE, sg->buf,
412 sg_dma_address(&sg->sg));
416 static void pl011_dma_probe(struct uart_amba_port *uap)
418 /* DMA is the sole user of the platform data right now */
419 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
420 struct device *dev = uap->port.dev;
421 struct dma_slave_config tx_conf = {
422 .dst_addr = uap->port.mapbase +
423 pl011_reg_to_offset(uap, REG_DR),
424 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
425 .direction = DMA_MEM_TO_DEV,
426 .dst_maxburst = uap->fifosize >> 1,
429 struct dma_chan *chan;
432 uap->dma_probed = true;
433 chan = dma_request_slave_channel_reason(dev, "tx");
435 if (PTR_ERR(chan) == -EPROBE_DEFER) {
436 uap->dma_probed = false;
440 /* We need platform data */
441 if (!plat || !plat->dma_filter) {
442 dev_info(uap->port.dev, "no DMA platform data\n");
446 /* Try to acquire a generic DMA engine slave TX channel */
448 dma_cap_set(DMA_SLAVE, mask);
450 chan = dma_request_channel(mask, plat->dma_filter,
453 dev_err(uap->port.dev, "no TX DMA channel!\n");
458 dmaengine_slave_config(chan, &tx_conf);
459 uap->dmatx.chan = chan;
461 dev_info(uap->port.dev, "DMA channel TX %s\n",
462 dma_chan_name(uap->dmatx.chan));
464 /* Optionally make use of an RX channel as well */
465 chan = dma_request_slave_channel(dev, "rx");
467 if (!chan && plat && plat->dma_rx_param) {
468 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
471 dev_err(uap->port.dev, "no RX DMA channel!\n");
477 struct dma_slave_config rx_conf = {
478 .src_addr = uap->port.mapbase +
479 pl011_reg_to_offset(uap, REG_DR),
480 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
481 .direction = DMA_DEV_TO_MEM,
482 .src_maxburst = uap->fifosize >> 2,
485 struct dma_slave_caps caps;
488 * Some DMA controllers provide information on their capabilities.
489 * If the controller does, check for suitable residue processing
490 * otherwise assime all is well.
492 if (0 == dma_get_slave_caps(chan, &caps)) {
493 if (caps.residue_granularity ==
494 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
495 dma_release_channel(chan);
496 dev_info(uap->port.dev,
497 "RX DMA disabled - no residue processing\n");
501 dmaengine_slave_config(chan, &rx_conf);
502 uap->dmarx.chan = chan;
504 uap->dmarx.auto_poll_rate = false;
505 if (plat && plat->dma_rx_poll_enable) {
506 /* Set poll rate if specified. */
507 if (plat->dma_rx_poll_rate) {
508 uap->dmarx.auto_poll_rate = false;
509 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
512 * 100 ms defaults to poll rate if not
513 * specified. This will be adjusted with
514 * the baud rate at set_termios.
516 uap->dmarx.auto_poll_rate = true;
517 uap->dmarx.poll_rate = 100;
519 /* 3 secs defaults poll_timeout if not specified. */
520 if (plat->dma_rx_poll_timeout)
521 uap->dmarx.poll_timeout =
522 plat->dma_rx_poll_timeout;
524 uap->dmarx.poll_timeout = 3000;
525 } else if (!plat && dev->of_node) {
526 uap->dmarx.auto_poll_rate = of_property_read_bool(
527 dev->of_node, "auto-poll");
528 if (uap->dmarx.auto_poll_rate) {
531 if (0 == of_property_read_u32(dev->of_node,
533 uap->dmarx.poll_rate = x;
535 uap->dmarx.poll_rate = 100;
536 if (0 == of_property_read_u32(dev->of_node,
537 "poll-timeout-ms", &x))
538 uap->dmarx.poll_timeout = x;
540 uap->dmarx.poll_timeout = 3000;
543 dev_info(uap->port.dev, "DMA channel RX %s\n",
544 dma_chan_name(uap->dmarx.chan));
548 static void pl011_dma_remove(struct uart_amba_port *uap)
551 dma_release_channel(uap->dmatx.chan);
553 dma_release_channel(uap->dmarx.chan);
556 /* Forward declare these for the refill routine */
557 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
558 static void pl011_start_tx_pio(struct uart_amba_port *uap);
561 * The current DMA TX buffer has been sent.
562 * Try to queue up another DMA buffer.
564 static void pl011_dma_tx_callback(void *data)
566 struct uart_amba_port *uap = data;
567 struct pl011_dmatx_data *dmatx = &uap->dmatx;
571 spin_lock_irqsave(&uap->port.lock, flags);
572 if (uap->dmatx.queued)
573 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
577 uap->dmacr = dmacr & ~UART011_TXDMAE;
578 pl011_write(uap->dmacr, uap, REG_DMACR);
581 * If TX DMA was disabled, it means that we've stopped the DMA for
582 * some reason (eg, XOFF received, or we want to send an X-char.)
584 * Note: we need to be careful here of a potential race between DMA
585 * and the rest of the driver - if the driver disables TX DMA while
586 * a TX buffer completing, we must update the tx queued status to
587 * get further refills (hence we check dmacr).
589 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
590 uart_circ_empty(&uap->port.state->xmit)) {
591 uap->dmatx.queued = false;
592 spin_unlock_irqrestore(&uap->port.lock, flags);
596 if (pl011_dma_tx_refill(uap) <= 0)
598 * We didn't queue a DMA buffer for some reason, but we
599 * have data pending to be sent. Re-enable the TX IRQ.
601 pl011_start_tx_pio(uap);
603 spin_unlock_irqrestore(&uap->port.lock, flags);
607 * Try to refill the TX DMA buffer.
608 * Locking: called with port lock held and IRQs disabled.
610 * 1 if we queued up a TX DMA buffer.
611 * 0 if we didn't want to handle this by DMA
614 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
616 struct pl011_dmatx_data *dmatx = &uap->dmatx;
617 struct dma_chan *chan = dmatx->chan;
618 struct dma_device *dma_dev = chan->device;
619 struct dma_async_tx_descriptor *desc;
620 struct circ_buf *xmit = &uap->port.state->xmit;
624 * Try to avoid the overhead involved in using DMA if the
625 * transaction fits in the first half of the FIFO, by using
626 * the standard interrupt handling. This ensures that we
627 * issue a uart_write_wakeup() at the appropriate time.
629 count = uart_circ_chars_pending(xmit);
630 if (count < (uap->fifosize >> 1)) {
631 uap->dmatx.queued = false;
636 * Bodge: don't send the last character by DMA, as this
637 * will prevent XON from notifying us to restart DMA.
641 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
642 if (count > PL011_DMA_BUFFER_SIZE)
643 count = PL011_DMA_BUFFER_SIZE;
645 if (xmit->tail < xmit->head)
646 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
648 size_t first = UART_XMIT_SIZE - xmit->tail;
653 second = count - first;
655 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
657 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
660 dmatx->sg.length = count;
662 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
663 uap->dmatx.queued = false;
664 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
668 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
669 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
671 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
672 uap->dmatx.queued = false;
674 * If DMA cannot be used right now, we complete this
675 * transaction via IRQ and let the TTY layer retry.
677 dev_dbg(uap->port.dev, "TX DMA busy\n");
681 /* Some data to go along to the callback */
682 desc->callback = pl011_dma_tx_callback;
683 desc->callback_param = uap;
685 /* All errors should happen at prepare time */
686 dmaengine_submit(desc);
688 /* Fire the DMA transaction */
689 dma_dev->device_issue_pending(chan);
691 uap->dmacr |= UART011_TXDMAE;
692 pl011_write(uap->dmacr, uap, REG_DMACR);
693 uap->dmatx.queued = true;
696 * Now we know that DMA will fire, so advance the ring buffer
697 * with the stuff we just dispatched.
699 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
700 uap->port.icount.tx += count;
702 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
703 uart_write_wakeup(&uap->port);
709 * We received a transmit interrupt without a pending X-char but with
710 * pending characters.
711 * Locking: called with port lock held and IRQs disabled.
713 * false if we want to use PIO to transmit
714 * true if we queued a DMA buffer
716 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
718 if (!uap->using_tx_dma)
722 * If we already have a TX buffer queued, but received a
723 * TX interrupt, it will be because we've just sent an X-char.
724 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
726 if (uap->dmatx.queued) {
727 uap->dmacr |= UART011_TXDMAE;
728 pl011_write(uap->dmacr, uap, REG_DMACR);
729 uap->im &= ~UART011_TXIM;
730 pl011_write(uap->im, uap, REG_IMSC);
735 * We don't have a TX buffer queued, so try to queue one.
736 * If we successfully queued a buffer, mask the TX IRQ.
738 if (pl011_dma_tx_refill(uap) > 0) {
739 uap->im &= ~UART011_TXIM;
740 pl011_write(uap->im, uap, REG_IMSC);
747 * Stop the DMA transmit (eg, due to received XOFF).
748 * Locking: called with port lock held and IRQs disabled.
750 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
752 if (uap->dmatx.queued) {
753 uap->dmacr &= ~UART011_TXDMAE;
754 pl011_write(uap->dmacr, uap, REG_DMACR);
759 * Try to start a DMA transmit, or in the case of an XON/OFF
760 * character queued for send, try to get that character out ASAP.
761 * Locking: called with port lock held and IRQs disabled.
763 * false if we want the TX IRQ to be enabled
764 * true if we have a buffer queued
766 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
770 if (!uap->using_tx_dma)
773 if (!uap->port.x_char) {
774 /* no X-char, try to push chars out in DMA mode */
777 if (!uap->dmatx.queued) {
778 if (pl011_dma_tx_refill(uap) > 0) {
779 uap->im &= ~UART011_TXIM;
780 pl011_write(uap->im, uap, REG_IMSC);
783 } else if (!(uap->dmacr & UART011_TXDMAE)) {
784 uap->dmacr |= UART011_TXDMAE;
785 pl011_write(uap->dmacr, uap, REG_DMACR);
791 * We have an X-char to send. Disable DMA to prevent it loading
792 * the TX fifo, and then see if we can stuff it into the FIFO.
795 uap->dmacr &= ~UART011_TXDMAE;
796 pl011_write(uap->dmacr, uap, REG_DMACR);
798 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
800 * No space in the FIFO, so enable the transmit interrupt
801 * so we know when there is space. Note that once we've
802 * loaded the character, we should just re-enable DMA.
807 pl011_write(uap->port.x_char, uap, REG_DR);
808 uap->port.icount.tx++;
809 uap->port.x_char = 0;
811 /* Success - restore the DMA state */
813 pl011_write(dmacr, uap, REG_DMACR);
819 * Flush the transmit buffer.
820 * Locking: called with port lock held and IRQs disabled.
822 static void pl011_dma_flush_buffer(struct uart_port *port)
823 __releases(&uap->port.lock)
824 __acquires(&uap->port.lock)
826 struct uart_amba_port *uap =
827 container_of(port, struct uart_amba_port, port);
829 if (!uap->using_tx_dma)
832 dmaengine_terminate_async(uap->dmatx.chan);
834 if (uap->dmatx.queued) {
835 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
837 uap->dmatx.queued = false;
838 uap->dmacr &= ~UART011_TXDMAE;
839 pl011_write(uap->dmacr, uap, REG_DMACR);
843 static void pl011_dma_rx_callback(void *data);
845 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
847 struct dma_chan *rxchan = uap->dmarx.chan;
848 struct pl011_dmarx_data *dmarx = &uap->dmarx;
849 struct dma_async_tx_descriptor *desc;
850 struct pl011_sgbuf *sgbuf;
855 /* Start the RX DMA job */
856 sgbuf = uap->dmarx.use_buf_b ?
857 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
858 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
860 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
862 * If the DMA engine is busy and cannot prepare a
863 * channel, no big deal, the driver will fall back
864 * to interrupt mode as a result of this error code.
867 uap->dmarx.running = false;
868 dmaengine_terminate_all(rxchan);
872 /* Some data to go along to the callback */
873 desc->callback = pl011_dma_rx_callback;
874 desc->callback_param = uap;
875 dmarx->cookie = dmaengine_submit(desc);
876 dma_async_issue_pending(rxchan);
878 uap->dmacr |= UART011_RXDMAE;
879 pl011_write(uap->dmacr, uap, REG_DMACR);
880 uap->dmarx.running = true;
882 uap->im &= ~UART011_RXIM;
883 pl011_write(uap->im, uap, REG_IMSC);
889 * This is called when either the DMA job is complete, or
890 * the FIFO timeout interrupt occurred. This must be called
891 * with the port spinlock uap->port.lock held.
893 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
894 u32 pending, bool use_buf_b,
897 struct tty_port *port = &uap->port.state->port;
898 struct pl011_sgbuf *sgbuf = use_buf_b ?
899 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
901 u32 fifotaken = 0; /* only used for vdbg() */
903 struct pl011_dmarx_data *dmarx = &uap->dmarx;
906 if (uap->dmarx.poll_rate) {
907 /* The data can be taken by polling */
908 dmataken = sgbuf->sg.length - dmarx->last_residue;
909 /* Recalculate the pending size */
910 if (pending >= dmataken)
914 /* Pick the remain data from the DMA */
918 * First take all chars in the DMA pipe, then look in the FIFO.
919 * Note that tty_insert_flip_buf() tries to take as many chars
922 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
925 uap->port.icount.rx += dma_count;
926 if (dma_count < pending)
927 dev_warn(uap->port.dev,
928 "couldn't insert all characters (TTY is full?)\n");
931 /* Reset the last_residue for Rx DMA poll */
932 if (uap->dmarx.poll_rate)
933 dmarx->last_residue = sgbuf->sg.length;
936 * Only continue with trying to read the FIFO if all DMA chars have
939 if (dma_count == pending && readfifo) {
940 /* Clear any error flags */
941 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
942 UART011_FEIS, uap, REG_ICR);
945 * If we read all the DMA'd characters, and we had an
946 * incomplete buffer, that could be due to an rx error, or
947 * maybe we just timed out. Read any pending chars and check
950 * Error conditions will only occur in the FIFO, these will
951 * trigger an immediate interrupt and stop the DMA job, so we
952 * will always find the error in the FIFO, never in the DMA
955 fifotaken = pl011_fifo_to_tty(uap);
958 spin_unlock(&uap->port.lock);
959 dev_vdbg(uap->port.dev,
960 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
961 dma_count, fifotaken);
962 tty_flip_buffer_push(port);
963 spin_lock(&uap->port.lock);
966 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
968 struct pl011_dmarx_data *dmarx = &uap->dmarx;
969 struct dma_chan *rxchan = dmarx->chan;
970 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
971 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
973 struct dma_tx_state state;
974 enum dma_status dmastat;
977 * Pause the transfer so we can trust the current counter,
978 * do this before we pause the PL011 block, else we may
981 if (dmaengine_pause(rxchan))
982 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
983 dmastat = rxchan->device->device_tx_status(rxchan,
984 dmarx->cookie, &state);
985 if (dmastat != DMA_PAUSED)
986 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
988 /* Disable RX DMA - incoming data will wait in the FIFO */
989 uap->dmacr &= ~UART011_RXDMAE;
990 pl011_write(uap->dmacr, uap, REG_DMACR);
991 uap->dmarx.running = false;
993 pending = sgbuf->sg.length - state.residue;
994 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
995 /* Then we terminate the transfer - we now know our residue */
996 dmaengine_terminate_all(rxchan);
999 * This will take the chars we have so far and insert
1000 * into the framework.
1002 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
1004 /* Switch buffer & re-trigger DMA job */
1005 dmarx->use_buf_b = !dmarx->use_buf_b;
1006 if (pl011_dma_rx_trigger_dma(uap)) {
1007 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1008 "fall back to interrupt mode\n");
1009 uap->im |= UART011_RXIM;
1010 pl011_write(uap->im, uap, REG_IMSC);
1014 static void pl011_dma_rx_callback(void *data)
1016 struct uart_amba_port *uap = data;
1017 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1018 struct dma_chan *rxchan = dmarx->chan;
1019 bool lastbuf = dmarx->use_buf_b;
1020 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1021 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1023 struct dma_tx_state state;
1027 * This completion interrupt occurs typically when the
1028 * RX buffer is totally stuffed but no timeout has yet
1029 * occurred. When that happens, we just want the RX
1030 * routine to flush out the secondary DMA buffer while
1031 * we immediately trigger the next DMA job.
1033 spin_lock_irq(&uap->port.lock);
1035 * Rx data can be taken by the UART interrupts during
1036 * the DMA irq handler. So we check the residue here.
1038 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1039 pending = sgbuf->sg.length - state.residue;
1040 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1041 /* Then we terminate the transfer - we now know our residue */
1042 dmaengine_terminate_all(rxchan);
1044 uap->dmarx.running = false;
1045 dmarx->use_buf_b = !lastbuf;
1046 ret = pl011_dma_rx_trigger_dma(uap);
1048 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1049 spin_unlock_irq(&uap->port.lock);
1051 * Do this check after we picked the DMA chars so we don't
1052 * get some IRQ immediately from RX.
1055 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1056 "fall back to interrupt mode\n");
1057 uap->im |= UART011_RXIM;
1058 pl011_write(uap->im, uap, REG_IMSC);
1063 * Stop accepting received characters, when we're shutting down or
1064 * suspending this port.
1065 * Locking: called with port lock held and IRQs disabled.
1067 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1069 /* FIXME. Just disable the DMA enable */
1070 uap->dmacr &= ~UART011_RXDMAE;
1071 pl011_write(uap->dmacr, uap, REG_DMACR);
1075 * Timer handler for Rx DMA polling.
1076 * Every polling, It checks the residue in the dma buffer and transfer
1077 * data to the tty. Also, last_residue is updated for the next polling.
1079 static void pl011_dma_rx_poll(unsigned long args)
1081 struct uart_amba_port *uap = (struct uart_amba_port *)args;
1082 struct tty_port *port = &uap->port.state->port;
1083 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1084 struct dma_chan *rxchan = uap->dmarx.chan;
1085 unsigned long flags = 0;
1086 unsigned int dmataken = 0;
1087 unsigned int size = 0;
1088 struct pl011_sgbuf *sgbuf;
1090 struct dma_tx_state state;
1092 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1093 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1094 if (likely(state.residue < dmarx->last_residue)) {
1095 dmataken = sgbuf->sg.length - dmarx->last_residue;
1096 size = dmarx->last_residue - state.residue;
1097 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1099 if (dma_count == size)
1100 dmarx->last_residue = state.residue;
1101 dmarx->last_jiffies = jiffies;
1103 tty_flip_buffer_push(port);
1106 * If no data is received in poll_timeout, the driver will fall back
1107 * to interrupt mode. We will retrigger DMA at the first interrupt.
1109 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1110 > uap->dmarx.poll_timeout) {
1112 spin_lock_irqsave(&uap->port.lock, flags);
1113 pl011_dma_rx_stop(uap);
1114 uap->im |= UART011_RXIM;
1115 pl011_write(uap->im, uap, REG_IMSC);
1116 spin_unlock_irqrestore(&uap->port.lock, flags);
1118 uap->dmarx.running = false;
1119 dmaengine_terminate_all(rxchan);
1120 del_timer(&uap->dmarx.timer);
1122 mod_timer(&uap->dmarx.timer,
1123 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1127 static void pl011_dma_startup(struct uart_amba_port *uap)
1131 if (!uap->dma_probed)
1132 pl011_dma_probe(uap);
1134 if (!uap->dmatx.chan)
1137 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1138 if (!uap->dmatx.buf) {
1139 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1140 uap->port.fifosize = uap->fifosize;
1144 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1146 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1147 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1148 uap->using_tx_dma = true;
1150 if (!uap->dmarx.chan)
1153 /* Allocate and map DMA RX buffers */
1154 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1157 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1158 "RX buffer A", ret);
1162 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1165 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1166 "RX buffer B", ret);
1167 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1172 uap->using_rx_dma = true;
1175 /* Turn on DMA error (RX/TX will be enabled on demand) */
1176 uap->dmacr |= UART011_DMAONERR;
1177 pl011_write(uap->dmacr, uap, REG_DMACR);
1180 * ST Micro variants has some specific dma burst threshold
1181 * compensation. Set this to 16 bytes, so burst will only
1182 * be issued above/below 16 bytes.
1184 if (uap->vendor->dma_threshold)
1185 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1188 if (uap->using_rx_dma) {
1189 if (pl011_dma_rx_trigger_dma(uap))
1190 dev_dbg(uap->port.dev, "could not trigger initial "
1191 "RX DMA job, fall back to interrupt mode\n");
1192 if (uap->dmarx.poll_rate) {
1193 init_timer(&(uap->dmarx.timer));
1194 uap->dmarx.timer.function = pl011_dma_rx_poll;
1195 uap->dmarx.timer.data = (unsigned long)uap;
1196 mod_timer(&uap->dmarx.timer,
1198 msecs_to_jiffies(uap->dmarx.poll_rate));
1199 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1200 uap->dmarx.last_jiffies = jiffies;
1205 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1207 if (!(uap->using_tx_dma || uap->using_rx_dma))
1210 /* Disable RX and TX DMA */
1211 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1214 spin_lock_irq(&uap->port.lock);
1215 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1216 pl011_write(uap->dmacr, uap, REG_DMACR);
1217 spin_unlock_irq(&uap->port.lock);
1219 if (uap->using_tx_dma) {
1220 /* In theory, this should already be done by pl011_dma_flush_buffer */
1221 dmaengine_terminate_all(uap->dmatx.chan);
1222 if (uap->dmatx.queued) {
1223 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1225 uap->dmatx.queued = false;
1228 kfree(uap->dmatx.buf);
1229 uap->using_tx_dma = false;
1232 if (uap->using_rx_dma) {
1233 dmaengine_terminate_all(uap->dmarx.chan);
1234 /* Clean up the RX DMA */
1235 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1236 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1237 if (uap->dmarx.poll_rate)
1238 del_timer_sync(&uap->dmarx.timer);
1239 uap->using_rx_dma = false;
1243 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1245 return uap->using_rx_dma;
1248 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1250 return uap->using_rx_dma && uap->dmarx.running;
1254 /* Blank functions if the DMA engine is not available */
1255 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1259 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1263 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1267 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1271 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1276 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1280 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1285 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1289 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1293 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1298 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1303 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1308 #define pl011_dma_flush_buffer NULL
1311 static void pl011_stop_tx(struct uart_port *port)
1313 struct uart_amba_port *uap =
1314 container_of(port, struct uart_amba_port, port);
1316 uap->im &= ~UART011_TXIM;
1317 pl011_write(uap->im, uap, REG_IMSC);
1318 pl011_dma_tx_stop(uap);
1321 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1323 /* Start TX with programmed I/O only (no DMA) */
1324 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1326 if (pl011_tx_chars(uap, false)) {
1327 uap->im |= UART011_TXIM;
1328 pl011_write(uap->im, uap, REG_IMSC);
1332 static void pl011_start_tx(struct uart_port *port)
1334 struct uart_amba_port *uap =
1335 container_of(port, struct uart_amba_port, port);
1337 if (!pl011_dma_tx_start(uap))
1338 pl011_start_tx_pio(uap);
1341 static void pl011_stop_rx(struct uart_port *port)
1343 struct uart_amba_port *uap =
1344 container_of(port, struct uart_amba_port, port);
1346 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1347 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1348 pl011_write(uap->im, uap, REG_IMSC);
1350 pl011_dma_rx_stop(uap);
1353 static void pl011_enable_ms(struct uart_port *port)
1355 struct uart_amba_port *uap =
1356 container_of(port, struct uart_amba_port, port);
1358 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1359 pl011_write(uap->im, uap, REG_IMSC);
1362 static void pl011_rx_chars(struct uart_amba_port *uap)
1363 __releases(&uap->port.lock)
1364 __acquires(&uap->port.lock)
1366 pl011_fifo_to_tty(uap);
1368 spin_unlock(&uap->port.lock);
1369 tty_flip_buffer_push(&uap->port.state->port);
1371 * If we were temporarily out of DMA mode for a while,
1372 * attempt to switch back to DMA mode again.
1374 if (pl011_dma_rx_available(uap)) {
1375 if (pl011_dma_rx_trigger_dma(uap)) {
1376 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1377 "fall back to interrupt mode again\n");
1378 uap->im |= UART011_RXIM;
1379 pl011_write(uap->im, uap, REG_IMSC);
1381 #ifdef CONFIG_DMA_ENGINE
1382 /* Start Rx DMA poll */
1383 if (uap->dmarx.poll_rate) {
1384 uap->dmarx.last_jiffies = jiffies;
1385 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1386 mod_timer(&uap->dmarx.timer,
1388 msecs_to_jiffies(uap->dmarx.poll_rate));
1393 spin_lock(&uap->port.lock);
1396 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1399 if (unlikely(!from_irq) &&
1400 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1401 return false; /* unable to transmit character */
1403 pl011_write(c, uap, REG_DR);
1404 uap->port.icount.tx++;
1409 /* Returns true if tx interrupts have to be (kept) enabled */
1410 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1412 struct circ_buf *xmit = &uap->port.state->xmit;
1413 int count = uap->fifosize >> 1;
1415 if (uap->port.x_char) {
1416 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1418 uap->port.x_char = 0;
1421 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1422 pl011_stop_tx(&uap->port);
1426 /* If we are using DMA mode, try to send some characters. */
1427 if (pl011_dma_tx_irq(uap))
1431 if (likely(from_irq) && count-- == 0)
1434 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1437 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1438 } while (!uart_circ_empty(xmit));
1440 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1441 uart_write_wakeup(&uap->port);
1443 if (uart_circ_empty(xmit)) {
1444 pl011_stop_tx(&uap->port);
1450 static void pl011_modem_status(struct uart_amba_port *uap)
1452 unsigned int status, delta;
1454 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1456 delta = status ^ uap->old_status;
1457 uap->old_status = status;
1462 if (delta & UART01x_FR_DCD)
1463 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1465 if (delta & uap->vendor->fr_dsr)
1466 uap->port.icount.dsr++;
1468 if (delta & uap->vendor->fr_cts)
1469 uart_handle_cts_change(&uap->port,
1470 status & uap->vendor->fr_cts);
1472 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1475 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1477 unsigned int dummy_read;
1479 if (!uap->vendor->cts_event_workaround)
1482 /* workaround to make sure that all bits are unlocked.. */
1483 pl011_write(0x00, uap, REG_ICR);
1486 * WA: introduce 26ns(1 uart clk) delay before W1C;
1487 * single apb access will incur 2 pclk(133.12Mhz) delay,
1488 * so add 2 dummy reads
1490 dummy_read = pl011_read(uap, REG_ICR);
1491 dummy_read = pl011_read(uap, REG_ICR);
1494 static irqreturn_t pl011_int(int irq, void *dev_id)
1496 struct uart_amba_port *uap = dev_id;
1497 unsigned long flags;
1498 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1502 spin_lock_irqsave(&uap->port.lock, flags);
1503 imsc = pl011_read(uap, REG_IMSC);
1504 status = pl011_read(uap, REG_RIS) & imsc;
1507 check_apply_cts_event_workaround(uap);
1509 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1513 if (status & (UART011_RTIS|UART011_RXIS)) {
1514 if (pl011_dma_rx_running(uap))
1515 pl011_dma_rx_irq(uap);
1517 pl011_rx_chars(uap);
1519 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1520 UART011_CTSMIS|UART011_RIMIS))
1521 pl011_modem_status(uap);
1522 if (status & UART011_TXIS)
1523 pl011_tx_chars(uap, true);
1525 if (pass_counter-- == 0)
1528 status = pl011_read(uap, REG_RIS) & imsc;
1529 } while (status != 0);
1533 spin_unlock_irqrestore(&uap->port.lock, flags);
1535 return IRQ_RETVAL(handled);
1538 static unsigned int pl011_tx_empty(struct uart_port *port)
1540 struct uart_amba_port *uap =
1541 container_of(port, struct uart_amba_port, port);
1543 /* Allow feature register bits to be inverted to work around errata */
1544 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1546 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1550 static unsigned int pl011_get_mctrl(struct uart_port *port)
1552 struct uart_amba_port *uap =
1553 container_of(port, struct uart_amba_port, port);
1554 unsigned int result = 0;
1555 unsigned int status = pl011_read(uap, REG_FR);
1557 #define TIOCMBIT(uartbit, tiocmbit) \
1558 if (status & uartbit) \
1561 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1562 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1563 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1564 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1569 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1571 struct uart_amba_port *uap =
1572 container_of(port, struct uart_amba_port, port);
1575 cr = pl011_read(uap, REG_CR);
1577 #define TIOCMBIT(tiocmbit, uartbit) \
1578 if (mctrl & tiocmbit) \
1583 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1584 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1585 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1586 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1587 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1590 /* We need to disable auto-RTS if we want to turn RTS off */
1591 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1595 pl011_write(cr, uap, REG_CR);
1598 static void pl011_break_ctl(struct uart_port *port, int break_state)
1600 struct uart_amba_port *uap =
1601 container_of(port, struct uart_amba_port, port);
1602 unsigned long flags;
1605 spin_lock_irqsave(&uap->port.lock, flags);
1606 lcr_h = pl011_read(uap, REG_LCRH_TX);
1607 if (break_state == -1)
1608 lcr_h |= UART01x_LCRH_BRK;
1610 lcr_h &= ~UART01x_LCRH_BRK;
1611 pl011_write(lcr_h, uap, REG_LCRH_TX);
1612 spin_unlock_irqrestore(&uap->port.lock, flags);
1615 #ifdef CONFIG_CONSOLE_POLL
1617 static void pl011_quiesce_irqs(struct uart_port *port)
1619 struct uart_amba_port *uap =
1620 container_of(port, struct uart_amba_port, port);
1622 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1624 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1625 * we simply mask it. start_tx() will unmask it.
1627 * Note we can race with start_tx(), and if the race happens, the
1628 * polling user might get another interrupt just after we clear it.
1629 * But it should be OK and can happen even w/o the race, e.g.
1630 * controller immediately got some new data and raised the IRQ.
1632 * And whoever uses polling routines assumes that it manages the device
1633 * (including tx queue), so we're also fine with start_tx()'s caller
1636 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1640 static int pl011_get_poll_char(struct uart_port *port)
1642 struct uart_amba_port *uap =
1643 container_of(port, struct uart_amba_port, port);
1644 unsigned int status;
1647 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1650 pl011_quiesce_irqs(port);
1652 status = pl011_read(uap, REG_FR);
1653 if (status & UART01x_FR_RXFE)
1654 return NO_POLL_CHAR;
1656 return pl011_read(uap, REG_DR);
1659 static void pl011_put_poll_char(struct uart_port *port,
1662 struct uart_amba_port *uap =
1663 container_of(port, struct uart_amba_port, port);
1665 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1668 pl011_write(ch, uap, REG_DR);
1671 #endif /* CONFIG_CONSOLE_POLL */
1673 static int pl011_hwinit(struct uart_port *port)
1675 struct uart_amba_port *uap =
1676 container_of(port, struct uart_amba_port, port);
1679 /* Optionaly enable pins to be muxed in and configured */
1680 pinctrl_pm_select_default_state(port->dev);
1683 * Try to enable the clock producer.
1685 retval = clk_prepare_enable(uap->clk);
1689 uap->port.uartclk = clk_get_rate(uap->clk);
1691 /* Clear pending error and receive interrupts */
1692 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1693 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1697 * Save interrupts enable mask, and enable RX interrupts in case if
1698 * the interrupt is used for NMI entry.
1700 uap->im = pl011_read(uap, REG_IMSC);
1701 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1703 if (dev_get_platdata(uap->port.dev)) {
1704 struct amba_pl011_data *plat;
1706 plat = dev_get_platdata(uap->port.dev);
1713 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1715 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1716 pl011_reg_to_offset(uap, REG_LCRH_TX);
1719 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1721 pl011_write(lcr_h, uap, REG_LCRH_RX);
1722 if (pl011_split_lcrh(uap)) {
1725 * Wait 10 PCLKs before writing LCRH_TX register,
1726 * to get this delay write read only register 10 times
1728 for (i = 0; i < 10; ++i)
1729 pl011_write(0xff, uap, REG_MIS);
1730 pl011_write(lcr_h, uap, REG_LCRH_TX);
1734 static int pl011_allocate_irq(struct uart_amba_port *uap)
1736 pl011_write(uap->im, uap, REG_IMSC);
1738 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1742 * Enable interrupts, only timeouts when using DMA
1743 * if initial RX DMA job failed, start in interrupt mode
1746 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1750 spin_lock_irq(&uap->port.lock);
1752 /* Clear out any spuriously appearing RX interrupts */
1753 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1756 * RXIS is asserted only when the RX FIFO transitions from below
1757 * to above the trigger threshold. If the RX FIFO is already
1758 * full to the threshold this can't happen and RXIS will now be
1759 * stuck off. Drain the RX FIFO explicitly to fix this:
1761 for (i = 0; i < uap->fifosize * 2; ++i) {
1762 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1765 pl011_read(uap, REG_DR);
1768 uap->im = UART011_RTIM;
1769 if (!pl011_dma_rx_running(uap))
1770 uap->im |= UART011_RXIM;
1771 pl011_write(uap->im, uap, REG_IMSC);
1772 spin_unlock_irq(&uap->port.lock);
1775 static int pl011_startup(struct uart_port *port)
1777 struct uart_amba_port *uap =
1778 container_of(port, struct uart_amba_port, port);
1782 retval = pl011_hwinit(port);
1786 retval = pl011_allocate_irq(uap);
1790 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1792 spin_lock_irq(&uap->port.lock);
1794 /* restore RTS and DTR */
1795 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1796 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1797 pl011_write(cr, uap, REG_CR);
1799 spin_unlock_irq(&uap->port.lock);
1802 * initialise the old status of the modem signals
1804 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1807 pl011_dma_startup(uap);
1809 pl011_enable_interrupts(uap);
1814 clk_disable_unprepare(uap->clk);
1818 static int sbsa_uart_startup(struct uart_port *port)
1820 struct uart_amba_port *uap =
1821 container_of(port, struct uart_amba_port, port);
1824 retval = pl011_hwinit(port);
1828 retval = pl011_allocate_irq(uap);
1832 /* The SBSA UART does not support any modem status lines. */
1833 uap->old_status = 0;
1835 pl011_enable_interrupts(uap);
1840 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1845 val = pl011_read(uap, lcrh);
1846 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1847 pl011_write(val, uap, lcrh);
1851 * disable the port. It should not disable RTS and DTR.
1852 * Also RTS and DTR state should be preserved to restore
1853 * it during startup().
1855 static void pl011_disable_uart(struct uart_amba_port *uap)
1859 uap->autorts = false;
1860 spin_lock_irq(&uap->port.lock);
1861 cr = pl011_read(uap, REG_CR);
1863 cr &= UART011_CR_RTS | UART011_CR_DTR;
1864 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1865 pl011_write(cr, uap, REG_CR);
1866 spin_unlock_irq(&uap->port.lock);
1869 * disable break condition and fifos
1871 pl011_shutdown_channel(uap, REG_LCRH_RX);
1872 if (pl011_split_lcrh(uap))
1873 pl011_shutdown_channel(uap, REG_LCRH_TX);
1876 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1878 spin_lock_irq(&uap->port.lock);
1880 /* mask all interrupts and clear all pending ones */
1882 pl011_write(uap->im, uap, REG_IMSC);
1883 pl011_write(0xffff, uap, REG_ICR);
1885 spin_unlock_irq(&uap->port.lock);
1888 static void pl011_shutdown(struct uart_port *port)
1890 struct uart_amba_port *uap =
1891 container_of(port, struct uart_amba_port, port);
1893 pl011_disable_interrupts(uap);
1895 pl011_dma_shutdown(uap);
1897 free_irq(uap->port.irq, uap);
1899 pl011_disable_uart(uap);
1902 * Shut down the clock producer
1904 clk_disable_unprepare(uap->clk);
1905 /* Optionally let pins go into sleep states */
1906 pinctrl_pm_select_sleep_state(port->dev);
1908 if (dev_get_platdata(uap->port.dev)) {
1909 struct amba_pl011_data *plat;
1911 plat = dev_get_platdata(uap->port.dev);
1916 if (uap->port.ops->flush_buffer)
1917 uap->port.ops->flush_buffer(port);
1920 static void sbsa_uart_shutdown(struct uart_port *port)
1922 struct uart_amba_port *uap =
1923 container_of(port, struct uart_amba_port, port);
1925 pl011_disable_interrupts(uap);
1927 free_irq(uap->port.irq, uap);
1929 if (uap->port.ops->flush_buffer)
1930 uap->port.ops->flush_buffer(port);
1934 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1936 port->read_status_mask = UART011_DR_OE | 255;
1937 if (termios->c_iflag & INPCK)
1938 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1939 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1940 port->read_status_mask |= UART011_DR_BE;
1943 * Characters to ignore
1945 port->ignore_status_mask = 0;
1946 if (termios->c_iflag & IGNPAR)
1947 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1948 if (termios->c_iflag & IGNBRK) {
1949 port->ignore_status_mask |= UART011_DR_BE;
1951 * If we're ignoring parity and break indicators,
1952 * ignore overruns too (for real raw support).
1954 if (termios->c_iflag & IGNPAR)
1955 port->ignore_status_mask |= UART011_DR_OE;
1959 * Ignore all characters if CREAD is not set.
1961 if ((termios->c_cflag & CREAD) == 0)
1962 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1966 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1967 struct ktermios *old)
1969 struct uart_amba_port *uap =
1970 container_of(port, struct uart_amba_port, port);
1971 unsigned int lcr_h, old_cr;
1972 unsigned long flags;
1973 unsigned int baud, quot, clkdiv;
1975 if (uap->vendor->oversampling)
1981 * Ask the core to calculate the divisor for us.
1983 baud = uart_get_baud_rate(port, termios, old, 0,
1984 port->uartclk / clkdiv);
1985 #ifdef CONFIG_DMA_ENGINE
1987 * Adjust RX DMA polling rate with baud rate if not specified.
1989 if (uap->dmarx.auto_poll_rate)
1990 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
1993 if (baud > port->uartclk/16)
1994 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
1996 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
1998 switch (termios->c_cflag & CSIZE) {
2000 lcr_h = UART01x_LCRH_WLEN_5;
2003 lcr_h = UART01x_LCRH_WLEN_6;
2006 lcr_h = UART01x_LCRH_WLEN_7;
2009 lcr_h = UART01x_LCRH_WLEN_8;
2012 if (termios->c_cflag & CSTOPB)
2013 lcr_h |= UART01x_LCRH_STP2;
2014 if (termios->c_cflag & PARENB) {
2015 lcr_h |= UART01x_LCRH_PEN;
2016 if (!(termios->c_cflag & PARODD))
2017 lcr_h |= UART01x_LCRH_EPS;
2018 if (termios->c_cflag & CMSPAR)
2019 lcr_h |= UART011_LCRH_SPS;
2021 if (uap->fifosize > 1)
2022 lcr_h |= UART01x_LCRH_FEN;
2024 spin_lock_irqsave(&port->lock, flags);
2027 * Update the per-port timeout.
2029 uart_update_timeout(port, termios->c_cflag, baud);
2031 pl011_setup_status_masks(port, termios);
2033 if (UART_ENABLE_MS(port, termios->c_cflag))
2034 pl011_enable_ms(port);
2036 /* first, disable everything */
2037 old_cr = pl011_read(uap, REG_CR);
2038 pl011_write(0, uap, REG_CR);
2040 if (termios->c_cflag & CRTSCTS) {
2041 if (old_cr & UART011_CR_RTS)
2042 old_cr |= UART011_CR_RTSEN;
2044 old_cr |= UART011_CR_CTSEN;
2045 uap->autorts = true;
2047 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2048 uap->autorts = false;
2051 if (uap->vendor->oversampling) {
2052 if (baud > port->uartclk / 16)
2053 old_cr |= ST_UART011_CR_OVSFACT;
2055 old_cr &= ~ST_UART011_CR_OVSFACT;
2059 * Workaround for the ST Micro oversampling variants to
2060 * increase the bitrate slightly, by lowering the divisor,
2061 * to avoid delayed sampling of start bit at high speeds,
2062 * else we see data corruption.
2064 if (uap->vendor->oversampling) {
2065 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2067 else if ((baud > 3250000) && (quot > 2))
2071 pl011_write(quot & 0x3f, uap, REG_FBRD);
2072 pl011_write(quot >> 6, uap, REG_IBRD);
2075 * ----------v----------v----------v----------v-----
2076 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2077 * REG_FBRD & REG_IBRD.
2078 * ----------^----------^----------^----------^-----
2080 pl011_write_lcr_h(uap, lcr_h);
2081 pl011_write(old_cr, uap, REG_CR);
2083 spin_unlock_irqrestore(&port->lock, flags);
2087 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2088 struct ktermios *old)
2090 struct uart_amba_port *uap =
2091 container_of(port, struct uart_amba_port, port);
2092 unsigned long flags;
2094 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2096 /* The SBSA UART only supports 8n1 without hardware flow control. */
2097 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2098 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2099 termios->c_cflag |= CS8 | CLOCAL;
2101 spin_lock_irqsave(&port->lock, flags);
2102 uart_update_timeout(port, CS8, uap->fixed_baud);
2103 pl011_setup_status_masks(port, termios);
2104 spin_unlock_irqrestore(&port->lock, flags);
2107 static const char *pl011_type(struct uart_port *port)
2109 struct uart_amba_port *uap =
2110 container_of(port, struct uart_amba_port, port);
2111 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2115 * Configure/autoconfigure the port.
2117 static void pl011_config_port(struct uart_port *port, int flags)
2119 if (flags & UART_CONFIG_TYPE)
2120 port->type = PORT_AMBA;
2124 * verify the new serial_struct (for TIOCSSERIAL).
2126 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2129 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2131 if (ser->irq < 0 || ser->irq >= nr_irqs)
2133 if (ser->baud_base < 9600)
2135 if (port->mapbase != (unsigned long) ser->iomem_base)
2140 static const struct uart_ops amba_pl011_pops = {
2141 .tx_empty = pl011_tx_empty,
2142 .set_mctrl = pl011_set_mctrl,
2143 .get_mctrl = pl011_get_mctrl,
2144 .stop_tx = pl011_stop_tx,
2145 .start_tx = pl011_start_tx,
2146 .stop_rx = pl011_stop_rx,
2147 .enable_ms = pl011_enable_ms,
2148 .break_ctl = pl011_break_ctl,
2149 .startup = pl011_startup,
2150 .shutdown = pl011_shutdown,
2151 .flush_buffer = pl011_dma_flush_buffer,
2152 .set_termios = pl011_set_termios,
2154 .config_port = pl011_config_port,
2155 .verify_port = pl011_verify_port,
2156 #ifdef CONFIG_CONSOLE_POLL
2157 .poll_init = pl011_hwinit,
2158 .poll_get_char = pl011_get_poll_char,
2159 .poll_put_char = pl011_put_poll_char,
2163 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2167 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2172 static const struct uart_ops sbsa_uart_pops = {
2173 .tx_empty = pl011_tx_empty,
2174 .set_mctrl = sbsa_uart_set_mctrl,
2175 .get_mctrl = sbsa_uart_get_mctrl,
2176 .stop_tx = pl011_stop_tx,
2177 .start_tx = pl011_start_tx,
2178 .stop_rx = pl011_stop_rx,
2179 .startup = sbsa_uart_startup,
2180 .shutdown = sbsa_uart_shutdown,
2181 .set_termios = sbsa_uart_set_termios,
2183 .config_port = pl011_config_port,
2184 .verify_port = pl011_verify_port,
2185 #ifdef CONFIG_CONSOLE_POLL
2186 .poll_init = pl011_hwinit,
2187 .poll_get_char = pl011_get_poll_char,
2188 .poll_put_char = pl011_put_poll_char,
2192 static struct uart_amba_port *amba_ports[UART_NR];
2194 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2196 static void pl011_console_putchar(struct uart_port *port, int ch)
2198 struct uart_amba_port *uap =
2199 container_of(port, struct uart_amba_port, port);
2201 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2203 pl011_write(ch, uap, REG_DR);
2207 pl011_console_write(struct console *co, const char *s, unsigned int count)
2209 struct uart_amba_port *uap = amba_ports[co->index];
2210 unsigned int old_cr = 0, new_cr;
2211 unsigned long flags;
2214 clk_enable(uap->clk);
2216 local_irq_save(flags);
2217 if (uap->port.sysrq)
2219 else if (oops_in_progress)
2220 locked = spin_trylock(&uap->port.lock);
2222 spin_lock(&uap->port.lock);
2225 * First save the CR then disable the interrupts
2227 if (!uap->vendor->always_enabled) {
2228 old_cr = pl011_read(uap, REG_CR);
2229 new_cr = old_cr & ~UART011_CR_CTSEN;
2230 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2231 pl011_write(new_cr, uap, REG_CR);
2234 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2237 * Finally, wait for transmitter to become empty and restore the
2238 * TCR. Allow feature register bits to be inverted to work around
2241 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2242 & uap->vendor->fr_busy)
2244 if (!uap->vendor->always_enabled)
2245 pl011_write(old_cr, uap, REG_CR);
2248 spin_unlock(&uap->port.lock);
2249 local_irq_restore(flags);
2251 clk_disable(uap->clk);
2254 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2255 int *parity, int *bits)
2257 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2258 unsigned int lcr_h, ibrd, fbrd;
2260 lcr_h = pl011_read(uap, REG_LCRH_TX);
2263 if (lcr_h & UART01x_LCRH_PEN) {
2264 if (lcr_h & UART01x_LCRH_EPS)
2270 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2275 ibrd = pl011_read(uap, REG_IBRD);
2276 fbrd = pl011_read(uap, REG_FBRD);
2278 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2280 if (uap->vendor->oversampling) {
2281 if (pl011_read(uap, REG_CR)
2282 & ST_UART011_CR_OVSFACT)
2288 static int pl011_console_setup(struct console *co, char *options)
2290 struct uart_amba_port *uap;
2298 * Check whether an invalid uart number has been specified, and
2299 * if so, search for the first available port that does have
2302 if (co->index >= UART_NR)
2304 uap = amba_ports[co->index];
2308 /* Allow pins to be muxed in and configured */
2309 pinctrl_pm_select_default_state(uap->port.dev);
2311 ret = clk_prepare(uap->clk);
2315 if (dev_get_platdata(uap->port.dev)) {
2316 struct amba_pl011_data *plat;
2318 plat = dev_get_platdata(uap->port.dev);
2323 uap->port.uartclk = clk_get_rate(uap->clk);
2325 if (uap->vendor->fixed_options) {
2326 baud = uap->fixed_baud;
2329 uart_parse_options(options,
2330 &baud, &parity, &bits, &flow);
2332 pl011_console_get_options(uap, &baud, &parity, &bits);
2335 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2339 * pl011_console_match - non-standard console matching
2340 * @co: registering console
2341 * @name: name from console command line
2342 * @idx: index from console command line
2343 * @options: ptr to option string from console command line
2345 * Only attempts to match console command lines of the form:
2346 * console=pl011,mmio|mmio32,<addr>[,<options>]
2347 * console=pl011,0x<addr>[,<options>]
2348 * This form is used to register an initial earlycon boot console and
2349 * replace it with the amba_console at pl011 driver init.
2351 * Performs console setup for a match (as required by interface)
2352 * If no <options> are specified, then assume the h/w is already setup.
2354 * Returns 0 if console matches; otherwise non-zero to use default matching
2356 static int pl011_console_match(struct console *co, char *name, int idx,
2359 unsigned char iotype;
2360 resource_size_t addr;
2364 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2365 * have a distinct console name, so make sure we check for that.
2366 * The actual implementation of the erratum occurs in the probe
2369 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2372 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2375 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2378 /* try to match the port specified on the command line */
2379 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2380 struct uart_port *port;
2385 port = &amba_ports[i]->port;
2387 if (port->mapbase != addr)
2392 return pl011_console_setup(co, options);
2398 static struct uart_driver amba_reg;
2399 static struct console amba_console = {
2401 .write = pl011_console_write,
2402 .device = uart_console_device,
2403 .setup = pl011_console_setup,
2404 .match = pl011_console_match,
2405 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2410 #define AMBA_CONSOLE (&amba_console)
2412 static void qdf2400_e44_putc(struct uart_port *port, int c)
2414 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2416 writel(c, port->membase + UART01x_DR);
2417 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2421 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2423 struct earlycon_device *dev = con->data;
2425 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2428 static void pl011_putc(struct uart_port *port, int c)
2430 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2432 if (port->iotype == UPIO_MEM32)
2433 writel(c, port->membase + UART01x_DR);
2435 writeb(c, port->membase + UART01x_DR);
2436 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2440 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2442 struct earlycon_device *dev = con->data;
2444 uart_console_write(&dev->port, s, n, pl011_putc);
2448 * On non-ACPI systems, earlycon is enabled by specifying
2449 * "earlycon=pl011,<address>" on the kernel command line.
2451 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2452 * by specifying only "earlycon" on the command line. Because it requires
2453 * SPCR, the console starts after ACPI is parsed, which is later than a
2454 * traditional early console.
2456 * To get the traditional early console that starts before ACPI is parsed,
2457 * specify the full "earlycon=pl011,<address>" option.
2459 static int __init pl011_early_console_setup(struct earlycon_device *device,
2462 if (!device->port.membase)
2465 device->con->write = pl011_early_write;
2469 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2470 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2473 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2474 * Erratum 44, traditional earlycon can be enabled by specifying
2475 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2477 * Alternatively, you can just specify "earlycon", and the early console
2478 * will be enabled with the information from the SPCR table. In this
2479 * case, the SPCR code will detect the need for the E44 work-around,
2480 * and set the console name to "qdf2400_e44".
2483 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2486 if (!device->port.membase)
2489 device->con->write = qdf2400_e44_early_write;
2492 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2495 #define AMBA_CONSOLE NULL
2498 static struct uart_driver amba_reg = {
2499 .owner = THIS_MODULE,
2500 .driver_name = "ttyAMA",
2501 .dev_name = "ttyAMA",
2502 .major = SERIAL_AMBA_MAJOR,
2503 .minor = SERIAL_AMBA_MINOR,
2505 .cons = AMBA_CONSOLE,
2508 static int pl011_probe_dt_alias(int index, struct device *dev)
2510 struct device_node *np;
2511 static bool seen_dev_with_alias = false;
2512 static bool seen_dev_without_alias = false;
2515 if (!IS_ENABLED(CONFIG_OF))
2522 ret = of_alias_get_id(np, "serial");
2524 seen_dev_without_alias = true;
2527 seen_dev_with_alias = true;
2528 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2529 dev_warn(dev, "requested serial port %d not available.\n", ret);
2534 if (seen_dev_with_alias && seen_dev_without_alias)
2535 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2540 /* unregisters the driver also if no more ports are left */
2541 static void pl011_unregister_port(struct uart_amba_port *uap)
2546 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2547 if (amba_ports[i] == uap)
2548 amba_ports[i] = NULL;
2549 else if (amba_ports[i])
2552 pl011_dma_remove(uap);
2554 uart_unregister_driver(&amba_reg);
2557 static int pl011_find_free_port(void)
2561 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2562 if (amba_ports[i] == NULL)
2568 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2569 struct resource *mmiobase, int index)
2573 base = devm_ioremap_resource(dev, mmiobase);
2575 return PTR_ERR(base);
2577 index = pl011_probe_dt_alias(index, dev);
2580 uap->port.dev = dev;
2581 uap->port.mapbase = mmiobase->start;
2582 uap->port.membase = base;
2583 uap->port.fifosize = uap->fifosize;
2584 uap->port.flags = UPF_BOOT_AUTOCONF;
2585 uap->port.line = index;
2586 spin_lock_init(&uap->port.lock);
2588 amba_ports[index] = uap;
2593 static int pl011_register_port(struct uart_amba_port *uap)
2597 /* Ensure interrupts from this UART are masked and cleared */
2598 pl011_write(0, uap, REG_IMSC);
2599 pl011_write(0xffff, uap, REG_ICR);
2601 if (!amba_reg.state) {
2602 ret = uart_register_driver(&amba_reg);
2604 dev_err(uap->port.dev,
2605 "Failed to register AMBA-PL011 driver\n");
2606 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2607 if (amba_ports[i] == uap)
2608 amba_ports[i] = NULL;
2613 ret = uart_add_one_port(&amba_reg, &uap->port);
2615 pl011_unregister_port(uap);
2620 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2622 struct uart_amba_port *uap;
2623 struct vendor_data *vendor = id->data;
2626 portnr = pl011_find_free_port();
2630 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2635 uap->clk = devm_clk_get(&dev->dev, NULL);
2636 if (IS_ERR(uap->clk))
2637 return PTR_ERR(uap->clk);
2639 uap->reg_offset = vendor->reg_offset;
2640 uap->vendor = vendor;
2641 uap->fifosize = vendor->get_fifosize(dev);
2642 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2643 uap->port.irq = dev->irq[0];
2644 uap->port.ops = &amba_pl011_pops;
2646 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2648 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2652 amba_set_drvdata(dev, uap);
2654 return pl011_register_port(uap);
2657 static int pl011_remove(struct amba_device *dev)
2659 struct uart_amba_port *uap = amba_get_drvdata(dev);
2661 uart_remove_one_port(&amba_reg, &uap->port);
2662 pl011_unregister_port(uap);
2666 #ifdef CONFIG_PM_SLEEP
2667 static int pl011_suspend(struct device *dev)
2669 struct uart_amba_port *uap = dev_get_drvdata(dev);
2674 return uart_suspend_port(&amba_reg, &uap->port);
2677 static int pl011_resume(struct device *dev)
2679 struct uart_amba_port *uap = dev_get_drvdata(dev);
2684 return uart_resume_port(&amba_reg, &uap->port);
2688 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2690 static int sbsa_uart_probe(struct platform_device *pdev)
2692 struct uart_amba_port *uap;
2698 * Check the mandatory baud rate parameter in the DT node early
2699 * so that we can easily exit with the error.
2701 if (pdev->dev.of_node) {
2702 struct device_node *np = pdev->dev.of_node;
2704 ret = of_property_read_u32(np, "current-speed", &baudrate);
2711 portnr = pl011_find_free_port();
2715 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2720 ret = platform_get_irq(pdev, 0);
2722 if (ret != -EPROBE_DEFER)
2723 dev_err(&pdev->dev, "cannot obtain irq\n");
2726 uap->port.irq = ret;
2728 #ifdef CONFIG_ACPI_SPCR_TABLE
2729 if (qdf2400_e44_present) {
2730 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2731 uap->vendor = &vendor_qdt_qdf2400_e44;
2734 uap->vendor = &vendor_sbsa;
2736 uap->reg_offset = uap->vendor->reg_offset;
2738 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2739 uap->port.ops = &sbsa_uart_pops;
2740 uap->fixed_baud = baudrate;
2742 snprintf(uap->type, sizeof(uap->type), "SBSA");
2744 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2746 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2750 platform_set_drvdata(pdev, uap);
2752 return pl011_register_port(uap);
2755 static int sbsa_uart_remove(struct platform_device *pdev)
2757 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2759 uart_remove_one_port(&amba_reg, &uap->port);
2760 pl011_unregister_port(uap);
2764 static const struct of_device_id sbsa_uart_of_match[] = {
2765 { .compatible = "arm,sbsa-uart", },
2768 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2770 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2775 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2777 static struct platform_driver arm_sbsa_uart_platform_driver = {
2778 .probe = sbsa_uart_probe,
2779 .remove = sbsa_uart_remove,
2781 .name = "sbsa-uart",
2782 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2783 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2784 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2788 static const struct amba_id pl011_ids[] = {
2792 .data = &vendor_arm,
2800 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2802 .data = &vendor_zte,
2807 MODULE_DEVICE_TABLE(amba, pl011_ids);
2809 static struct amba_driver pl011_driver = {
2811 .name = "uart-pl011",
2812 .pm = &pl011_dev_pm_ops,
2813 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2815 .id_table = pl011_ids,
2816 .probe = pl011_probe,
2817 .remove = pl011_remove,
2820 static int __init pl011_init(void)
2822 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2824 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2825 pr_warn("could not register SBSA UART platform driver\n");
2826 return amba_driver_register(&pl011_driver);
2829 static void __exit pl011_exit(void)
2831 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2832 amba_driver_unregister(&pl011_driver);
2836 * While this can be a module, if builtin it's most likely the console
2837 * So let's leave module_exit but move module_init to an earlier place
2839 arch_initcall(pl011_init);
2840 module_exit(pl011_exit);
2842 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2843 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2844 MODULE_LICENSE("GPL");