1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for AMBA serial ports
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 * Copyright 1999 ARM Limited
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 * Copyright (C) 2010 ST-Ericsson SA
11 * This is a generic driver for ARM AMBA-type serial ports. They
12 * have a lot of 16550-like features, but are not register compatible.
13 * Note that although they do have CTS, DCD and DSR inputs, they do
14 * not have an RI input, nor do they have DTR or RTS outputs. If
15 * required, these have to be supplied via some other means (eg, GPIO)
16 * and hooked into this driver.
20 #if defined(CONFIG_SERIAL_AMBA_PL011_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
24 #include <linux/module.h>
25 #include <linux/ioport.h>
26 #include <linux/init.h>
27 #include <linux/console.h>
28 #include <linux/sysrq.h>
29 #include <linux/device.h>
30 #include <linux/tty.h>
31 #include <linux/tty_flip.h>
32 #include <linux/serial_core.h>
33 #include <linux/serial.h>
34 #include <linux/amba/bus.h>
35 #include <linux/amba/serial.h>
36 #include <linux/clk.h>
37 #include <linux/slab.h>
38 #include <linux/dmaengine.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/scatterlist.h>
41 #include <linux/delay.h>
42 #include <linux/types.h>
44 #include <linux/of_device.h>
45 #include <linux/pinctrl/consumer.h>
46 #include <linux/sizes.h>
48 #include <linux/acpi.h>
50 #include "amba-pl011.h"
54 #define SERIAL_AMBA_MAJOR 204
55 #define SERIAL_AMBA_MINOR 64
56 #define SERIAL_AMBA_NR UART_NR
58 #define AMBA_ISR_PASS_LIMIT 256
60 #define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
61 #define UART_DUMMY_DR_RX (1 << 16)
63 static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
64 [REG_DR] = UART01x_DR,
65 [REG_FR] = UART01x_FR,
66 [REG_LCRH_RX] = UART011_LCRH,
67 [REG_LCRH_TX] = UART011_LCRH,
68 [REG_IBRD] = UART011_IBRD,
69 [REG_FBRD] = UART011_FBRD,
70 [REG_CR] = UART011_CR,
71 [REG_IFLS] = UART011_IFLS,
72 [REG_IMSC] = UART011_IMSC,
73 [REG_RIS] = UART011_RIS,
74 [REG_MIS] = UART011_MIS,
75 [REG_ICR] = UART011_ICR,
76 [REG_DMACR] = UART011_DMACR,
79 /* There is by now at least one vendor with differing details, so handle it */
81 const u16 *reg_offset;
91 bool cts_event_workaround;
95 unsigned int (*get_fifosize)(struct amba_device *dev);
98 static unsigned int get_fifosize_arm(struct amba_device *dev)
100 return amba_rev(dev) < 3 ? 16 : 32;
103 static struct vendor_data vendor_arm = {
104 .reg_offset = pl011_std_offsets,
105 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
106 .fr_busy = UART01x_FR_BUSY,
107 .fr_dsr = UART01x_FR_DSR,
108 .fr_cts = UART01x_FR_CTS,
109 .fr_ri = UART011_FR_RI,
110 .oversampling = false,
111 .dma_threshold = false,
112 .cts_event_workaround = false,
113 .always_enabled = false,
114 .fixed_options = false,
115 .get_fifosize = get_fifosize_arm,
118 static const struct vendor_data vendor_sbsa = {
119 .reg_offset = pl011_std_offsets,
120 .fr_busy = UART01x_FR_BUSY,
121 .fr_dsr = UART01x_FR_DSR,
122 .fr_cts = UART01x_FR_CTS,
123 .fr_ri = UART011_FR_RI,
125 .oversampling = false,
126 .dma_threshold = false,
127 .cts_event_workaround = false,
128 .always_enabled = true,
129 .fixed_options = true,
132 #ifdef CONFIG_ACPI_SPCR_TABLE
133 static const struct vendor_data vendor_qdt_qdf2400_e44 = {
134 .reg_offset = pl011_std_offsets,
135 .fr_busy = UART011_FR_TXFE,
136 .fr_dsr = UART01x_FR_DSR,
137 .fr_cts = UART01x_FR_CTS,
138 .fr_ri = UART011_FR_RI,
139 .inv_fr = UART011_FR_TXFE,
141 .oversampling = false,
142 .dma_threshold = false,
143 .cts_event_workaround = false,
144 .always_enabled = true,
145 .fixed_options = true,
149 static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
150 [REG_DR] = UART01x_DR,
151 [REG_ST_DMAWM] = ST_UART011_DMAWM,
152 [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
153 [REG_FR] = UART01x_FR,
154 [REG_LCRH_RX] = ST_UART011_LCRH_RX,
155 [REG_LCRH_TX] = ST_UART011_LCRH_TX,
156 [REG_IBRD] = UART011_IBRD,
157 [REG_FBRD] = UART011_FBRD,
158 [REG_CR] = UART011_CR,
159 [REG_IFLS] = UART011_IFLS,
160 [REG_IMSC] = UART011_IMSC,
161 [REG_RIS] = UART011_RIS,
162 [REG_MIS] = UART011_MIS,
163 [REG_ICR] = UART011_ICR,
164 [REG_DMACR] = UART011_DMACR,
165 [REG_ST_XFCR] = ST_UART011_XFCR,
166 [REG_ST_XON1] = ST_UART011_XON1,
167 [REG_ST_XON2] = ST_UART011_XON2,
168 [REG_ST_XOFF1] = ST_UART011_XOFF1,
169 [REG_ST_XOFF2] = ST_UART011_XOFF2,
170 [REG_ST_ITCR] = ST_UART011_ITCR,
171 [REG_ST_ITIP] = ST_UART011_ITIP,
172 [REG_ST_ABCR] = ST_UART011_ABCR,
173 [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
176 static unsigned int get_fifosize_st(struct amba_device *dev)
181 static struct vendor_data vendor_st = {
182 .reg_offset = pl011_st_offsets,
183 .ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
184 .fr_busy = UART01x_FR_BUSY,
185 .fr_dsr = UART01x_FR_DSR,
186 .fr_cts = UART01x_FR_CTS,
187 .fr_ri = UART011_FR_RI,
188 .oversampling = true,
189 .dma_threshold = true,
190 .cts_event_workaround = true,
191 .always_enabled = false,
192 .fixed_options = false,
193 .get_fifosize = get_fifosize_st,
196 static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
197 [REG_DR] = ZX_UART011_DR,
198 [REG_FR] = ZX_UART011_FR,
199 [REG_LCRH_RX] = ZX_UART011_LCRH,
200 [REG_LCRH_TX] = ZX_UART011_LCRH,
201 [REG_IBRD] = ZX_UART011_IBRD,
202 [REG_FBRD] = ZX_UART011_FBRD,
203 [REG_CR] = ZX_UART011_CR,
204 [REG_IFLS] = ZX_UART011_IFLS,
205 [REG_IMSC] = ZX_UART011_IMSC,
206 [REG_RIS] = ZX_UART011_RIS,
207 [REG_MIS] = ZX_UART011_MIS,
208 [REG_ICR] = ZX_UART011_ICR,
209 [REG_DMACR] = ZX_UART011_DMACR,
212 static unsigned int get_fifosize_zte(struct amba_device *dev)
217 static struct vendor_data vendor_zte = {
218 .reg_offset = pl011_zte_offsets,
220 .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
221 .fr_busy = ZX_UART01x_FR_BUSY,
222 .fr_dsr = ZX_UART01x_FR_DSR,
223 .fr_cts = ZX_UART01x_FR_CTS,
224 .fr_ri = ZX_UART011_FR_RI,
225 .get_fifosize = get_fifosize_zte,
228 /* Deals with DMA transactions */
231 struct scatterlist sg;
235 struct pl011_dmarx_data {
236 struct dma_chan *chan;
237 struct completion complete;
239 struct pl011_sgbuf sgbuf_a;
240 struct pl011_sgbuf sgbuf_b;
243 struct timer_list timer;
244 unsigned int last_residue;
245 unsigned long last_jiffies;
247 unsigned int poll_rate;
248 unsigned int poll_timeout;
251 struct pl011_dmatx_data {
252 struct dma_chan *chan;
253 struct scatterlist sg;
259 * We wrap our port structure around the generic uart_port.
261 struct uart_amba_port {
262 struct uart_port port;
263 const u16 *reg_offset;
265 const struct vendor_data *vendor;
266 unsigned int dmacr; /* dma control reg */
267 unsigned int im; /* interrupt mask */
268 unsigned int old_status;
269 unsigned int fifosize; /* vendor-specific */
270 unsigned int old_cr; /* state during shutdown */
271 unsigned int fixed_baud; /* vendor-set fixed baud rate */
273 #ifdef CONFIG_DMA_ENGINE
277 struct pl011_dmarx_data dmarx;
278 struct pl011_dmatx_data dmatx;
283 static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
286 return uap->reg_offset[reg];
289 static unsigned int pl011_read(const struct uart_amba_port *uap,
292 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
294 return (uap->port.iotype == UPIO_MEM32) ?
295 readl_relaxed(addr) : readw_relaxed(addr);
298 static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
301 void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
303 if (uap->port.iotype == UPIO_MEM32)
304 writel_relaxed(val, addr);
306 writew_relaxed(val, addr);
310 * Reads up to 256 characters from the FIFO or until it's empty and
311 * inserts them into the TTY layer. Returns the number of characters
312 * read from the FIFO.
314 static int pl011_fifo_to_tty(struct uart_amba_port *uap)
316 unsigned int ch, flag, fifotaken;
320 for (fifotaken = 0; fifotaken != 256; fifotaken++) {
321 status = pl011_read(uap, REG_FR);
322 if (status & UART01x_FR_RXFE)
325 /* Take chars from the FIFO and update status */
326 ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
328 uap->port.icount.rx++;
330 if (unlikely(ch & UART_DR_ERROR)) {
331 if (ch & UART011_DR_BE) {
332 ch &= ~(UART011_DR_FE | UART011_DR_PE);
333 uap->port.icount.brk++;
334 if (uart_handle_break(&uap->port))
336 } else if (ch & UART011_DR_PE)
337 uap->port.icount.parity++;
338 else if (ch & UART011_DR_FE)
339 uap->port.icount.frame++;
340 if (ch & UART011_DR_OE)
341 uap->port.icount.overrun++;
343 ch &= uap->port.read_status_mask;
345 if (ch & UART011_DR_BE)
347 else if (ch & UART011_DR_PE)
349 else if (ch & UART011_DR_FE)
353 spin_unlock(&uap->port.lock);
354 sysrq = uart_handle_sysrq_char(&uap->port, ch & 255);
355 spin_lock(&uap->port.lock);
358 uart_insert_char(&uap->port, ch, UART011_DR_OE, ch, flag);
366 * All the DMA operation mode stuff goes inside this ifdef.
367 * This assumes that you have a generic DMA device interface,
368 * no custom DMA interfaces are supported.
370 #ifdef CONFIG_DMA_ENGINE
372 #define PL011_DMA_BUFFER_SIZE PAGE_SIZE
374 static int pl011_sgbuf_init(struct dma_chan *chan, struct pl011_sgbuf *sg,
375 enum dma_data_direction dir)
379 sg->buf = dma_alloc_coherent(chan->device->dev,
380 PL011_DMA_BUFFER_SIZE, &dma_addr, GFP_KERNEL);
384 sg_init_table(&sg->sg, 1);
385 sg_set_page(&sg->sg, phys_to_page(dma_addr),
386 PL011_DMA_BUFFER_SIZE, offset_in_page(dma_addr));
387 sg_dma_address(&sg->sg) = dma_addr;
388 sg_dma_len(&sg->sg) = PL011_DMA_BUFFER_SIZE;
393 static void pl011_sgbuf_free(struct dma_chan *chan, struct pl011_sgbuf *sg,
394 enum dma_data_direction dir)
397 dma_free_coherent(chan->device->dev,
398 PL011_DMA_BUFFER_SIZE, sg->buf,
399 sg_dma_address(&sg->sg));
403 static void pl011_dma_probe(struct uart_amba_port *uap)
405 /* DMA is the sole user of the platform data right now */
406 struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
407 struct device *dev = uap->port.dev;
408 struct dma_slave_config tx_conf = {
409 .dst_addr = uap->port.mapbase +
410 pl011_reg_to_offset(uap, REG_DR),
411 .dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
412 .direction = DMA_MEM_TO_DEV,
413 .dst_maxburst = uap->fifosize >> 1,
416 struct dma_chan *chan;
419 uap->dma_probed = true;
420 chan = dma_request_slave_channel_reason(dev, "tx");
422 if (PTR_ERR(chan) == -EPROBE_DEFER) {
423 uap->dma_probed = false;
427 /* We need platform data */
428 if (!plat || !plat->dma_filter) {
429 dev_info(uap->port.dev, "no DMA platform data\n");
433 /* Try to acquire a generic DMA engine slave TX channel */
435 dma_cap_set(DMA_SLAVE, mask);
437 chan = dma_request_channel(mask, plat->dma_filter,
440 dev_err(uap->port.dev, "no TX DMA channel!\n");
445 dmaengine_slave_config(chan, &tx_conf);
446 uap->dmatx.chan = chan;
448 dev_info(uap->port.dev, "DMA channel TX %s\n",
449 dma_chan_name(uap->dmatx.chan));
451 /* Optionally make use of an RX channel as well */
452 chan = dma_request_slave_channel(dev, "rx");
454 if (!chan && plat && plat->dma_rx_param) {
455 chan = dma_request_channel(mask, plat->dma_filter, plat->dma_rx_param);
458 dev_err(uap->port.dev, "no RX DMA channel!\n");
464 struct dma_slave_config rx_conf = {
465 .src_addr = uap->port.mapbase +
466 pl011_reg_to_offset(uap, REG_DR),
467 .src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
468 .direction = DMA_DEV_TO_MEM,
469 .src_maxburst = uap->fifosize >> 2,
472 struct dma_slave_caps caps;
475 * Some DMA controllers provide information on their capabilities.
476 * If the controller does, check for suitable residue processing
477 * otherwise assime all is well.
479 if (0 == dma_get_slave_caps(chan, &caps)) {
480 if (caps.residue_granularity ==
481 DMA_RESIDUE_GRANULARITY_DESCRIPTOR) {
482 dma_release_channel(chan);
483 dev_info(uap->port.dev,
484 "RX DMA disabled - no residue processing\n");
488 dmaengine_slave_config(chan, &rx_conf);
489 uap->dmarx.chan = chan;
491 uap->dmarx.auto_poll_rate = false;
492 if (plat && plat->dma_rx_poll_enable) {
493 /* Set poll rate if specified. */
494 if (plat->dma_rx_poll_rate) {
495 uap->dmarx.auto_poll_rate = false;
496 uap->dmarx.poll_rate = plat->dma_rx_poll_rate;
499 * 100 ms defaults to poll rate if not
500 * specified. This will be adjusted with
501 * the baud rate at set_termios.
503 uap->dmarx.auto_poll_rate = true;
504 uap->dmarx.poll_rate = 100;
506 /* 3 secs defaults poll_timeout if not specified. */
507 if (plat->dma_rx_poll_timeout)
508 uap->dmarx.poll_timeout =
509 plat->dma_rx_poll_timeout;
511 uap->dmarx.poll_timeout = 3000;
512 } else if (!plat && dev->of_node) {
513 uap->dmarx.auto_poll_rate = of_property_read_bool(
514 dev->of_node, "auto-poll");
515 if (uap->dmarx.auto_poll_rate) {
518 if (0 == of_property_read_u32(dev->of_node,
520 uap->dmarx.poll_rate = x;
522 uap->dmarx.poll_rate = 100;
523 if (0 == of_property_read_u32(dev->of_node,
524 "poll-timeout-ms", &x))
525 uap->dmarx.poll_timeout = x;
527 uap->dmarx.poll_timeout = 3000;
530 dev_info(uap->port.dev, "DMA channel RX %s\n",
531 dma_chan_name(uap->dmarx.chan));
535 static void pl011_dma_remove(struct uart_amba_port *uap)
538 dma_release_channel(uap->dmatx.chan);
540 dma_release_channel(uap->dmarx.chan);
543 /* Forward declare these for the refill routine */
544 static int pl011_dma_tx_refill(struct uart_amba_port *uap);
545 static void pl011_start_tx_pio(struct uart_amba_port *uap);
548 * The current DMA TX buffer has been sent.
549 * Try to queue up another DMA buffer.
551 static void pl011_dma_tx_callback(void *data)
553 struct uart_amba_port *uap = data;
554 struct pl011_dmatx_data *dmatx = &uap->dmatx;
558 spin_lock_irqsave(&uap->port.lock, flags);
559 if (uap->dmatx.queued)
560 dma_unmap_sg(dmatx->chan->device->dev, &dmatx->sg, 1,
564 uap->dmacr = dmacr & ~UART011_TXDMAE;
565 pl011_write(uap->dmacr, uap, REG_DMACR);
568 * If TX DMA was disabled, it means that we've stopped the DMA for
569 * some reason (eg, XOFF received, or we want to send an X-char.)
571 * Note: we need to be careful here of a potential race between DMA
572 * and the rest of the driver - if the driver disables TX DMA while
573 * a TX buffer completing, we must update the tx queued status to
574 * get further refills (hence we check dmacr).
576 if (!(dmacr & UART011_TXDMAE) || uart_tx_stopped(&uap->port) ||
577 uart_circ_empty(&uap->port.state->xmit)) {
578 uap->dmatx.queued = false;
579 spin_unlock_irqrestore(&uap->port.lock, flags);
583 if (pl011_dma_tx_refill(uap) <= 0)
585 * We didn't queue a DMA buffer for some reason, but we
586 * have data pending to be sent. Re-enable the TX IRQ.
588 pl011_start_tx_pio(uap);
590 spin_unlock_irqrestore(&uap->port.lock, flags);
594 * Try to refill the TX DMA buffer.
595 * Locking: called with port lock held and IRQs disabled.
597 * 1 if we queued up a TX DMA buffer.
598 * 0 if we didn't want to handle this by DMA
601 static int pl011_dma_tx_refill(struct uart_amba_port *uap)
603 struct pl011_dmatx_data *dmatx = &uap->dmatx;
604 struct dma_chan *chan = dmatx->chan;
605 struct dma_device *dma_dev = chan->device;
606 struct dma_async_tx_descriptor *desc;
607 struct circ_buf *xmit = &uap->port.state->xmit;
611 * Try to avoid the overhead involved in using DMA if the
612 * transaction fits in the first half of the FIFO, by using
613 * the standard interrupt handling. This ensures that we
614 * issue a uart_write_wakeup() at the appropriate time.
616 count = uart_circ_chars_pending(xmit);
617 if (count < (uap->fifosize >> 1)) {
618 uap->dmatx.queued = false;
623 * Bodge: don't send the last character by DMA, as this
624 * will prevent XON from notifying us to restart DMA.
628 /* Else proceed to copy the TX chars to the DMA buffer and fire DMA */
629 if (count > PL011_DMA_BUFFER_SIZE)
630 count = PL011_DMA_BUFFER_SIZE;
632 if (xmit->tail < xmit->head)
633 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], count);
635 size_t first = UART_XMIT_SIZE - xmit->tail;
640 second = count - first;
642 memcpy(&dmatx->buf[0], &xmit->buf[xmit->tail], first);
644 memcpy(&dmatx->buf[first], &xmit->buf[0], second);
647 dmatx->sg.length = count;
649 if (dma_map_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE) != 1) {
650 uap->dmatx.queued = false;
651 dev_dbg(uap->port.dev, "unable to map TX DMA\n");
655 desc = dmaengine_prep_slave_sg(chan, &dmatx->sg, 1, DMA_MEM_TO_DEV,
656 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
658 dma_unmap_sg(dma_dev->dev, &dmatx->sg, 1, DMA_TO_DEVICE);
659 uap->dmatx.queued = false;
661 * If DMA cannot be used right now, we complete this
662 * transaction via IRQ and let the TTY layer retry.
664 dev_dbg(uap->port.dev, "TX DMA busy\n");
668 /* Some data to go along to the callback */
669 desc->callback = pl011_dma_tx_callback;
670 desc->callback_param = uap;
672 /* All errors should happen at prepare time */
673 dmaengine_submit(desc);
675 /* Fire the DMA transaction */
676 dma_dev->device_issue_pending(chan);
678 uap->dmacr |= UART011_TXDMAE;
679 pl011_write(uap->dmacr, uap, REG_DMACR);
680 uap->dmatx.queued = true;
683 * Now we know that DMA will fire, so advance the ring buffer
684 * with the stuff we just dispatched.
686 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
687 uap->port.icount.tx += count;
689 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
690 uart_write_wakeup(&uap->port);
696 * We received a transmit interrupt without a pending X-char but with
697 * pending characters.
698 * Locking: called with port lock held and IRQs disabled.
700 * false if we want to use PIO to transmit
701 * true if we queued a DMA buffer
703 static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
705 if (!uap->using_tx_dma)
709 * If we already have a TX buffer queued, but received a
710 * TX interrupt, it will be because we've just sent an X-char.
711 * Ensure the TX DMA is enabled and the TX IRQ is disabled.
713 if (uap->dmatx.queued) {
714 uap->dmacr |= UART011_TXDMAE;
715 pl011_write(uap->dmacr, uap, REG_DMACR);
716 uap->im &= ~UART011_TXIM;
717 pl011_write(uap->im, uap, REG_IMSC);
722 * We don't have a TX buffer queued, so try to queue one.
723 * If we successfully queued a buffer, mask the TX IRQ.
725 if (pl011_dma_tx_refill(uap) > 0) {
726 uap->im &= ~UART011_TXIM;
727 pl011_write(uap->im, uap, REG_IMSC);
734 * Stop the DMA transmit (eg, due to received XOFF).
735 * Locking: called with port lock held and IRQs disabled.
737 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
739 if (uap->dmatx.queued) {
740 uap->dmacr &= ~UART011_TXDMAE;
741 pl011_write(uap->dmacr, uap, REG_DMACR);
746 * Try to start a DMA transmit, or in the case of an XON/OFF
747 * character queued for send, try to get that character out ASAP.
748 * Locking: called with port lock held and IRQs disabled.
750 * false if we want the TX IRQ to be enabled
751 * true if we have a buffer queued
753 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
757 if (!uap->using_tx_dma)
760 if (!uap->port.x_char) {
761 /* no X-char, try to push chars out in DMA mode */
764 if (!uap->dmatx.queued) {
765 if (pl011_dma_tx_refill(uap) > 0) {
766 uap->im &= ~UART011_TXIM;
767 pl011_write(uap->im, uap, REG_IMSC);
770 } else if (!(uap->dmacr & UART011_TXDMAE)) {
771 uap->dmacr |= UART011_TXDMAE;
772 pl011_write(uap->dmacr, uap, REG_DMACR);
778 * We have an X-char to send. Disable DMA to prevent it loading
779 * the TX fifo, and then see if we can stuff it into the FIFO.
782 uap->dmacr &= ~UART011_TXDMAE;
783 pl011_write(uap->dmacr, uap, REG_DMACR);
785 if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
787 * No space in the FIFO, so enable the transmit interrupt
788 * so we know when there is space. Note that once we've
789 * loaded the character, we should just re-enable DMA.
794 pl011_write(uap->port.x_char, uap, REG_DR);
795 uap->port.icount.tx++;
796 uap->port.x_char = 0;
798 /* Success - restore the DMA state */
800 pl011_write(dmacr, uap, REG_DMACR);
806 * Flush the transmit buffer.
807 * Locking: called with port lock held and IRQs disabled.
809 static void pl011_dma_flush_buffer(struct uart_port *port)
810 __releases(&uap->port.lock)
811 __acquires(&uap->port.lock)
813 struct uart_amba_port *uap =
814 container_of(port, struct uart_amba_port, port);
816 if (!uap->using_tx_dma)
819 dmaengine_terminate_async(uap->dmatx.chan);
821 if (uap->dmatx.queued) {
822 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
824 uap->dmatx.queued = false;
825 uap->dmacr &= ~UART011_TXDMAE;
826 pl011_write(uap->dmacr, uap, REG_DMACR);
830 static void pl011_dma_rx_callback(void *data);
832 static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
834 struct dma_chan *rxchan = uap->dmarx.chan;
835 struct pl011_dmarx_data *dmarx = &uap->dmarx;
836 struct dma_async_tx_descriptor *desc;
837 struct pl011_sgbuf *sgbuf;
842 /* Start the RX DMA job */
843 sgbuf = uap->dmarx.use_buf_b ?
844 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
845 desc = dmaengine_prep_slave_sg(rxchan, &sgbuf->sg, 1,
847 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
849 * If the DMA engine is busy and cannot prepare a
850 * channel, no big deal, the driver will fall back
851 * to interrupt mode as a result of this error code.
854 uap->dmarx.running = false;
855 dmaengine_terminate_all(rxchan);
859 /* Some data to go along to the callback */
860 desc->callback = pl011_dma_rx_callback;
861 desc->callback_param = uap;
862 dmarx->cookie = dmaengine_submit(desc);
863 dma_async_issue_pending(rxchan);
865 uap->dmacr |= UART011_RXDMAE;
866 pl011_write(uap->dmacr, uap, REG_DMACR);
867 uap->dmarx.running = true;
869 uap->im &= ~UART011_RXIM;
870 pl011_write(uap->im, uap, REG_IMSC);
876 * This is called when either the DMA job is complete, or
877 * the FIFO timeout interrupt occurred. This must be called
878 * with the port spinlock uap->port.lock held.
880 static void pl011_dma_rx_chars(struct uart_amba_port *uap,
881 u32 pending, bool use_buf_b,
884 struct tty_port *port = &uap->port.state->port;
885 struct pl011_sgbuf *sgbuf = use_buf_b ?
886 &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
888 u32 fifotaken = 0; /* only used for vdbg() */
890 struct pl011_dmarx_data *dmarx = &uap->dmarx;
893 if (uap->dmarx.poll_rate) {
894 /* The data can be taken by polling */
895 dmataken = sgbuf->sg.length - dmarx->last_residue;
896 /* Recalculate the pending size */
897 if (pending >= dmataken)
901 /* Pick the remain data from the DMA */
905 * First take all chars in the DMA pipe, then look in the FIFO.
906 * Note that tty_insert_flip_buf() tries to take as many chars
909 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
912 uap->port.icount.rx += dma_count;
913 if (dma_count < pending)
914 dev_warn(uap->port.dev,
915 "couldn't insert all characters (TTY is full?)\n");
918 /* Reset the last_residue for Rx DMA poll */
919 if (uap->dmarx.poll_rate)
920 dmarx->last_residue = sgbuf->sg.length;
923 * Only continue with trying to read the FIFO if all DMA chars have
926 if (dma_count == pending && readfifo) {
927 /* Clear any error flags */
928 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
929 UART011_FEIS, uap, REG_ICR);
932 * If we read all the DMA'd characters, and we had an
933 * incomplete buffer, that could be due to an rx error, or
934 * maybe we just timed out. Read any pending chars and check
937 * Error conditions will only occur in the FIFO, these will
938 * trigger an immediate interrupt and stop the DMA job, so we
939 * will always find the error in the FIFO, never in the DMA
942 fifotaken = pl011_fifo_to_tty(uap);
945 spin_unlock(&uap->port.lock);
946 dev_vdbg(uap->port.dev,
947 "Took %d chars from DMA buffer and %d chars from the FIFO\n",
948 dma_count, fifotaken);
949 tty_flip_buffer_push(port);
950 spin_lock(&uap->port.lock);
953 static void pl011_dma_rx_irq(struct uart_amba_port *uap)
955 struct pl011_dmarx_data *dmarx = &uap->dmarx;
956 struct dma_chan *rxchan = dmarx->chan;
957 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
958 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
960 struct dma_tx_state state;
961 enum dma_status dmastat;
964 * Pause the transfer so we can trust the current counter,
965 * do this before we pause the PL011 block, else we may
968 if (dmaengine_pause(rxchan))
969 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
970 dmastat = rxchan->device->device_tx_status(rxchan,
971 dmarx->cookie, &state);
972 if (dmastat != DMA_PAUSED)
973 dev_err(uap->port.dev, "unable to pause DMA transfer\n");
975 /* Disable RX DMA - incoming data will wait in the FIFO */
976 uap->dmacr &= ~UART011_RXDMAE;
977 pl011_write(uap->dmacr, uap, REG_DMACR);
978 uap->dmarx.running = false;
980 pending = sgbuf->sg.length - state.residue;
981 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
982 /* Then we terminate the transfer - we now know our residue */
983 dmaengine_terminate_all(rxchan);
986 * This will take the chars we have so far and insert
987 * into the framework.
989 pl011_dma_rx_chars(uap, pending, dmarx->use_buf_b, true);
991 /* Switch buffer & re-trigger DMA job */
992 dmarx->use_buf_b = !dmarx->use_buf_b;
993 if (pl011_dma_rx_trigger_dma(uap)) {
994 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
995 "fall back to interrupt mode\n");
996 uap->im |= UART011_RXIM;
997 pl011_write(uap->im, uap, REG_IMSC);
1001 static void pl011_dma_rx_callback(void *data)
1003 struct uart_amba_port *uap = data;
1004 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1005 struct dma_chan *rxchan = dmarx->chan;
1006 bool lastbuf = dmarx->use_buf_b;
1007 struct pl011_sgbuf *sgbuf = dmarx->use_buf_b ?
1008 &dmarx->sgbuf_b : &dmarx->sgbuf_a;
1010 struct dma_tx_state state;
1014 * This completion interrupt occurs typically when the
1015 * RX buffer is totally stuffed but no timeout has yet
1016 * occurred. When that happens, we just want the RX
1017 * routine to flush out the secondary DMA buffer while
1018 * we immediately trigger the next DMA job.
1020 spin_lock_irq(&uap->port.lock);
1022 * Rx data can be taken by the UART interrupts during
1023 * the DMA irq handler. So we check the residue here.
1025 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1026 pending = sgbuf->sg.length - state.residue;
1027 BUG_ON(pending > PL011_DMA_BUFFER_SIZE);
1028 /* Then we terminate the transfer - we now know our residue */
1029 dmaengine_terminate_all(rxchan);
1031 uap->dmarx.running = false;
1032 dmarx->use_buf_b = !lastbuf;
1033 ret = pl011_dma_rx_trigger_dma(uap);
1035 pl011_dma_rx_chars(uap, pending, lastbuf, false);
1036 spin_unlock_irq(&uap->port.lock);
1038 * Do this check after we picked the DMA chars so we don't
1039 * get some IRQ immediately from RX.
1042 dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
1043 "fall back to interrupt mode\n");
1044 uap->im |= UART011_RXIM;
1045 pl011_write(uap->im, uap, REG_IMSC);
1050 * Stop accepting received characters, when we're shutting down or
1051 * suspending this port.
1052 * Locking: called with port lock held and IRQs disabled.
1054 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1056 if (!uap->using_rx_dma)
1059 /* FIXME. Just disable the DMA enable */
1060 uap->dmacr &= ~UART011_RXDMAE;
1061 pl011_write(uap->dmacr, uap, REG_DMACR);
1065 * Timer handler for Rx DMA polling.
1066 * Every polling, It checks the residue in the dma buffer and transfer
1067 * data to the tty. Also, last_residue is updated for the next polling.
1069 static void pl011_dma_rx_poll(struct timer_list *t)
1071 struct uart_amba_port *uap = from_timer(uap, t, dmarx.timer);
1072 struct tty_port *port = &uap->port.state->port;
1073 struct pl011_dmarx_data *dmarx = &uap->dmarx;
1074 struct dma_chan *rxchan = uap->dmarx.chan;
1075 unsigned long flags = 0;
1076 unsigned int dmataken = 0;
1077 unsigned int size = 0;
1078 struct pl011_sgbuf *sgbuf;
1080 struct dma_tx_state state;
1082 sgbuf = dmarx->use_buf_b ? &uap->dmarx.sgbuf_b : &uap->dmarx.sgbuf_a;
1083 rxchan->device->device_tx_status(rxchan, dmarx->cookie, &state);
1084 if (likely(state.residue < dmarx->last_residue)) {
1085 dmataken = sgbuf->sg.length - dmarx->last_residue;
1086 size = dmarx->last_residue - state.residue;
1087 dma_count = tty_insert_flip_string(port, sgbuf->buf + dmataken,
1089 if (dma_count == size)
1090 dmarx->last_residue = state.residue;
1091 dmarx->last_jiffies = jiffies;
1093 tty_flip_buffer_push(port);
1096 * If no data is received in poll_timeout, the driver will fall back
1097 * to interrupt mode. We will retrigger DMA at the first interrupt.
1099 if (jiffies_to_msecs(jiffies - dmarx->last_jiffies)
1100 > uap->dmarx.poll_timeout) {
1102 spin_lock_irqsave(&uap->port.lock, flags);
1103 pl011_dma_rx_stop(uap);
1104 uap->im |= UART011_RXIM;
1105 pl011_write(uap->im, uap, REG_IMSC);
1106 spin_unlock_irqrestore(&uap->port.lock, flags);
1108 uap->dmarx.running = false;
1109 dmaengine_terminate_all(rxchan);
1110 del_timer(&uap->dmarx.timer);
1112 mod_timer(&uap->dmarx.timer,
1113 jiffies + msecs_to_jiffies(uap->dmarx.poll_rate));
1117 static void pl011_dma_startup(struct uart_amba_port *uap)
1121 if (!uap->dma_probed)
1122 pl011_dma_probe(uap);
1124 if (!uap->dmatx.chan)
1127 uap->dmatx.buf = kmalloc(PL011_DMA_BUFFER_SIZE, GFP_KERNEL | __GFP_DMA);
1128 if (!uap->dmatx.buf) {
1129 dev_err(uap->port.dev, "no memory for DMA TX buffer\n");
1130 uap->port.fifosize = uap->fifosize;
1134 sg_init_one(&uap->dmatx.sg, uap->dmatx.buf, PL011_DMA_BUFFER_SIZE);
1136 /* The DMA buffer is now the FIFO the TTY subsystem can use */
1137 uap->port.fifosize = PL011_DMA_BUFFER_SIZE;
1138 uap->using_tx_dma = true;
1140 if (!uap->dmarx.chan)
1143 /* Allocate and map DMA RX buffers */
1144 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1147 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1148 "RX buffer A", ret);
1152 ret = pl011_sgbuf_init(uap->dmarx.chan, &uap->dmarx.sgbuf_b,
1155 dev_err(uap->port.dev, "failed to init DMA %s: %d\n",
1156 "RX buffer B", ret);
1157 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a,
1162 uap->using_rx_dma = true;
1165 /* Turn on DMA error (RX/TX will be enabled on demand) */
1166 uap->dmacr |= UART011_DMAONERR;
1167 pl011_write(uap->dmacr, uap, REG_DMACR);
1170 * ST Micro variants has some specific dma burst threshold
1171 * compensation. Set this to 16 bytes, so burst will only
1172 * be issued above/below 16 bytes.
1174 if (uap->vendor->dma_threshold)
1175 pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
1178 if (uap->using_rx_dma) {
1179 if (pl011_dma_rx_trigger_dma(uap))
1180 dev_dbg(uap->port.dev, "could not trigger initial "
1181 "RX DMA job, fall back to interrupt mode\n");
1182 if (uap->dmarx.poll_rate) {
1183 timer_setup(&uap->dmarx.timer, pl011_dma_rx_poll, 0);
1184 mod_timer(&uap->dmarx.timer,
1186 msecs_to_jiffies(uap->dmarx.poll_rate));
1187 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1188 uap->dmarx.last_jiffies = jiffies;
1193 static void pl011_dma_shutdown(struct uart_amba_port *uap)
1195 if (!(uap->using_tx_dma || uap->using_rx_dma))
1198 /* Disable RX and TX DMA */
1199 while (pl011_read(uap, REG_FR) & uap->vendor->fr_busy)
1202 spin_lock_irq(&uap->port.lock);
1203 uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
1204 pl011_write(uap->dmacr, uap, REG_DMACR);
1205 spin_unlock_irq(&uap->port.lock);
1207 if (uap->using_tx_dma) {
1208 /* In theory, this should already be done by pl011_dma_flush_buffer */
1209 dmaengine_terminate_all(uap->dmatx.chan);
1210 if (uap->dmatx.queued) {
1211 dma_unmap_sg(uap->dmatx.chan->device->dev, &uap->dmatx.sg, 1,
1213 uap->dmatx.queued = false;
1216 kfree(uap->dmatx.buf);
1217 uap->using_tx_dma = false;
1220 if (uap->using_rx_dma) {
1221 dmaengine_terminate_all(uap->dmarx.chan);
1222 /* Clean up the RX DMA */
1223 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_a, DMA_FROM_DEVICE);
1224 pl011_sgbuf_free(uap->dmarx.chan, &uap->dmarx.sgbuf_b, DMA_FROM_DEVICE);
1225 if (uap->dmarx.poll_rate)
1226 del_timer_sync(&uap->dmarx.timer);
1227 uap->using_rx_dma = false;
1231 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1233 return uap->using_rx_dma;
1236 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1238 return uap->using_rx_dma && uap->dmarx.running;
1242 /* Blank functions if the DMA engine is not available */
1243 static inline void pl011_dma_probe(struct uart_amba_port *uap)
1247 static inline void pl011_dma_remove(struct uart_amba_port *uap)
1251 static inline void pl011_dma_startup(struct uart_amba_port *uap)
1255 static inline void pl011_dma_shutdown(struct uart_amba_port *uap)
1259 static inline bool pl011_dma_tx_irq(struct uart_amba_port *uap)
1264 static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
1268 static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
1273 static inline void pl011_dma_rx_irq(struct uart_amba_port *uap)
1277 static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
1281 static inline int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
1286 static inline bool pl011_dma_rx_available(struct uart_amba_port *uap)
1291 static inline bool pl011_dma_rx_running(struct uart_amba_port *uap)
1296 #define pl011_dma_flush_buffer NULL
1299 static void pl011_stop_tx(struct uart_port *port)
1301 struct uart_amba_port *uap =
1302 container_of(port, struct uart_amba_port, port);
1304 uap->im &= ~UART011_TXIM;
1305 pl011_write(uap->im, uap, REG_IMSC);
1306 pl011_dma_tx_stop(uap);
1309 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
1311 /* Start TX with programmed I/O only (no DMA) */
1312 static void pl011_start_tx_pio(struct uart_amba_port *uap)
1314 if (pl011_tx_chars(uap, false)) {
1315 uap->im |= UART011_TXIM;
1316 pl011_write(uap->im, uap, REG_IMSC);
1320 static void pl011_start_tx(struct uart_port *port)
1322 struct uart_amba_port *uap =
1323 container_of(port, struct uart_amba_port, port);
1325 if (!pl011_dma_tx_start(uap))
1326 pl011_start_tx_pio(uap);
1329 static void pl011_stop_rx(struct uart_port *port)
1331 struct uart_amba_port *uap =
1332 container_of(port, struct uart_amba_port, port);
1334 uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
1335 UART011_PEIM|UART011_BEIM|UART011_OEIM);
1336 pl011_write(uap->im, uap, REG_IMSC);
1338 pl011_dma_rx_stop(uap);
1341 static void pl011_throttle_rx(struct uart_port *port)
1343 unsigned long flags;
1345 spin_lock_irqsave(&port->lock, flags);
1346 pl011_stop_rx(port);
1347 spin_unlock_irqrestore(&port->lock, flags);
1350 static void pl011_enable_ms(struct uart_port *port)
1352 struct uart_amba_port *uap =
1353 container_of(port, struct uart_amba_port, port);
1355 uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
1356 pl011_write(uap->im, uap, REG_IMSC);
1359 static void pl011_rx_chars(struct uart_amba_port *uap)
1360 __releases(&uap->port.lock)
1361 __acquires(&uap->port.lock)
1363 pl011_fifo_to_tty(uap);
1365 spin_unlock(&uap->port.lock);
1366 tty_flip_buffer_push(&uap->port.state->port);
1368 * If we were temporarily out of DMA mode for a while,
1369 * attempt to switch back to DMA mode again.
1371 if (pl011_dma_rx_available(uap)) {
1372 if (pl011_dma_rx_trigger_dma(uap)) {
1373 dev_dbg(uap->port.dev, "could not trigger RX DMA job "
1374 "fall back to interrupt mode again\n");
1375 uap->im |= UART011_RXIM;
1376 pl011_write(uap->im, uap, REG_IMSC);
1378 #ifdef CONFIG_DMA_ENGINE
1379 /* Start Rx DMA poll */
1380 if (uap->dmarx.poll_rate) {
1381 uap->dmarx.last_jiffies = jiffies;
1382 uap->dmarx.last_residue = PL011_DMA_BUFFER_SIZE;
1383 mod_timer(&uap->dmarx.timer,
1385 msecs_to_jiffies(uap->dmarx.poll_rate));
1390 spin_lock(&uap->port.lock);
1393 static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
1396 if (unlikely(!from_irq) &&
1397 pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1398 return false; /* unable to transmit character */
1400 pl011_write(c, uap, REG_DR);
1401 uap->port.icount.tx++;
1406 /* Returns true if tx interrupts have to be (kept) enabled */
1407 static bool pl011_tx_chars(struct uart_amba_port *uap, bool from_irq)
1409 struct circ_buf *xmit = &uap->port.state->xmit;
1410 int count = uap->fifosize >> 1;
1412 if (uap->port.x_char) {
1413 if (!pl011_tx_char(uap, uap->port.x_char, from_irq))
1415 uap->port.x_char = 0;
1418 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
1419 pl011_stop_tx(&uap->port);
1423 /* If we are using DMA mode, try to send some characters. */
1424 if (pl011_dma_tx_irq(uap))
1428 if (likely(from_irq) && count-- == 0)
1431 if (!pl011_tx_char(uap, xmit->buf[xmit->tail], from_irq))
1434 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1435 } while (!uart_circ_empty(xmit));
1437 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1438 uart_write_wakeup(&uap->port);
1440 if (uart_circ_empty(xmit)) {
1441 pl011_stop_tx(&uap->port);
1447 static void pl011_modem_status(struct uart_amba_port *uap)
1449 unsigned int status, delta;
1451 status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1453 delta = status ^ uap->old_status;
1454 uap->old_status = status;
1459 if (delta & UART01x_FR_DCD)
1460 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
1462 if (delta & uap->vendor->fr_dsr)
1463 uap->port.icount.dsr++;
1465 if (delta & uap->vendor->fr_cts)
1466 uart_handle_cts_change(&uap->port,
1467 status & uap->vendor->fr_cts);
1469 wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
1472 static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
1474 unsigned int dummy_read;
1476 if (!uap->vendor->cts_event_workaround)
1479 /* workaround to make sure that all bits are unlocked.. */
1480 pl011_write(0x00, uap, REG_ICR);
1483 * WA: introduce 26ns(1 uart clk) delay before W1C;
1484 * single apb access will incur 2 pclk(133.12Mhz) delay,
1485 * so add 2 dummy reads
1487 dummy_read = pl011_read(uap, REG_ICR);
1488 dummy_read = pl011_read(uap, REG_ICR);
1491 static irqreturn_t pl011_int(int irq, void *dev_id)
1493 struct uart_amba_port *uap = dev_id;
1494 unsigned long flags;
1495 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
1498 spin_lock_irqsave(&uap->port.lock, flags);
1499 status = pl011_read(uap, REG_RIS) & uap->im;
1502 check_apply_cts_event_workaround(uap);
1504 pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
1508 if (status & (UART011_RTIS|UART011_RXIS)) {
1509 if (pl011_dma_rx_running(uap))
1510 pl011_dma_rx_irq(uap);
1512 pl011_rx_chars(uap);
1514 if (status & (UART011_DSRMIS|UART011_DCDMIS|
1515 UART011_CTSMIS|UART011_RIMIS))
1516 pl011_modem_status(uap);
1517 if (status & UART011_TXIS)
1518 pl011_tx_chars(uap, true);
1520 if (pass_counter-- == 0)
1523 status = pl011_read(uap, REG_RIS) & uap->im;
1524 } while (status != 0);
1528 spin_unlock_irqrestore(&uap->port.lock, flags);
1530 return IRQ_RETVAL(handled);
1533 static unsigned int pl011_tx_empty(struct uart_port *port)
1535 struct uart_amba_port *uap =
1536 container_of(port, struct uart_amba_port, port);
1538 /* Allow feature register bits to be inverted to work around errata */
1539 unsigned int status = pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr;
1541 return status & (uap->vendor->fr_busy | UART01x_FR_TXFF) ?
1545 static unsigned int pl011_get_mctrl(struct uart_port *port)
1547 struct uart_amba_port *uap =
1548 container_of(port, struct uart_amba_port, port);
1549 unsigned int result = 0;
1550 unsigned int status = pl011_read(uap, REG_FR);
1552 #define TIOCMBIT(uartbit, tiocmbit) \
1553 if (status & uartbit) \
1556 TIOCMBIT(UART01x_FR_DCD, TIOCM_CAR);
1557 TIOCMBIT(uap->vendor->fr_dsr, TIOCM_DSR);
1558 TIOCMBIT(uap->vendor->fr_cts, TIOCM_CTS);
1559 TIOCMBIT(uap->vendor->fr_ri, TIOCM_RNG);
1564 static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
1566 struct uart_amba_port *uap =
1567 container_of(port, struct uart_amba_port, port);
1570 cr = pl011_read(uap, REG_CR);
1572 #define TIOCMBIT(tiocmbit, uartbit) \
1573 if (mctrl & tiocmbit) \
1578 TIOCMBIT(TIOCM_RTS, UART011_CR_RTS);
1579 TIOCMBIT(TIOCM_DTR, UART011_CR_DTR);
1580 TIOCMBIT(TIOCM_OUT1, UART011_CR_OUT1);
1581 TIOCMBIT(TIOCM_OUT2, UART011_CR_OUT2);
1582 TIOCMBIT(TIOCM_LOOP, UART011_CR_LBE);
1584 if (port->status & UPSTAT_AUTORTS) {
1585 /* We need to disable auto-RTS if we want to turn RTS off */
1586 TIOCMBIT(TIOCM_RTS, UART011_CR_RTSEN);
1590 pl011_write(cr, uap, REG_CR);
1593 static void pl011_break_ctl(struct uart_port *port, int break_state)
1595 struct uart_amba_port *uap =
1596 container_of(port, struct uart_amba_port, port);
1597 unsigned long flags;
1600 spin_lock_irqsave(&uap->port.lock, flags);
1601 lcr_h = pl011_read(uap, REG_LCRH_TX);
1602 if (break_state == -1)
1603 lcr_h |= UART01x_LCRH_BRK;
1605 lcr_h &= ~UART01x_LCRH_BRK;
1606 pl011_write(lcr_h, uap, REG_LCRH_TX);
1607 spin_unlock_irqrestore(&uap->port.lock, flags);
1610 #ifdef CONFIG_CONSOLE_POLL
1612 static void pl011_quiesce_irqs(struct uart_port *port)
1614 struct uart_amba_port *uap =
1615 container_of(port, struct uart_amba_port, port);
1617 pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
1619 * There is no way to clear TXIM as this is "ready to transmit IRQ", so
1620 * we simply mask it. start_tx() will unmask it.
1622 * Note we can race with start_tx(), and if the race happens, the
1623 * polling user might get another interrupt just after we clear it.
1624 * But it should be OK and can happen even w/o the race, e.g.
1625 * controller immediately got some new data and raised the IRQ.
1627 * And whoever uses polling routines assumes that it manages the device
1628 * (including tx queue), so we're also fine with start_tx()'s caller
1631 pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
1635 static int pl011_get_poll_char(struct uart_port *port)
1637 struct uart_amba_port *uap =
1638 container_of(port, struct uart_amba_port, port);
1639 unsigned int status;
1642 * The caller might need IRQs lowered, e.g. if used with KDB NMI
1645 pl011_quiesce_irqs(port);
1647 status = pl011_read(uap, REG_FR);
1648 if (status & UART01x_FR_RXFE)
1649 return NO_POLL_CHAR;
1651 return pl011_read(uap, REG_DR);
1654 static void pl011_put_poll_char(struct uart_port *port,
1657 struct uart_amba_port *uap =
1658 container_of(port, struct uart_amba_port, port);
1660 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
1663 pl011_write(ch, uap, REG_DR);
1666 #endif /* CONFIG_CONSOLE_POLL */
1668 static int pl011_hwinit(struct uart_port *port)
1670 struct uart_amba_port *uap =
1671 container_of(port, struct uart_amba_port, port);
1674 /* Optionaly enable pins to be muxed in and configured */
1675 pinctrl_pm_select_default_state(port->dev);
1678 * Try to enable the clock producer.
1680 retval = clk_prepare_enable(uap->clk);
1684 uap->port.uartclk = clk_get_rate(uap->clk);
1686 /* Clear pending error and receive interrupts */
1687 pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
1688 UART011_FEIS | UART011_RTIS | UART011_RXIS,
1692 * Save interrupts enable mask, and enable RX interrupts in case if
1693 * the interrupt is used for NMI entry.
1695 uap->im = pl011_read(uap, REG_IMSC);
1696 pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
1698 if (dev_get_platdata(uap->port.dev)) {
1699 struct amba_pl011_data *plat;
1701 plat = dev_get_platdata(uap->port.dev);
1708 static bool pl011_split_lcrh(const struct uart_amba_port *uap)
1710 return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
1711 pl011_reg_to_offset(uap, REG_LCRH_TX);
1714 static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
1716 pl011_write(lcr_h, uap, REG_LCRH_RX);
1717 if (pl011_split_lcrh(uap)) {
1720 * Wait 10 PCLKs before writing LCRH_TX register,
1721 * to get this delay write read only register 10 times
1723 for (i = 0; i < 10; ++i)
1724 pl011_write(0xff, uap, REG_MIS);
1725 pl011_write(lcr_h, uap, REG_LCRH_TX);
1729 static int pl011_allocate_irq(struct uart_amba_port *uap)
1731 pl011_write(uap->im, uap, REG_IMSC);
1733 return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
1737 * Enable interrupts, only timeouts when using DMA
1738 * if initial RX DMA job failed, start in interrupt mode
1741 static void pl011_enable_interrupts(struct uart_amba_port *uap)
1743 unsigned long flags;
1746 spin_lock_irqsave(&uap->port.lock, flags);
1748 /* Clear out any spuriously appearing RX interrupts */
1749 pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
1752 * RXIS is asserted only when the RX FIFO transitions from below
1753 * to above the trigger threshold. If the RX FIFO is already
1754 * full to the threshold this can't happen and RXIS will now be
1755 * stuck off. Drain the RX FIFO explicitly to fix this:
1757 for (i = 0; i < uap->fifosize * 2; ++i) {
1758 if (pl011_read(uap, REG_FR) & UART01x_FR_RXFE)
1761 pl011_read(uap, REG_DR);
1764 uap->im = UART011_RTIM;
1765 if (!pl011_dma_rx_running(uap))
1766 uap->im |= UART011_RXIM;
1767 pl011_write(uap->im, uap, REG_IMSC);
1768 spin_unlock_irqrestore(&uap->port.lock, flags);
1771 static void pl011_unthrottle_rx(struct uart_port *port)
1773 struct uart_amba_port *uap = container_of(port, struct uart_amba_port, port);
1774 unsigned long flags;
1776 spin_lock_irqsave(&uap->port.lock, flags);
1778 uap->im = UART011_RTIM;
1779 if (!pl011_dma_rx_running(uap))
1780 uap->im |= UART011_RXIM;
1782 pl011_write(uap->im, uap, REG_IMSC);
1784 spin_unlock_irqrestore(&uap->port.lock, flags);
1787 static int pl011_startup(struct uart_port *port)
1789 struct uart_amba_port *uap =
1790 container_of(port, struct uart_amba_port, port);
1794 retval = pl011_hwinit(port);
1798 retval = pl011_allocate_irq(uap);
1802 pl011_write(uap->vendor->ifls, uap, REG_IFLS);
1804 spin_lock_irq(&uap->port.lock);
1806 /* restore RTS and DTR */
1807 cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
1808 cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
1809 pl011_write(cr, uap, REG_CR);
1811 spin_unlock_irq(&uap->port.lock);
1814 * initialise the old status of the modem signals
1816 uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
1819 pl011_dma_startup(uap);
1821 pl011_enable_interrupts(uap);
1826 clk_disable_unprepare(uap->clk);
1830 static int sbsa_uart_startup(struct uart_port *port)
1832 struct uart_amba_port *uap =
1833 container_of(port, struct uart_amba_port, port);
1836 retval = pl011_hwinit(port);
1840 retval = pl011_allocate_irq(uap);
1844 /* The SBSA UART does not support any modem status lines. */
1845 uap->old_status = 0;
1847 pl011_enable_interrupts(uap);
1852 static void pl011_shutdown_channel(struct uart_amba_port *uap,
1857 val = pl011_read(uap, lcrh);
1858 val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
1859 pl011_write(val, uap, lcrh);
1863 * disable the port. It should not disable RTS and DTR.
1864 * Also RTS and DTR state should be preserved to restore
1865 * it during startup().
1867 static void pl011_disable_uart(struct uart_amba_port *uap)
1871 uap->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
1872 spin_lock_irq(&uap->port.lock);
1873 cr = pl011_read(uap, REG_CR);
1875 cr &= UART011_CR_RTS | UART011_CR_DTR;
1876 cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
1877 pl011_write(cr, uap, REG_CR);
1878 spin_unlock_irq(&uap->port.lock);
1881 * disable break condition and fifos
1883 pl011_shutdown_channel(uap, REG_LCRH_RX);
1884 if (pl011_split_lcrh(uap))
1885 pl011_shutdown_channel(uap, REG_LCRH_TX);
1888 static void pl011_disable_interrupts(struct uart_amba_port *uap)
1890 spin_lock_irq(&uap->port.lock);
1892 /* mask all interrupts and clear all pending ones */
1894 pl011_write(uap->im, uap, REG_IMSC);
1895 pl011_write(0xffff, uap, REG_ICR);
1897 spin_unlock_irq(&uap->port.lock);
1900 static void pl011_shutdown(struct uart_port *port)
1902 struct uart_amba_port *uap =
1903 container_of(port, struct uart_amba_port, port);
1905 pl011_disable_interrupts(uap);
1907 pl011_dma_shutdown(uap);
1909 free_irq(uap->port.irq, uap);
1911 pl011_disable_uart(uap);
1914 * Shut down the clock producer
1916 clk_disable_unprepare(uap->clk);
1917 /* Optionally let pins go into sleep states */
1918 pinctrl_pm_select_sleep_state(port->dev);
1920 if (dev_get_platdata(uap->port.dev)) {
1921 struct amba_pl011_data *plat;
1923 plat = dev_get_platdata(uap->port.dev);
1928 if (uap->port.ops->flush_buffer)
1929 uap->port.ops->flush_buffer(port);
1932 static void sbsa_uart_shutdown(struct uart_port *port)
1934 struct uart_amba_port *uap =
1935 container_of(port, struct uart_amba_port, port);
1937 pl011_disable_interrupts(uap);
1939 free_irq(uap->port.irq, uap);
1941 if (uap->port.ops->flush_buffer)
1942 uap->port.ops->flush_buffer(port);
1946 pl011_setup_status_masks(struct uart_port *port, struct ktermios *termios)
1948 port->read_status_mask = UART011_DR_OE | 255;
1949 if (termios->c_iflag & INPCK)
1950 port->read_status_mask |= UART011_DR_FE | UART011_DR_PE;
1951 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
1952 port->read_status_mask |= UART011_DR_BE;
1955 * Characters to ignore
1957 port->ignore_status_mask = 0;
1958 if (termios->c_iflag & IGNPAR)
1959 port->ignore_status_mask |= UART011_DR_FE | UART011_DR_PE;
1960 if (termios->c_iflag & IGNBRK) {
1961 port->ignore_status_mask |= UART011_DR_BE;
1963 * If we're ignoring parity and break indicators,
1964 * ignore overruns too (for real raw support).
1966 if (termios->c_iflag & IGNPAR)
1967 port->ignore_status_mask |= UART011_DR_OE;
1971 * Ignore all characters if CREAD is not set.
1973 if ((termios->c_cflag & CREAD) == 0)
1974 port->ignore_status_mask |= UART_DUMMY_DR_RX;
1978 pl011_set_termios(struct uart_port *port, struct ktermios *termios,
1979 struct ktermios *old)
1981 struct uart_amba_port *uap =
1982 container_of(port, struct uart_amba_port, port);
1983 unsigned int lcr_h, old_cr;
1984 unsigned long flags;
1985 unsigned int baud, quot, clkdiv;
1987 if (uap->vendor->oversampling)
1993 * Ask the core to calculate the divisor for us.
1995 baud = uart_get_baud_rate(port, termios, old, 0,
1996 port->uartclk / clkdiv);
1997 #ifdef CONFIG_DMA_ENGINE
1999 * Adjust RX DMA polling rate with baud rate if not specified.
2001 if (uap->dmarx.auto_poll_rate)
2002 uap->dmarx.poll_rate = DIV_ROUND_UP(10000000, baud);
2005 if (baud > port->uartclk/16)
2006 quot = DIV_ROUND_CLOSEST(port->uartclk * 8, baud);
2008 quot = DIV_ROUND_CLOSEST(port->uartclk * 4, baud);
2010 switch (termios->c_cflag & CSIZE) {
2012 lcr_h = UART01x_LCRH_WLEN_5;
2015 lcr_h = UART01x_LCRH_WLEN_6;
2018 lcr_h = UART01x_LCRH_WLEN_7;
2021 lcr_h = UART01x_LCRH_WLEN_8;
2024 if (termios->c_cflag & CSTOPB)
2025 lcr_h |= UART01x_LCRH_STP2;
2026 if (termios->c_cflag & PARENB) {
2027 lcr_h |= UART01x_LCRH_PEN;
2028 if (!(termios->c_cflag & PARODD))
2029 lcr_h |= UART01x_LCRH_EPS;
2030 if (termios->c_cflag & CMSPAR)
2031 lcr_h |= UART011_LCRH_SPS;
2033 if (uap->fifosize > 1)
2034 lcr_h |= UART01x_LCRH_FEN;
2036 spin_lock_irqsave(&port->lock, flags);
2039 * Update the per-port timeout.
2041 uart_update_timeout(port, termios->c_cflag, baud);
2043 pl011_setup_status_masks(port, termios);
2045 if (UART_ENABLE_MS(port, termios->c_cflag))
2046 pl011_enable_ms(port);
2048 /* first, disable everything */
2049 old_cr = pl011_read(uap, REG_CR);
2050 pl011_write(0, uap, REG_CR);
2052 if (termios->c_cflag & CRTSCTS) {
2053 if (old_cr & UART011_CR_RTS)
2054 old_cr |= UART011_CR_RTSEN;
2056 old_cr |= UART011_CR_CTSEN;
2057 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
2059 old_cr &= ~(UART011_CR_CTSEN | UART011_CR_RTSEN);
2060 port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
2063 if (uap->vendor->oversampling) {
2064 if (baud > port->uartclk / 16)
2065 old_cr |= ST_UART011_CR_OVSFACT;
2067 old_cr &= ~ST_UART011_CR_OVSFACT;
2071 * Workaround for the ST Micro oversampling variants to
2072 * increase the bitrate slightly, by lowering the divisor,
2073 * to avoid delayed sampling of start bit at high speeds,
2074 * else we see data corruption.
2076 if (uap->vendor->oversampling) {
2077 if ((baud >= 3000000) && (baud < 3250000) && (quot > 1))
2079 else if ((baud > 3250000) && (quot > 2))
2083 pl011_write(quot & 0x3f, uap, REG_FBRD);
2084 pl011_write(quot >> 6, uap, REG_IBRD);
2087 * ----------v----------v----------v----------v-----
2088 * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
2089 * REG_FBRD & REG_IBRD.
2090 * ----------^----------^----------^----------^-----
2092 pl011_write_lcr_h(uap, lcr_h);
2093 pl011_write(old_cr, uap, REG_CR);
2095 spin_unlock_irqrestore(&port->lock, flags);
2099 sbsa_uart_set_termios(struct uart_port *port, struct ktermios *termios,
2100 struct ktermios *old)
2102 struct uart_amba_port *uap =
2103 container_of(port, struct uart_amba_port, port);
2104 unsigned long flags;
2106 tty_termios_encode_baud_rate(termios, uap->fixed_baud, uap->fixed_baud);
2108 /* The SBSA UART only supports 8n1 without hardware flow control. */
2109 termios->c_cflag &= ~(CSIZE | CSTOPB | PARENB | PARODD);
2110 termios->c_cflag &= ~(CMSPAR | CRTSCTS);
2111 termios->c_cflag |= CS8 | CLOCAL;
2113 spin_lock_irqsave(&port->lock, flags);
2114 uart_update_timeout(port, CS8, uap->fixed_baud);
2115 pl011_setup_status_masks(port, termios);
2116 spin_unlock_irqrestore(&port->lock, flags);
2119 static const char *pl011_type(struct uart_port *port)
2121 struct uart_amba_port *uap =
2122 container_of(port, struct uart_amba_port, port);
2123 return uap->port.type == PORT_AMBA ? uap->type : NULL;
2127 * Configure/autoconfigure the port.
2129 static void pl011_config_port(struct uart_port *port, int flags)
2131 if (flags & UART_CONFIG_TYPE)
2132 port->type = PORT_AMBA;
2136 * verify the new serial_struct (for TIOCSSERIAL).
2138 static int pl011_verify_port(struct uart_port *port, struct serial_struct *ser)
2141 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
2143 if (ser->irq < 0 || ser->irq >= nr_irqs)
2145 if (ser->baud_base < 9600)
2147 if (port->mapbase != (unsigned long) ser->iomem_base)
2152 static const struct uart_ops amba_pl011_pops = {
2153 .tx_empty = pl011_tx_empty,
2154 .set_mctrl = pl011_set_mctrl,
2155 .get_mctrl = pl011_get_mctrl,
2156 .stop_tx = pl011_stop_tx,
2157 .start_tx = pl011_start_tx,
2158 .stop_rx = pl011_stop_rx,
2159 .throttle = pl011_throttle_rx,
2160 .unthrottle = pl011_unthrottle_rx,
2161 .enable_ms = pl011_enable_ms,
2162 .break_ctl = pl011_break_ctl,
2163 .startup = pl011_startup,
2164 .shutdown = pl011_shutdown,
2165 .flush_buffer = pl011_dma_flush_buffer,
2166 .set_termios = pl011_set_termios,
2168 .config_port = pl011_config_port,
2169 .verify_port = pl011_verify_port,
2170 #ifdef CONFIG_CONSOLE_POLL
2171 .poll_init = pl011_hwinit,
2172 .poll_get_char = pl011_get_poll_char,
2173 .poll_put_char = pl011_put_poll_char,
2177 static void sbsa_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
2181 static unsigned int sbsa_uart_get_mctrl(struct uart_port *port)
2186 static const struct uart_ops sbsa_uart_pops = {
2187 .tx_empty = pl011_tx_empty,
2188 .set_mctrl = sbsa_uart_set_mctrl,
2189 .get_mctrl = sbsa_uart_get_mctrl,
2190 .stop_tx = pl011_stop_tx,
2191 .start_tx = pl011_start_tx,
2192 .stop_rx = pl011_stop_rx,
2193 .startup = sbsa_uart_startup,
2194 .shutdown = sbsa_uart_shutdown,
2195 .set_termios = sbsa_uart_set_termios,
2197 .config_port = pl011_config_port,
2198 .verify_port = pl011_verify_port,
2199 #ifdef CONFIG_CONSOLE_POLL
2200 .poll_init = pl011_hwinit,
2201 .poll_get_char = pl011_get_poll_char,
2202 .poll_put_char = pl011_put_poll_char,
2206 static struct uart_amba_port *amba_ports[UART_NR];
2208 #ifdef CONFIG_SERIAL_AMBA_PL011_CONSOLE
2210 static void pl011_console_putchar(struct uart_port *port, int ch)
2212 struct uart_amba_port *uap =
2213 container_of(port, struct uart_amba_port, port);
2215 while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
2217 pl011_write(ch, uap, REG_DR);
2221 pl011_console_write(struct console *co, const char *s, unsigned int count)
2223 struct uart_amba_port *uap = amba_ports[co->index];
2224 unsigned int old_cr = 0, new_cr;
2225 unsigned long flags;
2228 clk_enable(uap->clk);
2230 local_irq_save(flags);
2231 if (uap->port.sysrq)
2233 else if (oops_in_progress)
2234 locked = spin_trylock(&uap->port.lock);
2236 spin_lock(&uap->port.lock);
2239 * First save the CR then disable the interrupts
2241 if (!uap->vendor->always_enabled) {
2242 old_cr = pl011_read(uap, REG_CR);
2243 new_cr = old_cr & ~UART011_CR_CTSEN;
2244 new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
2245 pl011_write(new_cr, uap, REG_CR);
2248 uart_console_write(&uap->port, s, count, pl011_console_putchar);
2251 * Finally, wait for transmitter to become empty and restore the
2252 * TCR. Allow feature register bits to be inverted to work around
2255 while ((pl011_read(uap, REG_FR) ^ uap->vendor->inv_fr)
2256 & uap->vendor->fr_busy)
2258 if (!uap->vendor->always_enabled)
2259 pl011_write(old_cr, uap, REG_CR);
2262 spin_unlock(&uap->port.lock);
2263 local_irq_restore(flags);
2265 clk_disable(uap->clk);
2268 static void pl011_console_get_options(struct uart_amba_port *uap, int *baud,
2269 int *parity, int *bits)
2271 if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
2272 unsigned int lcr_h, ibrd, fbrd;
2274 lcr_h = pl011_read(uap, REG_LCRH_TX);
2277 if (lcr_h & UART01x_LCRH_PEN) {
2278 if (lcr_h & UART01x_LCRH_EPS)
2284 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
2289 ibrd = pl011_read(uap, REG_IBRD);
2290 fbrd = pl011_read(uap, REG_FBRD);
2292 *baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
2294 if (uap->vendor->oversampling) {
2295 if (pl011_read(uap, REG_CR)
2296 & ST_UART011_CR_OVSFACT)
2302 static int pl011_console_setup(struct console *co, char *options)
2304 struct uart_amba_port *uap;
2312 * Check whether an invalid uart number has been specified, and
2313 * if so, search for the first available port that does have
2316 if (co->index >= UART_NR)
2318 uap = amba_ports[co->index];
2322 /* Allow pins to be muxed in and configured */
2323 pinctrl_pm_select_default_state(uap->port.dev);
2325 ret = clk_prepare(uap->clk);
2329 if (dev_get_platdata(uap->port.dev)) {
2330 struct amba_pl011_data *plat;
2332 plat = dev_get_platdata(uap->port.dev);
2337 uap->port.uartclk = clk_get_rate(uap->clk);
2339 if (uap->vendor->fixed_options) {
2340 baud = uap->fixed_baud;
2343 uart_parse_options(options,
2344 &baud, &parity, &bits, &flow);
2346 pl011_console_get_options(uap, &baud, &parity, &bits);
2349 return uart_set_options(&uap->port, co, baud, parity, bits, flow);
2353 * pl011_console_match - non-standard console matching
2354 * @co: registering console
2355 * @name: name from console command line
2356 * @idx: index from console command line
2357 * @options: ptr to option string from console command line
2359 * Only attempts to match console command lines of the form:
2360 * console=pl011,mmio|mmio32,<addr>[,<options>]
2361 * console=pl011,0x<addr>[,<options>]
2362 * This form is used to register an initial earlycon boot console and
2363 * replace it with the amba_console at pl011 driver init.
2365 * Performs console setup for a match (as required by interface)
2366 * If no <options> are specified, then assume the h/w is already setup.
2368 * Returns 0 if console matches; otherwise non-zero to use default matching
2370 static int pl011_console_match(struct console *co, char *name, int idx,
2373 unsigned char iotype;
2374 resource_size_t addr;
2378 * Systems affected by the Qualcomm Technologies QDF2400 E44 erratum
2379 * have a distinct console name, so make sure we check for that.
2380 * The actual implementation of the erratum occurs in the probe
2383 if ((strcmp(name, "qdf2400_e44") != 0) && (strcmp(name, "pl011") != 0))
2386 if (uart_parse_earlycon(options, &iotype, &addr, &options))
2389 if (iotype != UPIO_MEM && iotype != UPIO_MEM32)
2392 /* try to match the port specified on the command line */
2393 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2394 struct uart_port *port;
2399 port = &amba_ports[i]->port;
2401 if (port->mapbase != addr)
2406 return pl011_console_setup(co, options);
2412 static struct uart_driver amba_reg;
2413 static struct console amba_console = {
2415 .write = pl011_console_write,
2416 .device = uart_console_device,
2417 .setup = pl011_console_setup,
2418 .match = pl011_console_match,
2419 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2424 #define AMBA_CONSOLE (&amba_console)
2426 static void qdf2400_e44_putc(struct uart_port *port, int c)
2428 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2430 writel(c, port->membase + UART01x_DR);
2431 while (!(readl(port->membase + UART01x_FR) & UART011_FR_TXFE))
2435 static void qdf2400_e44_early_write(struct console *con, const char *s, unsigned n)
2437 struct earlycon_device *dev = con->data;
2439 uart_console_write(&dev->port, s, n, qdf2400_e44_putc);
2442 static void pl011_putc(struct uart_port *port, int c)
2444 while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
2446 if (port->iotype == UPIO_MEM32)
2447 writel(c, port->membase + UART01x_DR);
2449 writeb(c, port->membase + UART01x_DR);
2450 while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
2454 static void pl011_early_write(struct console *con, const char *s, unsigned n)
2456 struct earlycon_device *dev = con->data;
2458 uart_console_write(&dev->port, s, n, pl011_putc);
2462 * On non-ACPI systems, earlycon is enabled by specifying
2463 * "earlycon=pl011,<address>" on the kernel command line.
2465 * On ACPI ARM64 systems, an "early" console is enabled via the SPCR table,
2466 * by specifying only "earlycon" on the command line. Because it requires
2467 * SPCR, the console starts after ACPI is parsed, which is later than a
2468 * traditional early console.
2470 * To get the traditional early console that starts before ACPI is parsed,
2471 * specify the full "earlycon=pl011,<address>" option.
2473 static int __init pl011_early_console_setup(struct earlycon_device *device,
2476 if (!device->port.membase)
2479 device->con->write = pl011_early_write;
2483 OF_EARLYCON_DECLARE(pl011, "arm,pl011", pl011_early_console_setup);
2484 OF_EARLYCON_DECLARE(pl011, "arm,sbsa-uart", pl011_early_console_setup);
2487 * On Qualcomm Datacenter Technologies QDF2400 SOCs affected by
2488 * Erratum 44, traditional earlycon can be enabled by specifying
2489 * "earlycon=qdf2400_e44,<address>". Any options are ignored.
2491 * Alternatively, you can just specify "earlycon", and the early console
2492 * will be enabled with the information from the SPCR table. In this
2493 * case, the SPCR code will detect the need for the E44 work-around,
2494 * and set the console name to "qdf2400_e44".
2497 qdf2400_e44_early_console_setup(struct earlycon_device *device,
2500 if (!device->port.membase)
2503 device->con->write = qdf2400_e44_early_write;
2506 EARLYCON_DECLARE(qdf2400_e44, qdf2400_e44_early_console_setup);
2509 #define AMBA_CONSOLE NULL
2512 static struct uart_driver amba_reg = {
2513 .owner = THIS_MODULE,
2514 .driver_name = "ttyAMA",
2515 .dev_name = "ttyAMA",
2516 .major = SERIAL_AMBA_MAJOR,
2517 .minor = SERIAL_AMBA_MINOR,
2519 .cons = AMBA_CONSOLE,
2522 static int pl011_probe_dt_alias(int index, struct device *dev)
2524 struct device_node *np;
2525 static bool seen_dev_with_alias = false;
2526 static bool seen_dev_without_alias = false;
2529 if (!IS_ENABLED(CONFIG_OF))
2536 ret = of_alias_get_id(np, "serial");
2538 seen_dev_without_alias = true;
2541 seen_dev_with_alias = true;
2542 if (ret >= ARRAY_SIZE(amba_ports) || amba_ports[ret] != NULL) {
2543 dev_warn(dev, "requested serial port %d not available.\n", ret);
2548 if (seen_dev_with_alias && seen_dev_without_alias)
2549 dev_warn(dev, "aliased and non-aliased serial devices found in device tree. Serial port enumeration may be unpredictable.\n");
2554 /* unregisters the driver also if no more ports are left */
2555 static void pl011_unregister_port(struct uart_amba_port *uap)
2560 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) {
2561 if (amba_ports[i] == uap)
2562 amba_ports[i] = NULL;
2563 else if (amba_ports[i])
2566 pl011_dma_remove(uap);
2568 uart_unregister_driver(&amba_reg);
2571 static int pl011_find_free_port(void)
2575 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2576 if (amba_ports[i] == NULL)
2582 static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
2583 struct resource *mmiobase, int index)
2587 base = devm_ioremap_resource(dev, mmiobase);
2589 return PTR_ERR(base);
2591 index = pl011_probe_dt_alias(index, dev);
2594 uap->port.dev = dev;
2595 uap->port.mapbase = mmiobase->start;
2596 uap->port.membase = base;
2597 uap->port.fifosize = uap->fifosize;
2598 uap->port.flags = UPF_BOOT_AUTOCONF;
2599 uap->port.line = index;
2600 spin_lock_init(&uap->port.lock);
2602 amba_ports[index] = uap;
2607 static int pl011_register_port(struct uart_amba_port *uap)
2611 /* Ensure interrupts from this UART are masked and cleared */
2612 pl011_write(0, uap, REG_IMSC);
2613 pl011_write(0xffff, uap, REG_ICR);
2615 if (!amba_reg.state) {
2616 ret = uart_register_driver(&amba_reg);
2618 dev_err(uap->port.dev,
2619 "Failed to register AMBA-PL011 driver\n");
2620 for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
2621 if (amba_ports[i] == uap)
2622 amba_ports[i] = NULL;
2627 ret = uart_add_one_port(&amba_reg, &uap->port);
2629 pl011_unregister_port(uap);
2634 static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
2636 struct uart_amba_port *uap;
2637 struct vendor_data *vendor = id->data;
2640 portnr = pl011_find_free_port();
2644 uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
2649 uap->clk = devm_clk_get(&dev->dev, NULL);
2650 if (IS_ERR(uap->clk))
2651 return PTR_ERR(uap->clk);
2653 uap->reg_offset = vendor->reg_offset;
2654 uap->vendor = vendor;
2655 uap->fifosize = vendor->get_fifosize(dev);
2656 uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2657 uap->port.irq = dev->irq[0];
2658 uap->port.ops = &amba_pl011_pops;
2660 snprintf(uap->type, sizeof(uap->type), "PL011 rev%u", amba_rev(dev));
2662 ret = pl011_setup_port(&dev->dev, uap, &dev->res, portnr);
2666 amba_set_drvdata(dev, uap);
2668 return pl011_register_port(uap);
2671 static int pl011_remove(struct amba_device *dev)
2673 struct uart_amba_port *uap = amba_get_drvdata(dev);
2675 uart_remove_one_port(&amba_reg, &uap->port);
2676 pl011_unregister_port(uap);
2680 #ifdef CONFIG_PM_SLEEP
2681 static int pl011_suspend(struct device *dev)
2683 struct uart_amba_port *uap = dev_get_drvdata(dev);
2688 return uart_suspend_port(&amba_reg, &uap->port);
2691 static int pl011_resume(struct device *dev)
2693 struct uart_amba_port *uap = dev_get_drvdata(dev);
2698 return uart_resume_port(&amba_reg, &uap->port);
2702 static SIMPLE_DEV_PM_OPS(pl011_dev_pm_ops, pl011_suspend, pl011_resume);
2704 static int sbsa_uart_probe(struct platform_device *pdev)
2706 struct uart_amba_port *uap;
2712 * Check the mandatory baud rate parameter in the DT node early
2713 * so that we can easily exit with the error.
2715 if (pdev->dev.of_node) {
2716 struct device_node *np = pdev->dev.of_node;
2718 ret = of_property_read_u32(np, "current-speed", &baudrate);
2725 portnr = pl011_find_free_port();
2729 uap = devm_kzalloc(&pdev->dev, sizeof(struct uart_amba_port),
2734 ret = platform_get_irq(pdev, 0);
2736 if (ret != -EPROBE_DEFER)
2737 dev_err(&pdev->dev, "cannot obtain irq\n");
2740 uap->port.irq = ret;
2742 #ifdef CONFIG_ACPI_SPCR_TABLE
2743 if (qdf2400_e44_present) {
2744 dev_info(&pdev->dev, "working around QDF2400 SoC erratum 44\n");
2745 uap->vendor = &vendor_qdt_qdf2400_e44;
2748 uap->vendor = &vendor_sbsa;
2750 uap->reg_offset = uap->vendor->reg_offset;
2752 uap->port.iotype = uap->vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
2753 uap->port.ops = &sbsa_uart_pops;
2754 uap->fixed_baud = baudrate;
2756 snprintf(uap->type, sizeof(uap->type), "SBSA");
2758 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2760 ret = pl011_setup_port(&pdev->dev, uap, r, portnr);
2764 platform_set_drvdata(pdev, uap);
2766 return pl011_register_port(uap);
2769 static int sbsa_uart_remove(struct platform_device *pdev)
2771 struct uart_amba_port *uap = platform_get_drvdata(pdev);
2773 uart_remove_one_port(&amba_reg, &uap->port);
2774 pl011_unregister_port(uap);
2778 static const struct of_device_id sbsa_uart_of_match[] = {
2779 { .compatible = "arm,sbsa-uart", },
2782 MODULE_DEVICE_TABLE(of, sbsa_uart_of_match);
2784 static const struct acpi_device_id sbsa_uart_acpi_match[] = {
2789 MODULE_DEVICE_TABLE(acpi, sbsa_uart_acpi_match);
2791 static struct platform_driver arm_sbsa_uart_platform_driver = {
2792 .probe = sbsa_uart_probe,
2793 .remove = sbsa_uart_remove,
2795 .name = "sbsa-uart",
2796 .of_match_table = of_match_ptr(sbsa_uart_of_match),
2797 .acpi_match_table = ACPI_PTR(sbsa_uart_acpi_match),
2798 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2802 static const struct amba_id pl011_ids[] = {
2806 .data = &vendor_arm,
2814 .id = AMBA_LINUX_ID(0x00, 0x1, 0xffe),
2816 .data = &vendor_zte,
2821 MODULE_DEVICE_TABLE(amba, pl011_ids);
2823 static struct amba_driver pl011_driver = {
2825 .name = "uart-pl011",
2826 .pm = &pl011_dev_pm_ops,
2827 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_AMBA_PL011),
2829 .id_table = pl011_ids,
2830 .probe = pl011_probe,
2831 .remove = pl011_remove,
2834 static int __init pl011_init(void)
2836 printk(KERN_INFO "Serial: AMBA PL011 UART driver\n");
2838 if (platform_driver_register(&arm_sbsa_uart_platform_driver))
2839 pr_warn("could not register SBSA UART platform driver\n");
2840 return amba_driver_register(&pl011_driver);
2843 static void __exit pl011_exit(void)
2845 platform_driver_unregister(&arm_sbsa_uart_platform_driver);
2846 amba_driver_unregister(&pl011_driver);
2850 * While this can be a module, if builtin it's most likely the console
2851 * So let's leave module_exit but move module_init to an earlier place
2853 arch_initcall(pl011_init);
2854 module_exit(pl011_exit);
2856 MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
2857 MODULE_DESCRIPTION("ARM AMBA serial port driver");
2858 MODULE_LICENSE("GPL");