drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 #include "serial_mctrl_gpio.h"
  48
  49 /* Register definitions */
  50 #define URXD0 0x0  /* Receiver Register */
  51 #define URTX0 0x40 /* Transmitter Register */
  52 #define UCR1  0x80 /* Control Register 1 */
  53 #define UCR2  0x84 /* Control Register 2 */
  54 #define UCR3  0x88 /* Control Register 3 */
  55 #define UCR4  0x8c /* Control Register 4 */
  56 #define UFCR  0x90 /* FIFO Control Register */
  57 #define USR1  0x94 /* Status Register 1 */
  58 #define USR2  0x98 /* Status Register 2 */
  59 #define UESC  0x9c /* Escape Character Register */
  60 #define UTIM  0xa0 /* Escape Timer Register */
  61 #define UBIR  0xa4 /* BRM Incremental Register */
  62 #define UBMR  0xa8 /* BRM Modulator Register */
  63 #define UBRC  0xac /* Baud Rate Count Register */
  64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  67
  68 /* UART Control Register Bit Fields.*/
  69 #define URXD_DUMMY_READ (1<<16)
  70 #define URXD_CHARRDY    (1<<15)
  71 #define URXD_ERR        (1<<14)
  72 #define URXD_OVRRUN     (1<<13)
  73 #define URXD_FRMERR     (1<<12)
  74 #define URXD_BRK        (1<<11)
  75 #define URXD_PRERR      (1<<10)
  76 #define URXD_RX_DATA    (0xFF<<0)
  77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  83 #define UCR1_RXDMAEN    (1<<8)  /* Recv ready DMA enable */
  84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  91 #define UCR1_DOZE       (1<<1)  /* Doze */
  92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  96 #define UCR2_CTS        (1<<12) /* Clear to send */
  97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  98 #define UCR2_PREN       (1<<8)  /* Parity enable */
  99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
 100 #define UCR2_STPB       (1<<6)  /* Stop */
 101 #define UCR2_WS         (1<<5)  /* Word size */
 102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 106 #define UCR2_SRST       (1<<0)  /* SW reset */
 107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 110 #define UCR3_DSR        (1<<10) /* Data set ready */
 111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 112 #define UCR3_RI         (1<<8)  /* Ring indicator */
 113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 117 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 118 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 119 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 120 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 121 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 122 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 123 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 124 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 125 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 126 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 127 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 128 #define UCR4_IRSC       (1<<5)  /* IR special case */
 129 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 130 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 131 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 132 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 133 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 134 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 135 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 136 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 137 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 138 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 139 #define USR1_RTSS       (1<<14) /* RTS pin status */
 140 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 141 #define USR1_RTSD       (1<<12) /* RTS delta */
 142 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 143 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 144 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 145 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 146 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 147 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 148 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 149 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 150 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 151 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 152 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 153 #define USR2_IDLE        (1<<12) /* Idle condition */
 154 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 155 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 156 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 157 #define USR2_WAKE        (1<<7)  /* Wake */
 158 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 159 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 160 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 161 #define USR2_BRCD        (1<<2)  /* Break condition */
 162 #define USR2_ORE        (1<<1)   /* Overrun error */
 163 #define USR2_RDR        (1<<0)   /* Recv data ready */
 164 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 165 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 166 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 167 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 168 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 169 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 170 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 171
 172 /* We've been assigned a range on the "Low-density serial ports" major */
 173 #define SERIAL_IMX_MAJOR        207
 174 #define MINOR_START             16
 175 #define DEV_NAME                "ttymxc"
 176
 177 /*
 178  * This determines how often we check the modem status signals
 179  * for any change.  They generally aren't connected to an IRQ
 180  * so we have to poll them.  We also check immediately before
 181  * filling the TX fifo incase CTS has been dropped.
 182  */
 183 #define MCTRL_TIMEOUT   (250*HZ/1000)
 184
 185 #define DRIVER_NAME "IMX-uart"
 186
 187 #define UART_NR 8
 188
 189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 190 enum imx_uart_type {
 191         IMX1_UART,
 192         IMX21_UART,
 193         IMX53_UART,
 194         IMX6Q_UART,
 195 };
 196
 197 /* device type dependent stuff */
 198 struct imx_uart_data {
 199         unsigned uts_reg;
 200         enum imx_uart_type devtype;
 201 };
 202
 203 struct imx_port {
 204         struct uart_port        port;
 205         struct timer_list       timer;
 206         unsigned int            old_status;
 207         unsigned int            have_rtscts:1;
 208         unsigned int            have_rtsgpio:1;
 209         unsigned int            dte_mode:1;
 210         struct clk              *clk_ipg;
 211         struct clk              *clk_per;
 212         const struct imx_uart_data *devdata;
 213
 214         struct mctrl_gpios *gpios;
 215
 216         /* DMA fields */
 217         unsigned int            dma_is_inited:1;
 218         unsigned int            dma_is_enabled:1;
 219         unsigned int            dma_is_rxing:1;
 220         unsigned int            dma_is_txing:1;
 221         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 222         struct scatterlist      rx_sgl, tx_sgl[2];
 223         void                    *rx_buf;
 224         struct circ_buf         rx_ring;
 225         unsigned int            rx_periods;
 226         dma_cookie_t            rx_cookie;
 227         unsigned int            tx_bytes;
 228         unsigned int            dma_tx_nents;
 229         unsigned int            saved_reg[10];
 230         bool                    context_saved;
 231 };
 232
 233 struct imx_port_ucrs {
 234         unsigned int    ucr1;
 235         unsigned int    ucr2;
 236         unsigned int    ucr3;
 237 };
 238
 239 static struct imx_uart_data imx_uart_devdata[] = {
 240         [IMX1_UART] = {
 241                 .uts_reg = IMX1_UTS,
 242                 .devtype = IMX1_UART,
 243         },
 244         [IMX21_UART] = {
 245                 .uts_reg = IMX21_UTS,
 246                 .devtype = IMX21_UART,
 247         },
 248         [IMX53_UART] = {
 249                 .uts_reg = IMX21_UTS,
 250                 .devtype = IMX53_UART,
 251         },
 252         [IMX6Q_UART] = {
 253                 .uts_reg = IMX21_UTS,
 254                 .devtype = IMX6Q_UART,
 255         },
 256 };
 257
 258 static const struct platform_device_id imx_uart_devtype[] = {
 259         {
 260                 .name = "imx1-uart",
 261                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 262         }, {
 263                 .name = "imx21-uart",
 264                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 265         }, {
 266                 .name = "imx53-uart",
 267                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 268         }, {
 269                 .name = "imx6q-uart",
 270                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 271         }, {
 272                 /* sentinel */
 273         }
 274 };
 275 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 276
 277 static const struct of_device_id imx_uart_dt_ids[] = {
 278         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 279         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 280         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 281         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 282         { /* sentinel */ }
 283 };
 284 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 285
 286 static inline unsigned uts_reg(struct imx_port *sport)
 287 {
 288         return sport->devdata->uts_reg;
 289 }
 290
 291 static inline int is_imx1_uart(struct imx_port *sport)
 292 {
 293         return sport->devdata->devtype == IMX1_UART;
 294 }
 295
 296 static inline int is_imx21_uart(struct imx_port *sport)
 297 {
 298         return sport->devdata->devtype == IMX21_UART;
 299 }
 300
 301 static inline int is_imx53_uart(struct imx_port *sport)
 302 {
 303         return sport->devdata->devtype == IMX53_UART;
 304 }
 305
 306 static inline int is_imx6q_uart(struct imx_port *sport)
 307 {
 308         return sport->devdata->devtype == IMX6Q_UART;
 309 }
 310 /*
 311  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 312  */
 313 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 314 static void imx_port_ucrs_save(struct uart_port *port,
 315                                struct imx_port_ucrs *ucr)
 316 {
 317         /* save control registers */
 318         ucr->ucr1 = readl(port->membase + UCR1);
 319         ucr->ucr2 = readl(port->membase + UCR2);
 320         ucr->ucr3 = readl(port->membase + UCR3);
 321 }
 322
 323 static void imx_port_ucrs_restore(struct uart_port *port,
 324                                   struct imx_port_ucrs *ucr)
 325 {
 326         /* restore control registers */
 327         writel(ucr->ucr1, port->membase + UCR1);
 328         writel(ucr->ucr2, port->membase + UCR2);
 329         writel(ucr->ucr3, port->membase + UCR3);
 330 }
 331 #endif
 332
 333 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 334 {
 335         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 336
 337         sport->port.mctrl |= TIOCM_RTS;
 338         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 339 }
 340
 341 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 342 {
 343         *ucr2 &= ~UCR2_CTSC;
 344         *ucr2 |= UCR2_CTS;
 345
 346         sport->port.mctrl &= ~TIOCM_RTS;
 347         mctrl_gpio_set(sport->gpios, sport->port.mctrl);
 348 }
 349
 350 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 351 {
 352         *ucr2 |= UCR2_CTSC;
 353 }
 354
 355 /*
 356  * interrupts disabled on entry
 357  */
 358 static void imx_start_rx(struct uart_port *port)
 359 {
 360         struct imx_port *sport = (struct imx_port *)port;
 361         unsigned int ucr1, ucr2;
 362
 363         ucr1 = readl(port->membase + UCR1);
 364         ucr2 = readl(port->membase + UCR2);
 365
 366         ucr2 |= UCR2_RXEN;
 367
 368         if (sport->dma_is_enabled) {
 369                 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
 370         } else {
 371                 ucr1 |= UCR1_RRDYEN;
 372         }
 373
 374         /* Write UCR2 first as it includes RXEN */
 375         writel(ucr2, port->membase + UCR2);
 376         writel(ucr1, port->membase + UCR1);
 377 }
 378
 379 /*
 380  * interrupts disabled on entry
 381  */
 382 static void imx_stop_tx(struct uart_port *port)
 383 {
 384         struct imx_port *sport = (struct imx_port *)port;
 385         unsigned long temp;
 386
 387         /*
 388          * We are maybe in the SMP context, so if the DMA TX thread is running
 389          * on other cpu, we have to wait for it to finish.
 390          */
 391         if (sport->dma_is_enabled && sport->dma_is_txing)
 392                 return;
 393
 394         temp = readl(port->membase + UCR1);
 395         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 396
 397         /* in rs485 mode disable transmitter if shifter is empty */
 398         if (port->rs485.flags & SER_RS485_ENABLED &&
 399             readl(port->membase + USR2) & USR2_TXDC) {
 400                 temp = readl(port->membase + UCR2);
 401                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 402                         imx_port_rts_active(sport, &temp);
 403                 else
 404                         imx_port_rts_inactive(sport, &temp);
 405                 writel(temp, port->membase + UCR2);
 406
 407                 imx_start_rx(port);
 408
 409                 temp = readl(port->membase + UCR4);
 410                 temp &= ~UCR4_TCEN;
 411                 writel(temp, port->membase + UCR4);
 412         }
 413 }
 414
 415 /*
 416  * interrupts disabled on entry
 417  */
 418 static void imx_stop_rx(struct uart_port *port)
 419 {
 420         struct imx_port *sport = (struct imx_port *)port;
 421         unsigned long ucr1, ucr2;
 422
 423         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 424                 if (sport->port.suspended) {
 425                         dmaengine_terminate_all(sport->dma_chan_rx);
 426                         sport->dma_is_rxing = 0;
 427                 } else {
 428                         return;
 429                 }
 430         }
 431
 432         ucr1 = readl(sport->port.membase + UCR1);
 433         ucr2 = readl(sport->port.membase + UCR2);
 434
 435         if (sport->dma_is_enabled) {
 436                 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
 437         } else {
 438                 ucr1 &= ~UCR1_RRDYEN;
 439         }
 440         writel(ucr1, port->membase + UCR1);
 441
 442         ucr2 &= ~UCR2_RXEN;
 443         writel(ucr2, port->membase + UCR2);
 444 }
 445
 446 /*
 447  * Set the modem control timer to fire immediately.
 448  */
 449 static void imx_enable_ms(struct uart_port *port)
 450 {
 451         struct imx_port *sport = (struct imx_port *)port;
 452
 453         mod_timer(&sport->timer, jiffies);
 454
 455         mctrl_gpio_enable_ms(sport->gpios);
 456 }
 457
 458 static void imx_dma_tx(struct imx_port *sport);
 459 static inline void imx_transmit_buffer(struct imx_port *sport)
 460 {
 461         struct circ_buf *xmit = &sport->port.state->xmit;
 462         unsigned long temp;
 463
 464         if (sport->port.x_char) {
 465                 /* Send next char */
 466                 writel(sport->port.x_char, sport->port.membase + URTX0);
 467                 sport->port.icount.tx++;
 468                 sport->port.x_char = 0;
 469                 return;
 470         }
 471
 472         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 473                 imx_stop_tx(&sport->port);
 474                 return;
 475         }
 476
 477         if (sport->dma_is_enabled) {
 478                 /*
 479                  * We've just sent a X-char Ensure the TX DMA is enabled
 480                  * and the TX IRQ is disabled.
 481                  **/
 482                 temp = readl(sport->port.membase + UCR1);
 483                 temp &= ~UCR1_TXMPTYEN;
 484                 if (sport->dma_is_txing) {
 485                         temp |= UCR1_TDMAEN;
 486                         writel(temp, sport->port.membase + UCR1);
 487                 } else {
 488                         writel(temp, sport->port.membase + UCR1);
 489                         imx_dma_tx(sport);
 490                 }
 491         }
 492
 493         if (sport->dma_is_txing)
 494                 return;
 495
 496         while (!uart_circ_empty(xmit) &&
 497                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 498                 /* send xmit->buf[xmit->tail]
 499                  * out the port here */
 500                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 501                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 502                 sport->port.icount.tx++;
 503         }
 504
 505         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 506                 uart_write_wakeup(&sport->port);
 507
 508         if (uart_circ_empty(xmit))
 509                 imx_stop_tx(&sport->port);
 510 }
 511
 512 static void dma_tx_callback(void *data)
 513 {
 514         struct imx_port *sport = data;
 515         struct scatterlist *sgl = &sport->tx_sgl[0];
 516         struct circ_buf *xmit = &sport->port.state->xmit;
 517         unsigned long flags;
 518         unsigned long temp;
 519
 520         spin_lock_irqsave(&sport->port.lock, flags);
 521
 522         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 523
 524         temp = readl(sport->port.membase + UCR1);
 525         temp &= ~UCR1_TDMAEN;
 526         writel(temp, sport->port.membase + UCR1);
 527
 528         /* update the stat */
 529         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 530         sport->port.icount.tx += sport->tx_bytes;
 531
 532         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 533
 534         sport->dma_is_txing = 0;
 535
 536         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 537                 uart_write_wakeup(&sport->port);
 538
 539         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 540                 imx_dma_tx(sport);
 541         else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
 542                 temp = readl(sport->port.membase + UCR4);
 543                 temp |= UCR4_TCEN;
 544                 writel(temp, sport->port.membase + UCR4);
 545         }
 546
 547         spin_unlock_irqrestore(&sport->port.lock, flags);
 548 }
 549
 550 static void imx_dma_tx(struct imx_port *sport)
 551 {
 552         struct circ_buf *xmit = &sport->port.state->xmit;
 553         struct scatterlist *sgl = sport->tx_sgl;
 554         struct dma_async_tx_descriptor *desc;
 555         struct dma_chan *chan = sport->dma_chan_tx;
 556         struct device *dev = sport->port.dev;
 557         unsigned long temp;
 558         int ret;
 559
 560         if (sport->dma_is_txing)
 561                 return;
 562
 563         temp = readl(sport->port.membase + UCR4);
 564         temp &= ~UCR4_TCEN;
 565         writel(temp, sport->port.membase + UCR4);
 566
 567         sport->tx_bytes = uart_circ_chars_pending(xmit);
 568
 569         if (xmit->tail < xmit->head || xmit->head == 0) {
 570                 sport->dma_tx_nents = 1;
 571                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 572         } else {
 573                 sport->dma_tx_nents = 2;
 574                 sg_init_table(sgl, 2);
 575                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 576                                 UART_XMIT_SIZE - xmit->tail);
 577                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 578         }
 579
 580         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 581         if (ret == 0) {
 582                 dev_err(dev, "DMA mapping error for TX.\n");
 583                 return;
 584         }
 585         desc = dmaengine_prep_slave_sg(chan, sgl, ret,
 586                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 587         if (!desc) {
 588                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 589                              DMA_TO_DEVICE);
 590                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 591                 return;
 592         }
 593         desc->callback = dma_tx_callback;
 594         desc->callback_param = sport;
 595
 596         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 597                         uart_circ_chars_pending(xmit));
 598
 599         temp = readl(sport->port.membase + UCR1);
 600         temp |= UCR1_TDMAEN;
 601         writel(temp, sport->port.membase + UCR1);
 602
 603         /* fire it */
 604         sport->dma_is_txing = 1;
 605         dmaengine_submit(desc);
 606         dma_async_issue_pending(chan);
 607         return;
 608 }
 609
 610 /*
 611  * interrupts disabled on entry
 612  */
 613 static void imx_start_tx(struct uart_port *port)
 614 {
 615         struct imx_port *sport = (struct imx_port *)port;
 616         unsigned long temp;
 617
 618         if (port->rs485.flags & SER_RS485_ENABLED) {
 619                 temp = readl(port->membase + UCR2);
 620                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 621                         imx_port_rts_active(sport, &temp);
 622                 else
 623                         imx_port_rts_inactive(sport, &temp);
 624                 writel(temp, port->membase + UCR2);
 625
 626                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 627                         imx_stop_rx(port);
 628
 629                 /*
 630                  * Enable transmitter and shifter empty irq only if DMA is off.
 631                  * In the DMA case this is done in the tx-callback.
 632                  */
 633                 if (!sport->dma_is_enabled) {
 634                         temp = readl(port->membase + UCR4);
 635                         temp |= UCR4_TCEN;
 636                         writel(temp, port->membase + UCR4);
 637                 }
 638         }
 639
 640         if (!sport->dma_is_enabled) {
 641                 temp = readl(sport->port.membase + UCR1);
 642                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 643         }
 644
 645         if (sport->dma_is_enabled) {
 646                 if (sport->port.x_char) {
 647                         /* We have X-char to send, so enable TX IRQ and
 648                          * disable TX DMA to let TX interrupt to send X-char */
 649                         temp = readl(sport->port.membase + UCR1);
 650                         temp &= ~UCR1_TDMAEN;
 651                         temp |= UCR1_TXMPTYEN;
 652                         writel(temp, sport->port.membase + UCR1);
 653                         return;
 654                 }
 655
 656                 if (!uart_circ_empty(&port->state->xmit) &&
 657                     !uart_tx_stopped(port))
 658                         imx_dma_tx(sport);
 659                 return;
 660         }
 661 }
 662
 663 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 664 {
 665         struct imx_port *sport = dev_id;
 666         unsigned int val;
 667         unsigned long flags;
 668
 669         spin_lock_irqsave(&sport->port.lock, flags);
 670
 671         writel(USR1_RTSD, sport->port.membase + USR1);
 672         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 673         uart_handle_cts_change(&sport->port, !!val);
 674         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 675
 676         spin_unlock_irqrestore(&sport->port.lock, flags);
 677         return IRQ_HANDLED;
 678 }
 679
 680 static irqreturn_t imx_txint(int irq, void *dev_id)
 681 {
 682         struct imx_port *sport = dev_id;
 683         unsigned long flags;
 684
 685         spin_lock_irqsave(&sport->port.lock, flags);
 686         imx_transmit_buffer(sport);
 687         spin_unlock_irqrestore(&sport->port.lock, flags);
 688         return IRQ_HANDLED;
 689 }
 690
 691 static irqreturn_t imx_rxint(int irq, void *dev_id)
 692 {
 693         struct imx_port *sport = dev_id;
 694         unsigned int rx, flg, ignored = 0;
 695         struct tty_port *port = &sport->port.state->port;
 696         unsigned long flags, temp;
 697
 698         spin_lock_irqsave(&sport->port.lock, flags);
 699
 700         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 701                 flg = TTY_NORMAL;
 702                 sport->port.icount.rx++;
 703
 704                 rx = readl(sport->port.membase + URXD0);
 705
 706                 temp = readl(sport->port.membase + USR2);
 707                 if (temp & USR2_BRCD) {
 708                         writel(USR2_BRCD, sport->port.membase + USR2);
 709                         if (uart_handle_break(&sport->port))
 710                                 continue;
 711                 }
 712
 713                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 714                         continue;
 715
 716                 if (unlikely(rx & URXD_ERR)) {
 717                         if (rx & URXD_BRK)
 718                                 sport->port.icount.brk++;
 719                         else if (rx & URXD_PRERR)
 720                                 sport->port.icount.parity++;
 721                         else if (rx & URXD_FRMERR)
 722                                 sport->port.icount.frame++;
 723                         if (rx & URXD_OVRRUN)
 724                                 sport->port.icount.overrun++;
 725
 726                         if (rx & sport->port.ignore_status_mask) {
 727                                 if (++ignored > 100)
 728                                         goto out;
 729                                 continue;
 730                         }
 731
 732                         rx &= (sport->port.read_status_mask | 0xFF);
 733
 734                         if (rx & URXD_BRK)
 735                                 flg = TTY_BREAK;
 736                         else if (rx & URXD_PRERR)
 737                                 flg = TTY_PARITY;
 738                         else if (rx & URXD_FRMERR)
 739                                 flg = TTY_FRAME;
 740                         if (rx & URXD_OVRRUN)
 741                                 flg = TTY_OVERRUN;
 742
 743 #ifdef SUPPORT_SYSRQ
 744                         sport->port.sysrq = 0;
 745 #endif
 746                 }
 747
 748                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 749                         goto out;
 750
 751                 if (tty_insert_flip_char(port, rx, flg) == 0)
 752                         sport->port.icount.buf_overrun++;
 753         }
 754
 755 out:
 756         spin_unlock_irqrestore(&sport->port.lock, flags);
 757         tty_flip_buffer_push(port);
 758         return IRQ_HANDLED;
 759 }
 760
 761 static void imx_disable_rx_int(struct imx_port *sport)
 762 {
 763         unsigned long temp;
 764
 765         sport->dma_is_rxing = 1;
 766
 767         /* disable the receiver ready and aging timer interrupts */
 768         temp = readl(sport->port.membase + UCR1);
 769         temp &= ~(UCR1_RRDYEN);
 770         writel(temp, sport->port.membase + UCR1);
 771
 772         temp = readl(sport->port.membase + UCR2);
 773         temp &= ~(UCR2_ATEN);
 774         writel(temp, sport->port.membase + UCR2);
 775
 776         /* disable the rx errors interrupts */
 777         temp = readl(sport->port.membase + UCR4);
 778         temp &= ~UCR4_OREN;
 779         writel(temp, sport->port.membase + UCR4);
 780 }
 781
 782 static void clear_rx_errors(struct imx_port *sport);
 783 static int start_rx_dma(struct imx_port *sport);
 784 /*
 785  * If the RXFIFO is filled with some data, and then we
 786  * arise a DMA operation to receive them.
 787  */
 788 static void imx_dma_rxint(struct imx_port *sport)
 789 {
 790         unsigned long temp;
 791         unsigned long flags;
 792
 793         spin_lock_irqsave(&sport->port.lock, flags);
 794
 795         temp = readl(sport->port.membase + USR2);
 796         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 797
 798                 imx_disable_rx_int(sport);
 799
 800                 /* tell the DMA to receive the data. */
 801                 start_rx_dma(sport);
 802         }
 803
 804         spin_unlock_irqrestore(&sport->port.lock, flags);
 805 }
 806
 807 /*
 808  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 809  */
 810 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 811 {
 812         unsigned int tmp = TIOCM_DSR;
 813         unsigned usr1 = readl(sport->port.membase + USR1);
 814         unsigned usr2 = readl(sport->port.membase + USR2);
 815
 816         if (usr1 & USR1_RTSS)
 817                 tmp |= TIOCM_CTS;
 818
 819         /* in DCE mode DCDIN is always 0 */
 820         if (!(usr2 & USR2_DCDIN))
 821                 tmp |= TIOCM_CAR;
 822
 823         if (sport->dte_mode)
 824                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 825                         tmp |= TIOCM_RI;
 826
 827         return tmp;
 828 }
 829
 830 /*
 831  * Handle any change of modem status signal since we were last called.
 832  */
 833 static void imx_mctrl_check(struct imx_port *sport)
 834 {
 835         unsigned int status, changed;
 836
 837         status = imx_get_hwmctrl(sport);
 838         changed = status ^ sport->old_status;
 839
 840         if (changed == 0)
 841                 return;
 842
 843         sport->old_status = status;
 844
 845         if (changed & TIOCM_RI && status & TIOCM_RI)
 846                 sport->port.icount.rng++;
 847         if (changed & TIOCM_DSR)
 848                 sport->port.icount.dsr++;
 849         if (changed & TIOCM_CAR)
 850                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 851         if (changed & TIOCM_CTS)
 852                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 853
 854         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 855 }
 856
 857 static irqreturn_t imx_int(int irq, void *dev_id)
 858 {
 859         struct imx_port *sport = dev_id;
 860         unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
 861         irqreturn_t ret = IRQ_NONE;
 862
 863         usr1 = readl(sport->port.membase + USR1);
 864         usr2 = readl(sport->port.membase + USR2);
 865         ucr1 = readl(sport->port.membase + UCR1);
 866         ucr2 = readl(sport->port.membase + UCR2);
 867         ucr3 = readl(sport->port.membase + UCR3);
 868         ucr4 = readl(sport->port.membase + UCR4);
 869
 870         /*
 871          * Even if a condition is true that can trigger an irq only handle it if
 872          * the respective irq source is enabled. This prevents some undesired
 873          * actions, for example if a character that sits in the RX FIFO and that
 874          * should be fetched via DMA is tried to be fetched using PIO. Or the
 875          * receiver is currently off and so reading from URXD0 results in an
 876          * exception. So just mask the (raw) status bits for disabled irqs.
 877          */
 878         if ((ucr1 & UCR1_RRDYEN) == 0)
 879                 usr1 &= ~USR1_RRDY;
 880         if ((ucr2 & UCR2_ATEN) == 0)
 881                 usr1 &= ~USR1_AGTIM;
 882         if ((ucr1 & UCR1_TXMPTYEN) == 0)
 883                 usr1 &= ~USR1_TRDY;
 884         if ((ucr4 & UCR4_TCEN) == 0)
 885                 usr2 &= ~USR2_TXDC;
 886         if ((ucr3 & UCR3_DTRDEN) == 0)
 887                 usr1 &= ~USR1_DTRD;
 888         if ((ucr1 & UCR1_RTSDEN) == 0)
 889                 usr1 &= ~USR1_RTSD;
 890         if ((ucr3 & UCR3_AWAKEN) == 0)
 891                 usr1 &= ~USR1_AWAKE;
 892         if ((ucr4 & UCR4_OREN) == 0)
 893                 usr2 &= ~USR2_ORE;
 894
 895         if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
 896                 if (sport->dma_is_enabled)
 897                         imx_dma_rxint(sport);
 898                 else
 899                         imx_rxint(irq, dev_id);
 900                 ret = IRQ_HANDLED;
 901         }
 902
 903         if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
 904                 imx_txint(irq, dev_id);
 905                 ret = IRQ_HANDLED;
 906         }
 907
 908         if (usr1 & USR1_DTRD) {
 909                 unsigned long flags;
 910
 911                 if (usr1 & USR1_DTRD)
 912                         writel(USR1_DTRD, sport->port.membase + USR1);
 913
 914                 spin_lock_irqsave(&sport->port.lock, flags);
 915                 imx_mctrl_check(sport);
 916                 spin_unlock_irqrestore(&sport->port.lock, flags);
 917
 918                 ret = IRQ_HANDLED;
 919         }
 920
 921         if (usr1 & USR1_RTSD) {
 922                 imx_rtsint(irq, dev_id);
 923                 ret = IRQ_HANDLED;
 924         }
 925
 926         if (usr1 & USR1_AWAKE) {
 927                 writel(USR1_AWAKE, sport->port.membase + USR1);
 928                 ret = IRQ_HANDLED;
 929         }
 930
 931         if (usr2 & USR2_ORE) {
 932                 sport->port.icount.overrun++;
 933                 writel(USR2_ORE, sport->port.membase + USR2);
 934                 ret = IRQ_HANDLED;
 935         }
 936
 937         return ret;
 938 }
 939
 940 /*
 941  * Return TIOCSER_TEMT when transmitter is not busy.
 942  */
 943 static unsigned int imx_tx_empty(struct uart_port *port)
 944 {
 945         struct imx_port *sport = (struct imx_port *)port;
 946         unsigned int ret;
 947
 948         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 949
 950         /* If the TX DMA is working, return 0. */
 951         if (sport->dma_is_enabled && sport->dma_is_txing)
 952                 ret = 0;
 953
 954         return ret;
 955 }
 956
 957 static unsigned int imx_get_mctrl(struct uart_port *port)
 958 {
 959         struct imx_port *sport = (struct imx_port *)port;
 960         unsigned int ret = imx_get_hwmctrl(sport);
 961
 962         mctrl_gpio_get(sport->gpios, &ret);
 963
 964         return ret;
 965 }
 966
 967 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 968 {
 969         struct imx_port *sport = (struct imx_port *)port;
 970         unsigned long temp;
 971
 972         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 973                 temp = readl(sport->port.membase + UCR2);
 974                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 975                 if (mctrl & TIOCM_RTS)
 976                         temp |= UCR2_CTS | UCR2_CTSC;
 977                 writel(temp, sport->port.membase + UCR2);
 978         }
 979
 980         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 981         if (!(mctrl & TIOCM_DTR))
 982                 temp |= UCR3_DSR;
 983         writel(temp, sport->port.membase + UCR3);
 984
 985         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 986         if (mctrl & TIOCM_LOOP)
 987                 temp |= UTS_LOOP;
 988         writel(temp, sport->port.membase + uts_reg(sport));
 989
 990         mctrl_gpio_set(sport->gpios, mctrl);
 991 }
 992
 993 /*
 994  * Interrupts always disabled.
 995  */
 996 static void imx_break_ctl(struct uart_port *port, int break_state)
 997 {
 998         struct imx_port *sport = (struct imx_port *)port;
 999         unsigned long flags, temp;
1000
1001         spin_lock_irqsave(&sport->port.lock, flags);
1002
1003         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
1004
1005         if (break_state != 0)
1006                 temp |= UCR1_SNDBRK;
1007
1008         writel(temp, sport->port.membase + UCR1);
1009
1010         spin_unlock_irqrestore(&sport->port.lock, flags);
1011 }
1012
1013 /*
1014  * This is our per-port timeout handler, for checking the
1015  * modem status signals.
1016  */
1017 static void imx_timeout(unsigned long data)
1018 {
1019         struct imx_port *sport = (struct imx_port *)data;
1020         unsigned long flags;
1021
1022         if (sport->port.state) {
1023                 spin_lock_irqsave(&sport->port.lock, flags);
1024                 imx_mctrl_check(sport);
1025                 spin_unlock_irqrestore(&sport->port.lock, flags);
1026
1027                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1028         }
1029 }
1030
1031 #define RX_BUF_SIZE     (PAGE_SIZE)
1032
1033 /*
1034  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1035  *   [1] the RX DMA buffer is full.
1036  *   [2] the aging timer expires
1037  *
1038  * Condition [2] is triggered when a character has been sitting in the FIFO
1039  * for at least 8 byte durations.
1040  */
1041 static void dma_rx_callback(void *data)
1042 {
1043         struct imx_port *sport = data;
1044         struct dma_chan *chan = sport->dma_chan_rx;
1045         struct scatterlist *sgl = &sport->rx_sgl;
1046         struct tty_port *port = &sport->port.state->port;
1047         struct dma_tx_state state;
1048         struct circ_buf *rx_ring = &sport->rx_ring;
1049         enum dma_status status;
1050         unsigned int w_bytes = 0;
1051         unsigned int r_bytes;
1052         unsigned int bd_size;
1053
1054         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
1055
1056         if (status == DMA_ERROR) {
1057                 dev_err(sport->port.dev, "DMA transaction error.\n");
1058                 clear_rx_errors(sport);
1059                 return;
1060         }
1061
1062         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1063
1064                 /*
1065                  * The state-residue variable represents the empty space
1066                  * relative to the entire buffer. Taking this in consideration
1067                  * the head is always calculated base on the buffer total
1068                  * length - DMA transaction residue. The UART script from the
1069                  * SDMA firmware will jump to the next buffer descriptor,
1070                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1071                  * Taking this in consideration the tail is always at the
1072                  * beginning of the buffer descriptor that contains the head.
1073                  */
1074
1075                 /* Calculate the head */
1076                 rx_ring->head = sg_dma_len(sgl) - state.residue;
1077
1078                 /* Calculate the tail. */
1079                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1080                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1081
1082                 if (rx_ring->head <= sg_dma_len(sgl) &&
1083                     rx_ring->head > rx_ring->tail) {
1084
1085                         /* Move data from tail to head */
1086                         r_bytes = rx_ring->head - rx_ring->tail;
1087
1088                         /* CPU claims ownership of RX DMA buffer */
1089                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1090                                 DMA_FROM_DEVICE);
1091
1092                         w_bytes = tty_insert_flip_string(port,
1093                                 sport->rx_buf + rx_ring->tail, r_bytes);
1094
1095                         /* UART retrieves ownership of RX DMA buffer */
1096                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1097                                 DMA_FROM_DEVICE);
1098
1099                         if (w_bytes != r_bytes)
1100                                 sport->port.icount.buf_overrun++;
1101
1102                         sport->port.icount.rx += w_bytes;
1103                 } else  {
1104                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
1105                         WARN_ON(rx_ring->head <= rx_ring->tail);
1106                 }
1107         }
1108
1109         if (w_bytes) {
1110                 tty_flip_buffer_push(port);
1111                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1112         }
1113 }
1114
1115 /* RX DMA buffer periods */
1116 #define RX_DMA_PERIODS 4
1117
1118 static int start_rx_dma(struct imx_port *sport)
1119 {
1120         struct scatterlist *sgl = &sport->rx_sgl;
1121         struct dma_chan *chan = sport->dma_chan_rx;
1122         struct device *dev = sport->port.dev;
1123         struct dma_async_tx_descriptor *desc;
1124         int ret;
1125
1126         sport->rx_ring.head = 0;
1127         sport->rx_ring.tail = 0;
1128         sport->rx_periods = RX_DMA_PERIODS;
1129
1130         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1131         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1132         if (ret == 0) {
1133                 dev_err(dev, "DMA mapping error for RX.\n");
1134                 return -EINVAL;
1135         }
1136
1137         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1138                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1139                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1140
1141         if (!desc) {
1142                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1143                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1144                 return -EINVAL;
1145         }
1146         desc->callback = dma_rx_callback;
1147         desc->callback_param = sport;
1148
1149         dev_dbg(dev, "RX: prepare for the DMA.\n");
1150         sport->rx_cookie = dmaengine_submit(desc);
1151         dma_async_issue_pending(chan);
1152         return 0;
1153 }
1154
1155 static void clear_rx_errors(struct imx_port *sport)
1156 {
1157         unsigned int status_usr1, status_usr2;
1158
1159         status_usr1 = readl(sport->port.membase + USR1);
1160         status_usr2 = readl(sport->port.membase + USR2);
1161
1162         if (status_usr2 & USR2_BRCD) {
1163                 sport->port.icount.brk++;
1164                 writel(USR2_BRCD, sport->port.membase + USR2);
1165         } else if (status_usr1 & USR1_FRAMERR) {
1166                 sport->port.icount.frame++;
1167                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1168         } else if (status_usr1 & USR1_PARITYERR) {
1169                 sport->port.icount.parity++;
1170                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1171         }
1172
1173         if (status_usr2 & USR2_ORE) {
1174                 sport->port.icount.overrun++;
1175                 writel(USR2_ORE, sport->port.membase + USR2);
1176         }
1177
1178 }
1179
1180 #define TXTL_DEFAULT 2 /* reset default */
1181 #define RXTL_DEFAULT 1 /* reset default */
1182 #define TXTL_DMA 8 /* DMA burst setting */
1183 #define RXTL_DMA 9 /* DMA burst setting */
1184
1185 static void imx_setup_ufcr(struct imx_port *sport,
1186                           unsigned char txwl, unsigned char rxwl)
1187 {
1188         unsigned int val;
1189
1190         /* set receiver / transmitter trigger level */
1191         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1192         val |= txwl << UFCR_TXTL_SHF | rxwl;
1193         writel(val, sport->port.membase + UFCR);
1194 }
1195
1196 static void imx_uart_dma_exit(struct imx_port *sport)
1197 {
1198         if (sport->dma_chan_rx) {
1199                 dmaengine_terminate_sync(sport->dma_chan_rx);
1200                 dma_release_channel(sport->dma_chan_rx);
1201                 sport->dma_chan_rx = NULL;
1202                 sport->rx_cookie = -EINVAL;
1203                 kfree(sport->rx_buf);
1204                 sport->rx_buf = NULL;
1205         }
1206
1207         if (sport->dma_chan_tx) {
1208                 dmaengine_terminate_sync(sport->dma_chan_tx);
1209                 dma_release_channel(sport->dma_chan_tx);
1210                 sport->dma_chan_tx = NULL;
1211         }
1212
1213         sport->dma_is_inited = 0;
1214 }
1215
1216 static int imx_uart_dma_init(struct imx_port *sport)
1217 {
1218         struct dma_slave_config slave_config = {};
1219         struct device *dev = sport->port.dev;
1220         int ret;
1221
1222         /* Prepare for RX : */
1223         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1224         if (!sport->dma_chan_rx) {
1225                 dev_dbg(dev, "cannot get the DMA channel.\n");
1226                 ret = -EINVAL;
1227                 goto err;
1228         }
1229
1230         slave_config.direction = DMA_DEV_TO_MEM;
1231         slave_config.src_addr = sport->port.mapbase + URXD0;
1232         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1233         /* one byte less than the watermark level to enable the aging timer */
1234         slave_config.src_maxburst = RXTL_DMA - 1;
1235         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1236         if (ret) {
1237                 dev_err(dev, "error in RX dma configuration.\n");
1238                 goto err;
1239         }
1240
1241         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1242         if (!sport->rx_buf) {
1243                 ret = -ENOMEM;
1244                 goto err;
1245         }
1246         sport->rx_ring.buf = sport->rx_buf;
1247
1248         /* Prepare for TX : */
1249         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1250         if (!sport->dma_chan_tx) {
1251                 dev_err(dev, "cannot get the TX DMA channel!\n");
1252                 ret = -EINVAL;
1253                 goto err;
1254         }
1255
1256         slave_config.direction = DMA_MEM_TO_DEV;
1257         slave_config.dst_addr = sport->port.mapbase + URTX0;
1258         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1259         slave_config.dst_maxburst = TXTL_DMA;
1260         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1261         if (ret) {
1262                 dev_err(dev, "error in TX dma configuration.");
1263                 goto err;
1264         }
1265
1266         sport->dma_is_inited = 1;
1267
1268         return 0;
1269 err:
1270         imx_uart_dma_exit(sport);
1271         return ret;
1272 }
1273
1274 static void imx_enable_dma(struct imx_port *sport)
1275 {
1276         unsigned long temp;
1277
1278         /* set UCR1 */
1279         temp = readl(sport->port.membase + UCR1);
1280         temp |= UCR1_RXDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1281         writel(temp, sport->port.membase + UCR1);
1282
1283         temp = readl(sport->port.membase + UCR2);
1284         temp |= UCR2_ATEN;
1285         writel(temp, sport->port.membase + UCR2);
1286
1287         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1288
1289         sport->dma_is_enabled = 1;
1290 }
1291
1292 static void imx_disable_dma(struct imx_port *sport)
1293 {
1294         unsigned long temp;
1295
1296         /* clear UCR1 */
1297         temp = readl(sport->port.membase + UCR1);
1298         temp &= ~(UCR1_RXDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1299         writel(temp, sport->port.membase + UCR1);
1300
1301         /* clear UCR2 */
1302         temp = readl(sport->port.membase + UCR2);
1303         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1304         writel(temp, sport->port.membase + UCR2);
1305
1306         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1307
1308         sport->dma_is_enabled = 0;
1309 }
1310
1311 /* half the RX buffer size */
1312 #define CTSTL 16
1313
1314 static int imx_startup(struct uart_port *port)
1315 {
1316         struct imx_port *sport = (struct imx_port *)port;
1317         int retval, i;
1318         unsigned long flags, temp;
1319
1320         retval = clk_prepare_enable(sport->clk_per);
1321         if (retval)
1322                 return retval;
1323         retval = clk_prepare_enable(sport->clk_ipg);
1324         if (retval) {
1325                 clk_disable_unprepare(sport->clk_per);
1326                 return retval;
1327         }
1328
1329         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1330
1331         /* disable the DREN bit (Data Ready interrupt enable) before
1332          * requesting IRQs
1333          */
1334         temp = readl(sport->port.membase + UCR4);
1335
1336         /* set the trigger level for CTS */
1337         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1338         temp |= CTSTL << UCR4_CTSTL_SHF;
1339
1340         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1341
1342         /* Can we enable the DMA support? */
1343         if (!uart_console(port) && !sport->dma_is_inited)
1344                 imx_uart_dma_init(sport);
1345
1346         spin_lock_irqsave(&sport->port.lock, flags);
1347         /* Reset fifo's and state machines */
1348         i = 100;
1349
1350         temp = readl(sport->port.membase + UCR2);
1351         temp &= ~UCR2_SRST;
1352         writel(temp, sport->port.membase + UCR2);
1353
1354         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1355                 udelay(1);
1356
1357         /*
1358          * Finally, clear and enable interrupts
1359          */
1360         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1361         writel(USR2_ORE, sport->port.membase + USR2);
1362
1363         temp = readl(sport->port.membase + UCR1);
1364         temp &= ~UCR1_RRDYEN;
1365         temp |= UCR1_UARTEN;
1366         if (sport->have_rtscts)
1367                         temp |= UCR1_RTSDEN;
1368
1369         writel(temp, sport->port.membase + UCR1);
1370
1371         temp = readl(sport->port.membase + UCR4);
1372         temp |= UCR4_OREN;
1373         writel(temp, sport->port.membase + UCR4);
1374
1375         temp = readl(sport->port.membase + UCR2);
1376         temp |= (UCR2_RXEN | UCR2_TXEN);
1377         if (!sport->have_rtscts)
1378                 temp |= UCR2_IRTS;
1379         /*
1380          * make sure the edge sensitive RTS-irq is disabled,
1381          * we're using RTSD instead.
1382          */
1383         if (!is_imx1_uart(sport))
1384                 temp &= ~UCR2_RTSEN;
1385         writel(temp, sport->port.membase + UCR2);
1386
1387         if (!is_imx1_uart(sport)) {
1388                 temp = readl(sport->port.membase + UCR3);
1389
1390                 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1391
1392                 if (sport->dte_mode)
1393                         /* disable broken interrupts */
1394                         temp &= ~(UCR3_RI | UCR3_DCD);
1395
1396                 writel(temp, sport->port.membase + UCR3);
1397         }
1398
1399         /*
1400          * Enable modem status interrupts
1401          */
1402         imx_enable_ms(&sport->port);
1403
1404         if (sport->dma_is_inited) {
1405                 imx_enable_dma(sport);
1406                 start_rx_dma(sport);
1407         } else {
1408                 temp = readl(sport->port.membase + UCR1);
1409                 temp |= UCR1_RRDYEN;
1410                 writel(temp, sport->port.membase + UCR1);
1411         }
1412
1413         spin_unlock_irqrestore(&sport->port.lock, flags);
1414
1415         return 0;
1416 }
1417
1418 static void imx_shutdown(struct uart_port *port)
1419 {
1420         struct imx_port *sport = (struct imx_port *)port;
1421         unsigned long temp;
1422         unsigned long flags;
1423
1424         if (sport->dma_is_enabled) {
1425                 sport->dma_is_rxing = 0;
1426                 sport->dma_is_txing = 0;
1427                 dmaengine_terminate_sync(sport->dma_chan_tx);
1428                 dmaengine_terminate_sync(sport->dma_chan_rx);
1429
1430                 spin_lock_irqsave(&sport->port.lock, flags);
1431                 imx_stop_tx(port);
1432                 imx_stop_rx(port);
1433                 imx_disable_dma(sport);
1434                 spin_unlock_irqrestore(&sport->port.lock, flags);
1435                 imx_uart_dma_exit(sport);
1436         }
1437
1438         mctrl_gpio_disable_ms(sport->gpios);
1439
1440         spin_lock_irqsave(&sport->port.lock, flags);
1441         temp = readl(sport->port.membase + UCR2);
1442         temp &= ~(UCR2_TXEN);
1443         writel(temp, sport->port.membase + UCR2);
1444         spin_unlock_irqrestore(&sport->port.lock, flags);
1445
1446         /*
1447          * Stop our timer.
1448          */
1449         del_timer_sync(&sport->timer);
1450
1451         /*
1452          * Disable all interrupts, port and break condition.
1453          */
1454
1455         spin_lock_irqsave(&sport->port.lock, flags);
1456         temp = readl(sport->port.membase + UCR1);
1457         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN |
1458                   UCR1_RXDMAEN | UCR1_ATDMAEN);
1459
1460         writel(temp, sport->port.membase + UCR1);
1461         spin_unlock_irqrestore(&sport->port.lock, flags);
1462
1463         clk_disable_unprepare(sport->clk_per);
1464         clk_disable_unprepare(sport->clk_ipg);
1465 }
1466
1467 static void imx_flush_buffer(struct uart_port *port)
1468 {
1469         struct imx_port *sport = (struct imx_port *)port;
1470         struct scatterlist *sgl = &sport->tx_sgl[0];
1471         unsigned long temp;
1472         int i = 100, ubir, ubmr, uts;
1473
1474         if (!sport->dma_chan_tx)
1475                 return;
1476
1477         sport->tx_bytes = 0;
1478         dmaengine_terminate_all(sport->dma_chan_tx);
1479         if (sport->dma_is_txing) {
1480                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1481                              DMA_TO_DEVICE);
1482                 temp = readl(sport->port.membase + UCR1);
1483                 temp &= ~UCR1_TDMAEN;
1484                 writel(temp, sport->port.membase + UCR1);
1485                 sport->dma_is_txing = false;
1486         }
1487
1488         /*
1489          * According to the Reference Manual description of the UART SRST bit:
1490          * "Reset the transmit and receive state machines,
1491          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1492          * and UTS[6-3]". As we don't need to restore the old values from
1493          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1494          */
1495         ubir = readl(sport->port.membase + UBIR);
1496         ubmr = readl(sport->port.membase + UBMR);
1497         uts = readl(sport->port.membase + IMX21_UTS);
1498
1499         temp = readl(sport->port.membase + UCR2);
1500         temp &= ~UCR2_SRST;
1501         writel(temp, sport->port.membase + UCR2);
1502
1503         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1504                 udelay(1);
1505
1506         /* Restore the registers */
1507         writel(ubir, sport->port.membase + UBIR);
1508         writel(ubmr, sport->port.membase + UBMR);
1509         writel(uts, sport->port.membase + IMX21_UTS);
1510 }
1511
1512 static void
1513 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1514                    struct ktermios *old)
1515 {
1516         struct imx_port *sport = (struct imx_port *)port;
1517         unsigned long flags;
1518         unsigned long ucr2, old_ucr1, old_ucr2;
1519         unsigned int baud, quot;
1520         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1521         unsigned long div, ufcr;
1522         unsigned long num, denom;
1523         uint64_t tdiv64;
1524
1525         /*
1526          * We only support CS7 and CS8.
1527          */
1528         while ((termios->c_cflag & CSIZE) != CS7 &&
1529                (termios->c_cflag & CSIZE) != CS8) {
1530                 termios->c_cflag &= ~CSIZE;
1531                 termios->c_cflag |= old_csize;
1532                 old_csize = CS8;
1533         }
1534
1535         if ((termios->c_cflag & CSIZE) == CS8)
1536                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1537         else
1538                 ucr2 = UCR2_SRST | UCR2_IRTS;
1539
1540         if (termios->c_cflag & CRTSCTS) {
1541                 if (sport->have_rtscts) {
1542                         ucr2 &= ~UCR2_IRTS;
1543
1544                         if (port->rs485.flags & SER_RS485_ENABLED) {
1545                                 /*
1546                                  * RTS is mandatory for rs485 operation, so keep
1547                                  * it under manual control and keep transmitter
1548                                  * disabled.
1549                                  */
1550                                 if (port->rs485.flags &
1551                                     SER_RS485_RTS_AFTER_SEND)
1552                                         imx_port_rts_active(sport, &ucr2);
1553                                 else
1554                                         imx_port_rts_inactive(sport, &ucr2);
1555                         } else {
1556                                 imx_port_rts_auto(sport, &ucr2);
1557                         }
1558                 } else {
1559                         termios->c_cflag &= ~CRTSCTS;
1560                 }
1561         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1562                 /* disable transmitter */
1563                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1564                         imx_port_rts_active(sport, &ucr2);
1565                 else
1566                         imx_port_rts_inactive(sport, &ucr2);
1567         }
1568
1569
1570         if (termios->c_cflag & CSTOPB)
1571                 ucr2 |= UCR2_STPB;
1572         if (termios->c_cflag & PARENB) {
1573                 ucr2 |= UCR2_PREN;
1574                 if (termios->c_cflag & PARODD)
1575                         ucr2 |= UCR2_PROE;
1576         }
1577
1578         del_timer_sync(&sport->timer);
1579
1580         /*
1581          * Ask the core to calculate the divisor for us.
1582          */
1583         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1584         quot = uart_get_divisor(port, baud);
1585
1586         spin_lock_irqsave(&sport->port.lock, flags);
1587
1588         sport->port.read_status_mask = 0;
1589         if (termios->c_iflag & INPCK)
1590                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1591         if (termios->c_iflag & (BRKINT | PARMRK))
1592                 sport->port.read_status_mask |= URXD_BRK;
1593
1594         /*
1595          * Characters to ignore
1596          */
1597         sport->port.ignore_status_mask = 0;
1598         if (termios->c_iflag & IGNPAR)
1599                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1600         if (termios->c_iflag & IGNBRK) {
1601                 sport->port.ignore_status_mask |= URXD_BRK;
1602                 /*
1603                  * If we're ignoring parity and break indicators,
1604                  * ignore overruns too (for real raw support).
1605                  */
1606                 if (termios->c_iflag & IGNPAR)
1607                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1608         }
1609
1610         if ((termios->c_cflag & CREAD) == 0)
1611                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1612
1613         /*
1614          * Update the per-port timeout.
1615          */
1616         uart_update_timeout(port, termios->c_cflag, baud);
1617
1618         /*
1619          * disable interrupts and drain transmitter
1620          */
1621         old_ucr1 = readl(sport->port.membase + UCR1);
1622         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1623                         sport->port.membase + UCR1);
1624
1625         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1626                 barrier();
1627
1628         /* then, disable everything */
1629         old_ucr2 = readl(sport->port.membase + UCR2);
1630         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1631                         sport->port.membase + UCR2);
1632         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1633
1634         /* custom-baudrate handling */
1635         div = sport->port.uartclk / (baud * 16);
1636         if (baud == 38400 && quot != div)
1637                 baud = sport->port.uartclk / (quot * 16);
1638
1639         div = sport->port.uartclk / (baud * 16);
1640         if (div > 7)
1641                 div = 7;
1642         if (!div)
1643                 div = 1;
1644
1645         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1646                 1 << 16, 1 << 16, &num, &denom);
1647
1648         tdiv64 = sport->port.uartclk;
1649         tdiv64 *= num;
1650         do_div(tdiv64, denom * 16 * div);
1651         tty_termios_encode_baud_rate(termios,
1652                                 (speed_t)tdiv64, (speed_t)tdiv64);
1653
1654         num -= 1;
1655         denom -= 1;
1656
1657         ufcr = readl(sport->port.membase + UFCR);
1658         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1659         writel(ufcr, sport->port.membase + UFCR);
1660
1661         writel(num, sport->port.membase + UBIR);
1662         writel(denom, sport->port.membase + UBMR);
1663
1664         if (!is_imx1_uart(sport))
1665                 writel(sport->port.uartclk / div / 1000,
1666                                 sport->port.membase + IMX21_ONEMS);
1667
1668         writel(old_ucr1, sport->port.membase + UCR1);
1669
1670         /* set the parity, stop bits and data size */
1671         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1672
1673         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1674                 imx_enable_ms(&sport->port);
1675
1676         spin_unlock_irqrestore(&sport->port.lock, flags);
1677 }
1678
1679 static const char *imx_type(struct uart_port *port)
1680 {
1681         struct imx_port *sport = (struct imx_port *)port;
1682
1683         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1684 }
1685
1686 /*
1687  * Configure/autoconfigure the port.
1688  */
1689 static void imx_config_port(struct uart_port *port, int flags)
1690 {
1691         struct imx_port *sport = (struct imx_port *)port;
1692
1693         if (flags & UART_CONFIG_TYPE)
1694                 sport->port.type = PORT_IMX;
1695 }
1696
1697 /*
1698  * Verify the new serial_struct (for TIOCSSERIAL).
1699  * The only change we allow are to the flags and type, and
1700  * even then only between PORT_IMX and PORT_UNKNOWN
1701  */
1702 static int
1703 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1704 {
1705         struct imx_port *sport = (struct imx_port *)port;
1706         int ret = 0;
1707
1708         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1709                 ret = -EINVAL;
1710         if (sport->port.irq != ser->irq)
1711                 ret = -EINVAL;
1712         if (ser->io_type != UPIO_MEM)
1713                 ret = -EINVAL;
1714         if (sport->port.uartclk / 16 != ser->baud_base)
1715                 ret = -EINVAL;
1716         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1717                 ret = -EINVAL;
1718         if (sport->port.iobase != ser->port)
1719                 ret = -EINVAL;
1720         if (ser->hub6 != 0)
1721                 ret = -EINVAL;
1722         return ret;
1723 }
1724
1725 #if defined(CONFIG_CONSOLE_POLL)
1726
1727 static int imx_poll_init(struct uart_port *port)
1728 {
1729         struct imx_port *sport = (struct imx_port *)port;
1730         unsigned long flags;
1731         unsigned long ucr1, ucr2;
1732         int retval;
1733
1734         retval = clk_prepare_enable(sport->clk_ipg);
1735         if (retval)
1736                 return retval;
1737         retval = clk_prepare_enable(sport->clk_per);
1738         if (retval)
1739                 clk_disable_unprepare(sport->clk_ipg);
1740
1741         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1742
1743         spin_lock_irqsave(&sport->port.lock, flags);
1744
1745         /*
1746          * Be careful about the order of enabling bits here. First enable the
1747          * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1748          * This prevents that a character that already sits in the RX fifo is
1749          * triggering an irq but the try to fetch it from there results in an
1750          * exception because UARTEN or RXEN is still off.
1751          */
1752         ucr1 = readl(port->membase + UCR1);
1753         ucr2 = readl(port->membase + UCR2);
1754
1755         if (is_imx1_uart(sport))
1756                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1757
1758         ucr1 |= UCR1_UARTEN;
1759         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1760
1761         ucr2 |= UCR2_RXEN;
1762
1763         writel(ucr1, sport->port.membase + UCR1);
1764         writel(ucr2, sport->port.membase + UCR2);
1765
1766         /* now enable irqs */
1767         writel(ucr1 | UCR1_RRDYEN, sport->port.membase + UCR1);
1768
1769         spin_unlock_irqrestore(&sport->port.lock, flags);
1770
1771         return 0;
1772 }
1773
1774 static int imx_poll_get_char(struct uart_port *port)
1775 {
1776         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1777                 return NO_POLL_CHAR;
1778
1779         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1780 }
1781
1782 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1783 {
1784         unsigned int status;
1785
1786         /* drain */
1787         do {
1788                 status = readl_relaxed(port->membase + USR1);
1789         } while (~status & USR1_TRDY);
1790
1791         /* write */
1792         writel_relaxed(c, port->membase + URTX0);
1793
1794         /* flush */
1795         do {
1796                 status = readl_relaxed(port->membase + USR2);
1797         } while (~status & USR2_TXDC);
1798 }
1799 #endif
1800
1801 static int imx_rs485_config(struct uart_port *port,
1802                             struct serial_rs485 *rs485conf)
1803 {
1804         struct imx_port *sport = (struct imx_port *)port;
1805         unsigned long temp;
1806
1807         /* unimplemented */
1808         rs485conf->delay_rts_before_send = 0;
1809         rs485conf->delay_rts_after_send = 0;
1810
1811         /* RTS is required to control the transmitter */
1812         if (!sport->have_rtscts && !sport->have_rtsgpio)
1813                 rs485conf->flags &= ~SER_RS485_ENABLED;
1814
1815         if (rs485conf->flags & SER_RS485_ENABLED) {
1816                 /* disable transmitter */
1817                 temp = readl(sport->port.membase + UCR2);
1818                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1819                         imx_port_rts_active(sport, &temp);
1820                 else
1821                         imx_port_rts_inactive(sport, &temp);
1822                 writel(temp, sport->port.membase + UCR2);
1823         }
1824
1825         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1826         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1827             rs485conf->flags & SER_RS485_RX_DURING_TX)
1828                 imx_start_rx(port);
1829
1830         port->rs485 = *rs485conf;
1831
1832         return 0;
1833 }
1834
1835 static const struct uart_ops imx_pops = {
1836         .tx_empty       = imx_tx_empty,
1837         .set_mctrl      = imx_set_mctrl,
1838         .get_mctrl      = imx_get_mctrl,
1839         .stop_tx        = imx_stop_tx,
1840         .start_tx       = imx_start_tx,
1841         .stop_rx        = imx_stop_rx,
1842         .enable_ms      = imx_enable_ms,
1843         .break_ctl      = imx_break_ctl,
1844         .startup        = imx_startup,
1845         .shutdown       = imx_shutdown,
1846         .flush_buffer   = imx_flush_buffer,
1847         .set_termios    = imx_set_termios,
1848         .type           = imx_type,
1849         .config_port    = imx_config_port,
1850         .verify_port    = imx_verify_port,
1851 #if defined(CONFIG_CONSOLE_POLL)
1852         .poll_init      = imx_poll_init,
1853         .poll_get_char  = imx_poll_get_char,
1854         .poll_put_char  = imx_poll_put_char,
1855 #endif
1856 };
1857
1858 static struct imx_port *imx_ports[UART_NR];
1859
1860 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1861 static void imx_console_putchar(struct uart_port *port, int ch)
1862 {
1863         struct imx_port *sport = (struct imx_port *)port;
1864
1865         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1866                 barrier();
1867
1868         writel(ch, sport->port.membase + URTX0);
1869 }
1870
1871 /*
1872  * Interrupts are disabled on entering
1873  */
1874 static void
1875 imx_console_write(struct console *co, const char *s, unsigned int count)
1876 {
1877         struct imx_port *sport = imx_ports[co->index];
1878         struct imx_port_ucrs old_ucr;
1879         unsigned int ucr1;
1880         unsigned long flags = 0;
1881         int locked = 1;
1882
1883         if (sport->port.sysrq)
1884                 locked = 0;
1885         else if (oops_in_progress)
1886                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1887         else
1888                 spin_lock_irqsave(&sport->port.lock, flags);
1889
1890         /*
1891          *      First, save UCR1/2/3 and then disable interrupts
1892          */
1893         imx_port_ucrs_save(&sport->port, &old_ucr);
1894         ucr1 = old_ucr.ucr1;
1895
1896         if (is_imx1_uart(sport))
1897                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1898         ucr1 |= UCR1_UARTEN;
1899         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1900
1901         writel(ucr1, sport->port.membase + UCR1);
1902
1903         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1904
1905         uart_console_write(&sport->port, s, count, imx_console_putchar);
1906
1907         /*
1908          *      Finally, wait for transmitter to become empty
1909          *      and restore UCR1/2/3
1910          */
1911         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1912
1913         imx_port_ucrs_restore(&sport->port, &old_ucr);
1914
1915         if (locked)
1916                 spin_unlock_irqrestore(&sport->port.lock, flags);
1917 }
1918
1919 /*
1920  * If the port was already initialised (eg, by a boot loader),
1921  * try to determine the current setup.
1922  */
1923 static void __init
1924 imx_console_get_options(struct imx_port *sport, int *baud,
1925                            int *parity, int *bits)
1926 {
1927
1928         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1929                 /* ok, the port was enabled */
1930                 unsigned int ucr2, ubir, ubmr, uartclk;
1931                 unsigned int baud_raw;
1932                 unsigned int ucfr_rfdiv;
1933
1934                 ucr2 = readl(sport->port.membase + UCR2);
1935
1936                 *parity = 'n';
1937                 if (ucr2 & UCR2_PREN) {
1938                         if (ucr2 & UCR2_PROE)
1939                                 *parity = 'o';
1940                         else
1941                                 *parity = 'e';
1942                 }
1943
1944                 if (ucr2 & UCR2_WS)
1945                         *bits = 8;
1946                 else
1947                         *bits = 7;
1948
1949                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1950                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1951
1952                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1953                 if (ucfr_rfdiv == 6)
1954                         ucfr_rfdiv = 7;
1955                 else
1956                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1957
1958                 uartclk = clk_get_rate(sport->clk_per);
1959                 uartclk /= ucfr_rfdiv;
1960
1961                 {       /*
1962                          * The next code provides exact computation of
1963                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1964                          * without need of float support or long long division,
1965                          * which would be required to prevent 32bit arithmetic overflow
1966                          */
1967                         unsigned int mul = ubir + 1;
1968                         unsigned int div = 16 * (ubmr + 1);
1969                         unsigned int rem = uartclk % div;
1970
1971                         baud_raw = (uartclk / div) * mul;
1972                         baud_raw += (rem * mul + div / 2) / div;
1973                         *baud = (baud_raw + 50) / 100 * 100;
1974                 }
1975
1976                 if (*baud != baud_raw)
1977                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1978                                 baud_raw, *baud);
1979         }
1980 }
1981
1982 static int __init
1983 imx_console_setup(struct console *co, char *options)
1984 {
1985         struct imx_port *sport;
1986         int baud = 9600;
1987         int bits = 8;
1988         int parity = 'n';
1989         int flow = 'n';
1990         int retval;
1991
1992         /*
1993          * Check whether an invalid uart number has been specified, and
1994          * if so, search for the first available port that does have
1995          * console support.
1996          */
1997         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1998                 co->index = 0;
1999         sport = imx_ports[co->index];
2000         if (sport == NULL)
2001                 return -ENODEV;
2002
2003         /* For setting the registers, we only need to enable the ipg clock. */
2004         retval = clk_prepare_enable(sport->clk_ipg);
2005         if (retval)
2006                 goto error_console;
2007
2008         if (options)
2009                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2010         else
2011                 imx_console_get_options(sport, &baud, &parity, &bits);
2012
2013         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2014
2015         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2016
2017         if (retval) {
2018                 clk_disable_unprepare(sport->clk_ipg);
2019                 goto error_console;
2020         }
2021
2022         retval = clk_prepare_enable(sport->clk_per);
2023         if (retval)
2024                 clk_disable_unprepare(sport->clk_ipg);
2025
2026 error_console:
2027         return retval;
2028 }
2029
2030 static struct uart_driver imx_reg;
2031 static struct console imx_console = {
2032         .name           = DEV_NAME,
2033         .write          = imx_console_write,
2034         .device         = uart_console_device,
2035         .setup          = imx_console_setup,
2036         .flags          = CON_PRINTBUFFER,
2037         .index          = -1,
2038         .data           = &imx_reg,
2039 };
2040
2041 #define IMX_CONSOLE     &imx_console
2042
2043 #ifdef CONFIG_OF
2044 static void imx_console_early_putchar(struct uart_port *port, int ch)
2045 {
2046         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
2047                 cpu_relax();
2048
2049         writel_relaxed(ch, port->membase + URTX0);
2050 }
2051
2052 static void imx_console_early_write(struct console *con, const char *s,
2053                                     unsigned count)
2054 {
2055         struct earlycon_device *dev = con->data;
2056
2057         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
2058 }
2059
2060 static int __init
2061 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
2062 {
2063         if (!dev->port.membase)
2064                 return -ENODEV;
2065
2066         dev->con->write = imx_console_early_write;
2067
2068         return 0;
2069 }
2070 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
2071 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
2072 #endif
2073
2074 #else
2075 #define IMX_CONSOLE     NULL
2076 #endif
2077
2078 static struct uart_driver imx_reg = {
2079         .owner          = THIS_MODULE,
2080         .driver_name    = DRIVER_NAME,
2081         .dev_name       = DEV_NAME,
2082         .major          = SERIAL_IMX_MAJOR,
2083         .minor          = MINOR_START,
2084         .nr             = ARRAY_SIZE(imx_ports),
2085         .cons           = IMX_CONSOLE,
2086 };
2087
2088 #ifdef CONFIG_OF
2089 /*
2090  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2091  * could successfully get all information from dt or a negative errno.
2092  */
2093 static int serial_imx_probe_dt(struct imx_port *sport,
2094                 struct platform_device *pdev)
2095 {
2096         struct device_node *np = pdev->dev.of_node;
2097         int ret;
2098
2099         sport->devdata = of_device_get_match_data(&pdev->dev);
2100         if (!sport->devdata)
2101                 /* no device tree device */
2102                 return 1;
2103
2104         ret = of_alias_get_id(np, "serial");
2105         if (ret < 0) {
2106                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2107                 return ret;
2108         }
2109         sport->port.line = ret;
2110
2111         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2112             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2113                 sport->have_rtscts = 1;
2114
2115         if (of_get_property(np, "fsl,dte-mode", NULL))
2116                 sport->dte_mode = 1;
2117
2118         if (of_get_property(np, "rts-gpios", NULL))
2119                 sport->have_rtsgpio = 1;
2120
2121         return 0;
2122 }
2123 #else
2124 static inline int serial_imx_probe_dt(struct imx_port *sport,
2125                 struct platform_device *pdev)
2126 {
2127         return 1;
2128 }
2129 #endif
2130
2131 static void serial_imx_probe_pdata(struct imx_port *sport,
2132                 struct platform_device *pdev)
2133 {
2134         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2135
2136         sport->port.line = pdev->id;
2137         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2138
2139         if (!pdata)
2140                 return;
2141
2142         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2143                 sport->have_rtscts = 1;
2144 }
2145
2146 static int serial_imx_probe(struct platform_device *pdev)
2147 {
2148         struct imx_port *sport;
2149         void __iomem *base;
2150         int ret = 0, reg;
2151         struct resource *res;
2152         int txirq, rxirq, rtsirq;
2153
2154         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2155         if (!sport)
2156                 return -ENOMEM;
2157
2158         ret = serial_imx_probe_dt(sport, pdev);
2159         if (ret > 0)
2160                 serial_imx_probe_pdata(sport, pdev);
2161         else if (ret < 0)
2162                 return ret;
2163
2164         if (sport->port.line >= ARRAY_SIZE(imx_ports)) {
2165                 dev_err(&pdev->dev, "serial%d out of range\n",
2166                         sport->port.line);
2167                 return -EINVAL;
2168         }
2169
2170         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2171         base = devm_ioremap_resource(&pdev->dev, res);
2172         if (IS_ERR(base))
2173                 return PTR_ERR(base);
2174
2175         rxirq = platform_get_irq(pdev, 0);
2176         txirq = platform_get_irq(pdev, 1);
2177         rtsirq = platform_get_irq(pdev, 2);
2178
2179         sport->port.dev = &pdev->dev;
2180         sport->port.mapbase = res->start;
2181         sport->port.membase = base;
2182         sport->port.type = PORT_IMX,
2183         sport->port.iotype = UPIO_MEM;
2184         sport->port.irq = rxirq;
2185         sport->port.fifosize = 32;
2186         sport->port.ops = &imx_pops;
2187         sport->port.rs485_config = imx_rs485_config;
2188         sport->port.rs485.flags =
2189                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2190         sport->port.flags = UPF_BOOT_AUTOCONF;
2191         init_timer(&sport->timer);
2192         sport->timer.function = imx_timeout;
2193         sport->timer.data     = (unsigned long)sport;
2194
2195         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2196         if (IS_ERR(sport->gpios))
2197                 return PTR_ERR(sport->gpios);
2198
2199         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2200         if (IS_ERR(sport->clk_ipg)) {
2201                 ret = PTR_ERR(sport->clk_ipg);
2202                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2203                 return ret;
2204         }
2205
2206         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2207         if (IS_ERR(sport->clk_per)) {
2208                 ret = PTR_ERR(sport->clk_per);
2209                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2210                 return ret;
2211         }
2212
2213         sport->port.uartclk = clk_get_rate(sport->clk_per);
2214
2215         /* For register access, we only need to enable the ipg clock. */
2216         ret = clk_prepare_enable(sport->clk_ipg);
2217         if (ret) {
2218                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2219                 return ret;
2220         }
2221
2222         /* Disable interrupts before requesting them */
2223         reg = readl_relaxed(sport->port.membase + UCR1);
2224         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2225                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2226         writel_relaxed(reg, sport->port.membase + UCR1);
2227
2228         if (!is_imx1_uart(sport) && sport->dte_mode) {
2229                 /*
2230                  * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2231                  * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2232                  * and DCD (when they are outputs) or enables the respective
2233                  * irqs. So set this bit early, i.e. before requesting irqs.
2234                  */
2235                 reg = readl(sport->port.membase + UFCR);
2236                 if (!(reg & UFCR_DCEDTE))
2237                         writel(reg | UFCR_DCEDTE, sport->port.membase + UFCR);
2238
2239                 /*
2240                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2241                  * enabled later because they cannot be cleared
2242                  * (confirmed on i.MX25) which makes them unusable.
2243                  */
2244                 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2245                        sport->port.membase + UCR3);
2246
2247         } else {
2248                 unsigned long ucr3 = UCR3_DSR;
2249
2250                 reg = readl(sport->port.membase + UFCR);
2251                 if (reg & UFCR_DCEDTE)
2252                         writel(reg & ~UFCR_DCEDTE, sport->port.membase + UFCR);
2253
2254                 if (!is_imx1_uart(sport))
2255                         ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2256                 writel(ucr3, sport->port.membase + UCR3);
2257         }
2258
2259         clk_disable_unprepare(sport->clk_ipg);
2260
2261         /*
2262          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2263          * chips only have one interrupt.
2264          */
2265         if (txirq > 0) {
2266                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2267                                        dev_name(&pdev->dev), sport);
2268                 if (ret) {
2269                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2270                                 ret);
2271                         return ret;
2272                 }
2273
2274                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2275                                        dev_name(&pdev->dev), sport);
2276                 if (ret) {
2277                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2278                                 ret);
2279                         return ret;
2280                 }
2281
2282                 ret = devm_request_irq(&pdev->dev, rtsirq, imx_rtsint, 0,
2283                                        dev_name(&pdev->dev), sport);
2284                 if (ret) {
2285                         dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2286                                 ret);
2287                         return ret;
2288                 }
2289         } else {
2290                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2291                                        dev_name(&pdev->dev), sport);
2292                 if (ret) {
2293                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2294                         return ret;
2295                 }
2296         }
2297
2298         imx_ports[sport->port.line] = sport;
2299
2300         platform_set_drvdata(pdev, sport);
2301
2302         return uart_add_one_port(&imx_reg, &sport->port);
2303 }
2304
2305 static int serial_imx_remove(struct platform_device *pdev)
2306 {
2307         struct imx_port *sport = platform_get_drvdata(pdev);
2308
2309         return uart_remove_one_port(&imx_reg, &sport->port);
2310 }
2311
2312 static void serial_imx_restore_context(struct imx_port *sport)
2313 {
2314         if (!sport->context_saved)
2315                 return;
2316
2317         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2318         writel(sport->saved_reg[5], sport->port.membase + UESC);
2319         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2320         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2321         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2322         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2323         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2324         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2325         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2326         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2327         sport->context_saved = false;
2328 }
2329
2330 static void serial_imx_save_context(struct imx_port *sport)
2331 {
2332         /* Save necessary regs */
2333         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2334         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2335         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2336         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2337         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2338         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2339         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2340         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2341         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2342         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2343         sport->context_saved = true;
2344 }
2345
2346 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2347 {
2348         unsigned int val;
2349
2350         val = readl(sport->port.membase + UCR3);
2351         if (on)
2352                 val |= UCR3_AWAKEN;
2353         else
2354                 val &= ~UCR3_AWAKEN;
2355         writel(val, sport->port.membase + UCR3);
2356
2357         if (sport->have_rtscts) {
2358                 val = readl(sport->port.membase + UCR1);
2359                 if (on)
2360                         val |= UCR1_RTSDEN;
2361                 else
2362                         val &= ~UCR1_RTSDEN;
2363                 writel(val, sport->port.membase + UCR1);
2364         }
2365 }
2366
2367 static int imx_serial_port_suspend_noirq(struct device *dev)
2368 {
2369         struct platform_device *pdev = to_platform_device(dev);
2370         struct imx_port *sport = platform_get_drvdata(pdev);
2371         int ret;
2372
2373         ret = clk_enable(sport->clk_ipg);
2374         if (ret)
2375                 return ret;
2376
2377         serial_imx_save_context(sport);
2378
2379         clk_disable(sport->clk_ipg);
2380
2381         return 0;
2382 }
2383
2384 static int imx_serial_port_resume_noirq(struct device *dev)
2385 {
2386         struct platform_device *pdev = to_platform_device(dev);
2387         struct imx_port *sport = platform_get_drvdata(pdev);
2388         int ret;
2389
2390         ret = clk_enable(sport->clk_ipg);
2391         if (ret)
2392                 return ret;
2393
2394         serial_imx_restore_context(sport);
2395
2396         clk_disable(sport->clk_ipg);
2397
2398         return 0;
2399 }
2400
2401 static int imx_serial_port_suspend(struct device *dev)
2402 {
2403         struct platform_device *pdev = to_platform_device(dev);
2404         struct imx_port *sport = platform_get_drvdata(pdev);
2405
2406         /* enable wakeup from i.MX UART */
2407         serial_imx_enable_wakeup(sport, true);
2408
2409         uart_suspend_port(&imx_reg, &sport->port);
2410         disable_irq(sport->port.irq);
2411
2412         /* Needed to enable clock in suspend_noirq */
2413         return clk_prepare(sport->clk_ipg);
2414 }
2415
2416 static int imx_serial_port_resume(struct device *dev)
2417 {
2418         struct platform_device *pdev = to_platform_device(dev);
2419         struct imx_port *sport = platform_get_drvdata(pdev);
2420
2421         /* disable wakeup from i.MX UART */
2422         serial_imx_enable_wakeup(sport, false);
2423
2424         uart_resume_port(&imx_reg, &sport->port);
2425         enable_irq(sport->port.irq);
2426
2427         clk_unprepare(sport->clk_ipg);
2428
2429         return 0;
2430 }
2431
2432 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2433         .suspend_noirq = imx_serial_port_suspend_noirq,
2434         .resume_noirq = imx_serial_port_resume_noirq,
2435         .suspend = imx_serial_port_suspend,
2436         .resume = imx_serial_port_resume,
2437 };
2438
2439 static struct platform_driver serial_imx_driver = {
2440         .probe          = serial_imx_probe,
2441         .remove         = serial_imx_remove,
2442
2443         .id_table       = imx_uart_devtype,
2444         .driver         = {
2445                 .name   = "imx-uart",
2446                 .of_match_table = imx_uart_dt_ids,
2447                 .pm     = &imx_serial_port_pm_ops,
2448         },
2449 };
2450
2451 static int __init imx_serial_init(void)
2452 {
2453         int ret = uart_register_driver(&imx_reg);
2454
2455         if (ret)
2456                 return ret;
2457
2458         ret = platform_driver_register(&serial_imx_driver);
2459         if (ret != 0)
2460                 uart_unregister_driver(&imx_reg);
2461
2462         return ret;
2463 }
2464
2465 static void __exit imx_serial_exit(void)
2466 {
2467         platform_driver_unregister(&serial_imx_driver);
2468         uart_unregister_driver(&imx_reg);
2469 }
2470
2471 module_init(imx_serial_init);
2472 module_exit(imx_serial_exit);
2473
2474 MODULE_AUTHOR("Sascha Hauer");
2475 MODULE_DESCRIPTION("IMX generic serial port driver");
2476 MODULE_LICENSE("GPL");
2477 MODULE_ALIAS("platform:imx-uart");