GNU Linux-libre 4.9.309-gnu1
[releases.git] / drivers / tty / serial / jsm / jsm.h
1 /************************************************************************
2  * Copyright 2003 Digi International (www.digi.com)
3  *
4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14  * PURPOSE.  See the GNU General Public License for more details.
15  *
16  * Contact Information:
17  * Scott H Kilau <Scott_Kilau@digi.com>
18  * Wendy Xiong   <wendyx@us.ibm.com>
19  *
20  ***********************************************************************/
21
22 #ifndef __JSM_DRIVER_H
23 #define __JSM_DRIVER_H
24
25 #include <linux/kernel.h>
26 #include <linux/types.h>        /* To pick up the varions Linux types */
27 #include <linux/tty.h>
28 #include <linux/serial_core.h>
29 #include <linux/device.h>
30
31 /*
32  * Debugging levels can be set using debug insmod variable
33  * They can also be compiled out completely.
34  */
35 enum {
36         DBG_INIT        = 0x01,
37         DBG_BASIC       = 0x02,
38         DBG_CORE        = 0x04,
39         DBG_OPEN        = 0x08,
40         DBG_CLOSE       = 0x10,
41         DBG_READ        = 0x20,
42         DBG_WRITE       = 0x40,
43         DBG_IOCTL       = 0x80,
44         DBG_PROC        = 0x100,
45         DBG_PARAM       = 0x200,
46         DBG_PSCAN       = 0x400,
47         DBG_EVENT       = 0x800,
48         DBG_DRAIN       = 0x1000,
49         DBG_MSIGS       = 0x2000,
50         DBG_MGMT        = 0x4000,
51         DBG_INTR        = 0x8000,
52         DBG_CARR        = 0x10000,
53 };
54
55 #define jsm_dbg(nlevel, pdev, fmt, ...)                         \
56 do {                                                            \
57         if (DBG_##nlevel & jsm_debug)                           \
58                 dev_dbg(pdev->dev, fmt, ##__VA_ARGS__);         \
59 } while (0)
60
61 #define MAXLINES        256
62 #define MAXPORTS        8
63 #define MAX_STOPS_SENT  5
64
65 /* Board ids */
66 #define PCI_DEVICE_ID_CLASSIC_4         0x0028
67 #define PCI_DEVICE_ID_CLASSIC_8         0x0029
68 #define PCI_DEVICE_ID_CLASSIC_4_422     0x00D0
69 #define PCI_DEVICE_ID_CLASSIC_8_422     0x00D1
70 #define PCI_DEVICE_ID_NEO_4             0x00B0
71 #define PCI_DEVICE_ID_NEO_1_422         0x00CC
72 #define PCI_DEVICE_ID_NEO_1_422_485     0x00CD
73 #define PCI_DEVICE_ID_NEO_2_422_485     0x00CE
74 #define PCIE_DEVICE_ID_NEO_8            0x00F0
75 #define PCIE_DEVICE_ID_NEO_4            0x00F1
76 #define PCIE_DEVICE_ID_NEO_4RJ45        0x00F2
77 #define PCIE_DEVICE_ID_NEO_8RJ45        0x00F3
78
79 /* Board type definitions */
80
81 #define T_NEO           0000
82 #define T_CLASSIC       0001
83 #define T_PCIBUS        0400
84
85 /* Board State Definitions */
86
87 #define BD_RUNNING      0x0
88 #define BD_REASON       0x7f
89 #define BD_NOTFOUND     0x1
90 #define BD_NOIOPORT     0x2
91 #define BD_NOMEM        0x3
92 #define BD_NOBIOS       0x4
93 #define BD_NOFEP        0x5
94 #define BD_FAILED       0x6
95 #define BD_ALLOCATED    0x7
96 #define BD_TRIBOOT      0x8
97 #define BD_BADKME       0x80
98
99
100 /* 4 extra for alignment play space */
101 #define WRITEBUFLEN     ((4096) + 4)
102
103 #define JSM_VERSION     "jsm: 1.2-1-INKERNEL"
104 #define JSM_PARTNUM     "40002438_A-INKERNEL"
105
106 struct jsm_board;
107 struct jsm_channel;
108
109 /************************************************************************
110  * Per board operations structure                                       *
111  ************************************************************************/
112 struct board_ops {
113         irq_handler_t intr;
114         void (*uart_init)(struct jsm_channel *ch);
115         void (*uart_off)(struct jsm_channel *ch);
116         void (*param)(struct jsm_channel *ch);
117         void (*assert_modem_signals)(struct jsm_channel *ch);
118         void (*flush_uart_write)(struct jsm_channel *ch);
119         void (*flush_uart_read)(struct jsm_channel *ch);
120         void (*disable_receiver)(struct jsm_channel *ch);
121         void (*enable_receiver)(struct jsm_channel *ch);
122         void (*send_break)(struct jsm_channel *ch);
123         void (*clear_break)(struct jsm_channel *ch);
124         void (*send_start_character)(struct jsm_channel *ch);
125         void (*send_stop_character)(struct jsm_channel *ch);
126         void (*copy_data_from_queue_to_uart)(struct jsm_channel *ch);
127         u32 (*get_uart_bytes_left)(struct jsm_channel *ch);
128         void (*send_immediate_char)(struct jsm_channel *ch, unsigned char);
129 };
130
131
132 /*
133  *      Per-board information
134  */
135 struct jsm_board
136 {
137         int             boardnum;       /* Board number: 0-32 */
138
139         int             type;           /* Type of board */
140         u8              rev;            /* PCI revision ID */
141         struct pci_dev  *pci_dev;
142         u32             maxports;       /* MAX ports this board can handle */
143
144         spinlock_t      bd_intr_lock;   /* Used to protect the poller tasklet and
145                                          * the interrupt routine from each other.
146                                          */
147
148         u32             nasync;         /* Number of ports on card */
149
150         u32             irq;            /* Interrupt request number */
151
152         u64             membase;        /* Start of base memory of the card */
153         u64             membase_end;    /* End of base memory of the card */
154
155         u8      __iomem *re_map_membase;/* Remapped memory of the card */
156
157         u64             iobase;         /* Start of io base of the card */
158         u64             iobase_end;     /* End of io base of the card */
159
160         u32             bd_uart_offset; /* Space between each UART */
161
162         struct jsm_channel *channels[MAXPORTS]; /* array of pointers to our channels. */
163
164         u32             bd_dividend;    /* Board/UARTs specific dividend */
165
166         struct board_ops *bd_ops;
167
168         struct list_head jsm_board_entry;
169 };
170
171 /************************************************************************
172  * Device flag definitions for ch_flags.
173  ************************************************************************/
174 #define CH_PRON         0x0001          /* Printer on string            */
175 #define CH_STOP         0x0002          /* Output is stopped            */
176 #define CH_STOPI        0x0004          /* Input is stopped             */
177 #define CH_CD           0x0008          /* Carrier is present           */
178 #define CH_FCAR         0x0010          /* Carrier forced on            */
179 #define CH_HANGUP       0x0020          /* Hangup received              */
180
181 #define CH_RECEIVER_OFF 0x0040          /* Receiver is off              */
182 #define CH_OPENING      0x0080          /* Port in fragile open state   */
183 #define CH_CLOSING      0x0100          /* Port in fragile close state  */
184 #define CH_FIFO_ENABLED 0x0200          /* Port has FIFOs enabled       */
185 #define CH_TX_FIFO_EMPTY 0x0400         /* TX Fifo is completely empty  */
186 #define CH_TX_FIFO_LWM  0x0800          /* TX Fifo is below Low Water   */
187 #define CH_BREAK_SENDING 0x1000         /* Break is being sent          */
188 #define CH_LOOPBACK 0x2000              /* Channel is in lookback mode  */
189 #define CH_BAUD0        0x08000         /* Used for checking B0 transitions */
190
191 /* Our Read/Error queue sizes */
192 #define RQUEUEMASK      0x1FFF          /* 8 K - 1 */
193 #define EQUEUEMASK      0x1FFF          /* 8 K - 1 */
194 #define RQUEUESIZE      (RQUEUEMASK + 1)
195 #define EQUEUESIZE      RQUEUESIZE
196
197
198 /************************************************************************
199  * Channel information structure.
200  ************************************************************************/
201 struct jsm_channel {
202         struct uart_port uart_port;
203         struct jsm_board        *ch_bd;         /* Board structure pointer      */
204
205         spinlock_t      ch_lock;        /* provide for serialization */
206         wait_queue_head_t ch_flags_wait;
207
208         u32             ch_portnum;     /* Port number, 0 offset.       */
209         u32             ch_open_count;  /* open count                   */
210         u32             ch_flags;       /* Channel flags                */
211
212         u64             ch_close_delay; /* How long we should drop RTS/DTR for */
213
214         tcflag_t        ch_c_iflag;     /* channel iflags               */
215         tcflag_t        ch_c_cflag;     /* channel cflags               */
216         tcflag_t        ch_c_oflag;     /* channel oflags               */
217         tcflag_t        ch_c_lflag;     /* channel lflags               */
218         u8              ch_stopc;       /* Stop character               */
219         u8              ch_startc;      /* Start character              */
220
221         u8              ch_mostat;      /* FEP output modem status      */
222         u8              ch_mistat;      /* FEP input modem status       */
223
224         /* Pointers to the "mapped" UART structs */
225         struct neo_uart_struct __iomem *ch_neo_uart; /* NEO card */
226         struct cls_uart_struct __iomem *ch_cls_uart; /* Classic card */
227
228         u8              ch_cached_lsr;  /* Cached value of the LSR register */
229
230         u8              *ch_rqueue;     /* Our read queue buffer - malloc'ed */
231         u16             ch_r_head;      /* Head location of the read queue */
232         u16             ch_r_tail;      /* Tail location of the read queue */
233
234         u8              *ch_equeue;     /* Our error queue buffer - malloc'ed */
235         u16             ch_e_head;      /* Head location of the error queue */
236         u16             ch_e_tail;      /* Tail location of the error queue */
237
238         u64             ch_rxcount;     /* total of data received so far */
239         u64             ch_txcount;     /* total of data transmitted so far */
240
241         u8              ch_r_tlevel;    /* Receive Trigger level */
242         u8              ch_t_tlevel;    /* Transmit Trigger level */
243
244         u8              ch_r_watermark; /* Receive Watermark */
245
246
247         u32             ch_stops_sent;  /* How many times I have sent a stop character
248                                          * to try to stop the other guy sending.
249                                          */
250         u64             ch_err_parity;  /* Count of parity errors on channel */
251         u64             ch_err_frame;   /* Count of framing errors on channel */
252         u64             ch_err_break;   /* Count of breaks on channel */
253         u64             ch_err_overrun; /* Count of overruns on channel */
254
255         u64             ch_xon_sends;   /* Count of xons transmitted */
256         u64             ch_xoff_sends;  /* Count of xoffs transmitted */
257 };
258
259 /************************************************************************
260  * Per channel/port Classic UART structures                             *
261  ************************************************************************
262  *              Base Structure Entries Usage Meanings to Host           *
263  *                                                                      *
264  *      W = read write          R = read only                           *
265  *                      U = Unused.                                     *
266  ************************************************************************/
267
268 struct cls_uart_struct {
269         u8 txrx;        /* WR  RHR/THR - Holding Reg */
270         u8 ier;         /* WR  IER - Interrupt Enable Reg */
271         u8 isr_fcr;     /* WR  ISR/FCR - Interrupt Status Reg/Fifo Control Reg*/
272         u8 lcr;         /* WR  LCR - Line Control Reg */
273         u8 mcr;         /* WR  MCR - Modem Control Reg */
274         u8 lsr;         /* WR  LSR - Line Status Reg */
275         u8 msr;         /* WR  MSR - Modem Status Reg */
276         u8 spr;         /* WR  SPR - Scratch Pad Reg */
277 };
278
279 /* Where to read the interrupt register (8bits) */
280 #define UART_CLASSIC_POLL_ADDR_OFFSET   0x40
281
282 #define UART_EXAR654_ENHANCED_REGISTER_SET 0xBF
283
284 #define UART_16654_FCR_TXTRIGGER_8      0x0
285 #define UART_16654_FCR_TXTRIGGER_16     0x10
286 #define UART_16654_FCR_TXTRIGGER_32     0x20
287 #define UART_16654_FCR_TXTRIGGER_56     0x30
288
289 #define UART_16654_FCR_RXTRIGGER_8      0x0
290 #define UART_16654_FCR_RXTRIGGER_16     0x40
291 #define UART_16654_FCR_RXTRIGGER_56     0x80
292 #define UART_16654_FCR_RXTRIGGER_60     0xC0
293
294 #define UART_IIR_CTSRTS                 0x20    /* Received CTS/RTS change of state */
295 #define UART_IIR_RDI_TIMEOUT            0x0C    /* Receiver data TIMEOUT */
296
297 /*
298  * These are the EXTENDED definitions for the Exar 654's Interrupt
299  * Enable Register.
300  */
301 #define UART_EXAR654_EFR_ECB      0x10    /* Enhanced control bit */
302 #define UART_EXAR654_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
303 #define UART_EXAR654_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
304 #define UART_EXAR654_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
305 #define UART_EXAR654_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
306
307 #define UART_EXAR654_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char  */
308 #define UART_EXAR654_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
309
310 #define UART_EXAR654_IER_XOFF     0x20    /* Xoff Interrupt Enable */
311 #define UART_EXAR654_IER_RTSDTR   0x40    /* Output Interrupt Enable */
312 #define UART_EXAR654_IER_CTSDSR   0x80    /* Input Interrupt Enable */
313
314 /************************************************************************
315  * Per channel/port NEO UART structure                                  *
316  ************************************************************************
317  *              Base Structure Entries Usage Meanings to Host           *
318  *                                                                      *
319  *      W = read write          R = read only                           *
320  *                      U = Unused.                                     *
321  ************************************************************************/
322
323 struct neo_uart_struct {
324          u8 txrx;               /* WR   RHR/THR - Holding Reg */
325          u8 ier;                /* WR   IER - Interrupt Enable Reg */
326          u8 isr_fcr;            /* WR   ISR/FCR - Interrupt Status Reg/Fifo Control Reg */
327          u8 lcr;                /* WR   LCR - Line Control Reg */
328          u8 mcr;                /* WR   MCR - Modem Control Reg */
329          u8 lsr;                /* WR   LSR - Line Status Reg */
330          u8 msr;                /* WR   MSR - Modem Status Reg */
331          u8 spr;                /* WR   SPR - Scratch Pad Reg */
332          u8 fctr;               /* WR   FCTR - Feature Control Reg */
333          u8 efr;                /* WR   EFR - Enhanced Function Reg */
334          u8 tfifo;              /* WR   TXCNT/TXTRG - Transmit FIFO Reg */
335          u8 rfifo;              /* WR   RXCNT/RXTRG - Receive FIFO Reg */
336          u8 xoffchar1;  /* WR   XOFF 1 - XOff Character 1 Reg */
337          u8 xoffchar2;  /* WR   XOFF 2 - XOff Character 2 Reg */
338          u8 xonchar1;   /* WR   XON 1 - Xon Character 1 Reg */
339          u8 xonchar2;   /* WR   XON 2 - XOn Character 2 Reg */
340
341          u8 reserved1[0x2ff - 0x200]; /* U      Reserved by Exar */
342          u8 txrxburst[64];      /* RW   64 bytes of RX/TX FIFO Data */
343          u8 reserved2[0x37f - 0x340]; /* U      Reserved by Exar */
344          u8 rxburst_with_errors[64];    /* R    64 bytes of RX FIFO Data + LSR */
345 };
346
347 /* Where to read the extended interrupt register (32bits instead of 8bits) */
348 #define UART_17158_POLL_ADDR_OFFSET     0x80
349
350 /*
351  * These are the redefinitions for the FCTR on the XR17C158, since
352  * Exar made them different than their earlier design. (XR16C854)
353  */
354
355 /* These are only applicable when table D is selected */
356 #define UART_17158_FCTR_RTS_NODELAY     0x00
357 #define UART_17158_FCTR_RTS_4DELAY      0x01
358 #define UART_17158_FCTR_RTS_6DELAY      0x02
359 #define UART_17158_FCTR_RTS_8DELAY      0x03
360 #define UART_17158_FCTR_RTS_12DELAY     0x12
361 #define UART_17158_FCTR_RTS_16DELAY     0x05
362 #define UART_17158_FCTR_RTS_20DELAY     0x13
363 #define UART_17158_FCTR_RTS_24DELAY     0x06
364 #define UART_17158_FCTR_RTS_28DELAY     0x14
365 #define UART_17158_FCTR_RTS_32DELAY     0x07
366 #define UART_17158_FCTR_RTS_36DELAY     0x16
367 #define UART_17158_FCTR_RTS_40DELAY     0x08
368 #define UART_17158_FCTR_RTS_44DELAY     0x09
369 #define UART_17158_FCTR_RTS_48DELAY     0x10
370 #define UART_17158_FCTR_RTS_52DELAY     0x11
371
372 #define UART_17158_FCTR_RTS_IRDA        0x10
373 #define UART_17158_FCTR_RS485           0x20
374 #define UART_17158_FCTR_TRGA            0x00
375 #define UART_17158_FCTR_TRGB            0x40
376 #define UART_17158_FCTR_TRGC            0x80
377 #define UART_17158_FCTR_TRGD            0xC0
378
379 /* 17158 trigger table selects.. */
380 #define UART_17158_FCTR_BIT6            0x40
381 #define UART_17158_FCTR_BIT7            0x80
382
383 /* 17158 TX/RX memmapped buffer offsets */
384 #define UART_17158_RX_FIFOSIZE          64
385 #define UART_17158_TX_FIFOSIZE          64
386
387 /* 17158 Extended IIR's */
388 #define UART_17158_IIR_RDI_TIMEOUT      0x0C    /* Receiver data TIMEOUT */
389 #define UART_17158_IIR_XONXOFF          0x10    /* Received an XON/XOFF char */
390 #define UART_17158_IIR_HWFLOW_STATE_CHANGE 0x20 /* CTS/DSR or RTS/DTR state change */
391 #define UART_17158_IIR_FIFO_ENABLED     0xC0    /* 16550 FIFOs are Enabled */
392
393 /*
394  * These are the extended interrupts that get sent
395  * back to us from the UART's 32bit interrupt register
396  */
397 #define UART_17158_RX_LINE_STATUS       0x1     /* RX Ready */
398 #define UART_17158_RXRDY_TIMEOUT        0x2     /* RX Ready Timeout */
399 #define UART_17158_TXRDY                0x3     /* TX Ready */
400 #define UART_17158_MSR                  0x4     /* Modem State Change */
401 #define UART_17158_TX_AND_FIFO_CLR      0x40    /* Transmitter Holding Reg Empty */
402 #define UART_17158_RX_FIFO_DATA_ERROR   0x80    /* UART detected an RX FIFO Data error */
403
404 /*
405  * These are the EXTENDED definitions for the 17C158's Interrupt
406  * Enable Register.
407  */
408 #define UART_17158_EFR_ECB      0x10    /* Enhanced control bit */
409 #define UART_17158_EFR_IXON     0x2     /* Receiver compares Xon1/Xoff1 */
410 #define UART_17158_EFR_IXOFF    0x8     /* Transmit Xon1/Xoff1 */
411 #define UART_17158_EFR_RTSDTR   0x40    /* Auto RTS/DTR Flow Control Enable */
412 #define UART_17158_EFR_CTSDSR   0x80    /* Auto CTS/DSR Flow COntrol Enable */
413
414 #define UART_17158_XOFF_DETECT  0x1     /* Indicates whether chip saw an incoming XOFF char */
415 #define UART_17158_XON_DETECT   0x2     /* Indicates whether chip saw an incoming XON char */
416
417 #define UART_17158_IER_RSVD1    0x10    /* Reserved by Exar */
418 #define UART_17158_IER_XOFF     0x20    /* Xoff Interrupt Enable */
419 #define UART_17158_IER_RTSDTR   0x40    /* Output Interrupt Enable */
420 #define UART_17158_IER_CTSDSR   0x80    /* Input Interrupt Enable */
421
422 #define PCI_DEVICE_NEO_2DB9_PCI_NAME            "Neo 2 - DB9 Universal PCI"
423 #define PCI_DEVICE_NEO_2DB9PRI_PCI_NAME         "Neo 2 - DB9 Universal PCI - Powered Ring Indicator"
424 #define PCI_DEVICE_NEO_2RJ45_PCI_NAME           "Neo 2 - RJ45 Universal PCI"
425 #define PCI_DEVICE_NEO_2RJ45PRI_PCI_NAME        "Neo 2 - RJ45 Universal PCI - Powered Ring Indicator"
426 #define PCIE_DEVICE_NEO_IBM_PCI_NAME            "Neo 4 - PCI Express - IBM"
427
428 /*
429  * Our Global Variables.
430  */
431 extern struct   uart_driver jsm_uart_driver;
432 extern struct   board_ops jsm_neo_ops;
433 extern struct   board_ops jsm_cls_ops;
434 extern int      jsm_debug;
435
436 /*************************************************************************
437  *
438  * Prototypes for non-static functions used in more than one module
439  *
440  *************************************************************************/
441 int jsm_tty_init(struct jsm_board *);
442 int jsm_uart_port_init(struct jsm_board *);
443 int jsm_remove_uart_port(struct jsm_board *);
444 void jsm_input(struct jsm_channel *ch);
445 void jsm_check_queue_flow_control(struct jsm_channel *ch);
446
447 #endif