GNU Linux-libre 4.9.309-gnu1
[releases.git] / drivers / tty / serial / jsm / jsm_neo.c
1 /************************************************************************
2  * Copyright 2003 Digi International (www.digi.com)
3  *
4  * Copyright (C) 2004 IBM Corporation. All rights reserved.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2, or (at your option)
9  * any later version.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY, EXPRESS OR IMPLIED; without even the
13  * implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
14  * PURPOSE.  See the GNU General Public License for more details.
15  *
16  * Contact Information:
17  * Scott H Kilau <Scott_Kilau@digi.com>
18  * Wendy Xiong   <wendyx@us.ibm.com>
19  *
20  ***********************************************************************/
21 #include <linux/delay.h>        /* For udelay */
22 #include <linux/serial_reg.h>   /* For the various UART offsets */
23 #include <linux/tty.h>
24 #include <linux/pci.h>
25 #include <asm/io.h>
26
27 #include "jsm.h"                /* Driver main header file */
28
29 static u32 jsm_offset_table[8] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
30
31 /*
32  * This function allows calls to ensure that all outstanding
33  * PCI writes have been completed, by doing a PCI read against
34  * a non-destructive, read-only location on the Neo card.
35  *
36  * In this case, we are reading the DVID (Read-only Device Identification)
37  * value of the Neo card.
38  */
39 static inline void neo_pci_posting_flush(struct jsm_board *bd)
40 {
41       readb(bd->re_map_membase + 0x8D);
42 }
43
44 static void neo_set_cts_flow_control(struct jsm_channel *ch)
45 {
46         u8 ier, efr;
47         ier = readb(&ch->ch_neo_uart->ier);
48         efr = readb(&ch->ch_neo_uart->efr);
49
50         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting CTSFLOW\n");
51
52         /* Turn on auto CTS flow control */
53         ier |= (UART_17158_IER_CTSDSR);
54         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_CTSDSR);
55
56         /* Turn off auto Xon flow control */
57         efr &= ~(UART_17158_EFR_IXON);
58
59         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
60         writeb(0, &ch->ch_neo_uart->efr);
61
62         /* Turn on UART enhanced bits */
63         writeb(efr, &ch->ch_neo_uart->efr);
64
65         /* Turn on table D, with 8 char hi/low watermarks */
66         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
67
68         /* Feed the UART our trigger levels */
69         writeb(8, &ch->ch_neo_uart->tfifo);
70         ch->ch_t_tlevel = 8;
71
72         writeb(ier, &ch->ch_neo_uart->ier);
73 }
74
75 static void neo_set_rts_flow_control(struct jsm_channel *ch)
76 {
77         u8 ier, efr;
78         ier = readb(&ch->ch_neo_uart->ier);
79         efr = readb(&ch->ch_neo_uart->efr);
80
81         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting RTSFLOW\n");
82
83         /* Turn on auto RTS flow control */
84         ier |= (UART_17158_IER_RTSDTR);
85         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_RTSDTR);
86
87         /* Turn off auto Xoff flow control */
88         ier &= ~(UART_17158_IER_XOFF);
89         efr &= ~(UART_17158_EFR_IXOFF);
90
91         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
92         writeb(0, &ch->ch_neo_uart->efr);
93
94         /* Turn on UART enhanced bits */
95         writeb(efr, &ch->ch_neo_uart->efr);
96
97         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_4DELAY), &ch->ch_neo_uart->fctr);
98         ch->ch_r_watermark = 4;
99
100         writeb(56, &ch->ch_neo_uart->rfifo);
101         ch->ch_r_tlevel = 56;
102
103         writeb(ier, &ch->ch_neo_uart->ier);
104
105         /*
106          * From the Neo UART spec sheet:
107          * The auto RTS/DTR function must be started by asserting
108          * RTS/DTR# output pin (MCR bit-0 or 1 to logic 1 after
109          * it is enabled.
110          */
111         ch->ch_mostat |= (UART_MCR_RTS);
112 }
113
114
115 static void neo_set_ixon_flow_control(struct jsm_channel *ch)
116 {
117         u8 ier, efr;
118         ier = readb(&ch->ch_neo_uart->ier);
119         efr = readb(&ch->ch_neo_uart->efr);
120
121         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXON FLOW\n");
122
123         /* Turn off auto CTS flow control */
124         ier &= ~(UART_17158_IER_CTSDSR);
125         efr &= ~(UART_17158_EFR_CTSDSR);
126
127         /* Turn on auto Xon flow control */
128         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXON);
129
130         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
131         writeb(0, &ch->ch_neo_uart->efr);
132
133         /* Turn on UART enhanced bits */
134         writeb(efr, &ch->ch_neo_uart->efr);
135
136         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
137         ch->ch_r_watermark = 4;
138
139         writeb(32, &ch->ch_neo_uart->rfifo);
140         ch->ch_r_tlevel = 32;
141
142         /* Tell UART what start/stop chars it should be looking for */
143         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
144         writeb(0, &ch->ch_neo_uart->xonchar2);
145
146         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
147         writeb(0, &ch->ch_neo_uart->xoffchar2);
148
149         writeb(ier, &ch->ch_neo_uart->ier);
150 }
151
152 static void neo_set_ixoff_flow_control(struct jsm_channel *ch)
153 {
154         u8 ier, efr;
155         ier = readb(&ch->ch_neo_uart->ier);
156         efr = readb(&ch->ch_neo_uart->efr);
157
158         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Setting IXOFF FLOW\n");
159
160         /* Turn off auto RTS flow control */
161         ier &= ~(UART_17158_IER_RTSDTR);
162         efr &= ~(UART_17158_EFR_RTSDTR);
163
164         /* Turn on auto Xoff flow control */
165         ier |= (UART_17158_IER_XOFF);
166         efr |= (UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
167
168         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
169         writeb(0, &ch->ch_neo_uart->efr);
170
171         /* Turn on UART enhanced bits */
172         writeb(efr, &ch->ch_neo_uart->efr);
173
174         /* Turn on table D, with 8 char hi/low watermarks */
175         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
176
177         writeb(8, &ch->ch_neo_uart->tfifo);
178         ch->ch_t_tlevel = 8;
179
180         /* Tell UART what start/stop chars it should be looking for */
181         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
182         writeb(0, &ch->ch_neo_uart->xonchar2);
183
184         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
185         writeb(0, &ch->ch_neo_uart->xoffchar2);
186
187         writeb(ier, &ch->ch_neo_uart->ier);
188 }
189
190 static void neo_set_no_input_flow_control(struct jsm_channel *ch)
191 {
192         u8 ier, efr;
193         ier = readb(&ch->ch_neo_uart->ier);
194         efr = readb(&ch->ch_neo_uart->efr);
195
196         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Input FLOW\n");
197
198         /* Turn off auto RTS flow control */
199         ier &= ~(UART_17158_IER_RTSDTR);
200         efr &= ~(UART_17158_EFR_RTSDTR);
201
202         /* Turn off auto Xoff flow control */
203         ier &= ~(UART_17158_IER_XOFF);
204         if (ch->ch_c_iflag & IXON)
205                 efr &= ~(UART_17158_EFR_IXOFF);
206         else
207                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXOFF);
208
209         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
210         writeb(0, &ch->ch_neo_uart->efr);
211
212         /* Turn on UART enhanced bits */
213         writeb(efr, &ch->ch_neo_uart->efr);
214
215         /* Turn on table D, with 8 char hi/low watermarks */
216         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
217
218         ch->ch_r_watermark = 0;
219
220         writeb(16, &ch->ch_neo_uart->tfifo);
221         ch->ch_t_tlevel = 16;
222
223         writeb(16, &ch->ch_neo_uart->rfifo);
224         ch->ch_r_tlevel = 16;
225
226         writeb(ier, &ch->ch_neo_uart->ier);
227 }
228
229 static void neo_set_no_output_flow_control(struct jsm_channel *ch)
230 {
231         u8 ier, efr;
232         ier = readb(&ch->ch_neo_uart->ier);
233         efr = readb(&ch->ch_neo_uart->efr);
234
235         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "Unsetting Output FLOW\n");
236
237         /* Turn off auto CTS flow control */
238         ier &= ~(UART_17158_IER_CTSDSR);
239         efr &= ~(UART_17158_EFR_CTSDSR);
240
241         /* Turn off auto Xon flow control */
242         if (ch->ch_c_iflag & IXOFF)
243                 efr &= ~(UART_17158_EFR_IXON);
244         else
245                 efr &= ~(UART_17158_EFR_ECB | UART_17158_EFR_IXON);
246
247         /* Why? Becuz Exar's spec says we have to zero it out before setting it */
248         writeb(0, &ch->ch_neo_uart->efr);
249
250         /* Turn on UART enhanced bits */
251         writeb(efr, &ch->ch_neo_uart->efr);
252
253         /* Turn on table D, with 8 char hi/low watermarks */
254         writeb((UART_17158_FCTR_TRGD | UART_17158_FCTR_RTS_8DELAY), &ch->ch_neo_uart->fctr);
255
256         ch->ch_r_watermark = 0;
257
258         writeb(16, &ch->ch_neo_uart->tfifo);
259         ch->ch_t_tlevel = 16;
260
261         writeb(16, &ch->ch_neo_uart->rfifo);
262         ch->ch_r_tlevel = 16;
263
264         writeb(ier, &ch->ch_neo_uart->ier);
265 }
266
267 static inline void neo_set_new_start_stop_chars(struct jsm_channel *ch)
268 {
269
270         /* if hardware flow control is set, then skip this whole thing */
271         if (ch->ch_c_cflag & CRTSCTS)
272                 return;
273
274         jsm_dbg(PARAM, &ch->ch_bd->pci_dev, "start\n");
275
276         /* Tell UART what start/stop chars it should be looking for */
277         writeb(ch->ch_startc, &ch->ch_neo_uart->xonchar1);
278         writeb(0, &ch->ch_neo_uart->xonchar2);
279
280         writeb(ch->ch_stopc, &ch->ch_neo_uart->xoffchar1);
281         writeb(0, &ch->ch_neo_uart->xoffchar2);
282 }
283
284 static void neo_copy_data_from_uart_to_queue(struct jsm_channel *ch)
285 {
286         int qleft = 0;
287         u8 linestatus = 0;
288         u8 error_mask = 0;
289         int n = 0;
290         int total = 0;
291         u16 head;
292         u16 tail;
293
294         if (!ch)
295                 return;
296
297         /* cache head and tail of queue */
298         head = ch->ch_r_head & RQUEUEMASK;
299         tail = ch->ch_r_tail & RQUEUEMASK;
300
301         /* Get our cached LSR */
302         linestatus = ch->ch_cached_lsr;
303         ch->ch_cached_lsr = 0;
304
305         /* Store how much space we have left in the queue */
306         if ((qleft = tail - head - 1) < 0)
307                 qleft += RQUEUEMASK + 1;
308
309         /*
310          * If the UART is not in FIFO mode, force the FIFO copy to
311          * NOT be run, by setting total to 0.
312          *
313          * On the other hand, if the UART IS in FIFO mode, then ask
314          * the UART to give us an approximation of data it has RX'ed.
315          */
316         if (!(ch->ch_flags & CH_FIFO_ENABLED))
317                 total = 0;
318         else {
319                 total = readb(&ch->ch_neo_uart->rfifo);
320
321                 /*
322                  * EXAR chip bug - RX FIFO COUNT - Fudge factor.
323                  *
324                  * This resolves a problem/bug with the Exar chip that sometimes
325                  * returns a bogus value in the rfifo register.
326                  * The count can be any where from 0-3 bytes "off".
327                  * Bizarre, but true.
328                  */
329                 total -= 3;
330         }
331
332         /*
333          * Finally, bound the copy to make sure we don't overflow
334          * our own queue...
335          * The byte by byte copy loop below this loop this will
336          * deal with the queue overflow possibility.
337          */
338         total = min(total, qleft);
339
340         while (total > 0) {
341                 /*
342                  * Grab the linestatus register, we need to check
343                  * to see if there are any errors in the FIFO.
344                  */
345                 linestatus = readb(&ch->ch_neo_uart->lsr);
346
347                 /*
348                  * Break out if there is a FIFO error somewhere.
349                  * This will allow us to go byte by byte down below,
350                  * finding the exact location of the error.
351                  */
352                 if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
353                         break;
354
355                 /* Make sure we don't go over the end of our queue */
356                 n = min(((u32) total), (RQUEUESIZE - (u32) head));
357
358                 /*
359                  * Cut down n even further if needed, this is to fix
360                  * a problem with memcpy_fromio() with the Neo on the
361                  * IBM pSeries platform.
362                  * 15 bytes max appears to be the magic number.
363                  */
364                 n = min((u32) n, (u32) 12);
365
366                 /*
367                  * Since we are grabbing the linestatus register, which
368                  * will reset some bits after our read, we need to ensure
369                  * we don't miss our TX FIFO emptys.
370                  */
371                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR))
372                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
373
374                 linestatus = 0;
375
376                 /* Copy data from uart to the queue */
377                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, n);
378                 /*
379                  * Since RX_FIFO_DATA_ERROR was 0, we are guaranteed
380                  * that all the data currently in the FIFO is free of
381                  * breaks and parity/frame/orun errors.
382                  */
383                 memset(ch->ch_equeue + head, 0, n);
384
385                 /* Add to and flip head if needed */
386                 head = (head + n) & RQUEUEMASK;
387                 total -= n;
388                 qleft -= n;
389                 ch->ch_rxcount += n;
390         }
391
392         /*
393          * Create a mask to determine whether we should
394          * insert the character (if any) into our queue.
395          */
396         if (ch->ch_c_iflag & IGNBRK)
397                 error_mask |= UART_LSR_BI;
398
399         /*
400          * Now cleanup any leftover bytes still in the UART.
401          * Also deal with any possible queue overflow here as well.
402          */
403         while (1) {
404
405                 /*
406                  * Its possible we have a linestatus from the loop above
407                  * this, so we "OR" on any extra bits.
408                  */
409                 linestatus |= readb(&ch->ch_neo_uart->lsr);
410
411                 /*
412                  * If the chip tells us there is no more data pending to
413                  * be read, we can then leave.
414                  * But before we do, cache the linestatus, just in case.
415                  */
416                 if (!(linestatus & UART_LSR_DR)) {
417                         ch->ch_cached_lsr = linestatus;
418                         break;
419                 }
420
421                 /* No need to store this bit */
422                 linestatus &= ~UART_LSR_DR;
423
424                 /*
425                  * Since we are grabbing the linestatus register, which
426                  * will reset some bits after our read, we need to ensure
427                  * we don't miss our TX FIFO emptys.
428                  */
429                 if (linestatus & (UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR)) {
430                         linestatus &= ~(UART_LSR_THRE | UART_17158_TX_AND_FIFO_CLR);
431                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
432                 }
433
434                 /*
435                  * Discard character if we are ignoring the error mask.
436                  */
437                 if (linestatus & error_mask) {
438                         u8 discard;
439                         linestatus = 0;
440                         memcpy_fromio(&discard, &ch->ch_neo_uart->txrxburst, 1);
441                         continue;
442                 }
443
444                 /*
445                  * If our queue is full, we have no choice but to drop some data.
446                  * The assumption is that HWFLOW or SWFLOW should have stopped
447                  * things way way before we got to this point.
448                  *
449                  * I decided that I wanted to ditch the oldest data first,
450                  * I hope thats okay with everyone? Yes? Good.
451                  */
452                 while (qleft < 1) {
453                         jsm_dbg(READ, &ch->ch_bd->pci_dev,
454                                 "Queue full, dropping DATA:%x LSR:%x\n",
455                                 ch->ch_rqueue[tail], ch->ch_equeue[tail]);
456
457                         ch->ch_r_tail = tail = (tail + 1) & RQUEUEMASK;
458                         ch->ch_err_overrun++;
459                         qleft++;
460                 }
461
462                 memcpy_fromio(ch->ch_rqueue + head, &ch->ch_neo_uart->txrxburst, 1);
463                 ch->ch_equeue[head] = (u8) linestatus;
464
465                 jsm_dbg(READ, &ch->ch_bd->pci_dev, "DATA/LSR pair: %x %x\n",
466                         ch->ch_rqueue[head], ch->ch_equeue[head]);
467
468                 /* Ditch any remaining linestatus value. */
469                 linestatus = 0;
470
471                 /* Add to and flip head if needed */
472                 head = (head + 1) & RQUEUEMASK;
473
474                 qleft--;
475                 ch->ch_rxcount++;
476         }
477
478         /*
479          * Write new final heads to channel structure.
480          */
481         ch->ch_r_head = head & RQUEUEMASK;
482         ch->ch_e_head = head & EQUEUEMASK;
483         jsm_input(ch);
484 }
485
486 static void neo_copy_data_from_queue_to_uart(struct jsm_channel *ch)
487 {
488         u16 head;
489         u16 tail;
490         int n;
491         int s;
492         int qlen;
493         u32 len_written = 0;
494         struct circ_buf *circ;
495
496         if (!ch)
497                 return;
498
499         circ = &ch->uart_port.state->xmit;
500
501         /* No data to write to the UART */
502         if (uart_circ_empty(circ))
503                 return;
504
505         /* If port is "stopped", don't send any data to the UART */
506         if ((ch->ch_flags & CH_STOP) || (ch->ch_flags & CH_BREAK_SENDING))
507                 return;
508         /*
509          * If FIFOs are disabled. Send data directly to txrx register
510          */
511         if (!(ch->ch_flags & CH_FIFO_ENABLED)) {
512                 u8 lsrbits = readb(&ch->ch_neo_uart->lsr);
513
514                 ch->ch_cached_lsr |= lsrbits;
515                 if (ch->ch_cached_lsr & UART_LSR_THRE) {
516                         ch->ch_cached_lsr &= ~(UART_LSR_THRE);
517
518                         writeb(circ->buf[circ->tail], &ch->ch_neo_uart->txrx);
519                         jsm_dbg(WRITE, &ch->ch_bd->pci_dev,
520                                 "Tx data: %x\n", circ->buf[circ->tail]);
521                         circ->tail = (circ->tail + 1) & (UART_XMIT_SIZE - 1);
522                         ch->ch_txcount++;
523                 }
524                 return;
525         }
526
527         /*
528          * We have to do it this way, because of the EXAR TXFIFO count bug.
529          */
530         if (!(ch->ch_flags & (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM)))
531                 return;
532
533         n = UART_17158_TX_FIFOSIZE - ch->ch_t_tlevel;
534
535         /* cache head and tail of queue */
536         head = circ->head & (UART_XMIT_SIZE - 1);
537         tail = circ->tail & (UART_XMIT_SIZE - 1);
538         qlen = uart_circ_chars_pending(circ);
539
540         /* Find minimum of the FIFO space, versus queue length */
541         n = min(n, qlen);
542
543         while (n > 0) {
544
545                 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
546                 s = min(s, n);
547
548                 if (s <= 0)
549                         break;
550
551                 memcpy_toio(&ch->ch_neo_uart->txrxburst, circ->buf + tail, s);
552                 /* Add and flip queue if needed */
553                 tail = (tail + s) & (UART_XMIT_SIZE - 1);
554                 n -= s;
555                 ch->ch_txcount += s;
556                 len_written += s;
557         }
558
559         /* Update the final tail */
560         circ->tail = tail & (UART_XMIT_SIZE - 1);
561
562         if (len_written >= ch->ch_t_tlevel)
563                 ch->ch_flags &= ~(CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
564
565         if (uart_circ_empty(circ))
566                 uart_write_wakeup(&ch->uart_port);
567 }
568
569 static void neo_parse_modem(struct jsm_channel *ch, u8 signals)
570 {
571         u8 msignals = signals;
572
573         jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
574                 "neo_parse_modem: port: %d msignals: %x\n",
575                 ch->ch_portnum, msignals);
576
577         /* Scrub off lower bits. They signify delta's, which I don't care about */
578         /* Keep DDCD and DDSR though */
579         msignals &= 0xf8;
580
581         if (msignals & UART_MSR_DDCD)
582                 uart_handle_dcd_change(&ch->uart_port, msignals & UART_MSR_DCD);
583         if (msignals & UART_MSR_DDSR)
584                 uart_handle_cts_change(&ch->uart_port, msignals & UART_MSR_CTS);
585         if (msignals & UART_MSR_DCD)
586                 ch->ch_mistat |= UART_MSR_DCD;
587         else
588                 ch->ch_mistat &= ~UART_MSR_DCD;
589
590         if (msignals & UART_MSR_DSR)
591                 ch->ch_mistat |= UART_MSR_DSR;
592         else
593                 ch->ch_mistat &= ~UART_MSR_DSR;
594
595         if (msignals & UART_MSR_RI)
596                 ch->ch_mistat |= UART_MSR_RI;
597         else
598                 ch->ch_mistat &= ~UART_MSR_RI;
599
600         if (msignals & UART_MSR_CTS)
601                 ch->ch_mistat |= UART_MSR_CTS;
602         else
603                 ch->ch_mistat &= ~UART_MSR_CTS;
604
605         jsm_dbg(MSIGS, &ch->ch_bd->pci_dev,
606                 "Port: %d DTR: %d RTS: %d CTS: %d DSR: %d " "RI: %d CD: %d\n",
607                 ch->ch_portnum,
608                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_DTR),
609                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MCR_RTS),
610                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_CTS),
611                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DSR),
612                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_RI),
613                 !!((ch->ch_mistat | ch->ch_mostat) & UART_MSR_DCD));
614 }
615
616 /* Make the UART raise any of the output signals we want up */
617 static void neo_assert_modem_signals(struct jsm_channel *ch)
618 {
619         if (!ch)
620                 return;
621
622         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
623
624         /* flush write operation */
625         neo_pci_posting_flush(ch->ch_bd);
626 }
627
628 /*
629  * Flush the WRITE FIFO on the Neo.
630  *
631  * NOTE: Channel lock MUST be held before calling this function!
632  */
633 static void neo_flush_uart_write(struct jsm_channel *ch)
634 {
635         u8 tmp = 0;
636         int i = 0;
637
638         if (!ch)
639                 return;
640
641         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
642
643         for (i = 0; i < 10; i++) {
644
645                 /* Check to see if the UART feels it completely flushed the FIFO. */
646                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
647                 if (tmp & UART_FCR_CLEAR_XMIT) {
648                         jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
649                                 "Still flushing TX UART... i: %d\n", i);
650                         udelay(10);
651                 }
652                 else
653                         break;
654         }
655
656         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
657 }
658
659
660 /*
661  * Flush the READ FIFO on the Neo.
662  *
663  * NOTE: Channel lock MUST be held before calling this function!
664  */
665 static void neo_flush_uart_read(struct jsm_channel *ch)
666 {
667         u8 tmp = 0;
668         int i = 0;
669
670         if (!ch)
671                 return;
672
673         writeb((UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR), &ch->ch_neo_uart->isr_fcr);
674
675         for (i = 0; i < 10; i++) {
676
677                 /* Check to see if the UART feels it completely flushed the FIFO. */
678                 tmp = readb(&ch->ch_neo_uart->isr_fcr);
679                 if (tmp & 2) {
680                         jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
681                                 "Still flushing RX UART... i: %d\n", i);
682                         udelay(10);
683                 }
684                 else
685                         break;
686         }
687 }
688
689 /*
690  * No locks are assumed to be held when calling this function.
691  */
692 static void neo_clear_break(struct jsm_channel *ch)
693 {
694         unsigned long lock_flags;
695
696         spin_lock_irqsave(&ch->ch_lock, lock_flags);
697
698         /* Turn break off, and unset some variables */
699         if (ch->ch_flags & CH_BREAK_SENDING) {
700                 u8 temp = readb(&ch->ch_neo_uart->lcr);
701                 writeb((temp & ~UART_LCR_SBC), &ch->ch_neo_uart->lcr);
702
703                 ch->ch_flags &= ~(CH_BREAK_SENDING);
704                 jsm_dbg(IOCTL, &ch->ch_bd->pci_dev,
705                         "clear break Finishing UART_LCR_SBC! finished: %lx\n",
706                         jiffies);
707
708                 /* flush write operation */
709                 neo_pci_posting_flush(ch->ch_bd);
710         }
711         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
712 }
713
714 /*
715  * Parse the ISR register.
716  */
717 static void neo_parse_isr(struct jsm_board *brd, u32 port)
718 {
719         struct jsm_channel *ch;
720         u8 isr;
721         u8 cause;
722         unsigned long lock_flags;
723
724         if (!brd)
725                 return;
726
727         if (port >= brd->maxports)
728                 return;
729
730         ch = brd->channels[port];
731         if (!ch)
732                 return;
733
734         /* Here we try to figure out what caused the interrupt to happen */
735         while (1) {
736
737                 isr = readb(&ch->ch_neo_uart->isr_fcr);
738
739                 /* Bail if no pending interrupt */
740                 if (isr & UART_IIR_NO_INT)
741                         break;
742
743                 /*
744                  * Yank off the upper 2 bits, which just show that the FIFO's are enabled.
745                  */
746                 isr &= ~(UART_17158_IIR_FIFO_ENABLED);
747
748                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d isr: %x\n",
749                         __FILE__, __LINE__, isr);
750
751                 if (isr & (UART_17158_IIR_RDI_TIMEOUT | UART_IIR_RDI)) {
752                         /* Read data from uart -> queue */
753                         neo_copy_data_from_uart_to_queue(ch);
754
755                         /* Call our tty layer to enforce queue flow control if needed. */
756                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
757                         jsm_check_queue_flow_control(ch);
758                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
759                 }
760
761                 if (isr & UART_IIR_THRI) {
762                         /* Transfer data (if any) from Write Queue -> UART. */
763                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
764                         ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
765                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
766                         neo_copy_data_from_queue_to_uart(ch);
767                 }
768
769                 if (isr & UART_17158_IIR_XONXOFF) {
770                         cause = readb(&ch->ch_neo_uart->xoffchar1);
771
772                         jsm_dbg(INTR, &ch->ch_bd->pci_dev,
773                                 "Port %d. Got ISR_XONXOFF: cause:%x\n",
774                                 port, cause);
775
776                         /*
777                          * Since the UART detected either an XON or
778                          * XOFF match, we need to figure out which
779                          * one it was, so we can suspend or resume data flow.
780                          */
781                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
782                         if (cause == UART_17158_XON_DETECT) {
783                                 /* Is output stopped right now, if so, resume it */
784                                 if (brd->channels[port]->ch_flags & CH_STOP) {
785                                         ch->ch_flags &= ~(CH_STOP);
786                                 }
787                                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
788                                         "Port %d. XON detected in incoming data\n",
789                                         port);
790                         }
791                         else if (cause == UART_17158_XOFF_DETECT) {
792                                 if (!(brd->channels[port]->ch_flags & CH_STOP)) {
793                                         ch->ch_flags |= CH_STOP;
794                                         jsm_dbg(INTR, &ch->ch_bd->pci_dev,
795                                                 "Setting CH_STOP\n");
796                                 }
797                                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
798                                         "Port: %d. XOFF detected in incoming data\n",
799                                         port);
800                         }
801                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
802                 }
803
804                 if (isr & UART_17158_IIR_HWFLOW_STATE_CHANGE) {
805                         /*
806                          * If we get here, this means the hardware is doing auto flow control.
807                          * Check to see whether RTS/DTR or CTS/DSR caused this interrupt.
808                          */
809                         cause = readb(&ch->ch_neo_uart->mcr);
810
811                         /* Which pin is doing auto flow? RTS or DTR? */
812                         spin_lock_irqsave(&ch->ch_lock, lock_flags);
813                         if ((cause & 0x4) == 0) {
814                                 if (cause & UART_MCR_RTS)
815                                         ch->ch_mostat |= UART_MCR_RTS;
816                                 else
817                                         ch->ch_mostat &= ~(UART_MCR_RTS);
818                         } else {
819                                 if (cause & UART_MCR_DTR)
820                                         ch->ch_mostat |= UART_MCR_DTR;
821                                 else
822                                         ch->ch_mostat &= ~(UART_MCR_DTR);
823                         }
824                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
825                 }
826
827                 /* Parse any modem signal changes */
828                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
829                         "MOD_STAT: sending to parse_modem_sigs\n");
830                 spin_lock_irqsave(&ch->uart_port.lock, lock_flags);
831                 neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
832                 spin_unlock_irqrestore(&ch->uart_port.lock, lock_flags);
833         }
834 }
835
836 static inline void neo_parse_lsr(struct jsm_board *brd, u32 port)
837 {
838         struct jsm_channel *ch;
839         int linestatus;
840         unsigned long lock_flags;
841
842         if (!brd)
843                 return;
844
845         if (port >= brd->maxports)
846                 return;
847
848         ch = brd->channels[port];
849         if (!ch)
850                 return;
851
852         linestatus = readb(&ch->ch_neo_uart->lsr);
853
854         jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d port: %d linestatus: %x\n",
855                 __FILE__, __LINE__, port, linestatus);
856
857         ch->ch_cached_lsr |= linestatus;
858
859         if (ch->ch_cached_lsr & UART_LSR_DR) {
860                 /* Read data from uart -> queue */
861                 neo_copy_data_from_uart_to_queue(ch);
862                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
863                 jsm_check_queue_flow_control(ch);
864                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
865         }
866
867         /*
868          * This is a special flag. It indicates that at least 1
869          * RX error (parity, framing, or break) has happened.
870          * Mark this in our struct, which will tell me that I have
871          *to do the special RX+LSR read for this FIFO load.
872          */
873         if (linestatus & UART_17158_RX_FIFO_DATA_ERROR)
874                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
875                         "%s:%d Port: %d Got an RX error, need to parse LSR\n",
876                         __FILE__, __LINE__, port);
877
878         /*
879          * The next 3 tests should *NOT* happen, as the above test
880          * should encapsulate all 3... At least, thats what Exar says.
881          */
882
883         if (linestatus & UART_LSR_PE) {
884                 ch->ch_err_parity++;
885                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. PAR ERR!\n",
886                         __FILE__, __LINE__, port);
887         }
888
889         if (linestatus & UART_LSR_FE) {
890                 ch->ch_err_frame++;
891                 jsm_dbg(INTR, &ch->ch_bd->pci_dev, "%s:%d Port: %d. FRM ERR!\n",
892                         __FILE__, __LINE__, port);
893         }
894
895         if (linestatus & UART_LSR_BI) {
896                 ch->ch_err_break++;
897                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
898                         "%s:%d Port: %d. BRK INTR!\n",
899                         __FILE__, __LINE__, port);
900         }
901
902         if (linestatus & UART_LSR_OE) {
903                 /*
904                  * Rx Oruns. Exar says that an orun will NOT corrupt
905                  * the FIFO. It will just replace the holding register
906                  * with this new data byte. So basically just ignore this.
907                  * Probably we should eventually have an orun stat in our driver...
908                  */
909                 ch->ch_err_overrun++;
910                 jsm_dbg(INTR, &ch->ch_bd->pci_dev,
911                         "%s:%d Port: %d. Rx Overrun!\n",
912                         __FILE__, __LINE__, port);
913         }
914
915         if (linestatus & UART_LSR_THRE) {
916                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
917                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
918                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
919
920                 /* Transfer data (if any) from Write Queue -> UART. */
921                 neo_copy_data_from_queue_to_uart(ch);
922         }
923         else if (linestatus & UART_17158_TX_AND_FIFO_CLR) {
924                 spin_lock_irqsave(&ch->ch_lock, lock_flags);
925                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
926                 spin_unlock_irqrestore(&ch->ch_lock, lock_flags);
927
928                 /* Transfer data (if any) from Write Queue -> UART. */
929                 neo_copy_data_from_queue_to_uart(ch);
930         }
931 }
932
933 /*
934  * neo_param()
935  * Send any/all changes to the line to the UART.
936  */
937 static void neo_param(struct jsm_channel *ch)
938 {
939         u8 lcr = 0;
940         u8 uart_lcr, ier;
941         u32 baud;
942         int quot;
943         struct jsm_board *bd;
944
945         bd = ch->ch_bd;
946         if (!bd)
947                 return;
948
949         /*
950          * If baud rate is zero, flush queues, and set mval to drop DTR.
951          */
952         if ((ch->ch_c_cflag & (CBAUD)) == 0) {
953                 ch->ch_r_head = ch->ch_r_tail = 0;
954                 ch->ch_e_head = ch->ch_e_tail = 0;
955
956                 neo_flush_uart_write(ch);
957                 neo_flush_uart_read(ch);
958
959                 ch->ch_flags |= (CH_BAUD0);
960                 ch->ch_mostat &= ~(UART_MCR_RTS | UART_MCR_DTR);
961                 neo_assert_modem_signals(ch);
962                 return;
963
964         } else {
965                 int i;
966                 unsigned int cflag;
967                 static struct {
968                         unsigned int rate;
969                         unsigned int cflag;
970                 } baud_rates[] = {
971                         { 921600, B921600 },
972                         { 460800, B460800 },
973                         { 230400, B230400 },
974                         { 115200, B115200 },
975                         {  57600, B57600  },
976                         {  38400, B38400  },
977                         {  19200, B19200  },
978                         {   9600, B9600   },
979                         {   4800, B4800   },
980                         {   2400, B2400   },
981                         {   1200, B1200   },
982                         {    600, B600    },
983                         {    300, B300    },
984                         {    200, B200    },
985                         {    150, B150    },
986                         {    134, B134    },
987                         {    110, B110    },
988                         {     75, B75     },
989                         {     50, B50     },
990                 };
991
992                 cflag = C_BAUD(ch->uart_port.state->port.tty);
993                 baud = 9600;
994                 for (i = 0; i < ARRAY_SIZE(baud_rates); i++) {
995                         if (baud_rates[i].cflag == cflag) {
996                                 baud = baud_rates[i].rate;
997                                 break;
998                         }
999                 }
1000
1001                 if (ch->ch_flags & CH_BAUD0)
1002                         ch->ch_flags &= ~(CH_BAUD0);
1003         }
1004
1005         if (ch->ch_c_cflag & PARENB)
1006                 lcr |= UART_LCR_PARITY;
1007
1008         if (!(ch->ch_c_cflag & PARODD))
1009                 lcr |= UART_LCR_EPAR;
1010
1011         /*
1012          * Not all platforms support mark/space parity,
1013          * so this will hide behind an ifdef.
1014          */
1015 #ifdef CMSPAR
1016         if (ch->ch_c_cflag & CMSPAR)
1017                 lcr |= UART_LCR_SPAR;
1018 #endif
1019
1020         if (ch->ch_c_cflag & CSTOPB)
1021                 lcr |= UART_LCR_STOP;
1022
1023         switch (ch->ch_c_cflag & CSIZE) {
1024         case CS5:
1025                 lcr |= UART_LCR_WLEN5;
1026                 break;
1027         case CS6:
1028                 lcr |= UART_LCR_WLEN6;
1029                 break;
1030         case CS7:
1031                 lcr |= UART_LCR_WLEN7;
1032                 break;
1033         case CS8:
1034         default:
1035                 lcr |= UART_LCR_WLEN8;
1036         break;
1037         }
1038
1039         ier = readb(&ch->ch_neo_uart->ier);
1040         uart_lcr = readb(&ch->ch_neo_uart->lcr);
1041
1042         quot = ch->ch_bd->bd_dividend / baud;
1043
1044         if (quot != 0) {
1045                 writeb(UART_LCR_DLAB, &ch->ch_neo_uart->lcr);
1046                 writeb((quot & 0xff), &ch->ch_neo_uart->txrx);
1047                 writeb((quot >> 8), &ch->ch_neo_uart->ier);
1048                 writeb(lcr, &ch->ch_neo_uart->lcr);
1049         }
1050
1051         if (uart_lcr != lcr)
1052                 writeb(lcr, &ch->ch_neo_uart->lcr);
1053
1054         if (ch->ch_c_cflag & CREAD)
1055                 ier |= (UART_IER_RDI | UART_IER_RLSI);
1056
1057         ier |= (UART_IER_THRI | UART_IER_MSI);
1058
1059         writeb(ier, &ch->ch_neo_uart->ier);
1060
1061         /* Set new start/stop chars */
1062         neo_set_new_start_stop_chars(ch);
1063
1064         if (ch->ch_c_cflag & CRTSCTS)
1065                 neo_set_cts_flow_control(ch);
1066         else if (ch->ch_c_iflag & IXON) {
1067                 /* If start/stop is set to disable, then we should disable flow control */
1068                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1069                         neo_set_no_output_flow_control(ch);
1070                 else
1071                         neo_set_ixon_flow_control(ch);
1072         }
1073         else
1074                 neo_set_no_output_flow_control(ch);
1075
1076         if (ch->ch_c_cflag & CRTSCTS)
1077                 neo_set_rts_flow_control(ch);
1078         else if (ch->ch_c_iflag & IXOFF) {
1079                 /* If start/stop is set to disable, then we should disable flow control */
1080                 if ((ch->ch_startc == __DISABLED_CHAR) || (ch->ch_stopc == __DISABLED_CHAR))
1081                         neo_set_no_input_flow_control(ch);
1082                 else
1083                         neo_set_ixoff_flow_control(ch);
1084         }
1085         else
1086                 neo_set_no_input_flow_control(ch);
1087         /*
1088          * Adjust the RX FIFO Trigger level if baud is less than 9600.
1089          * Not exactly elegant, but this is needed because of the Exar chip's
1090          * delay on firing off the RX FIFO interrupt on slower baud rates.
1091          */
1092         if (baud < 9600) {
1093                 writeb(1, &ch->ch_neo_uart->rfifo);
1094                 ch->ch_r_tlevel = 1;
1095         }
1096
1097         neo_assert_modem_signals(ch);
1098
1099         /* Get current status of the modem signals now */
1100         neo_parse_modem(ch, readb(&ch->ch_neo_uart->msr));
1101         return;
1102 }
1103
1104 /*
1105  * jsm_neo_intr()
1106  *
1107  * Neo specific interrupt handler.
1108  */
1109 static irqreturn_t neo_intr(int irq, void *voidbrd)
1110 {
1111         struct jsm_board *brd = voidbrd;
1112         struct jsm_channel *ch;
1113         int port = 0;
1114         int type = 0;
1115         int current_port;
1116         u32 tmp;
1117         u32 uart_poll;
1118         unsigned long lock_flags;
1119         unsigned long lock_flags2;
1120         int outofloop_count = 0;
1121
1122         /* Lock out the slow poller from running on this board. */
1123         spin_lock_irqsave(&brd->bd_intr_lock, lock_flags);
1124
1125         /*
1126          * Read in "extended" IRQ information from the 32bit Neo register.
1127          * Bits 0-7: What port triggered the interrupt.
1128          * Bits 8-31: Each 3bits indicate what type of interrupt occurred.
1129          */
1130         uart_poll = readl(brd->re_map_membase + UART_17158_POLL_ADDR_OFFSET);
1131
1132         jsm_dbg(INTR, &brd->pci_dev, "%s:%d uart_poll: %x\n",
1133                 __FILE__, __LINE__, uart_poll);
1134
1135         if (!uart_poll) {
1136                 jsm_dbg(INTR, &brd->pci_dev,
1137                         "Kernel interrupted to me, but no pending interrupts...\n");
1138                 spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1139                 return IRQ_NONE;
1140         }
1141
1142         /* At this point, we have at least SOMETHING to service, dig further... */
1143
1144         current_port = 0;
1145
1146         /* Loop on each port */
1147         while (((uart_poll & 0xff) != 0) && (outofloop_count < 0xff)){
1148
1149                 tmp = uart_poll;
1150                 outofloop_count++;
1151
1152                 /* Check current port to see if it has interrupt pending */
1153                 if ((tmp & jsm_offset_table[current_port]) != 0) {
1154                         port = current_port;
1155                         type = tmp >> (8 + (port * 3));
1156                         type &= 0x7;
1157                 } else {
1158                         current_port++;
1159                         continue;
1160                 }
1161
1162                 jsm_dbg(INTR, &brd->pci_dev, "%s:%d port: %x type: %x\n",
1163                         __FILE__, __LINE__, port, type);
1164
1165                 /* Remove this port + type from uart_poll */
1166                 uart_poll &= ~(jsm_offset_table[port]);
1167
1168                 if (!type) {
1169                         /* If no type, just ignore it, and move onto next port */
1170                         jsm_dbg(INTR, &brd->pci_dev,
1171                                 "Interrupt with no type! port: %d\n", port);
1172                         continue;
1173                 }
1174
1175                 /* Switch on type of interrupt we have */
1176                 switch (type) {
1177
1178                 case UART_17158_RXRDY_TIMEOUT:
1179                         /*
1180                          * RXRDY Time-out is cleared by reading data in the
1181                         * RX FIFO until it falls below the trigger level.
1182                          */
1183
1184                         /* Verify the port is in range. */
1185                         if (port >= brd->nasync)
1186                                 continue;
1187
1188                         ch = brd->channels[port];
1189                         neo_copy_data_from_uart_to_queue(ch);
1190
1191                         /* Call our tty layer to enforce queue flow control if needed. */
1192                         spin_lock_irqsave(&ch->ch_lock, lock_flags2);
1193                         jsm_check_queue_flow_control(ch);
1194                         spin_unlock_irqrestore(&ch->ch_lock, lock_flags2);
1195
1196                         continue;
1197
1198                 case UART_17158_RX_LINE_STATUS:
1199                         /*
1200                          * RXRDY and RX LINE Status (logic OR of LSR[4:1])
1201                          */
1202                         neo_parse_lsr(brd, port);
1203                         continue;
1204
1205                 case UART_17158_TXRDY:
1206                         /*
1207                          * TXRDY interrupt clears after reading ISR register for the UART channel.
1208                          */
1209
1210                         /*
1211                          * Yes, this is odd...
1212                          * Why would I check EVERY possibility of type of
1213                          * interrupt, when we know its TXRDY???
1214                          * Becuz for some reason, even tho we got triggered for TXRDY,
1215                          * it seems to be occasionally wrong. Instead of TX, which
1216                          * it should be, I was getting things like RXDY too. Weird.
1217                          */
1218                         neo_parse_isr(brd, port);
1219                         continue;
1220
1221                 case UART_17158_MSR:
1222                         /*
1223                          * MSR or flow control was seen.
1224                          */
1225                         neo_parse_isr(brd, port);
1226                         continue;
1227
1228                 default:
1229                         /*
1230                          * The UART triggered us with a bogus interrupt type.
1231                          * It appears the Exar chip, when REALLY bogged down, will throw
1232                          * these once and awhile.
1233                          * Its harmless, just ignore it and move on.
1234                          */
1235                         jsm_dbg(INTR, &brd->pci_dev,
1236                                 "%s:%d Unknown Interrupt type: %x\n",
1237                                 __FILE__, __LINE__, type);
1238                         continue;
1239                 }
1240         }
1241
1242         spin_unlock_irqrestore(&brd->bd_intr_lock, lock_flags);
1243
1244         jsm_dbg(INTR, &brd->pci_dev, "finish\n");
1245         return IRQ_HANDLED;
1246 }
1247
1248 /*
1249  * Neo specific way of turning off the receiver.
1250  * Used as a way to enforce queue flow control when in
1251  * hardware flow control mode.
1252  */
1253 static void neo_disable_receiver(struct jsm_channel *ch)
1254 {
1255         u8 tmp = readb(&ch->ch_neo_uart->ier);
1256         tmp &= ~(UART_IER_RDI);
1257         writeb(tmp, &ch->ch_neo_uart->ier);
1258
1259         /* flush write operation */
1260         neo_pci_posting_flush(ch->ch_bd);
1261 }
1262
1263
1264 /*
1265  * Neo specific way of turning on the receiver.
1266  * Used as a way to un-enforce queue flow control when in
1267  * hardware flow control mode.
1268  */
1269 static void neo_enable_receiver(struct jsm_channel *ch)
1270 {
1271         u8 tmp = readb(&ch->ch_neo_uart->ier);
1272         tmp |= (UART_IER_RDI);
1273         writeb(tmp, &ch->ch_neo_uart->ier);
1274
1275         /* flush write operation */
1276         neo_pci_posting_flush(ch->ch_bd);
1277 }
1278
1279 static void neo_send_start_character(struct jsm_channel *ch)
1280 {
1281         if (!ch)
1282                 return;
1283
1284         if (ch->ch_startc != __DISABLED_CHAR) {
1285                 ch->ch_xon_sends++;
1286                 writeb(ch->ch_startc, &ch->ch_neo_uart->txrx);
1287
1288                 /* flush write operation */
1289                 neo_pci_posting_flush(ch->ch_bd);
1290         }
1291 }
1292
1293 static void neo_send_stop_character(struct jsm_channel *ch)
1294 {
1295         if (!ch)
1296                 return;
1297
1298         if (ch->ch_stopc != __DISABLED_CHAR) {
1299                 ch->ch_xoff_sends++;
1300                 writeb(ch->ch_stopc, &ch->ch_neo_uart->txrx);
1301
1302                 /* flush write operation */
1303                 neo_pci_posting_flush(ch->ch_bd);
1304         }
1305 }
1306
1307 /*
1308  * neo_uart_init
1309  */
1310 static void neo_uart_init(struct jsm_channel *ch)
1311 {
1312         writeb(0, &ch->ch_neo_uart->ier);
1313         writeb(0, &ch->ch_neo_uart->efr);
1314         writeb(UART_EFR_ECB, &ch->ch_neo_uart->efr);
1315
1316         /* Clear out UART and FIFO */
1317         readb(&ch->ch_neo_uart->txrx);
1318         writeb((UART_FCR_ENABLE_FIFO|UART_FCR_CLEAR_RCVR|UART_FCR_CLEAR_XMIT), &ch->ch_neo_uart->isr_fcr);
1319         readb(&ch->ch_neo_uart->lsr);
1320         readb(&ch->ch_neo_uart->msr);
1321
1322         ch->ch_flags |= CH_FIFO_ENABLED;
1323
1324         /* Assert any signals we want up */
1325         writeb(ch->ch_mostat, &ch->ch_neo_uart->mcr);
1326 }
1327
1328 /*
1329  * Make the UART completely turn off.
1330  */
1331 static void neo_uart_off(struct jsm_channel *ch)
1332 {
1333         /* Turn off UART enhanced bits */
1334         writeb(0, &ch->ch_neo_uart->efr);
1335
1336         /* Stop all interrupts from occurring. */
1337         writeb(0, &ch->ch_neo_uart->ier);
1338 }
1339
1340 static u32 neo_get_uart_bytes_left(struct jsm_channel *ch)
1341 {
1342         u8 left = 0;
1343         u8 lsr = readb(&ch->ch_neo_uart->lsr);
1344
1345         /* We must cache the LSR as some of the bits get reset once read... */
1346         ch->ch_cached_lsr |= lsr;
1347
1348         /* Determine whether the Transmitter is empty or not */
1349         if (!(lsr & UART_LSR_TEMT))
1350                 left = 1;
1351         else {
1352                 ch->ch_flags |= (CH_TX_FIFO_EMPTY | CH_TX_FIFO_LWM);
1353                 left = 0;
1354         }
1355
1356         return left;
1357 }
1358
1359 /* Channel lock MUST be held by the calling function! */
1360 static void neo_send_break(struct jsm_channel *ch)
1361 {
1362         /*
1363          * Set the time we should stop sending the break.
1364          * If we are already sending a break, toss away the existing
1365          * time to stop, and use this new value instead.
1366          */
1367
1368         /* Tell the UART to start sending the break */
1369         if (!(ch->ch_flags & CH_BREAK_SENDING)) {
1370                 u8 temp = readb(&ch->ch_neo_uart->lcr);
1371                 writeb((temp | UART_LCR_SBC), &ch->ch_neo_uart->lcr);
1372                 ch->ch_flags |= (CH_BREAK_SENDING);
1373
1374                 /* flush write operation */
1375                 neo_pci_posting_flush(ch->ch_bd);
1376         }
1377 }
1378
1379 /*
1380  * neo_send_immediate_char.
1381  *
1382  * Sends a specific character as soon as possible to the UART,
1383  * jumping over any bytes that might be in the write queue.
1384  *
1385  * The channel lock MUST be held by the calling function.
1386  */
1387 static void neo_send_immediate_char(struct jsm_channel *ch, unsigned char c)
1388 {
1389         if (!ch)
1390                 return;
1391
1392         writeb(c, &ch->ch_neo_uart->txrx);
1393
1394         /* flush write operation */
1395         neo_pci_posting_flush(ch->ch_bd);
1396 }
1397
1398 struct board_ops jsm_neo_ops = {
1399         .intr                           = neo_intr,
1400         .uart_init                      = neo_uart_init,
1401         .uart_off                       = neo_uart_off,
1402         .param                          = neo_param,
1403         .assert_modem_signals           = neo_assert_modem_signals,
1404         .flush_uart_write               = neo_flush_uart_write,
1405         .flush_uart_read                = neo_flush_uart_read,
1406         .disable_receiver               = neo_disable_receiver,
1407         .enable_receiver                = neo_enable_receiver,
1408         .send_break                     = neo_send_break,
1409         .clear_break                    = neo_clear_break,
1410         .send_start_character           = neo_send_start_character,
1411         .send_stop_character            = neo_send_stop_character,
1412         .copy_data_from_queue_to_uart   = neo_copy_data_from_queue_to_uart,
1413         .get_uart_bytes_left            = neo_get_uart_bytes_left,
1414         .send_immediate_char            = neo_send_immediate_char
1415 };