drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/debugfs.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/pch_dma.h>
  39
  40 enum {
  41         PCH_UART_HANDLED_RX_INT_SHIFT,
  42         PCH_UART_HANDLED_TX_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  44         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  45         PCH_UART_HANDLED_MS_INT_SHIFT,
  46         PCH_UART_HANDLED_LS_INT_SHIFT,
  47 };
  48
  49 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  50
  51 /* Set the max number of UART port
  52  * Intel EG20T PCH: 4 port
  53  * LAPIS Semiconductor ML7213 IOH: 3 port
  54  * LAPIS Semiconductor ML7223 IOH: 2 port
  55 */
  56 #define PCH_UART_NR     4
  57
  58 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  59 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  60 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  61                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  62 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  63                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  65
  66 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  67
  68 #define PCH_UART_RBR            0x00
  69 #define PCH_UART_THR            0x00
  70
  71 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  72                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  73 #define PCH_UART_IER_ERBFI      0x00000001
  74 #define PCH_UART_IER_ETBEI      0x00000002
  75 #define PCH_UART_IER_ELSI       0x00000004
  76 #define PCH_UART_IER_EDSSI      0x00000008
  77
  78 #define PCH_UART_IIR_IP                 0x00000001
  79 #define PCH_UART_IIR_IID                0x00000006
  80 #define PCH_UART_IIR_MSI                0x00000000
  81 #define PCH_UART_IIR_TRI                0x00000002
  82 #define PCH_UART_IIR_RRI                0x00000004
  83 #define PCH_UART_IIR_REI                0x00000006
  84 #define PCH_UART_IIR_TOI                0x00000008
  85 #define PCH_UART_IIR_FIFO256            0x00000020
  86 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  87 #define PCH_UART_IIR_FE                 0x000000C0
  88
  89 #define PCH_UART_FCR_FIFOE              0x00000001
  90 #define PCH_UART_FCR_RFR                0x00000002
  91 #define PCH_UART_FCR_TFR                0x00000004
  92 #define PCH_UART_FCR_DMS                0x00000008
  93 #define PCH_UART_FCR_FIFO256            0x00000020
  94 #define PCH_UART_FCR_RFTL               0x000000C0
  95
  96 #define PCH_UART_FCR_RFTL1              0x00000000
  97 #define PCH_UART_FCR_RFTL64             0x00000040
  98 #define PCH_UART_FCR_RFTL128            0x00000080
  99 #define PCH_UART_FCR_RFTL224            0x000000C0
 100 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 101 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 102 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 103 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 104 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 105 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 106 #define PCH_UART_FCR_RFTL_SHIFT         6
 107
 108 #define PCH_UART_LCR_WLS        0x00000003
 109 #define PCH_UART_LCR_STB        0x00000004
 110 #define PCH_UART_LCR_PEN        0x00000008
 111 #define PCH_UART_LCR_EPS        0x00000010
 112 #define PCH_UART_LCR_SP         0x00000020
 113 #define PCH_UART_LCR_SB         0x00000040
 114 #define PCH_UART_LCR_DLAB       0x00000080
 115 #define PCH_UART_LCR_NP         0x00000000
 116 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 117 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 118 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 119 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 120                                 PCH_UART_LCR_SP)
 121
 122 #define PCH_UART_LCR_5BIT       0x00000000
 123 #define PCH_UART_LCR_6BIT       0x00000001
 124 #define PCH_UART_LCR_7BIT       0x00000002
 125 #define PCH_UART_LCR_8BIT       0x00000003
 126
 127 #define PCH_UART_MCR_DTR        0x00000001
 128 #define PCH_UART_MCR_RTS        0x00000002
 129 #define PCH_UART_MCR_OUT        0x0000000C
 130 #define PCH_UART_MCR_LOOP       0x00000010
 131 #define PCH_UART_MCR_AFE        0x00000020
 132
 133 #define PCH_UART_LSR_DR         0x00000001
 134 #define PCH_UART_LSR_ERR        (1<<7)
 135
 136 #define PCH_UART_MSR_DCTS       0x00000001
 137 #define PCH_UART_MSR_DDSR       0x00000002
 138 #define PCH_UART_MSR_TERI       0x00000004
 139 #define PCH_UART_MSR_DDCD       0x00000008
 140 #define PCH_UART_MSR_CTS        0x00000010
 141 #define PCH_UART_MSR_DSR        0x00000020
 142 #define PCH_UART_MSR_RI         0x00000040
 143 #define PCH_UART_MSR_DCD        0x00000080
 144 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 145                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 146
 147 #define PCH_UART_DLL            0x00
 148 #define PCH_UART_DLM            0x01
 149
 150 #define PCH_UART_BRCSR          0x0E
 151
 152 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 153 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 154 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 155 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 156 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 157
 158 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 159 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 160 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 161 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 162 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 163 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 164 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 165 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 166 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 167 #define PCH_UART_HAL_STB1               0
 168 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 169
 170 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 171 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 172 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 173                                         PCH_UART_HAL_CLR_RX_FIFO)
 174
 175 #define PCH_UART_HAL_DMA_MODE0          0
 176 #define PCH_UART_HAL_FIFO_DIS           0
 177 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 178 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 179                                         PCH_UART_FCR_FIFO256)
 180 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 181 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 182 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 183 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 184 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 185 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 186 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 187 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 188 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 189 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 190 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 191 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 192 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 193 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 194
 195 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 196 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 197 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 198 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 199 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 200
 201 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 202 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 203 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 204 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 205 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 206
 207 #define PCI_VENDOR_ID_ROHM              0x10DB
 208
 209 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 210
 211 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 212 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 213 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 214 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 215 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 216 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 217
 218 struct pch_uart_buffer {
 219         unsigned char *buf;
 220         int size;
 221 };
 222
 223 struct eg20t_port {
 224         struct uart_port port;
 225         int port_type;
 226         void __iomem *membase;
 227         resource_size_t mapbase;
 228         unsigned int iobase;
 229         struct pci_dev *pdev;
 230         int fifo_size;
 231         unsigned int uartclk;
 232         int start_tx;
 233         int start_rx;
 234         int tx_empty;
 235         int trigger;
 236         int trigger_level;
 237         struct pch_uart_buffer rxbuf;
 238         unsigned int dmsr;
 239         unsigned int fcr;
 240         unsigned int mcr;
 241         unsigned int use_dma;
 242         struct dma_async_tx_descriptor  *desc_tx;
 243         struct dma_async_tx_descriptor  *desc_rx;
 244         struct pch_dma_slave            param_tx;
 245         struct pch_dma_slave            param_rx;
 246         struct dma_chan                 *chan_tx;
 247         struct dma_chan                 *chan_rx;
 248         struct scatterlist              *sg_tx_p;
 249         int                             nent;
 250         int                             orig_nent;
 251         struct scatterlist              sg_rx;
 252         int                             tx_dma_use;
 253         void                            *rx_buf_virt;
 254         dma_addr_t                      rx_buf_dma;
 255
 256         struct dentry   *debugfs;
 257 #define IRQ_NAME_SIZE 17
 258         char                            irq_name[IRQ_NAME_SIZE];
 259
 260         /* protect the eg20t_port private structure and io access to membase */
 261         spinlock_t lock;
 262 };
 263
 264 /**
 265  * struct pch_uart_driver_data - private data structure for UART-DMA
 266  * @port_type:                  The type of UART port
 267  * @line_no:                    UART port line number (0, 1, 2...)
 268  */
 269 struct pch_uart_driver_data {
 270         int port_type;
 271         int line_no;
 272 };
 273
 274 enum pch_uart_num_t {
 275         pch_et20t_uart0 = 0,
 276         pch_et20t_uart1,
 277         pch_et20t_uart2,
 278         pch_et20t_uart3,
 279         pch_ml7213_uart0,
 280         pch_ml7213_uart1,
 281         pch_ml7213_uart2,
 282         pch_ml7223_uart0,
 283         pch_ml7223_uart1,
 284         pch_ml7831_uart0,
 285         pch_ml7831_uart1,
 286 };
 287
 288 static struct pch_uart_driver_data drv_dat[] = {
 289         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 290         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 291         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 292         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 293         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 294         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 295         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 296         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 297         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 298         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 299         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 300 };
 301
 302 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 303 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 304 #endif
 305 static unsigned int default_baud = 9600;
 306 static unsigned int user_uartclk = 0;
 307 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 308 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 309 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 310 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 311
 312 #ifdef CONFIG_DEBUG_FS
 313
 314 #define PCH_REGS_BUFSIZE        1024
 315
 316
 317 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 318                                 size_t count, loff_t *ppos)
 319 {
 320         struct eg20t_port *priv = file->private_data;
 321         char *buf;
 322         u32 len = 0;
 323         ssize_t ret;
 324         unsigned char lcr;
 325
 326         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 327         if (!buf)
 328                 return 0;
 329
 330         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 331                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 332
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "=================================\n");
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 337         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 338                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 343         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 344                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 345         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 346                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 347         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 348                         "BRCSR: \t0x%02x\n",
 349                         ioread8(priv->membase + PCH_UART_BRCSR));
 350
 351         lcr = ioread8(priv->membase + UART_LCR);
 352         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 353         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 354                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 355         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 356                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 357         iowrite8(lcr, priv->membase + UART_LCR);
 358
 359         if (len > PCH_REGS_BUFSIZE)
 360                 len = PCH_REGS_BUFSIZE;
 361
 362         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 363         kfree(buf);
 364         return ret;
 365 }
 366
 367 static const struct file_operations port_regs_ops = {
 368         .owner          = THIS_MODULE,
 369         .open           = simple_open,
 370         .read           = port_show_regs,
 371         .llseek         = default_llseek,
 372 };
 373 #endif  /* CONFIG_DEBUG_FS */
 374
 375 static const struct dmi_system_id pch_uart_dmi_table[] = {
 376         {
 377                 .ident = "CM-iTC",
 378                 {
 379                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 380                 },
 381                 (void *)CMITC_UARTCLK,
 382         },
 383         {
 384                 .ident = "FRI2",
 385                 {
 386                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 387                 },
 388                 (void *)FRI2_64_UARTCLK,
 389         },
 390         {
 391                 .ident = "Fish River Island II",
 392                 {
 393                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 394                 },
 395                 (void *)FRI2_48_UARTCLK,
 396         },
 397         {
 398                 .ident = "COMe-mTT",
 399                 {
 400                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 401                 },
 402                 (void *)NTC1_UARTCLK,
 403         },
 404         {
 405                 .ident = "nanoETXexpress-TT",
 406                 {
 407                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 408                 },
 409                 (void *)NTC1_UARTCLK,
 410         },
 411         {
 412                 .ident = "MinnowBoard",
 413                 {
 414                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 415                 },
 416                 (void *)MINNOW_UARTCLK,
 417         },
 418         { }
 419 };
 420
 421 /* Return UART clock, checking for board specific clocks. */
 422 static unsigned int pch_uart_get_uartclk(void)
 423 {
 424         const struct dmi_system_id *d;
 425
 426         if (user_uartclk)
 427                 return user_uartclk;
 428
 429         d = dmi_first_match(pch_uart_dmi_table);
 430         if (d)
 431                 return (unsigned long)d->driver_data;
 432
 433         return DEFAULT_UARTCLK;
 434 }
 435
 436 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 437                                           unsigned int flag)
 438 {
 439         u8 ier = ioread8(priv->membase + UART_IER);
 440         ier |= flag & PCH_UART_IER_MASK;
 441         iowrite8(ier, priv->membase + UART_IER);
 442 }
 443
 444 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 445                                            unsigned int flag)
 446 {
 447         u8 ier = ioread8(priv->membase + UART_IER);
 448         ier &= ~(flag & PCH_UART_IER_MASK);
 449         iowrite8(ier, priv->membase + UART_IER);
 450 }
 451
 452 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 453                                  unsigned int parity, unsigned int bits,
 454                                  unsigned int stb)
 455 {
 456         unsigned int dll, dlm, lcr;
 457         int div;
 458
 459         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 460         if (div < 0 || USHRT_MAX <= div) {
 461                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 462                 return -EINVAL;
 463         }
 464
 465         dll = (unsigned int)div & 0x00FFU;
 466         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 467
 468         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 469                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 470                 return -EINVAL;
 471         }
 472
 473         if (bits & ~PCH_UART_LCR_WLS) {
 474                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 475                 return -EINVAL;
 476         }
 477
 478         if (stb & ~PCH_UART_LCR_STB) {
 479                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 480                 return -EINVAL;
 481         }
 482
 483         lcr = parity;
 484         lcr |= bits;
 485         lcr |= stb;
 486
 487         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 488                  __func__, baud, div, lcr, jiffies);
 489         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 490         iowrite8(dll, priv->membase + PCH_UART_DLL);
 491         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 492         iowrite8(lcr, priv->membase + UART_LCR);
 493
 494         return 0;
 495 }
 496
 497 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 498                                     unsigned int flag)
 499 {
 500         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 501                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 502                         __func__, flag);
 503                 return -EINVAL;
 504         }
 505
 506         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 507         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 508                  priv->membase + UART_FCR);
 509         iowrite8(priv->fcr, priv->membase + UART_FCR);
 510
 511         return 0;
 512 }
 513
 514 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 515                                  unsigned int dmamode,
 516                                  unsigned int fifo_size, unsigned int trigger)
 517 {
 518         u8 fcr;
 519
 520         if (dmamode & ~PCH_UART_FCR_DMS) {
 521                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 522                         __func__, dmamode);
 523                 return -EINVAL;
 524         }
 525
 526         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 527                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 528                         __func__, fifo_size);
 529                 return -EINVAL;
 530         }
 531
 532         if (trigger & ~PCH_UART_FCR_RFTL) {
 533                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 534                         __func__, trigger);
 535                 return -EINVAL;
 536         }
 537
 538         switch (priv->fifo_size) {
 539         case 256:
 540                 priv->trigger_level =
 541                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 542                 break;
 543         case 64:
 544                 priv->trigger_level =
 545                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 546                 break;
 547         case 16:
 548                 priv->trigger_level =
 549                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 550                 break;
 551         default:
 552                 priv->trigger_level =
 553                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 554                 break;
 555         }
 556         fcr =
 557             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 558         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 559         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 560                  priv->membase + UART_FCR);
 561         iowrite8(fcr, priv->membase + UART_FCR);
 562         priv->fcr = fcr;
 563
 564         return 0;
 565 }
 566
 567 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 568 {
 569         unsigned int msr = ioread8(priv->membase + UART_MSR);
 570         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 571         return (u8)msr;
 572 }
 573
 574 static void pch_uart_hal_write(struct eg20t_port *priv,
 575                               const unsigned char *buf, int tx_size)
 576 {
 577         int i;
 578         unsigned int thr;
 579
 580         for (i = 0; i < tx_size;) {
 581                 thr = buf[i++];
 582                 iowrite8(thr, priv->membase + PCH_UART_THR);
 583         }
 584 }
 585
 586 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 587                              int rx_size)
 588 {
 589         int i;
 590         u8 rbr, lsr;
 591         struct uart_port *port = &priv->port;
 592
 593         lsr = ioread8(priv->membase + UART_LSR);
 594         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 595              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 596              lsr = ioread8(priv->membase + UART_LSR)) {
 597                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 598
 599                 if (lsr & UART_LSR_BI) {
 600                         port->icount.brk++;
 601                         if (uart_handle_break(port))
 602                                 continue;
 603                 }
 604 #ifdef SUPPORT_SYSRQ
 605                 if (port->sysrq) {
 606                         if (uart_handle_sysrq_char(port, rbr))
 607                                 continue;
 608                 }
 609 #endif
 610
 611                 buf[i++] = rbr;
 612         }
 613         return i;
 614 }
 615
 616 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 617 {
 618         return ioread8(priv->membase + UART_IIR) &\
 619                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 620 }
 621
 622 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 623 {
 624         return ioread8(priv->membase + UART_LSR);
 625 }
 626
 627 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 628 {
 629         unsigned int lcr;
 630
 631         lcr = ioread8(priv->membase + UART_LCR);
 632         if (on)
 633                 lcr |= PCH_UART_LCR_SB;
 634         else
 635                 lcr &= ~PCH_UART_LCR_SB;
 636
 637         iowrite8(lcr, priv->membase + UART_LCR);
 638 }
 639
 640 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 641                    int size)
 642 {
 643         struct uart_port *port = &priv->port;
 644         struct tty_port *tport = &port->state->port;
 645
 646         tty_insert_flip_string(tport, buf, size);
 647         tty_flip_buffer_push(tport);
 648
 649         return 0;
 650 }
 651
 652 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 653 {
 654         int ret = 0;
 655         struct uart_port *port = &priv->port;
 656
 657         if (port->x_char) {
 658                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 659                         __func__, port->x_char, jiffies);
 660                 buf[0] = port->x_char;
 661                 port->x_char = 0;
 662                 ret = 1;
 663         }
 664
 665         return ret;
 666 }
 667
 668 static int dma_push_rx(struct eg20t_port *priv, int size)
 669 {
 670         int room;
 671         struct uart_port *port = &priv->port;
 672         struct tty_port *tport = &port->state->port;
 673
 674         room = tty_buffer_request_room(tport, size);
 675
 676         if (room < size)
 677                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 678                          size - room);
 679         if (!room)
 680                 return 0;
 681
 682         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 683
 684         port->icount.rx += room;
 685
 686         return room;
 687 }
 688
 689 static void pch_free_dma(struct uart_port *port)
 690 {
 691         struct eg20t_port *priv;
 692         priv = container_of(port, struct eg20t_port, port);
 693
 694         if (priv->chan_tx) {
 695                 dma_release_channel(priv->chan_tx);
 696                 priv->chan_tx = NULL;
 697         }
 698         if (priv->chan_rx) {
 699                 dma_release_channel(priv->chan_rx);
 700                 priv->chan_rx = NULL;
 701         }
 702
 703         if (priv->rx_buf_dma) {
 704                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 705                                   priv->rx_buf_dma);
 706                 priv->rx_buf_virt = NULL;
 707                 priv->rx_buf_dma = 0;
 708         }
 709
 710         return;
 711 }
 712
 713 static bool filter(struct dma_chan *chan, void *slave)
 714 {
 715         struct pch_dma_slave *param = slave;
 716
 717         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 718                                                   chan->device->dev)) {
 719                 chan->private = param;
 720                 return true;
 721         } else {
 722                 return false;
 723         }
 724 }
 725
 726 static void pch_request_dma(struct uart_port *port)
 727 {
 728         dma_cap_mask_t mask;
 729         struct dma_chan *chan;
 730         struct pci_dev *dma_dev;
 731         struct pch_dma_slave *param;
 732         struct eg20t_port *priv =
 733                                 container_of(port, struct eg20t_port, port);
 734         dma_cap_zero(mask);
 735         dma_cap_set(DMA_SLAVE, mask);
 736
 737         /* Get DMA's dev information */
 738         dma_dev = pci_get_slot(priv->pdev->bus,
 739                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 740
 741         /* Set Tx DMA */
 742         param = &priv->param_tx;
 743         param->dma_dev = &dma_dev->dev;
 744         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 745
 746         param->tx_reg = port->mapbase + UART_TX;
 747         chan = dma_request_channel(mask, filter, param);
 748         if (!chan) {
 749                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 750                         __func__);
 751                 return;
 752         }
 753         priv->chan_tx = chan;
 754
 755         /* Set Rx DMA */
 756         param = &priv->param_rx;
 757         param->dma_dev = &dma_dev->dev;
 758         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 759
 760         param->rx_reg = port->mapbase + UART_RX;
 761         chan = dma_request_channel(mask, filter, param);
 762         if (!chan) {
 763                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 764                         __func__);
 765                 dma_release_channel(priv->chan_tx);
 766                 priv->chan_tx = NULL;
 767                 return;
 768         }
 769
 770         /* Get Consistent memory for DMA */
 771         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 772                                     &priv->rx_buf_dma, GFP_KERNEL);
 773         priv->chan_rx = chan;
 774 }
 775
 776 static void pch_dma_rx_complete(void *arg)
 777 {
 778         struct eg20t_port *priv = arg;
 779         struct uart_port *port = &priv->port;
 780         int count;
 781
 782         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 783         count = dma_push_rx(priv, priv->trigger_level);
 784         if (count)
 785                 tty_flip_buffer_push(&port->state->port);
 786         async_tx_ack(priv->desc_rx);
 787         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 788                                             PCH_UART_HAL_RX_ERR_INT);
 789 }
 790
 791 static void pch_dma_tx_complete(void *arg)
 792 {
 793         struct eg20t_port *priv = arg;
 794         struct uart_port *port = &priv->port;
 795         struct circ_buf *xmit = &port->state->xmit;
 796         struct scatterlist *sg = priv->sg_tx_p;
 797         int i;
 798
 799         for (i = 0; i < priv->nent; i++, sg++) {
 800                 xmit->tail += sg_dma_len(sg);
 801                 port->icount.tx += sg_dma_len(sg);
 802         }
 803         xmit->tail &= UART_XMIT_SIZE - 1;
 804         async_tx_ack(priv->desc_tx);
 805         dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
 806         priv->tx_dma_use = 0;
 807         priv->nent = 0;
 808         priv->orig_nent = 0;
 809         kfree(priv->sg_tx_p);
 810         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 811 }
 812
 813 static int pop_tx(struct eg20t_port *priv, int size)
 814 {
 815         int count = 0;
 816         struct uart_port *port = &priv->port;
 817         struct circ_buf *xmit = &port->state->xmit;
 818
 819         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 820                 goto pop_tx_end;
 821
 822         do {
 823                 int cnt_to_end =
 824                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 825                 int sz = min(size - count, cnt_to_end);
 826                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 827                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 828                 count += sz;
 829         } while (!uart_circ_empty(xmit) && count < size);
 830
 831 pop_tx_end:
 832         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 833                  count, size - count, jiffies);
 834
 835         return count;
 836 }
 837
 838 static int handle_rx_to(struct eg20t_port *priv)
 839 {
 840         struct pch_uart_buffer *buf;
 841         int rx_size;
 842         int ret;
 843         if (!priv->start_rx) {
 844                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 845                                                      PCH_UART_HAL_RX_ERR_INT);
 846                 return 0;
 847         }
 848         buf = &priv->rxbuf;
 849         do {
 850                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 851                 ret = push_rx(priv, buf->buf, rx_size);
 852                 if (ret)
 853                         return 0;
 854         } while (rx_size == buf->size);
 855
 856         return PCH_UART_HANDLED_RX_INT;
 857 }
 858
 859 static int handle_rx(struct eg20t_port *priv)
 860 {
 861         return handle_rx_to(priv);
 862 }
 863
 864 static int dma_handle_rx(struct eg20t_port *priv)
 865 {
 866         struct uart_port *port = &priv->port;
 867         struct dma_async_tx_descriptor *desc;
 868         struct scatterlist *sg;
 869
 870         priv = container_of(port, struct eg20t_port, port);
 871         sg = &priv->sg_rx;
 872
 873         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 874
 875         sg_dma_len(sg) = priv->trigger_level;
 876
 877         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 878                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 879
 880         sg_dma_address(sg) = priv->rx_buf_dma;
 881
 882         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 883                         sg, 1, DMA_DEV_TO_MEM,
 884                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 885
 886         if (!desc)
 887                 return 0;
 888
 889         priv->desc_rx = desc;
 890         desc->callback = pch_dma_rx_complete;
 891         desc->callback_param = priv;
 892         desc->tx_submit(desc);
 893         dma_async_issue_pending(priv->chan_rx);
 894
 895         return PCH_UART_HANDLED_RX_INT;
 896 }
 897
 898 static unsigned int handle_tx(struct eg20t_port *priv)
 899 {
 900         struct uart_port *port = &priv->port;
 901         struct circ_buf *xmit = &port->state->xmit;
 902         int fifo_size;
 903         int tx_size;
 904         int size;
 905         int tx_empty;
 906
 907         if (!priv->start_tx) {
 908                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 909                         __func__, jiffies);
 910                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 911                 priv->tx_empty = 1;
 912                 return 0;
 913         }
 914
 915         fifo_size = max(priv->fifo_size, 1);
 916         tx_empty = 1;
 917         if (pop_tx_x(priv, xmit->buf)) {
 918                 pch_uart_hal_write(priv, xmit->buf, 1);
 919                 port->icount.tx++;
 920                 tx_empty = 0;
 921                 fifo_size--;
 922         }
 923         size = min(xmit->head - xmit->tail, fifo_size);
 924         if (size < 0)
 925                 size = fifo_size;
 926
 927         tx_size = pop_tx(priv, size);
 928         if (tx_size > 0) {
 929                 port->icount.tx += tx_size;
 930                 tx_empty = 0;
 931         }
 932
 933         priv->tx_empty = tx_empty;
 934
 935         if (tx_empty) {
 936                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 937                 uart_write_wakeup(port);
 938         }
 939
 940         return PCH_UART_HANDLED_TX_INT;
 941 }
 942
 943 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 944 {
 945         struct uart_port *port = &priv->port;
 946         struct circ_buf *xmit = &port->state->xmit;
 947         struct scatterlist *sg;
 948         int nent;
 949         int fifo_size;
 950         int tx_empty;
 951         struct dma_async_tx_descriptor *desc;
 952         int num;
 953         int i;
 954         int bytes;
 955         int size;
 956         int rem;
 957
 958         if (!priv->start_tx) {
 959                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 960                         __func__, jiffies);
 961                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 962                 priv->tx_empty = 1;
 963                 return 0;
 964         }
 965
 966         if (priv->tx_dma_use) {
 967                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 968                         __func__, jiffies);
 969                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 970                 priv->tx_empty = 1;
 971                 return 0;
 972         }
 973
 974         fifo_size = max(priv->fifo_size, 1);
 975         tx_empty = 1;
 976         if (pop_tx_x(priv, xmit->buf)) {
 977                 pch_uart_hal_write(priv, xmit->buf, 1);
 978                 port->icount.tx++;
 979                 tx_empty = 0;
 980                 fifo_size--;
 981         }
 982
 983         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 984                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 985                              xmit->tail, UART_XMIT_SIZE));
 986         if (!bytes) {
 987                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 988                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 989                 uart_write_wakeup(port);
 990                 return 0;
 991         }
 992
 993         if (bytes > fifo_size) {
 994                 num = bytes / fifo_size + 1;
 995                 size = fifo_size;
 996                 rem = bytes % fifo_size;
 997         } else {
 998                 num = 1;
 999                 size = bytes;
1000                 rem = bytes;
1001         }
1002
1003         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1004                 __func__, num, size, rem);
1005
1006         priv->tx_dma_use = 1;
1007
1008         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1009         if (!priv->sg_tx_p) {
1010                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1011                 return 0;
1012         }
1013
1014         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1015         sg = priv->sg_tx_p;
1016
1017         for (i = 0; i < num; i++, sg++) {
1018                 if (i == (num - 1))
1019                         sg_set_page(sg, virt_to_page(xmit->buf),
1020                                     rem, fifo_size * i);
1021                 else
1022                         sg_set_page(sg, virt_to_page(xmit->buf),
1023                                     size, fifo_size * i);
1024         }
1025
1026         sg = priv->sg_tx_p;
1027         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1028         if (!nent) {
1029                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1030                 return 0;
1031         }
1032         priv->orig_nent = num;
1033         priv->nent = nent;
1034
1035         for (i = 0; i < nent; i++, sg++) {
1036                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1037                               fifo_size * i;
1038                 sg_dma_address(sg) = (sg_dma_address(sg) &
1039                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1040                 if (i == (nent - 1))
1041                         sg_dma_len(sg) = rem;
1042                 else
1043                         sg_dma_len(sg) = size;
1044         }
1045
1046         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1047                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1048                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1049         if (!desc) {
1050                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1051                         __func__);
1052                 return 0;
1053         }
1054         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1055         priv->desc_tx = desc;
1056         desc->callback = pch_dma_tx_complete;
1057         desc->callback_param = priv;
1058
1059         desc->tx_submit(desc);
1060
1061         dma_async_issue_pending(priv->chan_tx);
1062
1063         return PCH_UART_HANDLED_TX_INT;
1064 }
1065
1066 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1067 {
1068         struct uart_port *port = &priv->port;
1069         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1070         char   *error_msg[5] = {};
1071         int    i = 0;
1072
1073         if (lsr & PCH_UART_LSR_ERR)
1074                 error_msg[i++] = "Error data in FIFO\n";
1075
1076         if (lsr & UART_LSR_FE) {
1077                 port->icount.frame++;
1078                 error_msg[i++] = "  Framing Error\n";
1079         }
1080
1081         if (lsr & UART_LSR_PE) {
1082                 port->icount.parity++;
1083                 error_msg[i++] = "  Parity Error\n";
1084         }
1085
1086         if (lsr & UART_LSR_OE) {
1087                 port->icount.overrun++;
1088                 error_msg[i++] = "  Overrun Error\n";
1089         }
1090
1091         if (tty == NULL) {
1092                 for (i = 0; error_msg[i] != NULL; i++)
1093                         dev_err(&priv->pdev->dev, error_msg[i]);
1094         } else {
1095                 tty_kref_put(tty);
1096         }
1097 }
1098
1099 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1100 {
1101         struct eg20t_port *priv = dev_id;
1102         unsigned int handled;
1103         u8 lsr;
1104         int ret = 0;
1105         unsigned char iid;
1106         unsigned long flags;
1107         int next = 1;
1108         u8 msr;
1109
1110         spin_lock_irqsave(&priv->lock, flags);
1111         handled = 0;
1112         while (next) {
1113                 iid = pch_uart_hal_get_iid(priv);
1114                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1115                         break;
1116                 switch (iid) {
1117                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1118                         lsr = pch_uart_hal_get_line_status(priv);
1119                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1120                                                 UART_LSR_PE | UART_LSR_OE)) {
1121                                 pch_uart_err_ir(priv, lsr);
1122                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1123                         } else {
1124                                 ret = PCH_UART_HANDLED_LS_INT;
1125                         }
1126                         break;
1127                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1128                         if (priv->use_dma) {
1129                                 pch_uart_hal_disable_interrupt(priv,
1130                                                 PCH_UART_HAL_RX_INT |
1131                                                 PCH_UART_HAL_RX_ERR_INT);
1132                                 ret = dma_handle_rx(priv);
1133                                 if (!ret)
1134                                         pch_uart_hal_enable_interrupt(priv,
1135                                                 PCH_UART_HAL_RX_INT |
1136                                                 PCH_UART_HAL_RX_ERR_INT);
1137                         } else {
1138                                 ret = handle_rx(priv);
1139                         }
1140                         break;
1141                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1142                                                    (FIFO Timeout) */
1143                         ret = handle_rx_to(priv);
1144                         break;
1145                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1146                                                    Empty */
1147                         if (priv->use_dma)
1148                                 ret = dma_handle_tx(priv);
1149                         else
1150                                 ret = handle_tx(priv);
1151                         break;
1152                 case PCH_UART_IID_MS:   /* Modem Status */
1153                         msr = pch_uart_hal_get_modem(priv);
1154                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1155                                      means final interrupt */
1156                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1157                                 break;
1158                         ret |= PCH_UART_HANDLED_MS_INT;
1159                         break;
1160                 default:        /* Never junp to this label */
1161                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1162                                 iid, jiffies);
1163                         ret = -1;
1164                         next = 0;
1165                         break;
1166                 }
1167                 handled |= (unsigned int)ret;
1168         }
1169
1170         spin_unlock_irqrestore(&priv->lock, flags);
1171         return IRQ_RETVAL(handled);
1172 }
1173
1174 /* This function tests whether the transmitter fifo and shifter for the port
1175                                                 described by 'port' is empty. */
1176 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1177 {
1178         struct eg20t_port *priv;
1179
1180         priv = container_of(port, struct eg20t_port, port);
1181         if (priv->tx_empty)
1182                 return TIOCSER_TEMT;
1183         else
1184                 return 0;
1185 }
1186
1187 /* Returns the current state of modem control inputs. */
1188 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1189 {
1190         struct eg20t_port *priv;
1191         u8 modem;
1192         unsigned int ret = 0;
1193
1194         priv = container_of(port, struct eg20t_port, port);
1195         modem = pch_uart_hal_get_modem(priv);
1196
1197         if (modem & UART_MSR_DCD)
1198                 ret |= TIOCM_CAR;
1199
1200         if (modem & UART_MSR_RI)
1201                 ret |= TIOCM_RNG;
1202
1203         if (modem & UART_MSR_DSR)
1204                 ret |= TIOCM_DSR;
1205
1206         if (modem & UART_MSR_CTS)
1207                 ret |= TIOCM_CTS;
1208
1209         return ret;
1210 }
1211
1212 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1213 {
1214         u32 mcr = 0;
1215         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1216
1217         if (mctrl & TIOCM_DTR)
1218                 mcr |= UART_MCR_DTR;
1219         if (mctrl & TIOCM_RTS)
1220                 mcr |= UART_MCR_RTS;
1221         if (mctrl & TIOCM_LOOP)
1222                 mcr |= UART_MCR_LOOP;
1223
1224         if (priv->mcr & UART_MCR_AFE)
1225                 mcr |= UART_MCR_AFE;
1226
1227         if (mctrl)
1228                 iowrite8(mcr, priv->membase + UART_MCR);
1229 }
1230
1231 static void pch_uart_stop_tx(struct uart_port *port)
1232 {
1233         struct eg20t_port *priv;
1234         priv = container_of(port, struct eg20t_port, port);
1235         priv->start_tx = 0;
1236         priv->tx_dma_use = 0;
1237 }
1238
1239 static void pch_uart_start_tx(struct uart_port *port)
1240 {
1241         struct eg20t_port *priv;
1242
1243         priv = container_of(port, struct eg20t_port, port);
1244
1245         if (priv->use_dma) {
1246                 if (priv->tx_dma_use) {
1247                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1248                                 __func__);
1249                         return;
1250                 }
1251         }
1252
1253         priv->start_tx = 1;
1254         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1255 }
1256
1257 static void pch_uart_stop_rx(struct uart_port *port)
1258 {
1259         struct eg20t_port *priv;
1260         priv = container_of(port, struct eg20t_port, port);
1261         priv->start_rx = 0;
1262         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1263                                              PCH_UART_HAL_RX_ERR_INT);
1264 }
1265
1266 /* Enable the modem status interrupts. */
1267 static void pch_uart_enable_ms(struct uart_port *port)
1268 {
1269         struct eg20t_port *priv;
1270         priv = container_of(port, struct eg20t_port, port);
1271         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1272 }
1273
1274 /* Control the transmission of a break signal. */
1275 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1276 {
1277         struct eg20t_port *priv;
1278         unsigned long flags;
1279
1280         priv = container_of(port, struct eg20t_port, port);
1281         spin_lock_irqsave(&priv->lock, flags);
1282         pch_uart_hal_set_break(priv, ctl);
1283         spin_unlock_irqrestore(&priv->lock, flags);
1284 }
1285
1286 /* Grab any interrupt resources and initialise any low level driver state. */
1287 static int pch_uart_startup(struct uart_port *port)
1288 {
1289         struct eg20t_port *priv;
1290         int ret;
1291         int fifo_size;
1292         int trigger_level;
1293
1294         priv = container_of(port, struct eg20t_port, port);
1295         priv->tx_empty = 1;
1296
1297         if (port->uartclk)
1298                 priv->uartclk = port->uartclk;
1299         else
1300                 port->uartclk = priv->uartclk;
1301
1302         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1303         ret = pch_uart_hal_set_line(priv, default_baud,
1304                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1305                               PCH_UART_HAL_STB1);
1306         if (ret)
1307                 return ret;
1308
1309         switch (priv->fifo_size) {
1310         case 256:
1311                 fifo_size = PCH_UART_HAL_FIFO256;
1312                 break;
1313         case 64:
1314                 fifo_size = PCH_UART_HAL_FIFO64;
1315                 break;
1316         case 16:
1317                 fifo_size = PCH_UART_HAL_FIFO16;
1318                 break;
1319         case 1:
1320         default:
1321                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1322                 break;
1323         }
1324
1325         switch (priv->trigger) {
1326         case PCH_UART_HAL_TRIGGER1:
1327                 trigger_level = 1;
1328                 break;
1329         case PCH_UART_HAL_TRIGGER_L:
1330                 trigger_level = priv->fifo_size / 4;
1331                 break;
1332         case PCH_UART_HAL_TRIGGER_M:
1333                 trigger_level = priv->fifo_size / 2;
1334                 break;
1335         case PCH_UART_HAL_TRIGGER_H:
1336         default:
1337                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1338                 break;
1339         }
1340
1341         priv->trigger_level = trigger_level;
1342         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1343                                     fifo_size, priv->trigger);
1344         if (ret < 0)
1345                 return ret;
1346
1347         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1348                         priv->irq_name, priv);
1349         if (ret < 0)
1350                 return ret;
1351
1352         if (priv->use_dma)
1353                 pch_request_dma(port);
1354
1355         priv->start_rx = 1;
1356         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1357                                             PCH_UART_HAL_RX_ERR_INT);
1358         uart_update_timeout(port, CS8, default_baud);
1359
1360         return 0;
1361 }
1362
1363 static void pch_uart_shutdown(struct uart_port *port)
1364 {
1365         struct eg20t_port *priv;
1366         int ret;
1367
1368         priv = container_of(port, struct eg20t_port, port);
1369         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1370         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1371         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1372                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1373         if (ret)
1374                 dev_err(priv->port.dev,
1375                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1376
1377         pch_free_dma(port);
1378
1379         free_irq(priv->port.irq, priv);
1380 }
1381
1382 /* Change the port parameters, including word length, parity, stop
1383  *bits.  Update read_status_mask and ignore_status_mask to indicate
1384  *the types of events we are interested in receiving.  */
1385 static void pch_uart_set_termios(struct uart_port *port,
1386                                  struct ktermios *termios, struct ktermios *old)
1387 {
1388         int rtn;
1389         unsigned int baud, parity, bits, stb;
1390         struct eg20t_port *priv;
1391         unsigned long flags;
1392
1393         priv = container_of(port, struct eg20t_port, port);
1394         switch (termios->c_cflag & CSIZE) {
1395         case CS5:
1396                 bits = PCH_UART_HAL_5BIT;
1397                 break;
1398         case CS6:
1399                 bits = PCH_UART_HAL_6BIT;
1400                 break;
1401         case CS7:
1402                 bits = PCH_UART_HAL_7BIT;
1403                 break;
1404         default:                /* CS8 */
1405                 bits = PCH_UART_HAL_8BIT;
1406                 break;
1407         }
1408         if (termios->c_cflag & CSTOPB)
1409                 stb = PCH_UART_HAL_STB2;
1410         else
1411                 stb = PCH_UART_HAL_STB1;
1412
1413         if (termios->c_cflag & PARENB) {
1414                 if (termios->c_cflag & PARODD)
1415                         parity = PCH_UART_HAL_PARITY_ODD;
1416                 else
1417                         parity = PCH_UART_HAL_PARITY_EVEN;
1418
1419         } else
1420                 parity = PCH_UART_HAL_PARITY_NONE;
1421
1422         /* Only UART0 has auto hardware flow function */
1423         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1424                 priv->mcr |= UART_MCR_AFE;
1425         else
1426                 priv->mcr &= ~UART_MCR_AFE;
1427
1428         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1429
1430         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1431
1432         spin_lock_irqsave(&priv->lock, flags);
1433         spin_lock(&port->lock);
1434
1435         uart_update_timeout(port, termios->c_cflag, baud);
1436         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1437         if (rtn)
1438                 goto out;
1439
1440         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1441         /* Don't rewrite B0 */
1442         if (tty_termios_baud_rate(termios))
1443                 tty_termios_encode_baud_rate(termios, baud, baud);
1444
1445 out:
1446         spin_unlock(&port->lock);
1447         spin_unlock_irqrestore(&priv->lock, flags);
1448 }
1449
1450 static const char *pch_uart_type(struct uart_port *port)
1451 {
1452         return KBUILD_MODNAME;
1453 }
1454
1455 static void pch_uart_release_port(struct uart_port *port)
1456 {
1457         struct eg20t_port *priv;
1458
1459         priv = container_of(port, struct eg20t_port, port);
1460         pci_iounmap(priv->pdev, priv->membase);
1461         pci_release_regions(priv->pdev);
1462 }
1463
1464 static int pch_uart_request_port(struct uart_port *port)
1465 {
1466         struct eg20t_port *priv;
1467         int ret;
1468         void __iomem *membase;
1469
1470         priv = container_of(port, struct eg20t_port, port);
1471         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1472         if (ret < 0)
1473                 return -EBUSY;
1474
1475         membase = pci_iomap(priv->pdev, 1, 0);
1476         if (!membase) {
1477                 pci_release_regions(priv->pdev);
1478                 return -EBUSY;
1479         }
1480         priv->membase = port->membase = membase;
1481
1482         return 0;
1483 }
1484
1485 static void pch_uart_config_port(struct uart_port *port, int type)
1486 {
1487         struct eg20t_port *priv;
1488
1489         priv = container_of(port, struct eg20t_port, port);
1490         if (type & UART_CONFIG_TYPE) {
1491                 port->type = priv->port_type;
1492                 pch_uart_request_port(port);
1493         }
1494 }
1495
1496 static int pch_uart_verify_port(struct uart_port *port,
1497                                 struct serial_struct *serinfo)
1498 {
1499         struct eg20t_port *priv;
1500
1501         priv = container_of(port, struct eg20t_port, port);
1502         if (serinfo->flags & UPF_LOW_LATENCY) {
1503                 dev_info(priv->port.dev,
1504                         "PCH UART : Use PIO Mode (without DMA)\n");
1505                 priv->use_dma = 0;
1506                 serinfo->flags &= ~UPF_LOW_LATENCY;
1507         } else {
1508 #ifndef CONFIG_PCH_DMA
1509                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1510                         __func__);
1511                 return -EOPNOTSUPP;
1512 #endif
1513                 if (!priv->use_dma) {
1514                         pch_request_dma(port);
1515                         if (priv->chan_rx)
1516                                 priv->use_dma = 1;
1517                 }
1518                 dev_info(priv->port.dev, "PCH UART: %s\n",
1519                                 priv->use_dma ?
1520                                 "Use DMA Mode" : "No DMA");
1521         }
1522
1523         return 0;
1524 }
1525
1526 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1527 /*
1528  *      Wait for transmitter & holding register to empty
1529  */
1530 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1531 {
1532         unsigned int status, tmout = 10000;
1533
1534         /* Wait up to 10ms for the character(s) to be sent. */
1535         for (;;) {
1536                 status = ioread8(up->membase + UART_LSR);
1537
1538                 if ((status & bits) == bits)
1539                         break;
1540                 if (--tmout == 0)
1541                         break;
1542                 udelay(1);
1543         }
1544
1545         /* Wait up to 1s for flow control if necessary */
1546         if (up->port.flags & UPF_CONS_FLOW) {
1547                 unsigned int tmout;
1548                 for (tmout = 1000000; tmout; tmout--) {
1549                         unsigned int msr = ioread8(up->membase + UART_MSR);
1550                         if (msr & UART_MSR_CTS)
1551                                 break;
1552                         udelay(1);
1553                         touch_nmi_watchdog();
1554                 }
1555         }
1556 }
1557 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1558
1559 #ifdef CONFIG_CONSOLE_POLL
1560 /*
1561  * Console polling routines for communicate via uart while
1562  * in an interrupt or debug context.
1563  */
1564 static int pch_uart_get_poll_char(struct uart_port *port)
1565 {
1566         struct eg20t_port *priv =
1567                 container_of(port, struct eg20t_port, port);
1568         u8 lsr = ioread8(priv->membase + UART_LSR);
1569
1570         if (!(lsr & UART_LSR_DR))
1571                 return NO_POLL_CHAR;
1572
1573         return ioread8(priv->membase + PCH_UART_RBR);
1574 }
1575
1576
1577 static void pch_uart_put_poll_char(struct uart_port *port,
1578                          unsigned char c)
1579 {
1580         unsigned int ier;
1581         struct eg20t_port *priv =
1582                 container_of(port, struct eg20t_port, port);
1583
1584         /*
1585          * First save the IER then disable the interrupts
1586          */
1587         ier = ioread8(priv->membase + UART_IER);
1588         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1589
1590         wait_for_xmitr(priv, UART_LSR_THRE);
1591         /*
1592          * Send the character out.
1593          */
1594         iowrite8(c, priv->membase + PCH_UART_THR);
1595
1596         /*
1597          * Finally, wait for transmitter to become empty
1598          * and restore the IER
1599          */
1600         wait_for_xmitr(priv, BOTH_EMPTY);
1601         iowrite8(ier, priv->membase + UART_IER);
1602 }
1603 #endif /* CONFIG_CONSOLE_POLL */
1604
1605 static const struct uart_ops pch_uart_ops = {
1606         .tx_empty = pch_uart_tx_empty,
1607         .set_mctrl = pch_uart_set_mctrl,
1608         .get_mctrl = pch_uart_get_mctrl,
1609         .stop_tx = pch_uart_stop_tx,
1610         .start_tx = pch_uart_start_tx,
1611         .stop_rx = pch_uart_stop_rx,
1612         .enable_ms = pch_uart_enable_ms,
1613         .break_ctl = pch_uart_break_ctl,
1614         .startup = pch_uart_startup,
1615         .shutdown = pch_uart_shutdown,
1616         .set_termios = pch_uart_set_termios,
1617 /*      .pm             = pch_uart_pm,          Not supported yet */
1618         .type = pch_uart_type,
1619         .release_port = pch_uart_release_port,
1620         .request_port = pch_uart_request_port,
1621         .config_port = pch_uart_config_port,
1622         .verify_port = pch_uart_verify_port,
1623 #ifdef CONFIG_CONSOLE_POLL
1624         .poll_get_char = pch_uart_get_poll_char,
1625         .poll_put_char = pch_uart_put_poll_char,
1626 #endif
1627 };
1628
1629 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1630
1631 static void pch_console_putchar(struct uart_port *port, int ch)
1632 {
1633         struct eg20t_port *priv =
1634                 container_of(port, struct eg20t_port, port);
1635
1636         wait_for_xmitr(priv, UART_LSR_THRE);
1637         iowrite8(ch, priv->membase + PCH_UART_THR);
1638 }
1639
1640 /*
1641  *      Print a string to the serial port trying not to disturb
1642  *      any possible real use of the port...
1643  *
1644  *      The console_lock must be held when we get here.
1645  */
1646 static void
1647 pch_console_write(struct console *co, const char *s, unsigned int count)
1648 {
1649         struct eg20t_port *priv;
1650         unsigned long flags;
1651         int priv_locked = 1;
1652         int port_locked = 1;
1653         u8 ier;
1654
1655         priv = pch_uart_ports[co->index];
1656
1657         touch_nmi_watchdog();
1658
1659         local_irq_save(flags);
1660         if (priv->port.sysrq) {
1661                 /* call to uart_handle_sysrq_char already took the priv lock */
1662                 priv_locked = 0;
1663                 /* serial8250_handle_port() already took the port lock */
1664                 port_locked = 0;
1665         } else if (oops_in_progress) {
1666                 priv_locked = spin_trylock(&priv->lock);
1667                 port_locked = spin_trylock(&priv->port.lock);
1668         } else {
1669                 spin_lock(&priv->lock);
1670                 spin_lock(&priv->port.lock);
1671         }
1672
1673         /*
1674          *      First save the IER then disable the interrupts
1675          */
1676         ier = ioread8(priv->membase + UART_IER);
1677
1678         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1679
1680         uart_console_write(&priv->port, s, count, pch_console_putchar);
1681
1682         /*
1683          *      Finally, wait for transmitter to become empty
1684          *      and restore the IER
1685          */
1686         wait_for_xmitr(priv, BOTH_EMPTY);
1687         iowrite8(ier, priv->membase + UART_IER);
1688
1689         if (port_locked)
1690                 spin_unlock(&priv->port.lock);
1691         if (priv_locked)
1692                 spin_unlock(&priv->lock);
1693         local_irq_restore(flags);
1694 }
1695
1696 static int __init pch_console_setup(struct console *co, char *options)
1697 {
1698         struct uart_port *port;
1699         int baud = default_baud;
1700         int bits = 8;
1701         int parity = 'n';
1702         int flow = 'n';
1703
1704         /*
1705          * Check whether an invalid uart number has been specified, and
1706          * if so, search for the first available port that does have
1707          * console support.
1708          */
1709         if (co->index >= PCH_UART_NR)
1710                 co->index = 0;
1711         port = &pch_uart_ports[co->index]->port;
1712
1713         if (!port || (!port->iobase && !port->membase))
1714                 return -ENODEV;
1715
1716         port->uartclk = pch_uart_get_uartclk();
1717
1718         if (options)
1719                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1720
1721         return uart_set_options(port, co, baud, parity, bits, flow);
1722 }
1723
1724 static struct uart_driver pch_uart_driver;
1725
1726 static struct console pch_console = {
1727         .name           = PCH_UART_DRIVER_DEVICE,
1728         .write          = pch_console_write,
1729         .device         = uart_console_device,
1730         .setup          = pch_console_setup,
1731         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1732         .index          = -1,
1733         .data           = &pch_uart_driver,
1734 };
1735
1736 #define PCH_CONSOLE     (&pch_console)
1737 #else
1738 #define PCH_CONSOLE     NULL
1739 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1740
1741 static struct uart_driver pch_uart_driver = {
1742         .owner = THIS_MODULE,
1743         .driver_name = KBUILD_MODNAME,
1744         .dev_name = PCH_UART_DRIVER_DEVICE,
1745         .major = 0,
1746         .minor = 0,
1747         .nr = PCH_UART_NR,
1748         .cons = PCH_CONSOLE,
1749 };
1750
1751 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1752                                              const struct pci_device_id *id)
1753 {
1754         struct eg20t_port *priv;
1755         int ret;
1756         unsigned int iobase;
1757         unsigned int mapbase;
1758         unsigned char *rxbuf;
1759         int fifosize;
1760         int port_type;
1761         struct pch_uart_driver_data *board;
1762 #ifdef CONFIG_DEBUG_FS
1763         char name[32];  /* for debugfs file name */
1764 #endif
1765
1766         board = &drv_dat[id->driver_data];
1767         port_type = board->port_type;
1768
1769         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1770         if (priv == NULL)
1771                 goto init_port_alloc_err;
1772
1773         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1774         if (!rxbuf)
1775                 goto init_port_free_txbuf;
1776
1777         switch (port_type) {
1778         case PORT_PCH_8LINE:
1779                 fifosize = 256; /* EG20T/ML7213: UART0 */
1780                 break;
1781         case PORT_PCH_2LINE:
1782                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1783                 break;
1784         default:
1785                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1786                 goto init_port_hal_free;
1787         }
1788
1789         pci_enable_msi(pdev);
1790         pci_set_master(pdev);
1791
1792         spin_lock_init(&priv->lock);
1793
1794         iobase = pci_resource_start(pdev, 0);
1795         mapbase = pci_resource_start(pdev, 1);
1796         priv->mapbase = mapbase;
1797         priv->iobase = iobase;
1798         priv->pdev = pdev;
1799         priv->tx_empty = 1;
1800         priv->rxbuf.buf = rxbuf;
1801         priv->rxbuf.size = PAGE_SIZE;
1802
1803         priv->fifo_size = fifosize;
1804         priv->uartclk = pch_uart_get_uartclk();
1805         priv->port_type = port_type;
1806         priv->port.dev = &pdev->dev;
1807         priv->port.iobase = iobase;
1808         priv->port.membase = NULL;
1809         priv->port.mapbase = mapbase;
1810         priv->port.irq = pdev->irq;
1811         priv->port.iotype = UPIO_PORT;
1812         priv->port.ops = &pch_uart_ops;
1813         priv->port.flags = UPF_BOOT_AUTOCONF;
1814         priv->port.fifosize = fifosize;
1815         priv->port.line = board->line_no;
1816         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1817
1818         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1819                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1820                  priv->port.line);
1821
1822         spin_lock_init(&priv->port.lock);
1823
1824         pci_set_drvdata(pdev, priv);
1825         priv->trigger_level = 1;
1826         priv->fcr = 0;
1827
1828         if (pdev->dev.of_node)
1829                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1830                                          , &user_uartclk);
1831
1832 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1833         pch_uart_ports[board->line_no] = priv;
1834 #endif
1835         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1836         if (ret < 0)
1837                 goto init_port_hal_free;
1838
1839 #ifdef CONFIG_DEBUG_FS
1840         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1841         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1842                                 NULL, priv, &port_regs_ops);
1843 #endif
1844
1845         return priv;
1846
1847 init_port_hal_free:
1848 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1849         pch_uart_ports[board->line_no] = NULL;
1850 #endif
1851         free_page((unsigned long)rxbuf);
1852 init_port_free_txbuf:
1853         kfree(priv);
1854 init_port_alloc_err:
1855
1856         return NULL;
1857 }
1858
1859 static void pch_uart_exit_port(struct eg20t_port *priv)
1860 {
1861
1862 #ifdef CONFIG_DEBUG_FS
1863         debugfs_remove(priv->debugfs);
1864 #endif
1865         uart_remove_one_port(&pch_uart_driver, &priv->port);
1866         free_page((unsigned long)priv->rxbuf.buf);
1867 }
1868
1869 static void pch_uart_pci_remove(struct pci_dev *pdev)
1870 {
1871         struct eg20t_port *priv = pci_get_drvdata(pdev);
1872
1873         pci_disable_msi(pdev);
1874
1875 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1876         pch_uart_ports[priv->port.line] = NULL;
1877 #endif
1878         pch_uart_exit_port(priv);
1879         pci_disable_device(pdev);
1880         kfree(priv);
1881         return;
1882 }
1883 #ifdef CONFIG_PM
1884 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1885 {
1886         struct eg20t_port *priv = pci_get_drvdata(pdev);
1887
1888         uart_suspend_port(&pch_uart_driver, &priv->port);
1889
1890         pci_save_state(pdev);
1891         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1892         return 0;
1893 }
1894
1895 static int pch_uart_pci_resume(struct pci_dev *pdev)
1896 {
1897         struct eg20t_port *priv = pci_get_drvdata(pdev);
1898         int ret;
1899
1900         pci_set_power_state(pdev, PCI_D0);
1901         pci_restore_state(pdev);
1902
1903         ret = pci_enable_device(pdev);
1904         if (ret) {
1905                 dev_err(&pdev->dev,
1906                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1907                 return ret;
1908         }
1909
1910         uart_resume_port(&pch_uart_driver, &priv->port);
1911
1912         return 0;
1913 }
1914 #else
1915 #define pch_uart_pci_suspend NULL
1916 #define pch_uart_pci_resume NULL
1917 #endif
1918
1919 static const struct pci_device_id pch_uart_pci_id[] = {
1920         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1921          .driver_data = pch_et20t_uart0},
1922         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1923          .driver_data = pch_et20t_uart1},
1924         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1925          .driver_data = pch_et20t_uart2},
1926         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1927          .driver_data = pch_et20t_uart3},
1928         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1929          .driver_data = pch_ml7213_uart0},
1930         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1931          .driver_data = pch_ml7213_uart1},
1932         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1933          .driver_data = pch_ml7213_uart2},
1934         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1935          .driver_data = pch_ml7223_uart0},
1936         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1937          .driver_data = pch_ml7223_uart1},
1938         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1939          .driver_data = pch_ml7831_uart0},
1940         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1941          .driver_data = pch_ml7831_uart1},
1942         {0,},
1943 };
1944
1945 static int pch_uart_pci_probe(struct pci_dev *pdev,
1946                                         const struct pci_device_id *id)
1947 {
1948         int ret;
1949         struct eg20t_port *priv;
1950
1951         ret = pci_enable_device(pdev);
1952         if (ret < 0)
1953                 goto probe_error;
1954
1955         priv = pch_uart_init_port(pdev, id);
1956         if (!priv) {
1957                 ret = -EBUSY;
1958                 goto probe_disable_device;
1959         }
1960         pci_set_drvdata(pdev, priv);
1961
1962         return ret;
1963
1964 probe_disable_device:
1965         pci_disable_msi(pdev);
1966         pci_disable_device(pdev);
1967 probe_error:
1968         return ret;
1969 }
1970
1971 static struct pci_driver pch_uart_pci_driver = {
1972         .name = "pch_uart",
1973         .id_table = pch_uart_pci_id,
1974         .probe = pch_uart_pci_probe,
1975         .remove = pch_uart_pci_remove,
1976         .suspend = pch_uart_pci_suspend,
1977         .resume = pch_uart_pci_resume,
1978 };
1979
1980 static int __init pch_uart_module_init(void)
1981 {
1982         int ret;
1983
1984         /* register as UART driver */
1985         ret = uart_register_driver(&pch_uart_driver);
1986         if (ret < 0)
1987                 return ret;
1988
1989         /* register as PCI driver */
1990         ret = pci_register_driver(&pch_uart_pci_driver);
1991         if (ret < 0)
1992                 uart_unregister_driver(&pch_uart_driver);
1993
1994         return ret;
1995 }
1996 module_init(pch_uart_module_init);
1997
1998 static void __exit pch_uart_module_exit(void)
1999 {
2000         pci_unregister_driver(&pch_uart_pci_driver);
2001         uart_unregister_driver(&pch_uart_driver);
2002 }
2003 module_exit(pch_uart_module_exit);
2004
2005 MODULE_LICENSE("GPL v2");
2006 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2007 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2008
2009 module_param(default_baud, uint, S_IRUGO);
2010 MODULE_PARM_DESC(default_baud,
2011                  "Default BAUD for initial driver state and console (default 9600)");
2012 module_param(user_uartclk, uint, S_IRUGO);
2013 MODULE_PARM_DESC(user_uartclk,
2014                  "Override UART default or board specific UART clock");