drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/debugfs.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/pch_dma.h>
  39
  40 enum {
  41         PCH_UART_HANDLED_RX_INT_SHIFT,
  42         PCH_UART_HANDLED_TX_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  44         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  45         PCH_UART_HANDLED_MS_INT_SHIFT,
  46         PCH_UART_HANDLED_LS_INT_SHIFT,
  47 };
  48
  49 enum {
  50         PCH_UART_8LINE,
  51         PCH_UART_2LINE,
  52 };
  53
  54 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  55
  56 /* Set the max number of UART port
  57  * Intel EG20T PCH: 4 port
  58  * LAPIS Semiconductor ML7213 IOH: 3 port
  59  * LAPIS Semiconductor ML7223 IOH: 2 port
  60 */
  61 #define PCH_UART_NR     4
  62
  63 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  65 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  66                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  67 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  68                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  69 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  70
  71 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  72
  73 #define PCH_UART_RBR            0x00
  74 #define PCH_UART_THR            0x00
  75
  76 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  77                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  78 #define PCH_UART_IER_ERBFI      0x00000001
  79 #define PCH_UART_IER_ETBEI      0x00000002
  80 #define PCH_UART_IER_ELSI       0x00000004
  81 #define PCH_UART_IER_EDSSI      0x00000008
  82
  83 #define PCH_UART_IIR_IP                 0x00000001
  84 #define PCH_UART_IIR_IID                0x00000006
  85 #define PCH_UART_IIR_MSI                0x00000000
  86 #define PCH_UART_IIR_TRI                0x00000002
  87 #define PCH_UART_IIR_RRI                0x00000004
  88 #define PCH_UART_IIR_REI                0x00000006
  89 #define PCH_UART_IIR_TOI                0x00000008
  90 #define PCH_UART_IIR_FIFO256            0x00000020
  91 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  92 #define PCH_UART_IIR_FE                 0x000000C0
  93
  94 #define PCH_UART_FCR_FIFOE              0x00000001
  95 #define PCH_UART_FCR_RFR                0x00000002
  96 #define PCH_UART_FCR_TFR                0x00000004
  97 #define PCH_UART_FCR_DMS                0x00000008
  98 #define PCH_UART_FCR_FIFO256            0x00000020
  99 #define PCH_UART_FCR_RFTL               0x000000C0
 100
 101 #define PCH_UART_FCR_RFTL1              0x00000000
 102 #define PCH_UART_FCR_RFTL64             0x00000040
 103 #define PCH_UART_FCR_RFTL128            0x00000080
 104 #define PCH_UART_FCR_RFTL224            0x000000C0
 105 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 106 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 107 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 108 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 109 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 110 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 111 #define PCH_UART_FCR_RFTL_SHIFT         6
 112
 113 #define PCH_UART_LCR_WLS        0x00000003
 114 #define PCH_UART_LCR_STB        0x00000004
 115 #define PCH_UART_LCR_PEN        0x00000008
 116 #define PCH_UART_LCR_EPS        0x00000010
 117 #define PCH_UART_LCR_SP         0x00000020
 118 #define PCH_UART_LCR_SB         0x00000040
 119 #define PCH_UART_LCR_DLAB       0x00000080
 120 #define PCH_UART_LCR_NP         0x00000000
 121 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 122 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 123 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 124 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 125                                 PCH_UART_LCR_SP)
 126
 127 #define PCH_UART_LCR_5BIT       0x00000000
 128 #define PCH_UART_LCR_6BIT       0x00000001
 129 #define PCH_UART_LCR_7BIT       0x00000002
 130 #define PCH_UART_LCR_8BIT       0x00000003
 131
 132 #define PCH_UART_MCR_DTR        0x00000001
 133 #define PCH_UART_MCR_RTS        0x00000002
 134 #define PCH_UART_MCR_OUT        0x0000000C
 135 #define PCH_UART_MCR_LOOP       0x00000010
 136 #define PCH_UART_MCR_AFE        0x00000020
 137
 138 #define PCH_UART_LSR_DR         0x00000001
 139 #define PCH_UART_LSR_ERR        (1<<7)
 140
 141 #define PCH_UART_MSR_DCTS       0x00000001
 142 #define PCH_UART_MSR_DDSR       0x00000002
 143 #define PCH_UART_MSR_TERI       0x00000004
 144 #define PCH_UART_MSR_DDCD       0x00000008
 145 #define PCH_UART_MSR_CTS        0x00000010
 146 #define PCH_UART_MSR_DSR        0x00000020
 147 #define PCH_UART_MSR_RI         0x00000040
 148 #define PCH_UART_MSR_DCD        0x00000080
 149 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 150                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 151
 152 #define PCH_UART_DLL            0x00
 153 #define PCH_UART_DLM            0x01
 154
 155 #define PCH_UART_BRCSR          0x0E
 156
 157 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 158 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 159 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 160 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 161 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 162
 163 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 164 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 165 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 166 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 167 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 168 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 169 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 170 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 171 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 172 #define PCH_UART_HAL_STB1               0
 173 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 174
 175 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 176 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 177 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 178                                         PCH_UART_HAL_CLR_RX_FIFO)
 179
 180 #define PCH_UART_HAL_DMA_MODE0          0
 181 #define PCH_UART_HAL_FIFO_DIS           0
 182 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 183 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 184                                         PCH_UART_FCR_FIFO256)
 185 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 186 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 187 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 188 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 189 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 190 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 191 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 192 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 193 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 194 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 195 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 196 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 197 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 198 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 199
 200 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 201 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 202 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 203 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 204 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 205
 206 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 207 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 208 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 209 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 210 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 211
 212 #define PCI_VENDOR_ID_ROHM              0x10DB
 213
 214 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 215
 216 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 217 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 218 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 219 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 220 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 221 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 222
 223 struct pch_uart_buffer {
 224         unsigned char *buf;
 225         int size;
 226 };
 227
 228 struct eg20t_port {
 229         struct uart_port port;
 230         int port_type;
 231         void __iomem *membase;
 232         resource_size_t mapbase;
 233         unsigned int iobase;
 234         struct pci_dev *pdev;
 235         int fifo_size;
 236         unsigned int uartclk;
 237         int start_tx;
 238         int start_rx;
 239         int tx_empty;
 240         int trigger;
 241         int trigger_level;
 242         struct pch_uart_buffer rxbuf;
 243         unsigned int dmsr;
 244         unsigned int fcr;
 245         unsigned int mcr;
 246         unsigned int use_dma;
 247         struct dma_async_tx_descriptor  *desc_tx;
 248         struct dma_async_tx_descriptor  *desc_rx;
 249         struct pch_dma_slave            param_tx;
 250         struct pch_dma_slave            param_rx;
 251         struct dma_chan                 *chan_tx;
 252         struct dma_chan                 *chan_rx;
 253         struct scatterlist              *sg_tx_p;
 254         int                             nent;
 255         int                             orig_nent;
 256         struct scatterlist              sg_rx;
 257         int                             tx_dma_use;
 258         void                            *rx_buf_virt;
 259         dma_addr_t                      rx_buf_dma;
 260
 261         struct dentry   *debugfs;
 262 #define IRQ_NAME_SIZE 17
 263         char                            irq_name[IRQ_NAME_SIZE];
 264
 265         /* protect the eg20t_port private structure and io access to membase */
 266         spinlock_t lock;
 267 };
 268
 269 /**
 270  * struct pch_uart_driver_data - private data structure for UART-DMA
 271  * @port_type:                  The number of DMA channel
 272  * @line_no:                    UART port line number (0, 1, 2...)
 273  */
 274 struct pch_uart_driver_data {
 275         int port_type;
 276         int line_no;
 277 };
 278
 279 enum pch_uart_num_t {
 280         pch_et20t_uart0 = 0,
 281         pch_et20t_uart1,
 282         pch_et20t_uart2,
 283         pch_et20t_uart3,
 284         pch_ml7213_uart0,
 285         pch_ml7213_uart1,
 286         pch_ml7213_uart2,
 287         pch_ml7223_uart0,
 288         pch_ml7223_uart1,
 289         pch_ml7831_uart0,
 290         pch_ml7831_uart1,
 291 };
 292
 293 static struct pch_uart_driver_data drv_dat[] = {
 294         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 295         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 296         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 297         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 298         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 299         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 300         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 301         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 302         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 303         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 304         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 305 };
 306
 307 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 308 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 309 #endif
 310 static unsigned int default_baud = 9600;
 311 static unsigned int user_uartclk = 0;
 312 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 313 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 314 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 315 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 316
 317 #ifdef CONFIG_DEBUG_FS
 318
 319 #define PCH_REGS_BUFSIZE        1024
 320
 321
 322 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 323                                 size_t count, loff_t *ppos)
 324 {
 325         struct eg20t_port *priv = file->private_data;
 326         char *buf;
 327         u32 len = 0;
 328         ssize_t ret;
 329         unsigned char lcr;
 330
 331         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 332         if (!buf)
 333                 return 0;
 334
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 337
 338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 339                         "=================================\n");
 340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 341                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 342         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 343                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 344         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 345                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 346         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 347                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 348         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 349                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 350         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 351                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 352         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 353                         "BRCSR: \t0x%02x\n",
 354                         ioread8(priv->membase + PCH_UART_BRCSR));
 355
 356         lcr = ioread8(priv->membase + UART_LCR);
 357         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 358         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 359                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 360         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 361                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 362         iowrite8(lcr, priv->membase + UART_LCR);
 363
 364         if (len > PCH_REGS_BUFSIZE)
 365                 len = PCH_REGS_BUFSIZE;
 366
 367         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 368         kfree(buf);
 369         return ret;
 370 }
 371
 372 static const struct file_operations port_regs_ops = {
 373         .owner          = THIS_MODULE,
 374         .open           = simple_open,
 375         .read           = port_show_regs,
 376         .llseek         = default_llseek,
 377 };
 378 #endif  /* CONFIG_DEBUG_FS */
 379
 380 static struct dmi_system_id pch_uart_dmi_table[] = {
 381         {
 382                 .ident = "CM-iTC",
 383                 {
 384                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 385                 },
 386                 (void *)CMITC_UARTCLK,
 387         },
 388         {
 389                 .ident = "FRI2",
 390                 {
 391                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 392                 },
 393                 (void *)FRI2_64_UARTCLK,
 394         },
 395         {
 396                 .ident = "Fish River Island II",
 397                 {
 398                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 399                 },
 400                 (void *)FRI2_48_UARTCLK,
 401         },
 402         {
 403                 .ident = "COMe-mTT",
 404                 {
 405                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 406                 },
 407                 (void *)NTC1_UARTCLK,
 408         },
 409         {
 410                 .ident = "nanoETXexpress-TT",
 411                 {
 412                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 413                 },
 414                 (void *)NTC1_UARTCLK,
 415         },
 416         {
 417                 .ident = "MinnowBoard",
 418                 {
 419                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 420                 },
 421                 (void *)MINNOW_UARTCLK,
 422         },
 423         { }
 424 };
 425
 426 /* Return UART clock, checking for board specific clocks. */
 427 static unsigned int pch_uart_get_uartclk(void)
 428 {
 429         const struct dmi_system_id *d;
 430
 431         if (user_uartclk)
 432                 return user_uartclk;
 433
 434         d = dmi_first_match(pch_uart_dmi_table);
 435         if (d)
 436                 return (unsigned long)d->driver_data;
 437
 438         return DEFAULT_UARTCLK;
 439 }
 440
 441 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 442                                           unsigned int flag)
 443 {
 444         u8 ier = ioread8(priv->membase + UART_IER);
 445         ier |= flag & PCH_UART_IER_MASK;
 446         iowrite8(ier, priv->membase + UART_IER);
 447 }
 448
 449 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 450                                            unsigned int flag)
 451 {
 452         u8 ier = ioread8(priv->membase + UART_IER);
 453         ier &= ~(flag & PCH_UART_IER_MASK);
 454         iowrite8(ier, priv->membase + UART_IER);
 455 }
 456
 457 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 458                                  unsigned int parity, unsigned int bits,
 459                                  unsigned int stb)
 460 {
 461         unsigned int dll, dlm, lcr;
 462         int div;
 463
 464         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 465         if (div < 0 || USHRT_MAX <= div) {
 466                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 467                 return -EINVAL;
 468         }
 469
 470         dll = (unsigned int)div & 0x00FFU;
 471         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 472
 473         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 474                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 475                 return -EINVAL;
 476         }
 477
 478         if (bits & ~PCH_UART_LCR_WLS) {
 479                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 480                 return -EINVAL;
 481         }
 482
 483         if (stb & ~PCH_UART_LCR_STB) {
 484                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 485                 return -EINVAL;
 486         }
 487
 488         lcr = parity;
 489         lcr |= bits;
 490         lcr |= stb;
 491
 492         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 493                  __func__, baud, div, lcr, jiffies);
 494         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 495         iowrite8(dll, priv->membase + PCH_UART_DLL);
 496         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 497         iowrite8(lcr, priv->membase + UART_LCR);
 498
 499         return 0;
 500 }
 501
 502 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 503                                     unsigned int flag)
 504 {
 505         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 506                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 507                         __func__, flag);
 508                 return -EINVAL;
 509         }
 510
 511         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 512         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 513                  priv->membase + UART_FCR);
 514         iowrite8(priv->fcr, priv->membase + UART_FCR);
 515
 516         return 0;
 517 }
 518
 519 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 520                                  unsigned int dmamode,
 521                                  unsigned int fifo_size, unsigned int trigger)
 522 {
 523         u8 fcr;
 524
 525         if (dmamode & ~PCH_UART_FCR_DMS) {
 526                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 527                         __func__, dmamode);
 528                 return -EINVAL;
 529         }
 530
 531         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 532                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 533                         __func__, fifo_size);
 534                 return -EINVAL;
 535         }
 536
 537         if (trigger & ~PCH_UART_FCR_RFTL) {
 538                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 539                         __func__, trigger);
 540                 return -EINVAL;
 541         }
 542
 543         switch (priv->fifo_size) {
 544         case 256:
 545                 priv->trigger_level =
 546                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 547                 break;
 548         case 64:
 549                 priv->trigger_level =
 550                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 551                 break;
 552         case 16:
 553                 priv->trigger_level =
 554                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 555                 break;
 556         default:
 557                 priv->trigger_level =
 558                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 559                 break;
 560         }
 561         fcr =
 562             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 563         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 564         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 565                  priv->membase + UART_FCR);
 566         iowrite8(fcr, priv->membase + UART_FCR);
 567         priv->fcr = fcr;
 568
 569         return 0;
 570 }
 571
 572 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 573 {
 574         unsigned int msr = ioread8(priv->membase + UART_MSR);
 575         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 576         return (u8)msr;
 577 }
 578
 579 static void pch_uart_hal_write(struct eg20t_port *priv,
 580                               const unsigned char *buf, int tx_size)
 581 {
 582         int i;
 583         unsigned int thr;
 584
 585         for (i = 0; i < tx_size;) {
 586                 thr = buf[i++];
 587                 iowrite8(thr, priv->membase + PCH_UART_THR);
 588         }
 589 }
 590
 591 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 592                              int rx_size)
 593 {
 594         int i;
 595         u8 rbr, lsr;
 596         struct uart_port *port = &priv->port;
 597
 598         lsr = ioread8(priv->membase + UART_LSR);
 599         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 600              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 601              lsr = ioread8(priv->membase + UART_LSR)) {
 602                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 603
 604                 if (lsr & UART_LSR_BI) {
 605                         port->icount.brk++;
 606                         if (uart_handle_break(port))
 607                                 continue;
 608                 }
 609 #ifdef SUPPORT_SYSRQ
 610                 if (port->sysrq) {
 611                         if (uart_handle_sysrq_char(port, rbr))
 612                                 continue;
 613                 }
 614 #endif
 615
 616                 buf[i++] = rbr;
 617         }
 618         return i;
 619 }
 620
 621 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 622 {
 623         return ioread8(priv->membase + UART_IIR) &\
 624                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 625 }
 626
 627 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 628 {
 629         return ioread8(priv->membase + UART_LSR);
 630 }
 631
 632 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 633 {
 634         unsigned int lcr;
 635
 636         lcr = ioread8(priv->membase + UART_LCR);
 637         if (on)
 638                 lcr |= PCH_UART_LCR_SB;
 639         else
 640                 lcr &= ~PCH_UART_LCR_SB;
 641
 642         iowrite8(lcr, priv->membase + UART_LCR);
 643 }
 644
 645 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 646                    int size)
 647 {
 648         struct uart_port *port = &priv->port;
 649         struct tty_port *tport = &port->state->port;
 650
 651         tty_insert_flip_string(tport, buf, size);
 652         tty_flip_buffer_push(tport);
 653
 654         return 0;
 655 }
 656
 657 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 658 {
 659         int ret = 0;
 660         struct uart_port *port = &priv->port;
 661
 662         if (port->x_char) {
 663                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 664                         __func__, port->x_char, jiffies);
 665                 buf[0] = port->x_char;
 666                 port->x_char = 0;
 667                 ret = 1;
 668         }
 669
 670         return ret;
 671 }
 672
 673 static int dma_push_rx(struct eg20t_port *priv, int size)
 674 {
 675         int room;
 676         struct uart_port *port = &priv->port;
 677         struct tty_port *tport = &port->state->port;
 678
 679         room = tty_buffer_request_room(tport, size);
 680
 681         if (room < size)
 682                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 683                          size - room);
 684         if (!room)
 685                 return 0;
 686
 687         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 688
 689         port->icount.rx += room;
 690
 691         return room;
 692 }
 693
 694 static void pch_free_dma(struct uart_port *port)
 695 {
 696         struct eg20t_port *priv;
 697         priv = container_of(port, struct eg20t_port, port);
 698
 699         if (priv->chan_tx) {
 700                 dma_release_channel(priv->chan_tx);
 701                 priv->chan_tx = NULL;
 702         }
 703         if (priv->chan_rx) {
 704                 dma_release_channel(priv->chan_rx);
 705                 priv->chan_rx = NULL;
 706         }
 707
 708         if (priv->rx_buf_dma) {
 709                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 710                                   priv->rx_buf_dma);
 711                 priv->rx_buf_virt = NULL;
 712                 priv->rx_buf_dma = 0;
 713         }
 714
 715         return;
 716 }
 717
 718 static bool filter(struct dma_chan *chan, void *slave)
 719 {
 720         struct pch_dma_slave *param = slave;
 721
 722         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 723                                                   chan->device->dev)) {
 724                 chan->private = param;
 725                 return true;
 726         } else {
 727                 return false;
 728         }
 729 }
 730
 731 static void pch_request_dma(struct uart_port *port)
 732 {
 733         dma_cap_mask_t mask;
 734         struct dma_chan *chan;
 735         struct pci_dev *dma_dev;
 736         struct pch_dma_slave *param;
 737         struct eg20t_port *priv =
 738                                 container_of(port, struct eg20t_port, port);
 739         dma_cap_zero(mask);
 740         dma_cap_set(DMA_SLAVE, mask);
 741
 742         /* Get DMA's dev information */
 743         dma_dev = pci_get_slot(priv->pdev->bus,
 744                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 745
 746         /* Set Tx DMA */
 747         param = &priv->param_tx;
 748         param->dma_dev = &dma_dev->dev;
 749         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 750
 751         param->tx_reg = port->mapbase + UART_TX;
 752         chan = dma_request_channel(mask, filter, param);
 753         if (!chan) {
 754                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 755                         __func__);
 756                 return;
 757         }
 758         priv->chan_tx = chan;
 759
 760         /* Set Rx DMA */
 761         param = &priv->param_rx;
 762         param->dma_dev = &dma_dev->dev;
 763         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 764
 765         param->rx_reg = port->mapbase + UART_RX;
 766         chan = dma_request_channel(mask, filter, param);
 767         if (!chan) {
 768                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 769                         __func__);
 770                 dma_release_channel(priv->chan_tx);
 771                 priv->chan_tx = NULL;
 772                 return;
 773         }
 774
 775         /* Get Consistent memory for DMA */
 776         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 777                                     &priv->rx_buf_dma, GFP_KERNEL);
 778         priv->chan_rx = chan;
 779 }
 780
 781 static void pch_dma_rx_complete(void *arg)
 782 {
 783         struct eg20t_port *priv = arg;
 784         struct uart_port *port = &priv->port;
 785         int count;
 786
 787         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 788         count = dma_push_rx(priv, priv->trigger_level);
 789         if (count)
 790                 tty_flip_buffer_push(&port->state->port);
 791         async_tx_ack(priv->desc_rx);
 792         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 793                                             PCH_UART_HAL_RX_ERR_INT);
 794 }
 795
 796 static void pch_dma_tx_complete(void *arg)
 797 {
 798         struct eg20t_port *priv = arg;
 799         struct uart_port *port = &priv->port;
 800         struct circ_buf *xmit = &port->state->xmit;
 801         struct scatterlist *sg = priv->sg_tx_p;
 802         int i;
 803
 804         for (i = 0; i < priv->nent; i++, sg++) {
 805                 xmit->tail += sg_dma_len(sg);
 806                 port->icount.tx += sg_dma_len(sg);
 807         }
 808         xmit->tail &= UART_XMIT_SIZE - 1;
 809         async_tx_ack(priv->desc_tx);
 810         dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
 811         priv->tx_dma_use = 0;
 812         priv->nent = 0;
 813         priv->orig_nent = 0;
 814         kfree(priv->sg_tx_p);
 815         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 816 }
 817
 818 static int pop_tx(struct eg20t_port *priv, int size)
 819 {
 820         int count = 0;
 821         struct uart_port *port = &priv->port;
 822         struct circ_buf *xmit = &port->state->xmit;
 823
 824         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 825                 goto pop_tx_end;
 826
 827         do {
 828                 int cnt_to_end =
 829                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 830                 int sz = min(size - count, cnt_to_end);
 831                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 832                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 833                 count += sz;
 834         } while (!uart_circ_empty(xmit) && count < size);
 835
 836 pop_tx_end:
 837         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 838                  count, size - count, jiffies);
 839
 840         return count;
 841 }
 842
 843 static int handle_rx_to(struct eg20t_port *priv)
 844 {
 845         struct pch_uart_buffer *buf;
 846         int rx_size;
 847         int ret;
 848         if (!priv->start_rx) {
 849                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 850                                                      PCH_UART_HAL_RX_ERR_INT);
 851                 return 0;
 852         }
 853         buf = &priv->rxbuf;
 854         do {
 855                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 856                 ret = push_rx(priv, buf->buf, rx_size);
 857                 if (ret)
 858                         return 0;
 859         } while (rx_size == buf->size);
 860
 861         return PCH_UART_HANDLED_RX_INT;
 862 }
 863
 864 static int handle_rx(struct eg20t_port *priv)
 865 {
 866         return handle_rx_to(priv);
 867 }
 868
 869 static int dma_handle_rx(struct eg20t_port *priv)
 870 {
 871         struct uart_port *port = &priv->port;
 872         struct dma_async_tx_descriptor *desc;
 873         struct scatterlist *sg;
 874
 875         priv = container_of(port, struct eg20t_port, port);
 876         sg = &priv->sg_rx;
 877
 878         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 879
 880         sg_dma_len(sg) = priv->trigger_level;
 881
 882         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 883                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 884                      ~PAGE_MASK);
 885
 886         sg_dma_address(sg) = priv->rx_buf_dma;
 887
 888         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 889                         sg, 1, DMA_DEV_TO_MEM,
 890                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 891
 892         if (!desc)
 893                 return 0;
 894
 895         priv->desc_rx = desc;
 896         desc->callback = pch_dma_rx_complete;
 897         desc->callback_param = priv;
 898         desc->tx_submit(desc);
 899         dma_async_issue_pending(priv->chan_rx);
 900
 901         return PCH_UART_HANDLED_RX_INT;
 902 }
 903
 904 static unsigned int handle_tx(struct eg20t_port *priv)
 905 {
 906         struct uart_port *port = &priv->port;
 907         struct circ_buf *xmit = &port->state->xmit;
 908         int fifo_size;
 909         int tx_size;
 910         int size;
 911         int tx_empty;
 912
 913         if (!priv->start_tx) {
 914                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 915                         __func__, jiffies);
 916                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 917                 priv->tx_empty = 1;
 918                 return 0;
 919         }
 920
 921         fifo_size = max(priv->fifo_size, 1);
 922         tx_empty = 1;
 923         if (pop_tx_x(priv, xmit->buf)) {
 924                 pch_uart_hal_write(priv, xmit->buf, 1);
 925                 port->icount.tx++;
 926                 tx_empty = 0;
 927                 fifo_size--;
 928         }
 929         size = min(xmit->head - xmit->tail, fifo_size);
 930         if (size < 0)
 931                 size = fifo_size;
 932
 933         tx_size = pop_tx(priv, size);
 934         if (tx_size > 0) {
 935                 port->icount.tx += tx_size;
 936                 tx_empty = 0;
 937         }
 938
 939         priv->tx_empty = tx_empty;
 940
 941         if (tx_empty) {
 942                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 943                 uart_write_wakeup(port);
 944         }
 945
 946         return PCH_UART_HANDLED_TX_INT;
 947 }
 948
 949 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 950 {
 951         struct uart_port *port = &priv->port;
 952         struct circ_buf *xmit = &port->state->xmit;
 953         struct scatterlist *sg;
 954         int nent;
 955         int fifo_size;
 956         int tx_empty;
 957         struct dma_async_tx_descriptor *desc;
 958         int num;
 959         int i;
 960         int bytes;
 961         int size;
 962         int rem;
 963
 964         if (!priv->start_tx) {
 965                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 966                         __func__, jiffies);
 967                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 968                 priv->tx_empty = 1;
 969                 return 0;
 970         }
 971
 972         if (priv->tx_dma_use) {
 973                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 974                         __func__, jiffies);
 975                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 976                 priv->tx_empty = 1;
 977                 return 0;
 978         }
 979
 980         fifo_size = max(priv->fifo_size, 1);
 981         tx_empty = 1;
 982         if (pop_tx_x(priv, xmit->buf)) {
 983                 pch_uart_hal_write(priv, xmit->buf, 1);
 984                 port->icount.tx++;
 985                 tx_empty = 0;
 986                 fifo_size--;
 987         }
 988
 989         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 990                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 991                              xmit->tail, UART_XMIT_SIZE));
 992         if (!bytes) {
 993                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 994                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 995                 uart_write_wakeup(port);
 996                 return 0;
 997         }
 998
 999         if (bytes > fifo_size) {
1000                 num = bytes / fifo_size + 1;
1001                 size = fifo_size;
1002                 rem = bytes % fifo_size;
1003         } else {
1004                 num = 1;
1005                 size = bytes;
1006                 rem = bytes;
1007         }
1008
1009         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1010                 __func__, num, size, rem);
1011
1012         priv->tx_dma_use = 1;
1013
1014         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1015         if (!priv->sg_tx_p) {
1016                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1017                 return 0;
1018         }
1019
1020         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1021         sg = priv->sg_tx_p;
1022
1023         for (i = 0; i < num; i++, sg++) {
1024                 if (i == (num - 1))
1025                         sg_set_page(sg, virt_to_page(xmit->buf),
1026                                     rem, fifo_size * i);
1027                 else
1028                         sg_set_page(sg, virt_to_page(xmit->buf),
1029                                     size, fifo_size * i);
1030         }
1031
1032         sg = priv->sg_tx_p;
1033         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1034         if (!nent) {
1035                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1036                 return 0;
1037         }
1038         priv->orig_nent = num;
1039         priv->nent = nent;
1040
1041         for (i = 0; i < nent; i++, sg++) {
1042                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1043                               fifo_size * i;
1044                 sg_dma_address(sg) = (sg_dma_address(sg) &
1045                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1046                 if (i == (nent - 1))
1047                         sg_dma_len(sg) = rem;
1048                 else
1049                         sg_dma_len(sg) = size;
1050         }
1051
1052         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1053                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1054                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1055         if (!desc) {
1056                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1057                         __func__);
1058                 return 0;
1059         }
1060         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1061         priv->desc_tx = desc;
1062         desc->callback = pch_dma_tx_complete;
1063         desc->callback_param = priv;
1064
1065         desc->tx_submit(desc);
1066
1067         dma_async_issue_pending(priv->chan_tx);
1068
1069         return PCH_UART_HANDLED_TX_INT;
1070 }
1071
1072 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1073 {
1074         struct uart_port *port = &priv->port;
1075         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1076         char   *error_msg[5] = {};
1077         int    i = 0;
1078
1079         if (lsr & PCH_UART_LSR_ERR)
1080                 error_msg[i++] = "Error data in FIFO\n";
1081
1082         if (lsr & UART_LSR_FE) {
1083                 port->icount.frame++;
1084                 error_msg[i++] = "  Framing Error\n";
1085         }
1086
1087         if (lsr & UART_LSR_PE) {
1088                 port->icount.parity++;
1089                 error_msg[i++] = "  Parity Error\n";
1090         }
1091
1092         if (lsr & UART_LSR_OE) {
1093                 port->icount.overrun++;
1094                 error_msg[i++] = "  Overrun Error\n";
1095         }
1096
1097         if (tty == NULL) {
1098                 for (i = 0; error_msg[i] != NULL; i++)
1099                         dev_err(&priv->pdev->dev, error_msg[i]);
1100         } else {
1101                 tty_kref_put(tty);
1102         }
1103 }
1104
1105 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1106 {
1107         struct eg20t_port *priv = dev_id;
1108         unsigned int handled;
1109         u8 lsr;
1110         int ret = 0;
1111         unsigned char iid;
1112         unsigned long flags;
1113         int next = 1;
1114         u8 msr;
1115
1116         spin_lock_irqsave(&priv->lock, flags);
1117         handled = 0;
1118         while (next) {
1119                 iid = pch_uart_hal_get_iid(priv);
1120                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1121                         break;
1122                 switch (iid) {
1123                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1124                         lsr = pch_uart_hal_get_line_status(priv);
1125                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1126                                                 UART_LSR_PE | UART_LSR_OE)) {
1127                                 pch_uart_err_ir(priv, lsr);
1128                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1129                         } else {
1130                                 ret = PCH_UART_HANDLED_LS_INT;
1131                         }
1132                         break;
1133                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1134                         if (priv->use_dma) {
1135                                 pch_uart_hal_disable_interrupt(priv,
1136                                                 PCH_UART_HAL_RX_INT |
1137                                                 PCH_UART_HAL_RX_ERR_INT);
1138                                 ret = dma_handle_rx(priv);
1139                                 if (!ret)
1140                                         pch_uart_hal_enable_interrupt(priv,
1141                                                 PCH_UART_HAL_RX_INT |
1142                                                 PCH_UART_HAL_RX_ERR_INT);
1143                         } else {
1144                                 ret = handle_rx(priv);
1145                         }
1146                         break;
1147                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1148                                                    (FIFO Timeout) */
1149                         ret = handle_rx_to(priv);
1150                         break;
1151                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1152                                                    Empty */
1153                         if (priv->use_dma)
1154                                 ret = dma_handle_tx(priv);
1155                         else
1156                                 ret = handle_tx(priv);
1157                         break;
1158                 case PCH_UART_IID_MS:   /* Modem Status */
1159                         msr = pch_uart_hal_get_modem(priv);
1160                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1161                                      means final interrupt */
1162                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1163                                 break;
1164                         ret |= PCH_UART_HANDLED_MS_INT;
1165                         break;
1166                 default:        /* Never junp to this label */
1167                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1168                                 iid, jiffies);
1169                         ret = -1;
1170                         next = 0;
1171                         break;
1172                 }
1173                 handled |= (unsigned int)ret;
1174         }
1175
1176         spin_unlock_irqrestore(&priv->lock, flags);
1177         return IRQ_RETVAL(handled);
1178 }
1179
1180 /* This function tests whether the transmitter fifo and shifter for the port
1181                                                 described by 'port' is empty. */
1182 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1183 {
1184         struct eg20t_port *priv;
1185
1186         priv = container_of(port, struct eg20t_port, port);
1187         if (priv->tx_empty)
1188                 return TIOCSER_TEMT;
1189         else
1190                 return 0;
1191 }
1192
1193 /* Returns the current state of modem control inputs. */
1194 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1195 {
1196         struct eg20t_port *priv;
1197         u8 modem;
1198         unsigned int ret = 0;
1199
1200         priv = container_of(port, struct eg20t_port, port);
1201         modem = pch_uart_hal_get_modem(priv);
1202
1203         if (modem & UART_MSR_DCD)
1204                 ret |= TIOCM_CAR;
1205
1206         if (modem & UART_MSR_RI)
1207                 ret |= TIOCM_RNG;
1208
1209         if (modem & UART_MSR_DSR)
1210                 ret |= TIOCM_DSR;
1211
1212         if (modem & UART_MSR_CTS)
1213                 ret |= TIOCM_CTS;
1214
1215         return ret;
1216 }
1217
1218 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1219 {
1220         u32 mcr = 0;
1221         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1222
1223         if (mctrl & TIOCM_DTR)
1224                 mcr |= UART_MCR_DTR;
1225         if (mctrl & TIOCM_RTS)
1226                 mcr |= UART_MCR_RTS;
1227         if (mctrl & TIOCM_LOOP)
1228                 mcr |= UART_MCR_LOOP;
1229
1230         if (priv->mcr & UART_MCR_AFE)
1231                 mcr |= UART_MCR_AFE;
1232
1233         if (mctrl)
1234                 iowrite8(mcr, priv->membase + UART_MCR);
1235 }
1236
1237 static void pch_uart_stop_tx(struct uart_port *port)
1238 {
1239         struct eg20t_port *priv;
1240         priv = container_of(port, struct eg20t_port, port);
1241         priv->start_tx = 0;
1242         priv->tx_dma_use = 0;
1243 }
1244
1245 static void pch_uart_start_tx(struct uart_port *port)
1246 {
1247         struct eg20t_port *priv;
1248
1249         priv = container_of(port, struct eg20t_port, port);
1250
1251         if (priv->use_dma) {
1252                 if (priv->tx_dma_use) {
1253                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1254                                 __func__);
1255                         return;
1256                 }
1257         }
1258
1259         priv->start_tx = 1;
1260         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1261 }
1262
1263 static void pch_uart_stop_rx(struct uart_port *port)
1264 {
1265         struct eg20t_port *priv;
1266         priv = container_of(port, struct eg20t_port, port);
1267         priv->start_rx = 0;
1268         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1269                                              PCH_UART_HAL_RX_ERR_INT);
1270 }
1271
1272 /* Enable the modem status interrupts. */
1273 static void pch_uart_enable_ms(struct uart_port *port)
1274 {
1275         struct eg20t_port *priv;
1276         priv = container_of(port, struct eg20t_port, port);
1277         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1278 }
1279
1280 /* Control the transmission of a break signal. */
1281 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1282 {
1283         struct eg20t_port *priv;
1284         unsigned long flags;
1285
1286         priv = container_of(port, struct eg20t_port, port);
1287         spin_lock_irqsave(&priv->lock, flags);
1288         pch_uart_hal_set_break(priv, ctl);
1289         spin_unlock_irqrestore(&priv->lock, flags);
1290 }
1291
1292 /* Grab any interrupt resources and initialise any low level driver state. */
1293 static int pch_uart_startup(struct uart_port *port)
1294 {
1295         struct eg20t_port *priv;
1296         int ret;
1297         int fifo_size;
1298         int trigger_level;
1299
1300         priv = container_of(port, struct eg20t_port, port);
1301         priv->tx_empty = 1;
1302
1303         if (port->uartclk)
1304                 priv->uartclk = port->uartclk;
1305         else
1306                 port->uartclk = priv->uartclk;
1307
1308         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1309         ret = pch_uart_hal_set_line(priv, default_baud,
1310                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1311                               PCH_UART_HAL_STB1);
1312         if (ret)
1313                 return ret;
1314
1315         switch (priv->fifo_size) {
1316         case 256:
1317                 fifo_size = PCH_UART_HAL_FIFO256;
1318                 break;
1319         case 64:
1320                 fifo_size = PCH_UART_HAL_FIFO64;
1321                 break;
1322         case 16:
1323                 fifo_size = PCH_UART_HAL_FIFO16;
1324                 break;
1325         case 1:
1326         default:
1327                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1328                 break;
1329         }
1330
1331         switch (priv->trigger) {
1332         case PCH_UART_HAL_TRIGGER1:
1333                 trigger_level = 1;
1334                 break;
1335         case PCH_UART_HAL_TRIGGER_L:
1336                 trigger_level = priv->fifo_size / 4;
1337                 break;
1338         case PCH_UART_HAL_TRIGGER_M:
1339                 trigger_level = priv->fifo_size / 2;
1340                 break;
1341         case PCH_UART_HAL_TRIGGER_H:
1342         default:
1343                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1344                 break;
1345         }
1346
1347         priv->trigger_level = trigger_level;
1348         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1349                                     fifo_size, priv->trigger);
1350         if (ret < 0)
1351                 return ret;
1352
1353         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1354                         priv->irq_name, priv);
1355         if (ret < 0)
1356                 return ret;
1357
1358         if (priv->use_dma)
1359                 pch_request_dma(port);
1360
1361         priv->start_rx = 1;
1362         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1363                                             PCH_UART_HAL_RX_ERR_INT);
1364         uart_update_timeout(port, CS8, default_baud);
1365
1366         return 0;
1367 }
1368
1369 static void pch_uart_shutdown(struct uart_port *port)
1370 {
1371         struct eg20t_port *priv;
1372         int ret;
1373
1374         priv = container_of(port, struct eg20t_port, port);
1375         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1376         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1377         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1378                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1379         if (ret)
1380                 dev_err(priv->port.dev,
1381                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1382
1383         pch_free_dma(port);
1384
1385         free_irq(priv->port.irq, priv);
1386 }
1387
1388 /* Change the port parameters, including word length, parity, stop
1389  *bits.  Update read_status_mask and ignore_status_mask to indicate
1390  *the types of events we are interested in receiving.  */
1391 static void pch_uart_set_termios(struct uart_port *port,
1392                                  struct ktermios *termios, struct ktermios *old)
1393 {
1394         int rtn;
1395         unsigned int baud, parity, bits, stb;
1396         struct eg20t_port *priv;
1397         unsigned long flags;
1398
1399         priv = container_of(port, struct eg20t_port, port);
1400         switch (termios->c_cflag & CSIZE) {
1401         case CS5:
1402                 bits = PCH_UART_HAL_5BIT;
1403                 break;
1404         case CS6:
1405                 bits = PCH_UART_HAL_6BIT;
1406                 break;
1407         case CS7:
1408                 bits = PCH_UART_HAL_7BIT;
1409                 break;
1410         default:                /* CS8 */
1411                 bits = PCH_UART_HAL_8BIT;
1412                 break;
1413         }
1414         if (termios->c_cflag & CSTOPB)
1415                 stb = PCH_UART_HAL_STB2;
1416         else
1417                 stb = PCH_UART_HAL_STB1;
1418
1419         if (termios->c_cflag & PARENB) {
1420                 if (termios->c_cflag & PARODD)
1421                         parity = PCH_UART_HAL_PARITY_ODD;
1422                 else
1423                         parity = PCH_UART_HAL_PARITY_EVEN;
1424
1425         } else
1426                 parity = PCH_UART_HAL_PARITY_NONE;
1427
1428         /* Only UART0 has auto hardware flow function */
1429         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1430                 priv->mcr |= UART_MCR_AFE;
1431         else
1432                 priv->mcr &= ~UART_MCR_AFE;
1433
1434         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1435
1436         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1437
1438         spin_lock_irqsave(&priv->lock, flags);
1439         spin_lock(&port->lock);
1440
1441         uart_update_timeout(port, termios->c_cflag, baud);
1442         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1443         if (rtn)
1444                 goto out;
1445
1446         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1447         /* Don't rewrite B0 */
1448         if (tty_termios_baud_rate(termios))
1449                 tty_termios_encode_baud_rate(termios, baud, baud);
1450
1451 out:
1452         spin_unlock(&port->lock);
1453         spin_unlock_irqrestore(&priv->lock, flags);
1454 }
1455
1456 static const char *pch_uart_type(struct uart_port *port)
1457 {
1458         return KBUILD_MODNAME;
1459 }
1460
1461 static void pch_uart_release_port(struct uart_port *port)
1462 {
1463         struct eg20t_port *priv;
1464
1465         priv = container_of(port, struct eg20t_port, port);
1466         pci_iounmap(priv->pdev, priv->membase);
1467         pci_release_regions(priv->pdev);
1468 }
1469
1470 static int pch_uart_request_port(struct uart_port *port)
1471 {
1472         struct eg20t_port *priv;
1473         int ret;
1474         void __iomem *membase;
1475
1476         priv = container_of(port, struct eg20t_port, port);
1477         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1478         if (ret < 0)
1479                 return -EBUSY;
1480
1481         membase = pci_iomap(priv->pdev, 1, 0);
1482         if (!membase) {
1483                 pci_release_regions(priv->pdev);
1484                 return -EBUSY;
1485         }
1486         priv->membase = port->membase = membase;
1487
1488         return 0;
1489 }
1490
1491 static void pch_uart_config_port(struct uart_port *port, int type)
1492 {
1493         struct eg20t_port *priv;
1494
1495         priv = container_of(port, struct eg20t_port, port);
1496         if (type & UART_CONFIG_TYPE) {
1497                 port->type = priv->port_type;
1498                 pch_uart_request_port(port);
1499         }
1500 }
1501
1502 static int pch_uart_verify_port(struct uart_port *port,
1503                                 struct serial_struct *serinfo)
1504 {
1505         struct eg20t_port *priv;
1506
1507         priv = container_of(port, struct eg20t_port, port);
1508         if (serinfo->flags & UPF_LOW_LATENCY) {
1509                 dev_info(priv->port.dev,
1510                         "PCH UART : Use PIO Mode (without DMA)\n");
1511                 priv->use_dma = 0;
1512                 serinfo->flags &= ~UPF_LOW_LATENCY;
1513         } else {
1514 #ifndef CONFIG_PCH_DMA
1515                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1516                         __func__);
1517                 return -EOPNOTSUPP;
1518 #endif
1519                 if (!priv->use_dma) {
1520                         pch_request_dma(port);
1521                         if (priv->chan_rx)
1522                                 priv->use_dma = 1;
1523                 }
1524                 dev_info(priv->port.dev, "PCH UART: %s\n",
1525                                 priv->use_dma ?
1526                                 "Use DMA Mode" : "No DMA");
1527         }
1528
1529         return 0;
1530 }
1531
1532 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1533 /*
1534  *      Wait for transmitter & holding register to empty
1535  */
1536 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1537 {
1538         unsigned int status, tmout = 10000;
1539
1540         /* Wait up to 10ms for the character(s) to be sent. */
1541         for (;;) {
1542                 status = ioread8(up->membase + UART_LSR);
1543
1544                 if ((status & bits) == bits)
1545                         break;
1546                 if (--tmout == 0)
1547                         break;
1548                 udelay(1);
1549         }
1550
1551         /* Wait up to 1s for flow control if necessary */
1552         if (up->port.flags & UPF_CONS_FLOW) {
1553                 unsigned int tmout;
1554                 for (tmout = 1000000; tmout; tmout--) {
1555                         unsigned int msr = ioread8(up->membase + UART_MSR);
1556                         if (msr & UART_MSR_CTS)
1557                                 break;
1558                         udelay(1);
1559                         touch_nmi_watchdog();
1560                 }
1561         }
1562 }
1563 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1564
1565 #ifdef CONFIG_CONSOLE_POLL
1566 /*
1567  * Console polling routines for communicate via uart while
1568  * in an interrupt or debug context.
1569  */
1570 static int pch_uart_get_poll_char(struct uart_port *port)
1571 {
1572         struct eg20t_port *priv =
1573                 container_of(port, struct eg20t_port, port);
1574         u8 lsr = ioread8(priv->membase + UART_LSR);
1575
1576         if (!(lsr & UART_LSR_DR))
1577                 return NO_POLL_CHAR;
1578
1579         return ioread8(priv->membase + PCH_UART_RBR);
1580 }
1581
1582
1583 static void pch_uart_put_poll_char(struct uart_port *port,
1584                          unsigned char c)
1585 {
1586         unsigned int ier;
1587         struct eg20t_port *priv =
1588                 container_of(port, struct eg20t_port, port);
1589
1590         /*
1591          * First save the IER then disable the interrupts
1592          */
1593         ier = ioread8(priv->membase + UART_IER);
1594         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1595
1596         wait_for_xmitr(priv, UART_LSR_THRE);
1597         /*
1598          * Send the character out.
1599          */
1600         iowrite8(c, priv->membase + PCH_UART_THR);
1601
1602         /*
1603          * Finally, wait for transmitter to become empty
1604          * and restore the IER
1605          */
1606         wait_for_xmitr(priv, BOTH_EMPTY);
1607         iowrite8(ier, priv->membase + UART_IER);
1608 }
1609 #endif /* CONFIG_CONSOLE_POLL */
1610
1611 static const struct uart_ops pch_uart_ops = {
1612         .tx_empty = pch_uart_tx_empty,
1613         .set_mctrl = pch_uart_set_mctrl,
1614         .get_mctrl = pch_uart_get_mctrl,
1615         .stop_tx = pch_uart_stop_tx,
1616         .start_tx = pch_uart_start_tx,
1617         .stop_rx = pch_uart_stop_rx,
1618         .enable_ms = pch_uart_enable_ms,
1619         .break_ctl = pch_uart_break_ctl,
1620         .startup = pch_uart_startup,
1621         .shutdown = pch_uart_shutdown,
1622         .set_termios = pch_uart_set_termios,
1623 /*      .pm             = pch_uart_pm,          Not supported yet */
1624         .type = pch_uart_type,
1625         .release_port = pch_uart_release_port,
1626         .request_port = pch_uart_request_port,
1627         .config_port = pch_uart_config_port,
1628         .verify_port = pch_uart_verify_port,
1629 #ifdef CONFIG_CONSOLE_POLL
1630         .poll_get_char = pch_uart_get_poll_char,
1631         .poll_put_char = pch_uart_put_poll_char,
1632 #endif
1633 };
1634
1635 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1636
1637 static void pch_console_putchar(struct uart_port *port, int ch)
1638 {
1639         struct eg20t_port *priv =
1640                 container_of(port, struct eg20t_port, port);
1641
1642         wait_for_xmitr(priv, UART_LSR_THRE);
1643         iowrite8(ch, priv->membase + PCH_UART_THR);
1644 }
1645
1646 /*
1647  *      Print a string to the serial port trying not to disturb
1648  *      any possible real use of the port...
1649  *
1650  *      The console_lock must be held when we get here.
1651  */
1652 static void
1653 pch_console_write(struct console *co, const char *s, unsigned int count)
1654 {
1655         struct eg20t_port *priv;
1656         unsigned long flags;
1657         int priv_locked = 1;
1658         int port_locked = 1;
1659         u8 ier;
1660
1661         priv = pch_uart_ports[co->index];
1662
1663         touch_nmi_watchdog();
1664
1665         local_irq_save(flags);
1666         if (priv->port.sysrq) {
1667                 /* call to uart_handle_sysrq_char already took the priv lock */
1668                 priv_locked = 0;
1669                 /* serial8250_handle_port() already took the port lock */
1670                 port_locked = 0;
1671         } else if (oops_in_progress) {
1672                 priv_locked = spin_trylock(&priv->lock);
1673                 port_locked = spin_trylock(&priv->port.lock);
1674         } else {
1675                 spin_lock(&priv->lock);
1676                 spin_lock(&priv->port.lock);
1677         }
1678
1679         /*
1680          *      First save the IER then disable the interrupts
1681          */
1682         ier = ioread8(priv->membase + UART_IER);
1683
1684         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1685
1686         uart_console_write(&priv->port, s, count, pch_console_putchar);
1687
1688         /*
1689          *      Finally, wait for transmitter to become empty
1690          *      and restore the IER
1691          */
1692         wait_for_xmitr(priv, BOTH_EMPTY);
1693         iowrite8(ier, priv->membase + UART_IER);
1694
1695         if (port_locked)
1696                 spin_unlock(&priv->port.lock);
1697         if (priv_locked)
1698                 spin_unlock(&priv->lock);
1699         local_irq_restore(flags);
1700 }
1701
1702 static int __init pch_console_setup(struct console *co, char *options)
1703 {
1704         struct uart_port *port;
1705         int baud = default_baud;
1706         int bits = 8;
1707         int parity = 'n';
1708         int flow = 'n';
1709
1710         /*
1711          * Check whether an invalid uart number has been specified, and
1712          * if so, search for the first available port that does have
1713          * console support.
1714          */
1715         if (co->index >= PCH_UART_NR)
1716                 co->index = 0;
1717         port = &pch_uart_ports[co->index]->port;
1718
1719         if (!port || (!port->iobase && !port->membase))
1720                 return -ENODEV;
1721
1722         port->uartclk = pch_uart_get_uartclk();
1723
1724         if (options)
1725                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1726
1727         return uart_set_options(port, co, baud, parity, bits, flow);
1728 }
1729
1730 static struct uart_driver pch_uart_driver;
1731
1732 static struct console pch_console = {
1733         .name           = PCH_UART_DRIVER_DEVICE,
1734         .write          = pch_console_write,
1735         .device         = uart_console_device,
1736         .setup          = pch_console_setup,
1737         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1738         .index          = -1,
1739         .data           = &pch_uart_driver,
1740 };
1741
1742 #define PCH_CONSOLE     (&pch_console)
1743 #else
1744 #define PCH_CONSOLE     NULL
1745 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1746
1747 static struct uart_driver pch_uart_driver = {
1748         .owner = THIS_MODULE,
1749         .driver_name = KBUILD_MODNAME,
1750         .dev_name = PCH_UART_DRIVER_DEVICE,
1751         .major = 0,
1752         .minor = 0,
1753         .nr = PCH_UART_NR,
1754         .cons = PCH_CONSOLE,
1755 };
1756
1757 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1758                                              const struct pci_device_id *id)
1759 {
1760         struct eg20t_port *priv;
1761         int ret;
1762         unsigned int iobase;
1763         unsigned int mapbase;
1764         unsigned char *rxbuf;
1765         int fifosize;
1766         int port_type;
1767         struct pch_uart_driver_data *board;
1768 #ifdef CONFIG_DEBUG_FS
1769         char name[32];  /* for debugfs file name */
1770 #endif
1771
1772         board = &drv_dat[id->driver_data];
1773         port_type = board->port_type;
1774
1775         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1776         if (priv == NULL)
1777                 goto init_port_alloc_err;
1778
1779         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1780         if (!rxbuf)
1781                 goto init_port_free_txbuf;
1782
1783         switch (port_type) {
1784         case PORT_UNKNOWN:
1785                 fifosize = 256; /* EG20T/ML7213: UART0 */
1786                 break;
1787         case PORT_8250:
1788                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1789                 break;
1790         default:
1791                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1792                 goto init_port_hal_free;
1793         }
1794
1795         pci_enable_msi(pdev);
1796         pci_set_master(pdev);
1797
1798         spin_lock_init(&priv->lock);
1799
1800         iobase = pci_resource_start(pdev, 0);
1801         mapbase = pci_resource_start(pdev, 1);
1802         priv->mapbase = mapbase;
1803         priv->iobase = iobase;
1804         priv->pdev = pdev;
1805         priv->tx_empty = 1;
1806         priv->rxbuf.buf = rxbuf;
1807         priv->rxbuf.size = PAGE_SIZE;
1808
1809         priv->fifo_size = fifosize;
1810         priv->uartclk = pch_uart_get_uartclk();
1811         priv->port_type = PORT_MAX_8250 + port_type + 1;
1812         priv->port.dev = &pdev->dev;
1813         priv->port.iobase = iobase;
1814         priv->port.membase = NULL;
1815         priv->port.mapbase = mapbase;
1816         priv->port.irq = pdev->irq;
1817         priv->port.iotype = UPIO_PORT;
1818         priv->port.ops = &pch_uart_ops;
1819         priv->port.flags = UPF_BOOT_AUTOCONF;
1820         priv->port.fifosize = fifosize;
1821         priv->port.line = board->line_no;
1822         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1823
1824         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1825                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1826                  priv->port.line);
1827
1828         spin_lock_init(&priv->port.lock);
1829
1830         pci_set_drvdata(pdev, priv);
1831         priv->trigger_level = 1;
1832         priv->fcr = 0;
1833
1834         if (pdev->dev.of_node)
1835                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1836                                          , &user_uartclk);
1837
1838 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1839         pch_uart_ports[board->line_no] = priv;
1840 #endif
1841         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1842         if (ret < 0)
1843                 goto init_port_hal_free;
1844
1845 #ifdef CONFIG_DEBUG_FS
1846         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1847         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1848                                 NULL, priv, &port_regs_ops);
1849 #endif
1850
1851         return priv;
1852
1853 init_port_hal_free:
1854 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1855         pch_uart_ports[board->line_no] = NULL;
1856 #endif
1857         free_page((unsigned long)rxbuf);
1858 init_port_free_txbuf:
1859         kfree(priv);
1860 init_port_alloc_err:
1861
1862         return NULL;
1863 }
1864
1865 static void pch_uart_exit_port(struct eg20t_port *priv)
1866 {
1867
1868 #ifdef CONFIG_DEBUG_FS
1869         if (priv->debugfs)
1870                 debugfs_remove(priv->debugfs);
1871 #endif
1872         uart_remove_one_port(&pch_uart_driver, &priv->port);
1873         free_page((unsigned long)priv->rxbuf.buf);
1874 }
1875
1876 static void pch_uart_pci_remove(struct pci_dev *pdev)
1877 {
1878         struct eg20t_port *priv = pci_get_drvdata(pdev);
1879
1880         pci_disable_msi(pdev);
1881
1882 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1883         pch_uart_ports[priv->port.line] = NULL;
1884 #endif
1885         pch_uart_exit_port(priv);
1886         pci_disable_device(pdev);
1887         kfree(priv);
1888         return;
1889 }
1890 #ifdef CONFIG_PM
1891 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1892 {
1893         struct eg20t_port *priv = pci_get_drvdata(pdev);
1894
1895         uart_suspend_port(&pch_uart_driver, &priv->port);
1896
1897         pci_save_state(pdev);
1898         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1899         return 0;
1900 }
1901
1902 static int pch_uart_pci_resume(struct pci_dev *pdev)
1903 {
1904         struct eg20t_port *priv = pci_get_drvdata(pdev);
1905         int ret;
1906
1907         pci_set_power_state(pdev, PCI_D0);
1908         pci_restore_state(pdev);
1909
1910         ret = pci_enable_device(pdev);
1911         if (ret) {
1912                 dev_err(&pdev->dev,
1913                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1914                 return ret;
1915         }
1916
1917         uart_resume_port(&pch_uart_driver, &priv->port);
1918
1919         return 0;
1920 }
1921 #else
1922 #define pch_uart_pci_suspend NULL
1923 #define pch_uart_pci_resume NULL
1924 #endif
1925
1926 static const struct pci_device_id pch_uart_pci_id[] = {
1927         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1928          .driver_data = pch_et20t_uart0},
1929         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1930          .driver_data = pch_et20t_uart1},
1931         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1932          .driver_data = pch_et20t_uart2},
1933         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1934          .driver_data = pch_et20t_uart3},
1935         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1936          .driver_data = pch_ml7213_uart0},
1937         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1938          .driver_data = pch_ml7213_uart1},
1939         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1940          .driver_data = pch_ml7213_uart2},
1941         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1942          .driver_data = pch_ml7223_uart0},
1943         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1944          .driver_data = pch_ml7223_uart1},
1945         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1946          .driver_data = pch_ml7831_uart0},
1947         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1948          .driver_data = pch_ml7831_uart1},
1949         {0,},
1950 };
1951
1952 static int pch_uart_pci_probe(struct pci_dev *pdev,
1953                                         const struct pci_device_id *id)
1954 {
1955         int ret;
1956         struct eg20t_port *priv;
1957
1958         ret = pci_enable_device(pdev);
1959         if (ret < 0)
1960                 goto probe_error;
1961
1962         priv = pch_uart_init_port(pdev, id);
1963         if (!priv) {
1964                 ret = -EBUSY;
1965                 goto probe_disable_device;
1966         }
1967         pci_set_drvdata(pdev, priv);
1968
1969         return ret;
1970
1971 probe_disable_device:
1972         pci_disable_msi(pdev);
1973         pci_disable_device(pdev);
1974 probe_error:
1975         return ret;
1976 }
1977
1978 static struct pci_driver pch_uart_pci_driver = {
1979         .name = "pch_uart",
1980         .id_table = pch_uart_pci_id,
1981         .probe = pch_uart_pci_probe,
1982         .remove = pch_uart_pci_remove,
1983         .suspend = pch_uart_pci_suspend,
1984         .resume = pch_uart_pci_resume,
1985 };
1986
1987 static int __init pch_uart_module_init(void)
1988 {
1989         int ret;
1990
1991         /* register as UART driver */
1992         ret = uart_register_driver(&pch_uart_driver);
1993         if (ret < 0)
1994                 return ret;
1995
1996         /* register as PCI driver */
1997         ret = pci_register_driver(&pch_uart_pci_driver);
1998         if (ret < 0)
1999                 uart_unregister_driver(&pch_uart_driver);
2000
2001         return ret;
2002 }
2003 module_init(pch_uart_module_init);
2004
2005 static void __exit pch_uart_module_exit(void)
2006 {
2007         pci_unregister_driver(&pch_uart_pci_driver);
2008         uart_unregister_driver(&pch_uart_driver);
2009 }
2010 module_exit(pch_uart_module_exit);
2011
2012 MODULE_LICENSE("GPL v2");
2013 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2014 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2015
2016 module_param(default_baud, uint, S_IRUGO);
2017 MODULE_PARM_DESC(default_baud,
2018                  "Default BAUD for initial driver state and console (default 9600)");
2019 module_param(user_uartclk, uint, S_IRUGO);
2020 MODULE_PARM_DESC(user_uartclk,
2021                  "Override UART default or board specific UART clock");