drivers/tty/serial/pch_uart.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   4  */
   5 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
   6 #define SUPPORT_SYSRQ
   7 #endif
   8 #include <linux/kernel.h>
   9 #include <linux/serial_reg.h>
  10 #include <linux/slab.h>
  11 #include <linux/module.h>
  12 #include <linux/pci.h>
  13 #include <linux/console.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/tty.h>
  16 #include <linux/tty_flip.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/dmi.h>
  20 #include <linux/nmi.h>
  21 #include <linux/delay.h>
  22 #include <linux/of.h>
  23
  24 #include <linux/debugfs.h>
  25 #include <linux/dmaengine.h>
  26 #include <linux/pch_dma.h>
  27
  28 enum {
  29         PCH_UART_HANDLED_RX_INT_SHIFT,
  30         PCH_UART_HANDLED_TX_INT_SHIFT,
  31         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  32         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  33         PCH_UART_HANDLED_MS_INT_SHIFT,
  34         PCH_UART_HANDLED_LS_INT_SHIFT,
  35 };
  36
  37 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  38
  39 /* Set the max number of UART port
  40  * Intel EG20T PCH: 4 port
  41  * LAPIS Semiconductor ML7213 IOH: 3 port
  42  * LAPIS Semiconductor ML7223 IOH: 2 port
  43 */
  44 #define PCH_UART_NR     4
  45
  46 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  47 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  48 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  49                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  50 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  51                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  52 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  53
  54 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  55
  56 #define PCH_UART_RBR            0x00
  57 #define PCH_UART_THR            0x00
  58
  59 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  60                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  61 #define PCH_UART_IER_ERBFI      0x00000001
  62 #define PCH_UART_IER_ETBEI      0x00000002
  63 #define PCH_UART_IER_ELSI       0x00000004
  64 #define PCH_UART_IER_EDSSI      0x00000008
  65
  66 #define PCH_UART_IIR_IP                 0x00000001
  67 #define PCH_UART_IIR_IID                0x00000006
  68 #define PCH_UART_IIR_MSI                0x00000000
  69 #define PCH_UART_IIR_TRI                0x00000002
  70 #define PCH_UART_IIR_RRI                0x00000004
  71 #define PCH_UART_IIR_REI                0x00000006
  72 #define PCH_UART_IIR_TOI                0x00000008
  73 #define PCH_UART_IIR_FIFO256            0x00000020
  74 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  75 #define PCH_UART_IIR_FE                 0x000000C0
  76
  77 #define PCH_UART_FCR_FIFOE              0x00000001
  78 #define PCH_UART_FCR_RFR                0x00000002
  79 #define PCH_UART_FCR_TFR                0x00000004
  80 #define PCH_UART_FCR_DMS                0x00000008
  81 #define PCH_UART_FCR_FIFO256            0x00000020
  82 #define PCH_UART_FCR_RFTL               0x000000C0
  83
  84 #define PCH_UART_FCR_RFTL1              0x00000000
  85 #define PCH_UART_FCR_RFTL64             0x00000040
  86 #define PCH_UART_FCR_RFTL128            0x00000080
  87 #define PCH_UART_FCR_RFTL224            0x000000C0
  88 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
  89 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
  90 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
  91 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
  92 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
  93 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
  94 #define PCH_UART_FCR_RFTL_SHIFT         6
  95
  96 #define PCH_UART_LCR_WLS        0x00000003
  97 #define PCH_UART_LCR_STB        0x00000004
  98 #define PCH_UART_LCR_PEN        0x00000008
  99 #define PCH_UART_LCR_EPS        0x00000010
 100 #define PCH_UART_LCR_SP         0x00000020
 101 #define PCH_UART_LCR_SB         0x00000040
 102 #define PCH_UART_LCR_DLAB       0x00000080
 103 #define PCH_UART_LCR_NP         0x00000000
 104 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 105 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 106 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 107 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 108                                 PCH_UART_LCR_SP)
 109
 110 #define PCH_UART_LCR_5BIT       0x00000000
 111 #define PCH_UART_LCR_6BIT       0x00000001
 112 #define PCH_UART_LCR_7BIT       0x00000002
 113 #define PCH_UART_LCR_8BIT       0x00000003
 114
 115 #define PCH_UART_MCR_DTR        0x00000001
 116 #define PCH_UART_MCR_RTS        0x00000002
 117 #define PCH_UART_MCR_OUT        0x0000000C
 118 #define PCH_UART_MCR_LOOP       0x00000010
 119 #define PCH_UART_MCR_AFE        0x00000020
 120
 121 #define PCH_UART_LSR_DR         0x00000001
 122 #define PCH_UART_LSR_ERR        (1<<7)
 123
 124 #define PCH_UART_MSR_DCTS       0x00000001
 125 #define PCH_UART_MSR_DDSR       0x00000002
 126 #define PCH_UART_MSR_TERI       0x00000004
 127 #define PCH_UART_MSR_DDCD       0x00000008
 128 #define PCH_UART_MSR_CTS        0x00000010
 129 #define PCH_UART_MSR_DSR        0x00000020
 130 #define PCH_UART_MSR_RI         0x00000040
 131 #define PCH_UART_MSR_DCD        0x00000080
 132 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 133                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 134
 135 #define PCH_UART_DLL            0x00
 136 #define PCH_UART_DLM            0x01
 137
 138 #define PCH_UART_BRCSR          0x0E
 139
 140 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 141 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 142 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 143 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 144 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 145
 146 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 147 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 148 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 149 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 150 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 151 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 152 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 153 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 154 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 155 #define PCH_UART_HAL_STB1               0
 156 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 157
 158 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 159 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 160 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 161                                         PCH_UART_HAL_CLR_RX_FIFO)
 162
 163 #define PCH_UART_HAL_DMA_MODE0          0
 164 #define PCH_UART_HAL_FIFO_DIS           0
 165 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 166 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 167                                         PCH_UART_FCR_FIFO256)
 168 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 169 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 170 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 171 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 172 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 173 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 174 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 175 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 176 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 177 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 178 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 179 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 180 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 181 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 182
 183 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 184 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 185 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 186 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 187 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 188
 189 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 190 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 191 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 192 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 193 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 194
 195 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 196
 197 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 198 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 199 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 200 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 201 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 202 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 203
 204 struct pch_uart_buffer {
 205         unsigned char *buf;
 206         int size;
 207 };
 208
 209 struct eg20t_port {
 210         struct uart_port port;
 211         int port_type;
 212         void __iomem *membase;
 213         resource_size_t mapbase;
 214         unsigned int iobase;
 215         struct pci_dev *pdev;
 216         int fifo_size;
 217         unsigned int uartclk;
 218         int start_tx;
 219         int start_rx;
 220         int tx_empty;
 221         int trigger;
 222         int trigger_level;
 223         struct pch_uart_buffer rxbuf;
 224         unsigned int dmsr;
 225         unsigned int fcr;
 226         unsigned int mcr;
 227         unsigned int use_dma;
 228         struct dma_async_tx_descriptor  *desc_tx;
 229         struct dma_async_tx_descriptor  *desc_rx;
 230         struct pch_dma_slave            param_tx;
 231         struct pch_dma_slave            param_rx;
 232         struct dma_chan                 *chan_tx;
 233         struct dma_chan                 *chan_rx;
 234         struct scatterlist              *sg_tx_p;
 235         int                             nent;
 236         int                             orig_nent;
 237         struct scatterlist              sg_rx;
 238         int                             tx_dma_use;
 239         void                            *rx_buf_virt;
 240         dma_addr_t                      rx_buf_dma;
 241
 242         struct dentry   *debugfs;
 243 #define IRQ_NAME_SIZE 17
 244         char                            irq_name[IRQ_NAME_SIZE];
 245
 246         /* protect the eg20t_port private structure and io access to membase */
 247         spinlock_t lock;
 248 };
 249
 250 /**
 251  * struct pch_uart_driver_data - private data structure for UART-DMA
 252  * @port_type:                  The type of UART port
 253  * @line_no:                    UART port line number (0, 1, 2...)
 254  */
 255 struct pch_uart_driver_data {
 256         int port_type;
 257         int line_no;
 258 };
 259
 260 enum pch_uart_num_t {
 261         pch_et20t_uart0 = 0,
 262         pch_et20t_uart1,
 263         pch_et20t_uart2,
 264         pch_et20t_uart3,
 265         pch_ml7213_uart0,
 266         pch_ml7213_uart1,
 267         pch_ml7213_uart2,
 268         pch_ml7223_uart0,
 269         pch_ml7223_uart1,
 270         pch_ml7831_uart0,
 271         pch_ml7831_uart1,
 272 };
 273
 274 static struct pch_uart_driver_data drv_dat[] = {
 275         [pch_et20t_uart0] = {PORT_PCH_8LINE, 0},
 276         [pch_et20t_uart1] = {PORT_PCH_2LINE, 1},
 277         [pch_et20t_uart2] = {PORT_PCH_2LINE, 2},
 278         [pch_et20t_uart3] = {PORT_PCH_2LINE, 3},
 279         [pch_ml7213_uart0] = {PORT_PCH_8LINE, 0},
 280         [pch_ml7213_uart1] = {PORT_PCH_2LINE, 1},
 281         [pch_ml7213_uart2] = {PORT_PCH_2LINE, 2},
 282         [pch_ml7223_uart0] = {PORT_PCH_8LINE, 0},
 283         [pch_ml7223_uart1] = {PORT_PCH_2LINE, 1},
 284         [pch_ml7831_uart0] = {PORT_PCH_8LINE, 0},
 285         [pch_ml7831_uart1] = {PORT_PCH_2LINE, 1},
 286 };
 287
 288 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 289 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 290 #endif
 291 static unsigned int default_baud = 9600;
 292 static unsigned int user_uartclk = 0;
 293 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 294 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 295 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 296 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 297
 298 #ifdef CONFIG_DEBUG_FS
 299
 300 #define PCH_REGS_BUFSIZE        1024
 301
 302
 303 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 304                                 size_t count, loff_t *ppos)
 305 {
 306         struct eg20t_port *priv = file->private_data;
 307         char *buf;
 308         u32 len = 0;
 309         ssize_t ret;
 310         unsigned char lcr;
 311
 312         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 313         if (!buf)
 314                 return 0;
 315
 316         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 317                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 318
 319         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 320                         "=================================\n");
 321         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 322                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 323         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 324                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 325         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 326                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 327         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 328                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 329         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 330                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 331         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 332                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 333         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 334                         "BRCSR: \t0x%02x\n",
 335                         ioread8(priv->membase + PCH_UART_BRCSR));
 336
 337         lcr = ioread8(priv->membase + UART_LCR);
 338         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 339         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 340                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 341         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 342                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 343         iowrite8(lcr, priv->membase + UART_LCR);
 344
 345         if (len > PCH_REGS_BUFSIZE)
 346                 len = PCH_REGS_BUFSIZE;
 347
 348         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 349         kfree(buf);
 350         return ret;
 351 }
 352
 353 static const struct file_operations port_regs_ops = {
 354         .owner          = THIS_MODULE,
 355         .open           = simple_open,
 356         .read           = port_show_regs,
 357         .llseek         = default_llseek,
 358 };
 359 #endif  /* CONFIG_DEBUG_FS */
 360
 361 static const struct dmi_system_id pch_uart_dmi_table[] = {
 362         {
 363                 .ident = "CM-iTC",
 364                 {
 365                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 366                 },
 367                 (void *)CMITC_UARTCLK,
 368         },
 369         {
 370                 .ident = "FRI2",
 371                 {
 372                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 373                 },
 374                 (void *)FRI2_64_UARTCLK,
 375         },
 376         {
 377                 .ident = "Fish River Island II",
 378                 {
 379                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 380                 },
 381                 (void *)FRI2_48_UARTCLK,
 382         },
 383         {
 384                 .ident = "COMe-mTT",
 385                 {
 386                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 387                 },
 388                 (void *)NTC1_UARTCLK,
 389         },
 390         {
 391                 .ident = "nanoETXexpress-TT",
 392                 {
 393                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 394                 },
 395                 (void *)NTC1_UARTCLK,
 396         },
 397         {
 398                 .ident = "MinnowBoard",
 399                 {
 400                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 401                 },
 402                 (void *)MINNOW_UARTCLK,
 403         },
 404         { }
 405 };
 406
 407 /* Return UART clock, checking for board specific clocks. */
 408 static unsigned int pch_uart_get_uartclk(void)
 409 {
 410         const struct dmi_system_id *d;
 411
 412         if (user_uartclk)
 413                 return user_uartclk;
 414
 415         d = dmi_first_match(pch_uart_dmi_table);
 416         if (d)
 417                 return (unsigned long)d->driver_data;
 418
 419         return DEFAULT_UARTCLK;
 420 }
 421
 422 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 423                                           unsigned int flag)
 424 {
 425         u8 ier = ioread8(priv->membase + UART_IER);
 426         ier |= flag & PCH_UART_IER_MASK;
 427         iowrite8(ier, priv->membase + UART_IER);
 428 }
 429
 430 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 431                                            unsigned int flag)
 432 {
 433         u8 ier = ioread8(priv->membase + UART_IER);
 434         ier &= ~(flag & PCH_UART_IER_MASK);
 435         iowrite8(ier, priv->membase + UART_IER);
 436 }
 437
 438 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 439                                  unsigned int parity, unsigned int bits,
 440                                  unsigned int stb)
 441 {
 442         unsigned int dll, dlm, lcr;
 443         int div;
 444
 445         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 446         if (div < 0 || USHRT_MAX <= div) {
 447                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 448                 return -EINVAL;
 449         }
 450
 451         dll = (unsigned int)div & 0x00FFU;
 452         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 453
 454         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 455                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 456                 return -EINVAL;
 457         }
 458
 459         if (bits & ~PCH_UART_LCR_WLS) {
 460                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 461                 return -EINVAL;
 462         }
 463
 464         if (stb & ~PCH_UART_LCR_STB) {
 465                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 466                 return -EINVAL;
 467         }
 468
 469         lcr = parity;
 470         lcr |= bits;
 471         lcr |= stb;
 472
 473         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 474                  __func__, baud, div, lcr, jiffies);
 475         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 476         iowrite8(dll, priv->membase + PCH_UART_DLL);
 477         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 478         iowrite8(lcr, priv->membase + UART_LCR);
 479
 480         return 0;
 481 }
 482
 483 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 484                                     unsigned int flag)
 485 {
 486         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 487                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 488                         __func__, flag);
 489                 return -EINVAL;
 490         }
 491
 492         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 493         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 494                  priv->membase + UART_FCR);
 495         iowrite8(priv->fcr, priv->membase + UART_FCR);
 496
 497         return 0;
 498 }
 499
 500 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 501                                  unsigned int dmamode,
 502                                  unsigned int fifo_size, unsigned int trigger)
 503 {
 504         u8 fcr;
 505
 506         if (dmamode & ~PCH_UART_FCR_DMS) {
 507                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 508                         __func__, dmamode);
 509                 return -EINVAL;
 510         }
 511
 512         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 513                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 514                         __func__, fifo_size);
 515                 return -EINVAL;
 516         }
 517
 518         if (trigger & ~PCH_UART_FCR_RFTL) {
 519                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 520                         __func__, trigger);
 521                 return -EINVAL;
 522         }
 523
 524         switch (priv->fifo_size) {
 525         case 256:
 526                 priv->trigger_level =
 527                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 528                 break;
 529         case 64:
 530                 priv->trigger_level =
 531                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 532                 break;
 533         case 16:
 534                 priv->trigger_level =
 535                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 536                 break;
 537         default:
 538                 priv->trigger_level =
 539                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 540                 break;
 541         }
 542         fcr =
 543             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 544         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 545         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 546                  priv->membase + UART_FCR);
 547         iowrite8(fcr, priv->membase + UART_FCR);
 548         priv->fcr = fcr;
 549
 550         return 0;
 551 }
 552
 553 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 554 {
 555         unsigned int msr = ioread8(priv->membase + UART_MSR);
 556         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 557         return (u8)msr;
 558 }
 559
 560 static void pch_uart_hal_write(struct eg20t_port *priv,
 561                               const unsigned char *buf, int tx_size)
 562 {
 563         int i;
 564         unsigned int thr;
 565
 566         for (i = 0; i < tx_size;) {
 567                 thr = buf[i++];
 568                 iowrite8(thr, priv->membase + PCH_UART_THR);
 569         }
 570 }
 571
 572 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 573                              int rx_size)
 574 {
 575         int i;
 576         u8 rbr, lsr;
 577         struct uart_port *port = &priv->port;
 578
 579         lsr = ioread8(priv->membase + UART_LSR);
 580         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 581              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 582              lsr = ioread8(priv->membase + UART_LSR)) {
 583                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 584
 585                 if (lsr & UART_LSR_BI) {
 586                         port->icount.brk++;
 587                         if (uart_handle_break(port))
 588                                 continue;
 589                 }
 590 #ifdef SUPPORT_SYSRQ
 591                 if (port->sysrq) {
 592                         if (uart_handle_sysrq_char(port, rbr))
 593                                 continue;
 594                 }
 595 #endif
 596
 597                 buf[i++] = rbr;
 598         }
 599         return i;
 600 }
 601
 602 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 603 {
 604         return ioread8(priv->membase + UART_IIR) &\
 605                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 606 }
 607
 608 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 609 {
 610         return ioread8(priv->membase + UART_LSR);
 611 }
 612
 613 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 614 {
 615         unsigned int lcr;
 616
 617         lcr = ioread8(priv->membase + UART_LCR);
 618         if (on)
 619                 lcr |= PCH_UART_LCR_SB;
 620         else
 621                 lcr &= ~PCH_UART_LCR_SB;
 622
 623         iowrite8(lcr, priv->membase + UART_LCR);
 624 }
 625
 626 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 627                    int size)
 628 {
 629         struct uart_port *port = &priv->port;
 630         struct tty_port *tport = &port->state->port;
 631
 632         tty_insert_flip_string(tport, buf, size);
 633         tty_flip_buffer_push(tport);
 634
 635         return 0;
 636 }
 637
 638 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 639 {
 640         int ret = 0;
 641         struct uart_port *port = &priv->port;
 642
 643         if (port->x_char) {
 644                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 645                         __func__, port->x_char, jiffies);
 646                 buf[0] = port->x_char;
 647                 port->x_char = 0;
 648                 ret = 1;
 649         }
 650
 651         return ret;
 652 }
 653
 654 static int dma_push_rx(struct eg20t_port *priv, int size)
 655 {
 656         int room;
 657         struct uart_port *port = &priv->port;
 658         struct tty_port *tport = &port->state->port;
 659
 660         room = tty_buffer_request_room(tport, size);
 661
 662         if (room < size)
 663                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 664                          size - room);
 665         if (!room)
 666                 return 0;
 667
 668         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 669
 670         port->icount.rx += room;
 671
 672         return room;
 673 }
 674
 675 static void pch_free_dma(struct uart_port *port)
 676 {
 677         struct eg20t_port *priv;
 678         priv = container_of(port, struct eg20t_port, port);
 679
 680         if (priv->chan_tx) {
 681                 dma_release_channel(priv->chan_tx);
 682                 priv->chan_tx = NULL;
 683         }
 684         if (priv->chan_rx) {
 685                 dma_release_channel(priv->chan_rx);
 686                 priv->chan_rx = NULL;
 687         }
 688
 689         if (priv->rx_buf_dma) {
 690                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 691                                   priv->rx_buf_dma);
 692                 priv->rx_buf_virt = NULL;
 693                 priv->rx_buf_dma = 0;
 694         }
 695
 696         return;
 697 }
 698
 699 static bool filter(struct dma_chan *chan, void *slave)
 700 {
 701         struct pch_dma_slave *param = slave;
 702
 703         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 704                                                   chan->device->dev)) {
 705                 chan->private = param;
 706                 return true;
 707         } else {
 708                 return false;
 709         }
 710 }
 711
 712 static void pch_request_dma(struct uart_port *port)
 713 {
 714         dma_cap_mask_t mask;
 715         struct dma_chan *chan;
 716         struct pci_dev *dma_dev;
 717         struct pch_dma_slave *param;
 718         struct eg20t_port *priv =
 719                                 container_of(port, struct eg20t_port, port);
 720         dma_cap_zero(mask);
 721         dma_cap_set(DMA_SLAVE, mask);
 722
 723         /* Get DMA's dev information */
 724         dma_dev = pci_get_slot(priv->pdev->bus,
 725                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 726
 727         /* Set Tx DMA */
 728         param = &priv->param_tx;
 729         param->dma_dev = &dma_dev->dev;
 730         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 731
 732         param->tx_reg = port->mapbase + UART_TX;
 733         chan = dma_request_channel(mask, filter, param);
 734         if (!chan) {
 735                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 736                         __func__);
 737                 pci_dev_put(dma_dev);
 738                 return;
 739         }
 740         priv->chan_tx = chan;
 741
 742         /* Set Rx DMA */
 743         param = &priv->param_rx;
 744         param->dma_dev = &dma_dev->dev;
 745         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 746
 747         param->rx_reg = port->mapbase + UART_RX;
 748         chan = dma_request_channel(mask, filter, param);
 749         if (!chan) {
 750                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 751                         __func__);
 752                 dma_release_channel(priv->chan_tx);
 753                 priv->chan_tx = NULL;
 754                 pci_dev_put(dma_dev);
 755                 return;
 756         }
 757
 758         /* Get Consistent memory for DMA */
 759         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 760                                     &priv->rx_buf_dma, GFP_KERNEL);
 761         priv->chan_rx = chan;
 762
 763         pci_dev_put(dma_dev);
 764 }
 765
 766 static void pch_dma_rx_complete(void *arg)
 767 {
 768         struct eg20t_port *priv = arg;
 769         struct uart_port *port = &priv->port;
 770         int count;
 771
 772         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 773         count = dma_push_rx(priv, priv->trigger_level);
 774         if (count)
 775                 tty_flip_buffer_push(&port->state->port);
 776         async_tx_ack(priv->desc_rx);
 777         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 778                                             PCH_UART_HAL_RX_ERR_INT);
 779 }
 780
 781 static void pch_dma_tx_complete(void *arg)
 782 {
 783         struct eg20t_port *priv = arg;
 784         struct uart_port *port = &priv->port;
 785         struct circ_buf *xmit = &port->state->xmit;
 786         struct scatterlist *sg = priv->sg_tx_p;
 787         int i;
 788
 789         for (i = 0; i < priv->nent; i++, sg++) {
 790                 xmit->tail += sg_dma_len(sg);
 791                 port->icount.tx += sg_dma_len(sg);
 792         }
 793         xmit->tail &= UART_XMIT_SIZE - 1;
 794         async_tx_ack(priv->desc_tx);
 795         dma_unmap_sg(port->dev, priv->sg_tx_p, priv->orig_nent, DMA_TO_DEVICE);
 796         priv->tx_dma_use = 0;
 797         priv->nent = 0;
 798         priv->orig_nent = 0;
 799         kfree(priv->sg_tx_p);
 800         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 801 }
 802
 803 static int pop_tx(struct eg20t_port *priv, int size)
 804 {
 805         int count = 0;
 806         struct uart_port *port = &priv->port;
 807         struct circ_buf *xmit = &port->state->xmit;
 808
 809         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 810                 goto pop_tx_end;
 811
 812         do {
 813                 int cnt_to_end =
 814                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 815                 int sz = min(size - count, cnt_to_end);
 816                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 817                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 818                 count += sz;
 819         } while (!uart_circ_empty(xmit) && count < size);
 820
 821 pop_tx_end:
 822         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 823                  count, size - count, jiffies);
 824
 825         return count;
 826 }
 827
 828 static int handle_rx_to(struct eg20t_port *priv)
 829 {
 830         struct pch_uart_buffer *buf;
 831         int rx_size;
 832         int ret;
 833         if (!priv->start_rx) {
 834                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 835                                                      PCH_UART_HAL_RX_ERR_INT);
 836                 return 0;
 837         }
 838         buf = &priv->rxbuf;
 839         do {
 840                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 841                 ret = push_rx(priv, buf->buf, rx_size);
 842                 if (ret)
 843                         return 0;
 844         } while (rx_size == buf->size);
 845
 846         return PCH_UART_HANDLED_RX_INT;
 847 }
 848
 849 static int handle_rx(struct eg20t_port *priv)
 850 {
 851         return handle_rx_to(priv);
 852 }
 853
 854 static int dma_handle_rx(struct eg20t_port *priv)
 855 {
 856         struct uart_port *port = &priv->port;
 857         struct dma_async_tx_descriptor *desc;
 858         struct scatterlist *sg;
 859
 860         priv = container_of(port, struct eg20t_port, port);
 861         sg = &priv->sg_rx;
 862
 863         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 864
 865         sg_dma_len(sg) = priv->trigger_level;
 866
 867         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 868                      sg_dma_len(sg), offset_in_page(priv->rx_buf_virt));
 869
 870         sg_dma_address(sg) = priv->rx_buf_dma;
 871
 872         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 873                         sg, 1, DMA_DEV_TO_MEM,
 874                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 875
 876         if (!desc)
 877                 return 0;
 878
 879         priv->desc_rx = desc;
 880         desc->callback = pch_dma_rx_complete;
 881         desc->callback_param = priv;
 882         desc->tx_submit(desc);
 883         dma_async_issue_pending(priv->chan_rx);
 884
 885         return PCH_UART_HANDLED_RX_INT;
 886 }
 887
 888 static unsigned int handle_tx(struct eg20t_port *priv)
 889 {
 890         struct uart_port *port = &priv->port;
 891         struct circ_buf *xmit = &port->state->xmit;
 892         int fifo_size;
 893         int tx_size;
 894         int size;
 895         int tx_empty;
 896
 897         if (!priv->start_tx) {
 898                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 899                         __func__, jiffies);
 900                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 901                 priv->tx_empty = 1;
 902                 return 0;
 903         }
 904
 905         fifo_size = max(priv->fifo_size, 1);
 906         tx_empty = 1;
 907         if (pop_tx_x(priv, xmit->buf)) {
 908                 pch_uart_hal_write(priv, xmit->buf, 1);
 909                 port->icount.tx++;
 910                 tx_empty = 0;
 911                 fifo_size--;
 912         }
 913         size = min(xmit->head - xmit->tail, fifo_size);
 914         if (size < 0)
 915                 size = fifo_size;
 916
 917         tx_size = pop_tx(priv, size);
 918         if (tx_size > 0) {
 919                 port->icount.tx += tx_size;
 920                 tx_empty = 0;
 921         }
 922
 923         priv->tx_empty = tx_empty;
 924
 925         if (tx_empty) {
 926                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 927                 uart_write_wakeup(port);
 928         }
 929
 930         return PCH_UART_HANDLED_TX_INT;
 931 }
 932
 933 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 934 {
 935         struct uart_port *port = &priv->port;
 936         struct circ_buf *xmit = &port->state->xmit;
 937         struct scatterlist *sg;
 938         int nent;
 939         int fifo_size;
 940         int tx_empty;
 941         struct dma_async_tx_descriptor *desc;
 942         int num;
 943         int i;
 944         int bytes;
 945         int size;
 946         int rem;
 947
 948         if (!priv->start_tx) {
 949                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 950                         __func__, jiffies);
 951                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 952                 priv->tx_empty = 1;
 953                 return 0;
 954         }
 955
 956         if (priv->tx_dma_use) {
 957                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 958                         __func__, jiffies);
 959                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 960                 priv->tx_empty = 1;
 961                 return 0;
 962         }
 963
 964         fifo_size = max(priv->fifo_size, 1);
 965         tx_empty = 1;
 966         if (pop_tx_x(priv, xmit->buf)) {
 967                 pch_uart_hal_write(priv, xmit->buf, 1);
 968                 port->icount.tx++;
 969                 tx_empty = 0;
 970                 fifo_size--;
 971         }
 972
 973         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 974                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 975                              xmit->tail, UART_XMIT_SIZE));
 976         if (!bytes) {
 977                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 978                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 979                 uart_write_wakeup(port);
 980                 return 0;
 981         }
 982
 983         if (bytes > fifo_size) {
 984                 num = bytes / fifo_size + 1;
 985                 size = fifo_size;
 986                 rem = bytes % fifo_size;
 987         } else {
 988                 num = 1;
 989                 size = bytes;
 990                 rem = bytes;
 991         }
 992
 993         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
 994                 __func__, num, size, rem);
 995
 996         priv->tx_dma_use = 1;
 997
 998         priv->sg_tx_p = kcalloc(num, sizeof(struct scatterlist), GFP_ATOMIC);
 999         if (!priv->sg_tx_p) {
1000                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1001                 return 0;
1002         }
1003
1004         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1005         sg = priv->sg_tx_p;
1006
1007         for (i = 0; i < num; i++, sg++) {
1008                 if (i == (num - 1))
1009                         sg_set_page(sg, virt_to_page(xmit->buf),
1010                                     rem, fifo_size * i);
1011                 else
1012                         sg_set_page(sg, virt_to_page(xmit->buf),
1013                                     size, fifo_size * i);
1014         }
1015
1016         sg = priv->sg_tx_p;
1017         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1018         if (!nent) {
1019                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1020                 return 0;
1021         }
1022         priv->orig_nent = num;
1023         priv->nent = nent;
1024
1025         for (i = 0; i < nent; i++, sg++) {
1026                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1027                               fifo_size * i;
1028                 sg_dma_address(sg) = (sg_dma_address(sg) &
1029                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1030                 if (i == (nent - 1))
1031                         sg_dma_len(sg) = rem;
1032                 else
1033                         sg_dma_len(sg) = size;
1034         }
1035
1036         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1037                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1038                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1039         if (!desc) {
1040                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1041                         __func__);
1042                 return 0;
1043         }
1044         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1045         priv->desc_tx = desc;
1046         desc->callback = pch_dma_tx_complete;
1047         desc->callback_param = priv;
1048
1049         desc->tx_submit(desc);
1050
1051         dma_async_issue_pending(priv->chan_tx);
1052
1053         return PCH_UART_HANDLED_TX_INT;
1054 }
1055
1056 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1057 {
1058         struct uart_port *port = &priv->port;
1059         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1060         char   *error_msg[5] = {};
1061         int    i = 0;
1062
1063         if (lsr & PCH_UART_LSR_ERR)
1064                 error_msg[i++] = "Error data in FIFO\n";
1065
1066         if (lsr & UART_LSR_FE) {
1067                 port->icount.frame++;
1068                 error_msg[i++] = "  Framing Error\n";
1069         }
1070
1071         if (lsr & UART_LSR_PE) {
1072                 port->icount.parity++;
1073                 error_msg[i++] = "  Parity Error\n";
1074         }
1075
1076         if (lsr & UART_LSR_OE) {
1077                 port->icount.overrun++;
1078                 error_msg[i++] = "  Overrun Error\n";
1079         }
1080
1081         if (tty == NULL) {
1082                 for (i = 0; error_msg[i] != NULL; i++)
1083                         dev_err(&priv->pdev->dev, error_msg[i]);
1084         } else {
1085                 tty_kref_put(tty);
1086         }
1087 }
1088
1089 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1090 {
1091         struct eg20t_port *priv = dev_id;
1092         unsigned int handled;
1093         u8 lsr;
1094         int ret = 0;
1095         unsigned char iid;
1096         unsigned long flags;
1097         int next = 1;
1098         u8 msr;
1099
1100         spin_lock_irqsave(&priv->lock, flags);
1101         handled = 0;
1102         while (next) {
1103                 iid = pch_uart_hal_get_iid(priv);
1104                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1105                         break;
1106                 switch (iid) {
1107                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1108                         lsr = pch_uart_hal_get_line_status(priv);
1109                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1110                                                 UART_LSR_PE | UART_LSR_OE)) {
1111                                 pch_uart_err_ir(priv, lsr);
1112                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1113                         } else {
1114                                 ret = PCH_UART_HANDLED_LS_INT;
1115                         }
1116                         break;
1117                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1118                         if (priv->use_dma) {
1119                                 pch_uart_hal_disable_interrupt(priv,
1120                                                 PCH_UART_HAL_RX_INT |
1121                                                 PCH_UART_HAL_RX_ERR_INT);
1122                                 ret = dma_handle_rx(priv);
1123                                 if (!ret)
1124                                         pch_uart_hal_enable_interrupt(priv,
1125                                                 PCH_UART_HAL_RX_INT |
1126                                                 PCH_UART_HAL_RX_ERR_INT);
1127                         } else {
1128                                 ret = handle_rx(priv);
1129                         }
1130                         break;
1131                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1132                                                    (FIFO Timeout) */
1133                         ret = handle_rx_to(priv);
1134                         break;
1135                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1136                                                    Empty */
1137                         if (priv->use_dma)
1138                                 ret = dma_handle_tx(priv);
1139                         else
1140                                 ret = handle_tx(priv);
1141                         break;
1142                 case PCH_UART_IID_MS:   /* Modem Status */
1143                         msr = pch_uart_hal_get_modem(priv);
1144                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1145                                      means final interrupt */
1146                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1147                                 break;
1148                         ret |= PCH_UART_HANDLED_MS_INT;
1149                         break;
1150                 default:        /* Never junp to this label */
1151                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1152                                 iid, jiffies);
1153                         ret = -1;
1154                         next = 0;
1155                         break;
1156                 }
1157                 handled |= (unsigned int)ret;
1158         }
1159
1160         spin_unlock_irqrestore(&priv->lock, flags);
1161         return IRQ_RETVAL(handled);
1162 }
1163
1164 /* This function tests whether the transmitter fifo and shifter for the port
1165                                                 described by 'port' is empty. */
1166 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1167 {
1168         struct eg20t_port *priv;
1169
1170         priv = container_of(port, struct eg20t_port, port);
1171         if (priv->tx_empty)
1172                 return TIOCSER_TEMT;
1173         else
1174                 return 0;
1175 }
1176
1177 /* Returns the current state of modem control inputs. */
1178 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1179 {
1180         struct eg20t_port *priv;
1181         u8 modem;
1182         unsigned int ret = 0;
1183
1184         priv = container_of(port, struct eg20t_port, port);
1185         modem = pch_uart_hal_get_modem(priv);
1186
1187         if (modem & UART_MSR_DCD)
1188                 ret |= TIOCM_CAR;
1189
1190         if (modem & UART_MSR_RI)
1191                 ret |= TIOCM_RNG;
1192
1193         if (modem & UART_MSR_DSR)
1194                 ret |= TIOCM_DSR;
1195
1196         if (modem & UART_MSR_CTS)
1197                 ret |= TIOCM_CTS;
1198
1199         return ret;
1200 }
1201
1202 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1203 {
1204         u32 mcr = 0;
1205         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1206
1207         if (mctrl & TIOCM_DTR)
1208                 mcr |= UART_MCR_DTR;
1209         if (mctrl & TIOCM_RTS)
1210                 mcr |= UART_MCR_RTS;
1211         if (mctrl & TIOCM_LOOP)
1212                 mcr |= UART_MCR_LOOP;
1213
1214         if (priv->mcr & UART_MCR_AFE)
1215                 mcr |= UART_MCR_AFE;
1216
1217         if (mctrl)
1218                 iowrite8(mcr, priv->membase + UART_MCR);
1219 }
1220
1221 static void pch_uart_stop_tx(struct uart_port *port)
1222 {
1223         struct eg20t_port *priv;
1224         priv = container_of(port, struct eg20t_port, port);
1225         priv->start_tx = 0;
1226         priv->tx_dma_use = 0;
1227 }
1228
1229 static void pch_uart_start_tx(struct uart_port *port)
1230 {
1231         struct eg20t_port *priv;
1232
1233         priv = container_of(port, struct eg20t_port, port);
1234
1235         if (priv->use_dma) {
1236                 if (priv->tx_dma_use) {
1237                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1238                                 __func__);
1239                         return;
1240                 }
1241         }
1242
1243         priv->start_tx = 1;
1244         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1245 }
1246
1247 static void pch_uart_stop_rx(struct uart_port *port)
1248 {
1249         struct eg20t_port *priv;
1250         priv = container_of(port, struct eg20t_port, port);
1251         priv->start_rx = 0;
1252         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1253                                              PCH_UART_HAL_RX_ERR_INT);
1254 }
1255
1256 /* Enable the modem status interrupts. */
1257 static void pch_uart_enable_ms(struct uart_port *port)
1258 {
1259         struct eg20t_port *priv;
1260         priv = container_of(port, struct eg20t_port, port);
1261         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1262 }
1263
1264 /* Control the transmission of a break signal. */
1265 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1266 {
1267         struct eg20t_port *priv;
1268         unsigned long flags;
1269
1270         priv = container_of(port, struct eg20t_port, port);
1271         spin_lock_irqsave(&priv->lock, flags);
1272         pch_uart_hal_set_break(priv, ctl);
1273         spin_unlock_irqrestore(&priv->lock, flags);
1274 }
1275
1276 /* Grab any interrupt resources and initialise any low level driver state. */
1277 static int pch_uart_startup(struct uart_port *port)
1278 {
1279         struct eg20t_port *priv;
1280         int ret;
1281         int fifo_size;
1282         int trigger_level;
1283
1284         priv = container_of(port, struct eg20t_port, port);
1285         priv->tx_empty = 1;
1286
1287         if (port->uartclk)
1288                 priv->uartclk = port->uartclk;
1289         else
1290                 port->uartclk = priv->uartclk;
1291
1292         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1293         ret = pch_uart_hal_set_line(priv, default_baud,
1294                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1295                               PCH_UART_HAL_STB1);
1296         if (ret)
1297                 return ret;
1298
1299         switch (priv->fifo_size) {
1300         case 256:
1301                 fifo_size = PCH_UART_HAL_FIFO256;
1302                 break;
1303         case 64:
1304                 fifo_size = PCH_UART_HAL_FIFO64;
1305                 break;
1306         case 16:
1307                 fifo_size = PCH_UART_HAL_FIFO16;
1308                 break;
1309         case 1:
1310         default:
1311                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1312                 break;
1313         }
1314
1315         switch (priv->trigger) {
1316         case PCH_UART_HAL_TRIGGER1:
1317                 trigger_level = 1;
1318                 break;
1319         case PCH_UART_HAL_TRIGGER_L:
1320                 trigger_level = priv->fifo_size / 4;
1321                 break;
1322         case PCH_UART_HAL_TRIGGER_M:
1323                 trigger_level = priv->fifo_size / 2;
1324                 break;
1325         case PCH_UART_HAL_TRIGGER_H:
1326         default:
1327                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1328                 break;
1329         }
1330
1331         priv->trigger_level = trigger_level;
1332         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1333                                     fifo_size, priv->trigger);
1334         if (ret < 0)
1335                 return ret;
1336
1337         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1338                         priv->irq_name, priv);
1339         if (ret < 0)
1340                 return ret;
1341
1342         if (priv->use_dma)
1343                 pch_request_dma(port);
1344
1345         priv->start_rx = 1;
1346         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1347                                             PCH_UART_HAL_RX_ERR_INT);
1348         uart_update_timeout(port, CS8, default_baud);
1349
1350         return 0;
1351 }
1352
1353 static void pch_uart_shutdown(struct uart_port *port)
1354 {
1355         struct eg20t_port *priv;
1356         int ret;
1357
1358         priv = container_of(port, struct eg20t_port, port);
1359         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1360         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1361         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1362                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1363         if (ret)
1364                 dev_err(priv->port.dev,
1365                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1366
1367         pch_free_dma(port);
1368
1369         free_irq(priv->port.irq, priv);
1370 }
1371
1372 /* Change the port parameters, including word length, parity, stop
1373  *bits.  Update read_status_mask and ignore_status_mask to indicate
1374  *the types of events we are interested in receiving.  */
1375 static void pch_uart_set_termios(struct uart_port *port,
1376                                  struct ktermios *termios, struct ktermios *old)
1377 {
1378         int rtn;
1379         unsigned int baud, parity, bits, stb;
1380         struct eg20t_port *priv;
1381         unsigned long flags;
1382
1383         priv = container_of(port, struct eg20t_port, port);
1384         switch (termios->c_cflag & CSIZE) {
1385         case CS5:
1386                 bits = PCH_UART_HAL_5BIT;
1387                 break;
1388         case CS6:
1389                 bits = PCH_UART_HAL_6BIT;
1390                 break;
1391         case CS7:
1392                 bits = PCH_UART_HAL_7BIT;
1393                 break;
1394         default:                /* CS8 */
1395                 bits = PCH_UART_HAL_8BIT;
1396                 break;
1397         }
1398         if (termios->c_cflag & CSTOPB)
1399                 stb = PCH_UART_HAL_STB2;
1400         else
1401                 stb = PCH_UART_HAL_STB1;
1402
1403         if (termios->c_cflag & PARENB) {
1404                 if (termios->c_cflag & PARODD)
1405                         parity = PCH_UART_HAL_PARITY_ODD;
1406                 else
1407                         parity = PCH_UART_HAL_PARITY_EVEN;
1408
1409         } else
1410                 parity = PCH_UART_HAL_PARITY_NONE;
1411
1412         /* Only UART0 has auto hardware flow function */
1413         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1414                 priv->mcr |= UART_MCR_AFE;
1415         else
1416                 priv->mcr &= ~UART_MCR_AFE;
1417
1418         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1419
1420         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1421
1422         spin_lock_irqsave(&priv->lock, flags);
1423         spin_lock(&port->lock);
1424
1425         uart_update_timeout(port, termios->c_cflag, baud);
1426         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1427         if (rtn)
1428                 goto out;
1429
1430         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1431         /* Don't rewrite B0 */
1432         if (tty_termios_baud_rate(termios))
1433                 tty_termios_encode_baud_rate(termios, baud, baud);
1434
1435 out:
1436         spin_unlock(&port->lock);
1437         spin_unlock_irqrestore(&priv->lock, flags);
1438 }
1439
1440 static const char *pch_uart_type(struct uart_port *port)
1441 {
1442         return KBUILD_MODNAME;
1443 }
1444
1445 static void pch_uart_release_port(struct uart_port *port)
1446 {
1447         struct eg20t_port *priv;
1448
1449         priv = container_of(port, struct eg20t_port, port);
1450         pci_iounmap(priv->pdev, priv->membase);
1451         pci_release_regions(priv->pdev);
1452 }
1453
1454 static int pch_uart_request_port(struct uart_port *port)
1455 {
1456         struct eg20t_port *priv;
1457         int ret;
1458         void __iomem *membase;
1459
1460         priv = container_of(port, struct eg20t_port, port);
1461         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1462         if (ret < 0)
1463                 return -EBUSY;
1464
1465         membase = pci_iomap(priv->pdev, 1, 0);
1466         if (!membase) {
1467                 pci_release_regions(priv->pdev);
1468                 return -EBUSY;
1469         }
1470         priv->membase = port->membase = membase;
1471
1472         return 0;
1473 }
1474
1475 static void pch_uart_config_port(struct uart_port *port, int type)
1476 {
1477         struct eg20t_port *priv;
1478
1479         priv = container_of(port, struct eg20t_port, port);
1480         if (type & UART_CONFIG_TYPE) {
1481                 port->type = priv->port_type;
1482                 pch_uart_request_port(port);
1483         }
1484 }
1485
1486 static int pch_uart_verify_port(struct uart_port *port,
1487                                 struct serial_struct *serinfo)
1488 {
1489         struct eg20t_port *priv;
1490
1491         priv = container_of(port, struct eg20t_port, port);
1492         if (serinfo->flags & UPF_LOW_LATENCY) {
1493                 dev_info(priv->port.dev,
1494                         "PCH UART : Use PIO Mode (without DMA)\n");
1495                 priv->use_dma = 0;
1496                 serinfo->flags &= ~UPF_LOW_LATENCY;
1497         } else {
1498 #ifndef CONFIG_PCH_DMA
1499                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1500                         __func__);
1501                 return -EOPNOTSUPP;
1502 #endif
1503                 if (!priv->use_dma) {
1504                         pch_request_dma(port);
1505                         if (priv->chan_rx)
1506                                 priv->use_dma = 1;
1507                 }
1508                 dev_info(priv->port.dev, "PCH UART: %s\n",
1509                                 priv->use_dma ?
1510                                 "Use DMA Mode" : "No DMA");
1511         }
1512
1513         return 0;
1514 }
1515
1516 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1517 /*
1518  *      Wait for transmitter & holding register to empty
1519  */
1520 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1521 {
1522         unsigned int status, tmout = 10000;
1523
1524         /* Wait up to 10ms for the character(s) to be sent. */
1525         for (;;) {
1526                 status = ioread8(up->membase + UART_LSR);
1527
1528                 if ((status & bits) == bits)
1529                         break;
1530                 if (--tmout == 0)
1531                         break;
1532                 udelay(1);
1533         }
1534
1535         /* Wait up to 1s for flow control if necessary */
1536         if (up->port.flags & UPF_CONS_FLOW) {
1537                 unsigned int tmout;
1538                 for (tmout = 1000000; tmout; tmout--) {
1539                         unsigned int msr = ioread8(up->membase + UART_MSR);
1540                         if (msr & UART_MSR_CTS)
1541                                 break;
1542                         udelay(1);
1543                         touch_nmi_watchdog();
1544                 }
1545         }
1546 }
1547 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1548
1549 #ifdef CONFIG_CONSOLE_POLL
1550 /*
1551  * Console polling routines for communicate via uart while
1552  * in an interrupt or debug context.
1553  */
1554 static int pch_uart_get_poll_char(struct uart_port *port)
1555 {
1556         struct eg20t_port *priv =
1557                 container_of(port, struct eg20t_port, port);
1558         u8 lsr = ioread8(priv->membase + UART_LSR);
1559
1560         if (!(lsr & UART_LSR_DR))
1561                 return NO_POLL_CHAR;
1562
1563         return ioread8(priv->membase + PCH_UART_RBR);
1564 }
1565
1566
1567 static void pch_uart_put_poll_char(struct uart_port *port,
1568                          unsigned char c)
1569 {
1570         unsigned int ier;
1571         struct eg20t_port *priv =
1572                 container_of(port, struct eg20t_port, port);
1573
1574         /*
1575          * First save the IER then disable the interrupts
1576          */
1577         ier = ioread8(priv->membase + UART_IER);
1578         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1579
1580         wait_for_xmitr(priv, UART_LSR_THRE);
1581         /*
1582          * Send the character out.
1583          */
1584         iowrite8(c, priv->membase + PCH_UART_THR);
1585
1586         /*
1587          * Finally, wait for transmitter to become empty
1588          * and restore the IER
1589          */
1590         wait_for_xmitr(priv, BOTH_EMPTY);
1591         iowrite8(ier, priv->membase + UART_IER);
1592 }
1593 #endif /* CONFIG_CONSOLE_POLL */
1594
1595 static const struct uart_ops pch_uart_ops = {
1596         .tx_empty = pch_uart_tx_empty,
1597         .set_mctrl = pch_uart_set_mctrl,
1598         .get_mctrl = pch_uart_get_mctrl,
1599         .stop_tx = pch_uart_stop_tx,
1600         .start_tx = pch_uart_start_tx,
1601         .stop_rx = pch_uart_stop_rx,
1602         .enable_ms = pch_uart_enable_ms,
1603         .break_ctl = pch_uart_break_ctl,
1604         .startup = pch_uart_startup,
1605         .shutdown = pch_uart_shutdown,
1606         .set_termios = pch_uart_set_termios,
1607 /*      .pm             = pch_uart_pm,          Not supported yet */
1608         .type = pch_uart_type,
1609         .release_port = pch_uart_release_port,
1610         .request_port = pch_uart_request_port,
1611         .config_port = pch_uart_config_port,
1612         .verify_port = pch_uart_verify_port,
1613 #ifdef CONFIG_CONSOLE_POLL
1614         .poll_get_char = pch_uart_get_poll_char,
1615         .poll_put_char = pch_uart_put_poll_char,
1616 #endif
1617 };
1618
1619 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1620
1621 static void pch_console_putchar(struct uart_port *port, int ch)
1622 {
1623         struct eg20t_port *priv =
1624                 container_of(port, struct eg20t_port, port);
1625
1626         wait_for_xmitr(priv, UART_LSR_THRE);
1627         iowrite8(ch, priv->membase + PCH_UART_THR);
1628 }
1629
1630 /*
1631  *      Print a string to the serial port trying not to disturb
1632  *      any possible real use of the port...
1633  *
1634  *      The console_lock must be held when we get here.
1635  */
1636 static void
1637 pch_console_write(struct console *co, const char *s, unsigned int count)
1638 {
1639         struct eg20t_port *priv;
1640         unsigned long flags;
1641         int priv_locked = 1;
1642         int port_locked = 1;
1643         u8 ier;
1644
1645         priv = pch_uart_ports[co->index];
1646
1647         touch_nmi_watchdog();
1648
1649         local_irq_save(flags);
1650         if (priv->port.sysrq) {
1651                 /* call to uart_handle_sysrq_char already took the priv lock */
1652                 priv_locked = 0;
1653                 /* serial8250_handle_port() already took the port lock */
1654                 port_locked = 0;
1655         } else if (oops_in_progress) {
1656                 priv_locked = spin_trylock(&priv->lock);
1657                 port_locked = spin_trylock(&priv->port.lock);
1658         } else {
1659                 spin_lock(&priv->lock);
1660                 spin_lock(&priv->port.lock);
1661         }
1662
1663         /*
1664          *      First save the IER then disable the interrupts
1665          */
1666         ier = ioread8(priv->membase + UART_IER);
1667
1668         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1669
1670         uart_console_write(&priv->port, s, count, pch_console_putchar);
1671
1672         /*
1673          *      Finally, wait for transmitter to become empty
1674          *      and restore the IER
1675          */
1676         wait_for_xmitr(priv, BOTH_EMPTY);
1677         iowrite8(ier, priv->membase + UART_IER);
1678
1679         if (port_locked)
1680                 spin_unlock(&priv->port.lock);
1681         if (priv_locked)
1682                 spin_unlock(&priv->lock);
1683         local_irq_restore(flags);
1684 }
1685
1686 static int __init pch_console_setup(struct console *co, char *options)
1687 {
1688         struct uart_port *port;
1689         int baud = default_baud;
1690         int bits = 8;
1691         int parity = 'n';
1692         int flow = 'n';
1693
1694         /*
1695          * Check whether an invalid uart number has been specified, and
1696          * if so, search for the first available port that does have
1697          * console support.
1698          */
1699         if (co->index >= PCH_UART_NR)
1700                 co->index = 0;
1701         port = &pch_uart_ports[co->index]->port;
1702
1703         if (!port || (!port->iobase && !port->membase))
1704                 return -ENODEV;
1705
1706         port->uartclk = pch_uart_get_uartclk();
1707
1708         if (options)
1709                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1710
1711         return uart_set_options(port, co, baud, parity, bits, flow);
1712 }
1713
1714 static struct uart_driver pch_uart_driver;
1715
1716 static struct console pch_console = {
1717         .name           = PCH_UART_DRIVER_DEVICE,
1718         .write          = pch_console_write,
1719         .device         = uart_console_device,
1720         .setup          = pch_console_setup,
1721         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1722         .index          = -1,
1723         .data           = &pch_uart_driver,
1724 };
1725
1726 #define PCH_CONSOLE     (&pch_console)
1727 #else
1728 #define PCH_CONSOLE     NULL
1729 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1730
1731 static struct uart_driver pch_uart_driver = {
1732         .owner = THIS_MODULE,
1733         .driver_name = KBUILD_MODNAME,
1734         .dev_name = PCH_UART_DRIVER_DEVICE,
1735         .major = 0,
1736         .minor = 0,
1737         .nr = PCH_UART_NR,
1738         .cons = PCH_CONSOLE,
1739 };
1740
1741 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1742                                              const struct pci_device_id *id)
1743 {
1744         struct eg20t_port *priv;
1745         int ret;
1746         unsigned int iobase;
1747         unsigned int mapbase;
1748         unsigned char *rxbuf;
1749         int fifosize;
1750         int port_type;
1751         struct pch_uart_driver_data *board;
1752 #ifdef CONFIG_DEBUG_FS
1753         char name[32];  /* for debugfs file name */
1754 #endif
1755
1756         board = &drv_dat[id->driver_data];
1757         port_type = board->port_type;
1758
1759         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1760         if (priv == NULL)
1761                 goto init_port_alloc_err;
1762
1763         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1764         if (!rxbuf)
1765                 goto init_port_free_txbuf;
1766
1767         switch (port_type) {
1768         case PORT_PCH_8LINE:
1769                 fifosize = 256; /* EG20T/ML7213: UART0 */
1770                 break;
1771         case PORT_PCH_2LINE:
1772                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1773                 break;
1774         default:
1775                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1776                 goto init_port_hal_free;
1777         }
1778
1779         pci_enable_msi(pdev);
1780         pci_set_master(pdev);
1781
1782         spin_lock_init(&priv->lock);
1783
1784         iobase = pci_resource_start(pdev, 0);
1785         mapbase = pci_resource_start(pdev, 1);
1786         priv->mapbase = mapbase;
1787         priv->iobase = iobase;
1788         priv->pdev = pdev;
1789         priv->tx_empty = 1;
1790         priv->rxbuf.buf = rxbuf;
1791         priv->rxbuf.size = PAGE_SIZE;
1792
1793         priv->fifo_size = fifosize;
1794         priv->uartclk = pch_uart_get_uartclk();
1795         priv->port_type = port_type;
1796         priv->port.dev = &pdev->dev;
1797         priv->port.iobase = iobase;
1798         priv->port.membase = NULL;
1799         priv->port.mapbase = mapbase;
1800         priv->port.irq = pdev->irq;
1801         priv->port.iotype = UPIO_PORT;
1802         priv->port.ops = &pch_uart_ops;
1803         priv->port.flags = UPF_BOOT_AUTOCONF;
1804         priv->port.fifosize = fifosize;
1805         priv->port.line = board->line_no;
1806         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1807
1808         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1809                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1810                  priv->port.line);
1811
1812         spin_lock_init(&priv->port.lock);
1813
1814         pci_set_drvdata(pdev, priv);
1815         priv->trigger_level = 1;
1816         priv->fcr = 0;
1817
1818         if (pdev->dev.of_node)
1819                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1820                                          , &user_uartclk);
1821
1822 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1823         pch_uart_ports[board->line_no] = priv;
1824 #endif
1825         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1826         if (ret < 0)
1827                 goto init_port_hal_free;
1828
1829 #ifdef CONFIG_DEBUG_FS
1830         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1831         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1832                                 NULL, priv, &port_regs_ops);
1833 #endif
1834
1835         return priv;
1836
1837 init_port_hal_free:
1838 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1839         pch_uart_ports[board->line_no] = NULL;
1840 #endif
1841         free_page((unsigned long)rxbuf);
1842 init_port_free_txbuf:
1843         kfree(priv);
1844 init_port_alloc_err:
1845
1846         return NULL;
1847 }
1848
1849 static void pch_uart_exit_port(struct eg20t_port *priv)
1850 {
1851
1852 #ifdef CONFIG_DEBUG_FS
1853         debugfs_remove(priv->debugfs);
1854 #endif
1855         uart_remove_one_port(&pch_uart_driver, &priv->port);
1856         free_page((unsigned long)priv->rxbuf.buf);
1857 }
1858
1859 static void pch_uart_pci_remove(struct pci_dev *pdev)
1860 {
1861         struct eg20t_port *priv = pci_get_drvdata(pdev);
1862
1863         pci_disable_msi(pdev);
1864
1865 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1866         pch_uart_ports[priv->port.line] = NULL;
1867 #endif
1868         pch_uart_exit_port(priv);
1869         pci_disable_device(pdev);
1870         kfree(priv);
1871         return;
1872 }
1873 #ifdef CONFIG_PM
1874 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1875 {
1876         struct eg20t_port *priv = pci_get_drvdata(pdev);
1877
1878         uart_suspend_port(&pch_uart_driver, &priv->port);
1879
1880         pci_save_state(pdev);
1881         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1882         return 0;
1883 }
1884
1885 static int pch_uart_pci_resume(struct pci_dev *pdev)
1886 {
1887         struct eg20t_port *priv = pci_get_drvdata(pdev);
1888         int ret;
1889
1890         pci_set_power_state(pdev, PCI_D0);
1891         pci_restore_state(pdev);
1892
1893         ret = pci_enable_device(pdev);
1894         if (ret) {
1895                 dev_err(&pdev->dev,
1896                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1897                 return ret;
1898         }
1899
1900         uart_resume_port(&pch_uart_driver, &priv->port);
1901
1902         return 0;
1903 }
1904 #else
1905 #define pch_uart_pci_suspend NULL
1906 #define pch_uart_pci_resume NULL
1907 #endif
1908
1909 static const struct pci_device_id pch_uart_pci_id[] = {
1910         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1911          .driver_data = pch_et20t_uart0},
1912         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1913          .driver_data = pch_et20t_uart1},
1914         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1915          .driver_data = pch_et20t_uart2},
1916         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1917          .driver_data = pch_et20t_uart3},
1918         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1919          .driver_data = pch_ml7213_uart0},
1920         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1921          .driver_data = pch_ml7213_uart1},
1922         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1923          .driver_data = pch_ml7213_uart2},
1924         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1925          .driver_data = pch_ml7223_uart0},
1926         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1927          .driver_data = pch_ml7223_uart1},
1928         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1929          .driver_data = pch_ml7831_uart0},
1930         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1931          .driver_data = pch_ml7831_uart1},
1932         {0,},
1933 };
1934
1935 static int pch_uart_pci_probe(struct pci_dev *pdev,
1936                                         const struct pci_device_id *id)
1937 {
1938         int ret;
1939         struct eg20t_port *priv;
1940
1941         ret = pci_enable_device(pdev);
1942         if (ret < 0)
1943                 goto probe_error;
1944
1945         priv = pch_uart_init_port(pdev, id);
1946         if (!priv) {
1947                 ret = -EBUSY;
1948                 goto probe_disable_device;
1949         }
1950         pci_set_drvdata(pdev, priv);
1951
1952         return ret;
1953
1954 probe_disable_device:
1955         pci_disable_msi(pdev);
1956         pci_disable_device(pdev);
1957 probe_error:
1958         return ret;
1959 }
1960
1961 static struct pci_driver pch_uart_pci_driver = {
1962         .name = "pch_uart",
1963         .id_table = pch_uart_pci_id,
1964         .probe = pch_uart_pci_probe,
1965         .remove = pch_uart_pci_remove,
1966         .suspend = pch_uart_pci_suspend,
1967         .resume = pch_uart_pci_resume,
1968 };
1969
1970 static int __init pch_uart_module_init(void)
1971 {
1972         int ret;
1973
1974         /* register as UART driver */
1975         ret = uart_register_driver(&pch_uart_driver);
1976         if (ret < 0)
1977                 return ret;
1978
1979         /* register as PCI driver */
1980         ret = pci_register_driver(&pch_uart_pci_driver);
1981         if (ret < 0)
1982                 uart_unregister_driver(&pch_uart_driver);
1983
1984         return ret;
1985 }
1986 module_init(pch_uart_module_init);
1987
1988 static void __exit pch_uart_module_exit(void)
1989 {
1990         pci_unregister_driver(&pch_uart_pci_driver);
1991         uart_unregister_driver(&pch_uart_driver);
1992 }
1993 module_exit(pch_uart_module_exit);
1994
1995 MODULE_LICENSE("GPL v2");
1996 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
1997 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
1998
1999 module_param(default_baud, uint, S_IRUGO);
2000 MODULE_PARM_DESC(default_baud,
2001                  "Default BAUD for initial driver state and console (default 9600)");
2002 module_param(user_uartclk, uint, S_IRUGO);
2003 MODULE_PARM_DESC(user_uartclk,
2004                  "Override UART default or board specific UART clock");