drivers/tty/serial/pch_uart.c

   1 /*
   2  *Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  *This program is free software; you can redistribute it and/or modify
   5  *it under the terms of the GNU General Public License as published by
   6  *the Free Software Foundation; version 2 of the License.
   7  *
   8  *This program is distributed in the hope that it will be useful,
   9  *but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  *MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  *GNU General Public License for more details.
  12  *
  13  *You should have received a copy of the GNU General Public License
  14  *along with this program; if not, write to the Free Software
  15  *Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307, USA.
  16  */
  17 #if defined(CONFIG_SERIAL_PCH_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  18 #define SUPPORT_SYSRQ
  19 #endif
  20 #include <linux/kernel.h>
  21 #include <linux/serial_reg.h>
  22 #include <linux/slab.h>
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/console.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/tty.h>
  28 #include <linux/tty_flip.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/io.h>
  31 #include <linux/dmi.h>
  32 #include <linux/nmi.h>
  33 #include <linux/delay.h>
  34 #include <linux/of.h>
  35
  36 #include <linux/debugfs.h>
  37 #include <linux/dmaengine.h>
  38 #include <linux/pch_dma.h>
  39
  40 enum {
  41         PCH_UART_HANDLED_RX_INT_SHIFT,
  42         PCH_UART_HANDLED_TX_INT_SHIFT,
  43         PCH_UART_HANDLED_RX_ERR_INT_SHIFT,
  44         PCH_UART_HANDLED_RX_TRG_INT_SHIFT,
  45         PCH_UART_HANDLED_MS_INT_SHIFT,
  46         PCH_UART_HANDLED_LS_INT_SHIFT,
  47 };
  48
  49 enum {
  50         PCH_UART_8LINE,
  51         PCH_UART_2LINE,
  52 };
  53
  54 #define PCH_UART_DRIVER_DEVICE "ttyPCH"
  55
  56 /* Set the max number of UART port
  57  * Intel EG20T PCH: 4 port
  58  * LAPIS Semiconductor ML7213 IOH: 3 port
  59  * LAPIS Semiconductor ML7223 IOH: 2 port
  60 */
  61 #define PCH_UART_NR     4
  62
  63 #define PCH_UART_HANDLED_RX_INT (1<<((PCH_UART_HANDLED_RX_INT_SHIFT)<<1))
  64 #define PCH_UART_HANDLED_TX_INT (1<<((PCH_UART_HANDLED_TX_INT_SHIFT)<<1))
  65 #define PCH_UART_HANDLED_RX_ERR_INT     (1<<((\
  66                                         PCH_UART_HANDLED_RX_ERR_INT_SHIFT)<<1))
  67 #define PCH_UART_HANDLED_RX_TRG_INT     (1<<((\
  68                                         PCH_UART_HANDLED_RX_TRG_INT_SHIFT)<<1))
  69 #define PCH_UART_HANDLED_MS_INT (1<<((PCH_UART_HANDLED_MS_INT_SHIFT)<<1))
  70
  71 #define PCH_UART_HANDLED_LS_INT (1<<((PCH_UART_HANDLED_LS_INT_SHIFT)<<1))
  72
  73 #define PCH_UART_RBR            0x00
  74 #define PCH_UART_THR            0x00
  75
  76 #define PCH_UART_IER_MASK       (PCH_UART_IER_ERBFI|PCH_UART_IER_ETBEI|\
  77                                 PCH_UART_IER_ELSI|PCH_UART_IER_EDSSI)
  78 #define PCH_UART_IER_ERBFI      0x00000001
  79 #define PCH_UART_IER_ETBEI      0x00000002
  80 #define PCH_UART_IER_ELSI       0x00000004
  81 #define PCH_UART_IER_EDSSI      0x00000008
  82
  83 #define PCH_UART_IIR_IP                 0x00000001
  84 #define PCH_UART_IIR_IID                0x00000006
  85 #define PCH_UART_IIR_MSI                0x00000000
  86 #define PCH_UART_IIR_TRI                0x00000002
  87 #define PCH_UART_IIR_RRI                0x00000004
  88 #define PCH_UART_IIR_REI                0x00000006
  89 #define PCH_UART_IIR_TOI                0x00000008
  90 #define PCH_UART_IIR_FIFO256            0x00000020
  91 #define PCH_UART_IIR_FIFO64             PCH_UART_IIR_FIFO256
  92 #define PCH_UART_IIR_FE                 0x000000C0
  93
  94 #define PCH_UART_FCR_FIFOE              0x00000001
  95 #define PCH_UART_FCR_RFR                0x00000002
  96 #define PCH_UART_FCR_TFR                0x00000004
  97 #define PCH_UART_FCR_DMS                0x00000008
  98 #define PCH_UART_FCR_FIFO256            0x00000020
  99 #define PCH_UART_FCR_RFTL               0x000000C0
 100
 101 #define PCH_UART_FCR_RFTL1              0x00000000
 102 #define PCH_UART_FCR_RFTL64             0x00000040
 103 #define PCH_UART_FCR_RFTL128            0x00000080
 104 #define PCH_UART_FCR_RFTL224            0x000000C0
 105 #define PCH_UART_FCR_RFTL16             PCH_UART_FCR_RFTL64
 106 #define PCH_UART_FCR_RFTL32             PCH_UART_FCR_RFTL128
 107 #define PCH_UART_FCR_RFTL56             PCH_UART_FCR_RFTL224
 108 #define PCH_UART_FCR_RFTL4              PCH_UART_FCR_RFTL64
 109 #define PCH_UART_FCR_RFTL8              PCH_UART_FCR_RFTL128
 110 #define PCH_UART_FCR_RFTL14             PCH_UART_FCR_RFTL224
 111 #define PCH_UART_FCR_RFTL_SHIFT         6
 112
 113 #define PCH_UART_LCR_WLS        0x00000003
 114 #define PCH_UART_LCR_STB        0x00000004
 115 #define PCH_UART_LCR_PEN        0x00000008
 116 #define PCH_UART_LCR_EPS        0x00000010
 117 #define PCH_UART_LCR_SP         0x00000020
 118 #define PCH_UART_LCR_SB         0x00000040
 119 #define PCH_UART_LCR_DLAB       0x00000080
 120 #define PCH_UART_LCR_NP         0x00000000
 121 #define PCH_UART_LCR_OP         PCH_UART_LCR_PEN
 122 #define PCH_UART_LCR_EP         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS)
 123 #define PCH_UART_LCR_1P         (PCH_UART_LCR_PEN | PCH_UART_LCR_SP)
 124 #define PCH_UART_LCR_0P         (PCH_UART_LCR_PEN | PCH_UART_LCR_EPS |\
 125                                 PCH_UART_LCR_SP)
 126
 127 #define PCH_UART_LCR_5BIT       0x00000000
 128 #define PCH_UART_LCR_6BIT       0x00000001
 129 #define PCH_UART_LCR_7BIT       0x00000002
 130 #define PCH_UART_LCR_8BIT       0x00000003
 131
 132 #define PCH_UART_MCR_DTR        0x00000001
 133 #define PCH_UART_MCR_RTS        0x00000002
 134 #define PCH_UART_MCR_OUT        0x0000000C
 135 #define PCH_UART_MCR_LOOP       0x00000010
 136 #define PCH_UART_MCR_AFE        0x00000020
 137
 138 #define PCH_UART_LSR_DR         0x00000001
 139 #define PCH_UART_LSR_ERR        (1<<7)
 140
 141 #define PCH_UART_MSR_DCTS       0x00000001
 142 #define PCH_UART_MSR_DDSR       0x00000002
 143 #define PCH_UART_MSR_TERI       0x00000004
 144 #define PCH_UART_MSR_DDCD       0x00000008
 145 #define PCH_UART_MSR_CTS        0x00000010
 146 #define PCH_UART_MSR_DSR        0x00000020
 147 #define PCH_UART_MSR_RI         0x00000040
 148 #define PCH_UART_MSR_DCD        0x00000080
 149 #define PCH_UART_MSR_DELTA      (PCH_UART_MSR_DCTS | PCH_UART_MSR_DDSR |\
 150                                 PCH_UART_MSR_TERI | PCH_UART_MSR_DDCD)
 151
 152 #define PCH_UART_DLL            0x00
 153 #define PCH_UART_DLM            0x01
 154
 155 #define PCH_UART_BRCSR          0x0E
 156
 157 #define PCH_UART_IID_RLS        (PCH_UART_IIR_REI)
 158 #define PCH_UART_IID_RDR        (PCH_UART_IIR_RRI)
 159 #define PCH_UART_IID_RDR_TO     (PCH_UART_IIR_RRI | PCH_UART_IIR_TOI)
 160 #define PCH_UART_IID_THRE       (PCH_UART_IIR_TRI)
 161 #define PCH_UART_IID_MS         (PCH_UART_IIR_MSI)
 162
 163 #define PCH_UART_HAL_PARITY_NONE        (PCH_UART_LCR_NP)
 164 #define PCH_UART_HAL_PARITY_ODD         (PCH_UART_LCR_OP)
 165 #define PCH_UART_HAL_PARITY_EVEN        (PCH_UART_LCR_EP)
 166 #define PCH_UART_HAL_PARITY_FIX1        (PCH_UART_LCR_1P)
 167 #define PCH_UART_HAL_PARITY_FIX0        (PCH_UART_LCR_0P)
 168 #define PCH_UART_HAL_5BIT               (PCH_UART_LCR_5BIT)
 169 #define PCH_UART_HAL_6BIT               (PCH_UART_LCR_6BIT)
 170 #define PCH_UART_HAL_7BIT               (PCH_UART_LCR_7BIT)
 171 #define PCH_UART_HAL_8BIT               (PCH_UART_LCR_8BIT)
 172 #define PCH_UART_HAL_STB1               0
 173 #define PCH_UART_HAL_STB2               (PCH_UART_LCR_STB)
 174
 175 #define PCH_UART_HAL_CLR_TX_FIFO        (PCH_UART_FCR_TFR)
 176 #define PCH_UART_HAL_CLR_RX_FIFO        (PCH_UART_FCR_RFR)
 177 #define PCH_UART_HAL_CLR_ALL_FIFO       (PCH_UART_HAL_CLR_TX_FIFO | \
 178                                         PCH_UART_HAL_CLR_RX_FIFO)
 179
 180 #define PCH_UART_HAL_DMA_MODE0          0
 181 #define PCH_UART_HAL_FIFO_DIS           0
 182 #define PCH_UART_HAL_FIFO16             (PCH_UART_FCR_FIFOE)
 183 #define PCH_UART_HAL_FIFO256            (PCH_UART_FCR_FIFOE | \
 184                                         PCH_UART_FCR_FIFO256)
 185 #define PCH_UART_HAL_FIFO64             (PCH_UART_HAL_FIFO256)
 186 #define PCH_UART_HAL_TRIGGER1           (PCH_UART_FCR_RFTL1)
 187 #define PCH_UART_HAL_TRIGGER64          (PCH_UART_FCR_RFTL64)
 188 #define PCH_UART_HAL_TRIGGER128         (PCH_UART_FCR_RFTL128)
 189 #define PCH_UART_HAL_TRIGGER224         (PCH_UART_FCR_RFTL224)
 190 #define PCH_UART_HAL_TRIGGER16          (PCH_UART_FCR_RFTL16)
 191 #define PCH_UART_HAL_TRIGGER32          (PCH_UART_FCR_RFTL32)
 192 #define PCH_UART_HAL_TRIGGER56          (PCH_UART_FCR_RFTL56)
 193 #define PCH_UART_HAL_TRIGGER4           (PCH_UART_FCR_RFTL4)
 194 #define PCH_UART_HAL_TRIGGER8           (PCH_UART_FCR_RFTL8)
 195 #define PCH_UART_HAL_TRIGGER14          (PCH_UART_FCR_RFTL14)
 196 #define PCH_UART_HAL_TRIGGER_L          (PCH_UART_FCR_RFTL64)
 197 #define PCH_UART_HAL_TRIGGER_M          (PCH_UART_FCR_RFTL128)
 198 #define PCH_UART_HAL_TRIGGER_H          (PCH_UART_FCR_RFTL224)
 199
 200 #define PCH_UART_HAL_RX_INT             (PCH_UART_IER_ERBFI)
 201 #define PCH_UART_HAL_TX_INT             (PCH_UART_IER_ETBEI)
 202 #define PCH_UART_HAL_RX_ERR_INT         (PCH_UART_IER_ELSI)
 203 #define PCH_UART_HAL_MS_INT             (PCH_UART_IER_EDSSI)
 204 #define PCH_UART_HAL_ALL_INT            (PCH_UART_IER_MASK)
 205
 206 #define PCH_UART_HAL_DTR                (PCH_UART_MCR_DTR)
 207 #define PCH_UART_HAL_RTS                (PCH_UART_MCR_RTS)
 208 #define PCH_UART_HAL_OUT                (PCH_UART_MCR_OUT)
 209 #define PCH_UART_HAL_LOOP               (PCH_UART_MCR_LOOP)
 210 #define PCH_UART_HAL_AFE                (PCH_UART_MCR_AFE)
 211
 212 #define PCI_VENDOR_ID_ROHM              0x10DB
 213
 214 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
 215
 216 #define DEFAULT_UARTCLK   1843200 /*   1.8432 MHz */
 217 #define CMITC_UARTCLK   192000000 /* 192.0000 MHz */
 218 #define FRI2_64_UARTCLK  64000000 /*  64.0000 MHz */
 219 #define FRI2_48_UARTCLK  48000000 /*  48.0000 MHz */
 220 #define NTC1_UARTCLK     64000000 /*  64.0000 MHz */
 221 #define MINNOW_UARTCLK   50000000 /*  50.0000 MHz */
 222
 223 struct pch_uart_buffer {
 224         unsigned char *buf;
 225         int size;
 226 };
 227
 228 struct eg20t_port {
 229         struct uart_port port;
 230         int port_type;
 231         void __iomem *membase;
 232         resource_size_t mapbase;
 233         unsigned int iobase;
 234         struct pci_dev *pdev;
 235         int fifo_size;
 236         unsigned int uartclk;
 237         int start_tx;
 238         int start_rx;
 239         int tx_empty;
 240         int trigger;
 241         int trigger_level;
 242         struct pch_uart_buffer rxbuf;
 243         unsigned int dmsr;
 244         unsigned int fcr;
 245         unsigned int mcr;
 246         unsigned int use_dma;
 247         struct dma_async_tx_descriptor  *desc_tx;
 248         struct dma_async_tx_descriptor  *desc_rx;
 249         struct pch_dma_slave            param_tx;
 250         struct pch_dma_slave            param_rx;
 251         struct dma_chan                 *chan_tx;
 252         struct dma_chan                 *chan_rx;
 253         struct scatterlist              *sg_tx_p;
 254         int                             nent;
 255         int                             orig_nent;
 256         struct scatterlist              sg_rx;
 257         int                             tx_dma_use;
 258         void                            *rx_buf_virt;
 259         dma_addr_t                      rx_buf_dma;
 260
 261         struct dentry   *debugfs;
 262 #define IRQ_NAME_SIZE 17
 263         char                            irq_name[IRQ_NAME_SIZE];
 264
 265         /* protect the eg20t_port private structure and io access to membase */
 266         spinlock_t lock;
 267 };
 268
 269 /**
 270  * struct pch_uart_driver_data - private data structure for UART-DMA
 271  * @port_type:                  The number of DMA channel
 272  * @line_no:                    UART port line number (0, 1, 2...)
 273  */
 274 struct pch_uart_driver_data {
 275         int port_type;
 276         int line_no;
 277 };
 278
 279 enum pch_uart_num_t {
 280         pch_et20t_uart0 = 0,
 281         pch_et20t_uart1,
 282         pch_et20t_uart2,
 283         pch_et20t_uart3,
 284         pch_ml7213_uart0,
 285         pch_ml7213_uart1,
 286         pch_ml7213_uart2,
 287         pch_ml7223_uart0,
 288         pch_ml7223_uart1,
 289         pch_ml7831_uart0,
 290         pch_ml7831_uart1,
 291 };
 292
 293 static struct pch_uart_driver_data drv_dat[] = {
 294         [pch_et20t_uart0] = {PCH_UART_8LINE, 0},
 295         [pch_et20t_uart1] = {PCH_UART_2LINE, 1},
 296         [pch_et20t_uart2] = {PCH_UART_2LINE, 2},
 297         [pch_et20t_uart3] = {PCH_UART_2LINE, 3},
 298         [pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
 299         [pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
 300         [pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
 301         [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
 302         [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
 303         [pch_ml7831_uart0] = {PCH_UART_8LINE, 0},
 304         [pch_ml7831_uart1] = {PCH_UART_2LINE, 1},
 305 };
 306
 307 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
 308 static struct eg20t_port *pch_uart_ports[PCH_UART_NR];
 309 #endif
 310 static unsigned int default_baud = 9600;
 311 static unsigned int user_uartclk = 0;
 312 static const int trigger_level_256[4] = { 1, 64, 128, 224 };
 313 static const int trigger_level_64[4] = { 1, 16, 32, 56 };
 314 static const int trigger_level_16[4] = { 1, 4, 8, 14 };
 315 static const int trigger_level_1[4] = { 1, 1, 1, 1 };
 316
 317 #ifdef CONFIG_DEBUG_FS
 318
 319 #define PCH_REGS_BUFSIZE        1024
 320
 321
 322 static ssize_t port_show_regs(struct file *file, char __user *user_buf,
 323                                 size_t count, loff_t *ppos)
 324 {
 325         struct eg20t_port *priv = file->private_data;
 326         char *buf;
 327         u32 len = 0;
 328         ssize_t ret;
 329         unsigned char lcr;
 330
 331         buf = kzalloc(PCH_REGS_BUFSIZE, GFP_KERNEL);
 332         if (!buf)
 333                 return 0;
 334
 335         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 336                         "PCH EG20T port[%d] regs:\n", priv->port.line);
 337
 338         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 339                         "=================================\n");
 340         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 341                         "IER: \t0x%02x\n", ioread8(priv->membase + UART_IER));
 342         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 343                         "IIR: \t0x%02x\n", ioread8(priv->membase + UART_IIR));
 344         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 345                         "LCR: \t0x%02x\n", ioread8(priv->membase + UART_LCR));
 346         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 347                         "MCR: \t0x%02x\n", ioread8(priv->membase + UART_MCR));
 348         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 349                         "LSR: \t0x%02x\n", ioread8(priv->membase + UART_LSR));
 350         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 351                         "MSR: \t0x%02x\n", ioread8(priv->membase + UART_MSR));
 352         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 353                         "BRCSR: \t0x%02x\n",
 354                         ioread8(priv->membase + PCH_UART_BRCSR));
 355
 356         lcr = ioread8(priv->membase + UART_LCR);
 357         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 358         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 359                         "DLL: \t0x%02x\n", ioread8(priv->membase + UART_DLL));
 360         len += snprintf(buf + len, PCH_REGS_BUFSIZE - len,
 361                         "DLM: \t0x%02x\n", ioread8(priv->membase + UART_DLM));
 362         iowrite8(lcr, priv->membase + UART_LCR);
 363
 364         if (len > PCH_REGS_BUFSIZE)
 365                 len = PCH_REGS_BUFSIZE;
 366
 367         ret =  simple_read_from_buffer(user_buf, count, ppos, buf, len);
 368         kfree(buf);
 369         return ret;
 370 }
 371
 372 static const struct file_operations port_regs_ops = {
 373         .owner          = THIS_MODULE,
 374         .open           = simple_open,
 375         .read           = port_show_regs,
 376         .llseek         = default_llseek,
 377 };
 378 #endif  /* CONFIG_DEBUG_FS */
 379
 380 static struct dmi_system_id pch_uart_dmi_table[] = {
 381         {
 382                 .ident = "CM-iTC",
 383                 {
 384                         DMI_MATCH(DMI_BOARD_NAME, "CM-iTC"),
 385                 },
 386                 (void *)CMITC_UARTCLK,
 387         },
 388         {
 389                 .ident = "FRI2",
 390                 {
 391                         DMI_MATCH(DMI_BIOS_VERSION, "FRI2"),
 392                 },
 393                 (void *)FRI2_64_UARTCLK,
 394         },
 395         {
 396                 .ident = "Fish River Island II",
 397                 {
 398                         DMI_MATCH(DMI_PRODUCT_NAME, "Fish River Island II"),
 399                 },
 400                 (void *)FRI2_48_UARTCLK,
 401         },
 402         {
 403                 .ident = "COMe-mTT",
 404                 {
 405                         DMI_MATCH(DMI_BOARD_NAME, "COMe-mTT"),
 406                 },
 407                 (void *)NTC1_UARTCLK,
 408         },
 409         {
 410                 .ident = "nanoETXexpress-TT",
 411                 {
 412                         DMI_MATCH(DMI_BOARD_NAME, "nanoETXexpress-TT"),
 413                 },
 414                 (void *)NTC1_UARTCLK,
 415         },
 416         {
 417                 .ident = "MinnowBoard",
 418                 {
 419                         DMI_MATCH(DMI_BOARD_NAME, "MinnowBoard"),
 420                 },
 421                 (void *)MINNOW_UARTCLK,
 422         },
 423         { }
 424 };
 425
 426 /* Return UART clock, checking for board specific clocks. */
 427 static unsigned int pch_uart_get_uartclk(void)
 428 {
 429         const struct dmi_system_id *d;
 430
 431         if (user_uartclk)
 432                 return user_uartclk;
 433
 434         d = dmi_first_match(pch_uart_dmi_table);
 435         if (d)
 436                 return (unsigned long)d->driver_data;
 437
 438         return DEFAULT_UARTCLK;
 439 }
 440
 441 static void pch_uart_hal_enable_interrupt(struct eg20t_port *priv,
 442                                           unsigned int flag)
 443 {
 444         u8 ier = ioread8(priv->membase + UART_IER);
 445         ier |= flag & PCH_UART_IER_MASK;
 446         iowrite8(ier, priv->membase + UART_IER);
 447 }
 448
 449 static void pch_uart_hal_disable_interrupt(struct eg20t_port *priv,
 450                                            unsigned int flag)
 451 {
 452         u8 ier = ioread8(priv->membase + UART_IER);
 453         ier &= ~(flag & PCH_UART_IER_MASK);
 454         iowrite8(ier, priv->membase + UART_IER);
 455 }
 456
 457 static int pch_uart_hal_set_line(struct eg20t_port *priv, unsigned int baud,
 458                                  unsigned int parity, unsigned int bits,
 459                                  unsigned int stb)
 460 {
 461         unsigned int dll, dlm, lcr;
 462         int div;
 463
 464         div = DIV_ROUND_CLOSEST(priv->uartclk / 16, baud);
 465         if (div < 0 || USHRT_MAX <= div) {
 466                 dev_err(priv->port.dev, "Invalid Baud(div=0x%x)\n", div);
 467                 return -EINVAL;
 468         }
 469
 470         dll = (unsigned int)div & 0x00FFU;
 471         dlm = ((unsigned int)div >> 8) & 0x00FFU;
 472
 473         if (parity & ~(PCH_UART_LCR_PEN | PCH_UART_LCR_EPS | PCH_UART_LCR_SP)) {
 474                 dev_err(priv->port.dev, "Invalid parity(0x%x)\n", parity);
 475                 return -EINVAL;
 476         }
 477
 478         if (bits & ~PCH_UART_LCR_WLS) {
 479                 dev_err(priv->port.dev, "Invalid bits(0x%x)\n", bits);
 480                 return -EINVAL;
 481         }
 482
 483         if (stb & ~PCH_UART_LCR_STB) {
 484                 dev_err(priv->port.dev, "Invalid STB(0x%x)\n", stb);
 485                 return -EINVAL;
 486         }
 487
 488         lcr = parity;
 489         lcr |= bits;
 490         lcr |= stb;
 491
 492         dev_dbg(priv->port.dev, "%s:baud = %u, div = %04x, lcr = %02x (%lu)\n",
 493                  __func__, baud, div, lcr, jiffies);
 494         iowrite8(PCH_UART_LCR_DLAB, priv->membase + UART_LCR);
 495         iowrite8(dll, priv->membase + PCH_UART_DLL);
 496         iowrite8(dlm, priv->membase + PCH_UART_DLM);
 497         iowrite8(lcr, priv->membase + UART_LCR);
 498
 499         return 0;
 500 }
 501
 502 static int pch_uart_hal_fifo_reset(struct eg20t_port *priv,
 503                                     unsigned int flag)
 504 {
 505         if (flag & ~(PCH_UART_FCR_TFR | PCH_UART_FCR_RFR)) {
 506                 dev_err(priv->port.dev, "%s:Invalid flag(0x%x)\n",
 507                         __func__, flag);
 508                 return -EINVAL;
 509         }
 510
 511         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr, priv->membase + UART_FCR);
 512         iowrite8(PCH_UART_FCR_FIFOE | priv->fcr | flag,
 513                  priv->membase + UART_FCR);
 514         iowrite8(priv->fcr, priv->membase + UART_FCR);
 515
 516         return 0;
 517 }
 518
 519 static int pch_uart_hal_set_fifo(struct eg20t_port *priv,
 520                                  unsigned int dmamode,
 521                                  unsigned int fifo_size, unsigned int trigger)
 522 {
 523         u8 fcr;
 524
 525         if (dmamode & ~PCH_UART_FCR_DMS) {
 526                 dev_err(priv->port.dev, "%s:Invalid DMA Mode(0x%x)\n",
 527                         __func__, dmamode);
 528                 return -EINVAL;
 529         }
 530
 531         if (fifo_size & ~(PCH_UART_FCR_FIFOE | PCH_UART_FCR_FIFO256)) {
 532                 dev_err(priv->port.dev, "%s:Invalid FIFO SIZE(0x%x)\n",
 533                         __func__, fifo_size);
 534                 return -EINVAL;
 535         }
 536
 537         if (trigger & ~PCH_UART_FCR_RFTL) {
 538                 dev_err(priv->port.dev, "%s:Invalid TRIGGER(0x%x)\n",
 539                         __func__, trigger);
 540                 return -EINVAL;
 541         }
 542
 543         switch (priv->fifo_size) {
 544         case 256:
 545                 priv->trigger_level =
 546                     trigger_level_256[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 547                 break;
 548         case 64:
 549                 priv->trigger_level =
 550                     trigger_level_64[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 551                 break;
 552         case 16:
 553                 priv->trigger_level =
 554                     trigger_level_16[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 555                 break;
 556         default:
 557                 priv->trigger_level =
 558                     trigger_level_1[trigger >> PCH_UART_FCR_RFTL_SHIFT];
 559                 break;
 560         }
 561         fcr =
 562             dmamode | fifo_size | trigger | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR;
 563         iowrite8(PCH_UART_FCR_FIFOE, priv->membase + UART_FCR);
 564         iowrite8(PCH_UART_FCR_FIFOE | PCH_UART_FCR_RFR | PCH_UART_FCR_TFR,
 565                  priv->membase + UART_FCR);
 566         iowrite8(fcr, priv->membase + UART_FCR);
 567         priv->fcr = fcr;
 568
 569         return 0;
 570 }
 571
 572 static u8 pch_uart_hal_get_modem(struct eg20t_port *priv)
 573 {
 574         unsigned int msr = ioread8(priv->membase + UART_MSR);
 575         priv->dmsr = msr & PCH_UART_MSR_DELTA;
 576         return (u8)msr;
 577 }
 578
 579 static void pch_uart_hal_write(struct eg20t_port *priv,
 580                               const unsigned char *buf, int tx_size)
 581 {
 582         int i;
 583         unsigned int thr;
 584
 585         for (i = 0; i < tx_size;) {
 586                 thr = buf[i++];
 587                 iowrite8(thr, priv->membase + PCH_UART_THR);
 588         }
 589 }
 590
 591 static int pch_uart_hal_read(struct eg20t_port *priv, unsigned char *buf,
 592                              int rx_size)
 593 {
 594         int i;
 595         u8 rbr, lsr;
 596         struct uart_port *port = &priv->port;
 597
 598         lsr = ioread8(priv->membase + UART_LSR);
 599         for (i = 0, lsr = ioread8(priv->membase + UART_LSR);
 600              i < rx_size && lsr & (UART_LSR_DR | UART_LSR_BI);
 601              lsr = ioread8(priv->membase + UART_LSR)) {
 602                 rbr = ioread8(priv->membase + PCH_UART_RBR);
 603
 604                 if (lsr & UART_LSR_BI) {
 605                         port->icount.brk++;
 606                         if (uart_handle_break(port))
 607                                 continue;
 608                 }
 609 #ifdef SUPPORT_SYSRQ
 610                 if (port->sysrq) {
 611                         if (uart_handle_sysrq_char(port, rbr))
 612                                 continue;
 613                 }
 614 #endif
 615
 616                 buf[i++] = rbr;
 617         }
 618         return i;
 619 }
 620
 621 static unsigned char pch_uart_hal_get_iid(struct eg20t_port *priv)
 622 {
 623         return ioread8(priv->membase + UART_IIR) &\
 624                       (PCH_UART_IIR_IID | PCH_UART_IIR_TOI | PCH_UART_IIR_IP);
 625 }
 626
 627 static u8 pch_uart_hal_get_line_status(struct eg20t_port *priv)
 628 {
 629         return ioread8(priv->membase + UART_LSR);
 630 }
 631
 632 static void pch_uart_hal_set_break(struct eg20t_port *priv, int on)
 633 {
 634         unsigned int lcr;
 635
 636         lcr = ioread8(priv->membase + UART_LCR);
 637         if (on)
 638                 lcr |= PCH_UART_LCR_SB;
 639         else
 640                 lcr &= ~PCH_UART_LCR_SB;
 641
 642         iowrite8(lcr, priv->membase + UART_LCR);
 643 }
 644
 645 static int push_rx(struct eg20t_port *priv, const unsigned char *buf,
 646                    int size)
 647 {
 648         struct uart_port *port = &priv->port;
 649         struct tty_port *tport = &port->state->port;
 650
 651         tty_insert_flip_string(tport, buf, size);
 652         tty_flip_buffer_push(tport);
 653
 654         return 0;
 655 }
 656
 657 static int pop_tx_x(struct eg20t_port *priv, unsigned char *buf)
 658 {
 659         int ret = 0;
 660         struct uart_port *port = &priv->port;
 661
 662         if (port->x_char) {
 663                 dev_dbg(priv->port.dev, "%s:X character send %02x (%lu)\n",
 664                         __func__, port->x_char, jiffies);
 665                 buf[0] = port->x_char;
 666                 port->x_char = 0;
 667                 ret = 1;
 668         }
 669
 670         return ret;
 671 }
 672
 673 static int dma_push_rx(struct eg20t_port *priv, int size)
 674 {
 675         int room;
 676         struct uart_port *port = &priv->port;
 677         struct tty_port *tport = &port->state->port;
 678
 679         room = tty_buffer_request_room(tport, size);
 680
 681         if (room < size)
 682                 dev_warn(port->dev, "Rx overrun: dropping %u bytes\n",
 683                          size - room);
 684         if (!room)
 685                 return 0;
 686
 687         tty_insert_flip_string(tport, sg_virt(&priv->sg_rx), size);
 688
 689         port->icount.rx += room;
 690
 691         return room;
 692 }
 693
 694 static void pch_free_dma(struct uart_port *port)
 695 {
 696         struct eg20t_port *priv;
 697         priv = container_of(port, struct eg20t_port, port);
 698
 699         if (priv->chan_tx) {
 700                 dma_release_channel(priv->chan_tx);
 701                 priv->chan_tx = NULL;
 702         }
 703         if (priv->chan_rx) {
 704                 dma_release_channel(priv->chan_rx);
 705                 priv->chan_rx = NULL;
 706         }
 707
 708         if (priv->rx_buf_dma) {
 709                 dma_free_coherent(port->dev, port->fifosize, priv->rx_buf_virt,
 710                                   priv->rx_buf_dma);
 711                 priv->rx_buf_virt = NULL;
 712                 priv->rx_buf_dma = 0;
 713         }
 714
 715         return;
 716 }
 717
 718 static bool filter(struct dma_chan *chan, void *slave)
 719 {
 720         struct pch_dma_slave *param = slave;
 721
 722         if ((chan->chan_id == param->chan_id) && (param->dma_dev ==
 723                                                   chan->device->dev)) {
 724                 chan->private = param;
 725                 return true;
 726         } else {
 727                 return false;
 728         }
 729 }
 730
 731 static void pch_request_dma(struct uart_port *port)
 732 {
 733         dma_cap_mask_t mask;
 734         struct dma_chan *chan;
 735         struct pci_dev *dma_dev;
 736         struct pch_dma_slave *param;
 737         struct eg20t_port *priv =
 738                                 container_of(port, struct eg20t_port, port);
 739         dma_cap_zero(mask);
 740         dma_cap_set(DMA_SLAVE, mask);
 741
 742         /* Get DMA's dev information */
 743         dma_dev = pci_get_slot(priv->pdev->bus,
 744                         PCI_DEVFN(PCI_SLOT(priv->pdev->devfn), 0));
 745
 746         /* Set Tx DMA */
 747         param = &priv->param_tx;
 748         param->dma_dev = &dma_dev->dev;
 749         param->chan_id = priv->port.line * 2; /* Tx = 0, 2, 4, ... */
 750
 751         param->tx_reg = port->mapbase + UART_TX;
 752         chan = dma_request_channel(mask, filter, param);
 753         if (!chan) {
 754                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Tx)\n",
 755                         __func__);
 756                 pci_dev_put(dma_dev);
 757                 return;
 758         }
 759         priv->chan_tx = chan;
 760
 761         /* Set Rx DMA */
 762         param = &priv->param_rx;
 763         param->dma_dev = &dma_dev->dev;
 764         param->chan_id = priv->port.line * 2 + 1; /* Rx = Tx + 1 */
 765
 766         param->rx_reg = port->mapbase + UART_RX;
 767         chan = dma_request_channel(mask, filter, param);
 768         if (!chan) {
 769                 dev_err(priv->port.dev, "%s:dma_request_channel FAILS(Rx)\n",
 770                         __func__);
 771                 dma_release_channel(priv->chan_tx);
 772                 priv->chan_tx = NULL;
 773                 pci_dev_put(dma_dev);
 774                 return;
 775         }
 776
 777         /* Get Consistent memory for DMA */
 778         priv->rx_buf_virt = dma_alloc_coherent(port->dev, port->fifosize,
 779                                     &priv->rx_buf_dma, GFP_KERNEL);
 780         priv->chan_rx = chan;
 781
 782         pci_dev_put(dma_dev);
 783 }
 784
 785 static void pch_dma_rx_complete(void *arg)
 786 {
 787         struct eg20t_port *priv = arg;
 788         struct uart_port *port = &priv->port;
 789         int count;
 790
 791         dma_sync_sg_for_cpu(port->dev, &priv->sg_rx, 1, DMA_FROM_DEVICE);
 792         count = dma_push_rx(priv, priv->trigger_level);
 793         if (count)
 794                 tty_flip_buffer_push(&port->state->port);
 795         async_tx_ack(priv->desc_rx);
 796         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
 797                                             PCH_UART_HAL_RX_ERR_INT);
 798 }
 799
 800 static void pch_dma_tx_complete(void *arg)
 801 {
 802         struct eg20t_port *priv = arg;
 803         struct uart_port *port = &priv->port;
 804         struct circ_buf *xmit = &port->state->xmit;
 805         struct scatterlist *sg = priv->sg_tx_p;
 806         int i;
 807
 808         for (i = 0; i < priv->nent; i++, sg++) {
 809                 xmit->tail += sg_dma_len(sg);
 810                 port->icount.tx += sg_dma_len(sg);
 811         }
 812         xmit->tail &= UART_XMIT_SIZE - 1;
 813         async_tx_ack(priv->desc_tx);
 814         dma_unmap_sg(port->dev, sg, priv->orig_nent, DMA_TO_DEVICE);
 815         priv->tx_dma_use = 0;
 816         priv->nent = 0;
 817         priv->orig_nent = 0;
 818         kfree(priv->sg_tx_p);
 819         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
 820 }
 821
 822 static int pop_tx(struct eg20t_port *priv, int size)
 823 {
 824         int count = 0;
 825         struct uart_port *port = &priv->port;
 826         struct circ_buf *xmit = &port->state->xmit;
 827
 828         if (uart_tx_stopped(port) || uart_circ_empty(xmit) || count >= size)
 829                 goto pop_tx_end;
 830
 831         do {
 832                 int cnt_to_end =
 833                     CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 834                 int sz = min(size - count, cnt_to_end);
 835                 pch_uart_hal_write(priv, &xmit->buf[xmit->tail], sz);
 836                 xmit->tail = (xmit->tail + sz) & (UART_XMIT_SIZE - 1);
 837                 count += sz;
 838         } while (!uart_circ_empty(xmit) && count < size);
 839
 840 pop_tx_end:
 841         dev_dbg(priv->port.dev, "%d characters. Remained %d characters.(%lu)\n",
 842                  count, size - count, jiffies);
 843
 844         return count;
 845 }
 846
 847 static int handle_rx_to(struct eg20t_port *priv)
 848 {
 849         struct pch_uart_buffer *buf;
 850         int rx_size;
 851         int ret;
 852         if (!priv->start_rx) {
 853                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
 854                                                      PCH_UART_HAL_RX_ERR_INT);
 855                 return 0;
 856         }
 857         buf = &priv->rxbuf;
 858         do {
 859                 rx_size = pch_uart_hal_read(priv, buf->buf, buf->size);
 860                 ret = push_rx(priv, buf->buf, rx_size);
 861                 if (ret)
 862                         return 0;
 863         } while (rx_size == buf->size);
 864
 865         return PCH_UART_HANDLED_RX_INT;
 866 }
 867
 868 static int handle_rx(struct eg20t_port *priv)
 869 {
 870         return handle_rx_to(priv);
 871 }
 872
 873 static int dma_handle_rx(struct eg20t_port *priv)
 874 {
 875         struct uart_port *port = &priv->port;
 876         struct dma_async_tx_descriptor *desc;
 877         struct scatterlist *sg;
 878
 879         priv = container_of(port, struct eg20t_port, port);
 880         sg = &priv->sg_rx;
 881
 882         sg_init_table(&priv->sg_rx, 1); /* Initialize SG table */
 883
 884         sg_dma_len(sg) = priv->trigger_level;
 885
 886         sg_set_page(&priv->sg_rx, virt_to_page(priv->rx_buf_virt),
 887                      sg_dma_len(sg), (unsigned long)priv->rx_buf_virt &
 888                      ~PAGE_MASK);
 889
 890         sg_dma_address(sg) = priv->rx_buf_dma;
 891
 892         desc = dmaengine_prep_slave_sg(priv->chan_rx,
 893                         sg, 1, DMA_DEV_TO_MEM,
 894                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 895
 896         if (!desc)
 897                 return 0;
 898
 899         priv->desc_rx = desc;
 900         desc->callback = pch_dma_rx_complete;
 901         desc->callback_param = priv;
 902         desc->tx_submit(desc);
 903         dma_async_issue_pending(priv->chan_rx);
 904
 905         return PCH_UART_HANDLED_RX_INT;
 906 }
 907
 908 static unsigned int handle_tx(struct eg20t_port *priv)
 909 {
 910         struct uart_port *port = &priv->port;
 911         struct circ_buf *xmit = &port->state->xmit;
 912         int fifo_size;
 913         int tx_size;
 914         int size;
 915         int tx_empty;
 916
 917         if (!priv->start_tx) {
 918                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 919                         __func__, jiffies);
 920                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 921                 priv->tx_empty = 1;
 922                 return 0;
 923         }
 924
 925         fifo_size = max(priv->fifo_size, 1);
 926         tx_empty = 1;
 927         if (pop_tx_x(priv, xmit->buf)) {
 928                 pch_uart_hal_write(priv, xmit->buf, 1);
 929                 port->icount.tx++;
 930                 tx_empty = 0;
 931                 fifo_size--;
 932         }
 933         size = min(xmit->head - xmit->tail, fifo_size);
 934         if (size < 0)
 935                 size = fifo_size;
 936
 937         tx_size = pop_tx(priv, size);
 938         if (tx_size > 0) {
 939                 port->icount.tx += tx_size;
 940                 tx_empty = 0;
 941         }
 942
 943         priv->tx_empty = tx_empty;
 944
 945         if (tx_empty) {
 946                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 947                 uart_write_wakeup(port);
 948         }
 949
 950         return PCH_UART_HANDLED_TX_INT;
 951 }
 952
 953 static unsigned int dma_handle_tx(struct eg20t_port *priv)
 954 {
 955         struct uart_port *port = &priv->port;
 956         struct circ_buf *xmit = &port->state->xmit;
 957         struct scatterlist *sg;
 958         int nent;
 959         int fifo_size;
 960         int tx_empty;
 961         struct dma_async_tx_descriptor *desc;
 962         int num;
 963         int i;
 964         int bytes;
 965         int size;
 966         int rem;
 967
 968         if (!priv->start_tx) {
 969                 dev_info(priv->port.dev, "%s:Tx isn't started. (%lu)\n",
 970                         __func__, jiffies);
 971                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 972                 priv->tx_empty = 1;
 973                 return 0;
 974         }
 975
 976         if (priv->tx_dma_use) {
 977                 dev_dbg(priv->port.dev, "%s:Tx is not completed. (%lu)\n",
 978                         __func__, jiffies);
 979                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 980                 priv->tx_empty = 1;
 981                 return 0;
 982         }
 983
 984         fifo_size = max(priv->fifo_size, 1);
 985         tx_empty = 1;
 986         if (pop_tx_x(priv, xmit->buf)) {
 987                 pch_uart_hal_write(priv, xmit->buf, 1);
 988                 port->icount.tx++;
 989                 tx_empty = 0;
 990                 fifo_size--;
 991         }
 992
 993         bytes = min((int)CIRC_CNT(xmit->head, xmit->tail,
 994                              UART_XMIT_SIZE), CIRC_CNT_TO_END(xmit->head,
 995                              xmit->tail, UART_XMIT_SIZE));
 996         if (!bytes) {
 997                 dev_dbg(priv->port.dev, "%s 0 bytes return\n", __func__);
 998                 pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_TX_INT);
 999                 uart_write_wakeup(port);
1000                 return 0;
1001         }
1002
1003         if (bytes > fifo_size) {
1004                 num = bytes / fifo_size + 1;
1005                 size = fifo_size;
1006                 rem = bytes % fifo_size;
1007         } else {
1008                 num = 1;
1009                 size = bytes;
1010                 rem = bytes;
1011         }
1012
1013         dev_dbg(priv->port.dev, "%s num=%d size=%d rem=%d\n",
1014                 __func__, num, size, rem);
1015
1016         priv->tx_dma_use = 1;
1017
1018         priv->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC);
1019         if (!priv->sg_tx_p) {
1020                 dev_err(priv->port.dev, "%s:kzalloc Failed\n", __func__);
1021                 return 0;
1022         }
1023
1024         sg_init_table(priv->sg_tx_p, num); /* Initialize SG table */
1025         sg = priv->sg_tx_p;
1026
1027         for (i = 0; i < num; i++, sg++) {
1028                 if (i == (num - 1))
1029                         sg_set_page(sg, virt_to_page(xmit->buf),
1030                                     rem, fifo_size * i);
1031                 else
1032                         sg_set_page(sg, virt_to_page(xmit->buf),
1033                                     size, fifo_size * i);
1034         }
1035
1036         sg = priv->sg_tx_p;
1037         nent = dma_map_sg(port->dev, sg, num, DMA_TO_DEVICE);
1038         if (!nent) {
1039                 dev_err(priv->port.dev, "%s:dma_map_sg Failed\n", __func__);
1040                 return 0;
1041         }
1042         priv->orig_nent = num;
1043         priv->nent = nent;
1044
1045         for (i = 0; i < nent; i++, sg++) {
1046                 sg->offset = (xmit->tail & (UART_XMIT_SIZE - 1)) +
1047                               fifo_size * i;
1048                 sg_dma_address(sg) = (sg_dma_address(sg) &
1049                                     ~(UART_XMIT_SIZE - 1)) + sg->offset;
1050                 if (i == (nent - 1))
1051                         sg_dma_len(sg) = rem;
1052                 else
1053                         sg_dma_len(sg) = size;
1054         }
1055
1056         desc = dmaengine_prep_slave_sg(priv->chan_tx,
1057                                         priv->sg_tx_p, nent, DMA_MEM_TO_DEV,
1058                                         DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1059         if (!desc) {
1060                 dev_err(priv->port.dev, "%s:dmaengine_prep_slave_sg Failed\n",
1061                         __func__);
1062                 return 0;
1063         }
1064         dma_sync_sg_for_device(port->dev, priv->sg_tx_p, nent, DMA_TO_DEVICE);
1065         priv->desc_tx = desc;
1066         desc->callback = pch_dma_tx_complete;
1067         desc->callback_param = priv;
1068
1069         desc->tx_submit(desc);
1070
1071         dma_async_issue_pending(priv->chan_tx);
1072
1073         return PCH_UART_HANDLED_TX_INT;
1074 }
1075
1076 static void pch_uart_err_ir(struct eg20t_port *priv, unsigned int lsr)
1077 {
1078         struct uart_port *port = &priv->port;
1079         struct tty_struct *tty = tty_port_tty_get(&port->state->port);
1080         char   *error_msg[5] = {};
1081         int    i = 0;
1082
1083         if (lsr & PCH_UART_LSR_ERR)
1084                 error_msg[i++] = "Error data in FIFO\n";
1085
1086         if (lsr & UART_LSR_FE) {
1087                 port->icount.frame++;
1088                 error_msg[i++] = "  Framing Error\n";
1089         }
1090
1091         if (lsr & UART_LSR_PE) {
1092                 port->icount.parity++;
1093                 error_msg[i++] = "  Parity Error\n";
1094         }
1095
1096         if (lsr & UART_LSR_OE) {
1097                 port->icount.overrun++;
1098                 error_msg[i++] = "  Overrun Error\n";
1099         }
1100
1101         if (tty == NULL) {
1102                 for (i = 0; error_msg[i] != NULL; i++)
1103                         dev_err(&priv->pdev->dev, error_msg[i]);
1104         } else {
1105                 tty_kref_put(tty);
1106         }
1107 }
1108
1109 static irqreturn_t pch_uart_interrupt(int irq, void *dev_id)
1110 {
1111         struct eg20t_port *priv = dev_id;
1112         unsigned int handled;
1113         u8 lsr;
1114         int ret = 0;
1115         unsigned char iid;
1116         unsigned long flags;
1117         int next = 1;
1118         u8 msr;
1119
1120         spin_lock_irqsave(&priv->lock, flags);
1121         handled = 0;
1122         while (next) {
1123                 iid = pch_uart_hal_get_iid(priv);
1124                 if (iid & PCH_UART_IIR_IP) /* No Interrupt */
1125                         break;
1126                 switch (iid) {
1127                 case PCH_UART_IID_RLS:  /* Receiver Line Status */
1128                         lsr = pch_uart_hal_get_line_status(priv);
1129                         if (lsr & (PCH_UART_LSR_ERR | UART_LSR_FE |
1130                                                 UART_LSR_PE | UART_LSR_OE)) {
1131                                 pch_uart_err_ir(priv, lsr);
1132                                 ret = PCH_UART_HANDLED_RX_ERR_INT;
1133                         } else {
1134                                 ret = PCH_UART_HANDLED_LS_INT;
1135                         }
1136                         break;
1137                 case PCH_UART_IID_RDR:  /* Received Data Ready */
1138                         if (priv->use_dma) {
1139                                 pch_uart_hal_disable_interrupt(priv,
1140                                                 PCH_UART_HAL_RX_INT |
1141                                                 PCH_UART_HAL_RX_ERR_INT);
1142                                 ret = dma_handle_rx(priv);
1143                                 if (!ret)
1144                                         pch_uart_hal_enable_interrupt(priv,
1145                                                 PCH_UART_HAL_RX_INT |
1146                                                 PCH_UART_HAL_RX_ERR_INT);
1147                         } else {
1148                                 ret = handle_rx(priv);
1149                         }
1150                         break;
1151                 case PCH_UART_IID_RDR_TO:       /* Received Data Ready
1152                                                    (FIFO Timeout) */
1153                         ret = handle_rx_to(priv);
1154                         break;
1155                 case PCH_UART_IID_THRE: /* Transmitter Holding Register
1156                                                    Empty */
1157                         if (priv->use_dma)
1158                                 ret = dma_handle_tx(priv);
1159                         else
1160                                 ret = handle_tx(priv);
1161                         break;
1162                 case PCH_UART_IID_MS:   /* Modem Status */
1163                         msr = pch_uart_hal_get_modem(priv);
1164                         next = 0; /* MS ir prioirty is the lowest. So, MS ir
1165                                      means final interrupt */
1166                         if ((msr & UART_MSR_ANY_DELTA) == 0)
1167                                 break;
1168                         ret |= PCH_UART_HANDLED_MS_INT;
1169                         break;
1170                 default:        /* Never junp to this label */
1171                         dev_err(priv->port.dev, "%s:iid=%02x (%lu)\n", __func__,
1172                                 iid, jiffies);
1173                         ret = -1;
1174                         next = 0;
1175                         break;
1176                 }
1177                 handled |= (unsigned int)ret;
1178         }
1179
1180         spin_unlock_irqrestore(&priv->lock, flags);
1181         return IRQ_RETVAL(handled);
1182 }
1183
1184 /* This function tests whether the transmitter fifo and shifter for the port
1185                                                 described by 'port' is empty. */
1186 static unsigned int pch_uart_tx_empty(struct uart_port *port)
1187 {
1188         struct eg20t_port *priv;
1189
1190         priv = container_of(port, struct eg20t_port, port);
1191         if (priv->tx_empty)
1192                 return TIOCSER_TEMT;
1193         else
1194                 return 0;
1195 }
1196
1197 /* Returns the current state of modem control inputs. */
1198 static unsigned int pch_uart_get_mctrl(struct uart_port *port)
1199 {
1200         struct eg20t_port *priv;
1201         u8 modem;
1202         unsigned int ret = 0;
1203
1204         priv = container_of(port, struct eg20t_port, port);
1205         modem = pch_uart_hal_get_modem(priv);
1206
1207         if (modem & UART_MSR_DCD)
1208                 ret |= TIOCM_CAR;
1209
1210         if (modem & UART_MSR_RI)
1211                 ret |= TIOCM_RNG;
1212
1213         if (modem & UART_MSR_DSR)
1214                 ret |= TIOCM_DSR;
1215
1216         if (modem & UART_MSR_CTS)
1217                 ret |= TIOCM_CTS;
1218
1219         return ret;
1220 }
1221
1222 static void pch_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1223 {
1224         u32 mcr = 0;
1225         struct eg20t_port *priv = container_of(port, struct eg20t_port, port);
1226
1227         if (mctrl & TIOCM_DTR)
1228                 mcr |= UART_MCR_DTR;
1229         if (mctrl & TIOCM_RTS)
1230                 mcr |= UART_MCR_RTS;
1231         if (mctrl & TIOCM_LOOP)
1232                 mcr |= UART_MCR_LOOP;
1233
1234         if (priv->mcr & UART_MCR_AFE)
1235                 mcr |= UART_MCR_AFE;
1236
1237         if (mctrl)
1238                 iowrite8(mcr, priv->membase + UART_MCR);
1239 }
1240
1241 static void pch_uart_stop_tx(struct uart_port *port)
1242 {
1243         struct eg20t_port *priv;
1244         priv = container_of(port, struct eg20t_port, port);
1245         priv->start_tx = 0;
1246         priv->tx_dma_use = 0;
1247 }
1248
1249 static void pch_uart_start_tx(struct uart_port *port)
1250 {
1251         struct eg20t_port *priv;
1252
1253         priv = container_of(port, struct eg20t_port, port);
1254
1255         if (priv->use_dma) {
1256                 if (priv->tx_dma_use) {
1257                         dev_dbg(priv->port.dev, "%s : Tx DMA is NOT empty.\n",
1258                                 __func__);
1259                         return;
1260                 }
1261         }
1262
1263         priv->start_tx = 1;
1264         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_TX_INT);
1265 }
1266
1267 static void pch_uart_stop_rx(struct uart_port *port)
1268 {
1269         struct eg20t_port *priv;
1270         priv = container_of(port, struct eg20t_port, port);
1271         priv->start_rx = 0;
1272         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_RX_INT |
1273                                              PCH_UART_HAL_RX_ERR_INT);
1274 }
1275
1276 /* Enable the modem status interrupts. */
1277 static void pch_uart_enable_ms(struct uart_port *port)
1278 {
1279         struct eg20t_port *priv;
1280         priv = container_of(port, struct eg20t_port, port);
1281         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_MS_INT);
1282 }
1283
1284 /* Control the transmission of a break signal. */
1285 static void pch_uart_break_ctl(struct uart_port *port, int ctl)
1286 {
1287         struct eg20t_port *priv;
1288         unsigned long flags;
1289
1290         priv = container_of(port, struct eg20t_port, port);
1291         spin_lock_irqsave(&priv->lock, flags);
1292         pch_uart_hal_set_break(priv, ctl);
1293         spin_unlock_irqrestore(&priv->lock, flags);
1294 }
1295
1296 /* Grab any interrupt resources and initialise any low level driver state. */
1297 static int pch_uart_startup(struct uart_port *port)
1298 {
1299         struct eg20t_port *priv;
1300         int ret;
1301         int fifo_size;
1302         int trigger_level;
1303
1304         priv = container_of(port, struct eg20t_port, port);
1305         priv->tx_empty = 1;
1306
1307         if (port->uartclk)
1308                 priv->uartclk = port->uartclk;
1309         else
1310                 port->uartclk = priv->uartclk;
1311
1312         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1313         ret = pch_uart_hal_set_line(priv, default_baud,
1314                               PCH_UART_HAL_PARITY_NONE, PCH_UART_HAL_8BIT,
1315                               PCH_UART_HAL_STB1);
1316         if (ret)
1317                 return ret;
1318
1319         switch (priv->fifo_size) {
1320         case 256:
1321                 fifo_size = PCH_UART_HAL_FIFO256;
1322                 break;
1323         case 64:
1324                 fifo_size = PCH_UART_HAL_FIFO64;
1325                 break;
1326         case 16:
1327                 fifo_size = PCH_UART_HAL_FIFO16;
1328                 break;
1329         case 1:
1330         default:
1331                 fifo_size = PCH_UART_HAL_FIFO_DIS;
1332                 break;
1333         }
1334
1335         switch (priv->trigger) {
1336         case PCH_UART_HAL_TRIGGER1:
1337                 trigger_level = 1;
1338                 break;
1339         case PCH_UART_HAL_TRIGGER_L:
1340                 trigger_level = priv->fifo_size / 4;
1341                 break;
1342         case PCH_UART_HAL_TRIGGER_M:
1343                 trigger_level = priv->fifo_size / 2;
1344                 break;
1345         case PCH_UART_HAL_TRIGGER_H:
1346         default:
1347                 trigger_level = priv->fifo_size - (priv->fifo_size / 8);
1348                 break;
1349         }
1350
1351         priv->trigger_level = trigger_level;
1352         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1353                                     fifo_size, priv->trigger);
1354         if (ret < 0)
1355                 return ret;
1356
1357         ret = request_irq(priv->port.irq, pch_uart_interrupt, IRQF_SHARED,
1358                         priv->irq_name, priv);
1359         if (ret < 0)
1360                 return ret;
1361
1362         if (priv->use_dma)
1363                 pch_request_dma(port);
1364
1365         priv->start_rx = 1;
1366         pch_uart_hal_enable_interrupt(priv, PCH_UART_HAL_RX_INT |
1367                                             PCH_UART_HAL_RX_ERR_INT);
1368         uart_update_timeout(port, CS8, default_baud);
1369
1370         return 0;
1371 }
1372
1373 static void pch_uart_shutdown(struct uart_port *port)
1374 {
1375         struct eg20t_port *priv;
1376         int ret;
1377
1378         priv = container_of(port, struct eg20t_port, port);
1379         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1380         pch_uart_hal_fifo_reset(priv, PCH_UART_HAL_CLR_ALL_FIFO);
1381         ret = pch_uart_hal_set_fifo(priv, PCH_UART_HAL_DMA_MODE0,
1382                               PCH_UART_HAL_FIFO_DIS, PCH_UART_HAL_TRIGGER1);
1383         if (ret)
1384                 dev_err(priv->port.dev,
1385                         "pch_uart_hal_set_fifo Failed(ret=%d)\n", ret);
1386
1387         pch_free_dma(port);
1388
1389         free_irq(priv->port.irq, priv);
1390 }
1391
1392 /* Change the port parameters, including word length, parity, stop
1393  *bits.  Update read_status_mask and ignore_status_mask to indicate
1394  *the types of events we are interested in receiving.  */
1395 static void pch_uart_set_termios(struct uart_port *port,
1396                                  struct ktermios *termios, struct ktermios *old)
1397 {
1398         int rtn;
1399         unsigned int baud, parity, bits, stb;
1400         struct eg20t_port *priv;
1401         unsigned long flags;
1402
1403         priv = container_of(port, struct eg20t_port, port);
1404         switch (termios->c_cflag & CSIZE) {
1405         case CS5:
1406                 bits = PCH_UART_HAL_5BIT;
1407                 break;
1408         case CS6:
1409                 bits = PCH_UART_HAL_6BIT;
1410                 break;
1411         case CS7:
1412                 bits = PCH_UART_HAL_7BIT;
1413                 break;
1414         default:                /* CS8 */
1415                 bits = PCH_UART_HAL_8BIT;
1416                 break;
1417         }
1418         if (termios->c_cflag & CSTOPB)
1419                 stb = PCH_UART_HAL_STB2;
1420         else
1421                 stb = PCH_UART_HAL_STB1;
1422
1423         if (termios->c_cflag & PARENB) {
1424                 if (termios->c_cflag & PARODD)
1425                         parity = PCH_UART_HAL_PARITY_ODD;
1426                 else
1427                         parity = PCH_UART_HAL_PARITY_EVEN;
1428
1429         } else
1430                 parity = PCH_UART_HAL_PARITY_NONE;
1431
1432         /* Only UART0 has auto hardware flow function */
1433         if ((termios->c_cflag & CRTSCTS) && (priv->fifo_size == 256))
1434                 priv->mcr |= UART_MCR_AFE;
1435         else
1436                 priv->mcr &= ~UART_MCR_AFE;
1437
1438         termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
1439
1440         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16);
1441
1442         spin_lock_irqsave(&priv->lock, flags);
1443         spin_lock(&port->lock);
1444
1445         uart_update_timeout(port, termios->c_cflag, baud);
1446         rtn = pch_uart_hal_set_line(priv, baud, parity, bits, stb);
1447         if (rtn)
1448                 goto out;
1449
1450         pch_uart_set_mctrl(&priv->port, priv->port.mctrl);
1451         /* Don't rewrite B0 */
1452         if (tty_termios_baud_rate(termios))
1453                 tty_termios_encode_baud_rate(termios, baud, baud);
1454
1455 out:
1456         spin_unlock(&port->lock);
1457         spin_unlock_irqrestore(&priv->lock, flags);
1458 }
1459
1460 static const char *pch_uart_type(struct uart_port *port)
1461 {
1462         return KBUILD_MODNAME;
1463 }
1464
1465 static void pch_uart_release_port(struct uart_port *port)
1466 {
1467         struct eg20t_port *priv;
1468
1469         priv = container_of(port, struct eg20t_port, port);
1470         pci_iounmap(priv->pdev, priv->membase);
1471         pci_release_regions(priv->pdev);
1472 }
1473
1474 static int pch_uart_request_port(struct uart_port *port)
1475 {
1476         struct eg20t_port *priv;
1477         int ret;
1478         void __iomem *membase;
1479
1480         priv = container_of(port, struct eg20t_port, port);
1481         ret = pci_request_regions(priv->pdev, KBUILD_MODNAME);
1482         if (ret < 0)
1483                 return -EBUSY;
1484
1485         membase = pci_iomap(priv->pdev, 1, 0);
1486         if (!membase) {
1487                 pci_release_regions(priv->pdev);
1488                 return -EBUSY;
1489         }
1490         priv->membase = port->membase = membase;
1491
1492         return 0;
1493 }
1494
1495 static void pch_uart_config_port(struct uart_port *port, int type)
1496 {
1497         struct eg20t_port *priv;
1498
1499         priv = container_of(port, struct eg20t_port, port);
1500         if (type & UART_CONFIG_TYPE) {
1501                 port->type = priv->port_type;
1502                 pch_uart_request_port(port);
1503         }
1504 }
1505
1506 static int pch_uart_verify_port(struct uart_port *port,
1507                                 struct serial_struct *serinfo)
1508 {
1509         struct eg20t_port *priv;
1510
1511         priv = container_of(port, struct eg20t_port, port);
1512         if (serinfo->flags & UPF_LOW_LATENCY) {
1513                 dev_info(priv->port.dev,
1514                         "PCH UART : Use PIO Mode (without DMA)\n");
1515                 priv->use_dma = 0;
1516                 serinfo->flags &= ~UPF_LOW_LATENCY;
1517         } else {
1518 #ifndef CONFIG_PCH_DMA
1519                 dev_err(priv->port.dev, "%s : PCH DMA is not Loaded.\n",
1520                         __func__);
1521                 return -EOPNOTSUPP;
1522 #endif
1523                 if (!priv->use_dma) {
1524                         pch_request_dma(port);
1525                         if (priv->chan_rx)
1526                                 priv->use_dma = 1;
1527                 }
1528                 dev_info(priv->port.dev, "PCH UART: %s\n",
1529                                 priv->use_dma ?
1530                                 "Use DMA Mode" : "No DMA");
1531         }
1532
1533         return 0;
1534 }
1535
1536 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_PCH_UART_CONSOLE)
1537 /*
1538  *      Wait for transmitter & holding register to empty
1539  */
1540 static void wait_for_xmitr(struct eg20t_port *up, int bits)
1541 {
1542         unsigned int status, tmout = 10000;
1543
1544         /* Wait up to 10ms for the character(s) to be sent. */
1545         for (;;) {
1546                 status = ioread8(up->membase + UART_LSR);
1547
1548                 if ((status & bits) == bits)
1549                         break;
1550                 if (--tmout == 0)
1551                         break;
1552                 udelay(1);
1553         }
1554
1555         /* Wait up to 1s for flow control if necessary */
1556         if (up->port.flags & UPF_CONS_FLOW) {
1557                 unsigned int tmout;
1558                 for (tmout = 1000000; tmout; tmout--) {
1559                         unsigned int msr = ioread8(up->membase + UART_MSR);
1560                         if (msr & UART_MSR_CTS)
1561                                 break;
1562                         udelay(1);
1563                         touch_nmi_watchdog();
1564                 }
1565         }
1566 }
1567 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_PCH_UART_CONSOLE */
1568
1569 #ifdef CONFIG_CONSOLE_POLL
1570 /*
1571  * Console polling routines for communicate via uart while
1572  * in an interrupt or debug context.
1573  */
1574 static int pch_uart_get_poll_char(struct uart_port *port)
1575 {
1576         struct eg20t_port *priv =
1577                 container_of(port, struct eg20t_port, port);
1578         u8 lsr = ioread8(priv->membase + UART_LSR);
1579
1580         if (!(lsr & UART_LSR_DR))
1581                 return NO_POLL_CHAR;
1582
1583         return ioread8(priv->membase + PCH_UART_RBR);
1584 }
1585
1586
1587 static void pch_uart_put_poll_char(struct uart_port *port,
1588                          unsigned char c)
1589 {
1590         unsigned int ier;
1591         struct eg20t_port *priv =
1592                 container_of(port, struct eg20t_port, port);
1593
1594         /*
1595          * First save the IER then disable the interrupts
1596          */
1597         ier = ioread8(priv->membase + UART_IER);
1598         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1599
1600         wait_for_xmitr(priv, UART_LSR_THRE);
1601         /*
1602          * Send the character out.
1603          */
1604         iowrite8(c, priv->membase + PCH_UART_THR);
1605
1606         /*
1607          * Finally, wait for transmitter to become empty
1608          * and restore the IER
1609          */
1610         wait_for_xmitr(priv, BOTH_EMPTY);
1611         iowrite8(ier, priv->membase + UART_IER);
1612 }
1613 #endif /* CONFIG_CONSOLE_POLL */
1614
1615 static const struct uart_ops pch_uart_ops = {
1616         .tx_empty = pch_uart_tx_empty,
1617         .set_mctrl = pch_uart_set_mctrl,
1618         .get_mctrl = pch_uart_get_mctrl,
1619         .stop_tx = pch_uart_stop_tx,
1620         .start_tx = pch_uart_start_tx,
1621         .stop_rx = pch_uart_stop_rx,
1622         .enable_ms = pch_uart_enable_ms,
1623         .break_ctl = pch_uart_break_ctl,
1624         .startup = pch_uart_startup,
1625         .shutdown = pch_uart_shutdown,
1626         .set_termios = pch_uart_set_termios,
1627 /*      .pm             = pch_uart_pm,          Not supported yet */
1628         .type = pch_uart_type,
1629         .release_port = pch_uart_release_port,
1630         .request_port = pch_uart_request_port,
1631         .config_port = pch_uart_config_port,
1632         .verify_port = pch_uart_verify_port,
1633 #ifdef CONFIG_CONSOLE_POLL
1634         .poll_get_char = pch_uart_get_poll_char,
1635         .poll_put_char = pch_uart_put_poll_char,
1636 #endif
1637 };
1638
1639 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1640
1641 static void pch_console_putchar(struct uart_port *port, int ch)
1642 {
1643         struct eg20t_port *priv =
1644                 container_of(port, struct eg20t_port, port);
1645
1646         wait_for_xmitr(priv, UART_LSR_THRE);
1647         iowrite8(ch, priv->membase + PCH_UART_THR);
1648 }
1649
1650 /*
1651  *      Print a string to the serial port trying not to disturb
1652  *      any possible real use of the port...
1653  *
1654  *      The console_lock must be held when we get here.
1655  */
1656 static void
1657 pch_console_write(struct console *co, const char *s, unsigned int count)
1658 {
1659         struct eg20t_port *priv;
1660         unsigned long flags;
1661         int priv_locked = 1;
1662         int port_locked = 1;
1663         u8 ier;
1664
1665         priv = pch_uart_ports[co->index];
1666
1667         touch_nmi_watchdog();
1668
1669         local_irq_save(flags);
1670         if (priv->port.sysrq) {
1671                 /* call to uart_handle_sysrq_char already took the priv lock */
1672                 priv_locked = 0;
1673                 /* serial8250_handle_port() already took the port lock */
1674                 port_locked = 0;
1675         } else if (oops_in_progress) {
1676                 priv_locked = spin_trylock(&priv->lock);
1677                 port_locked = spin_trylock(&priv->port.lock);
1678         } else {
1679                 spin_lock(&priv->lock);
1680                 spin_lock(&priv->port.lock);
1681         }
1682
1683         /*
1684          *      First save the IER then disable the interrupts
1685          */
1686         ier = ioread8(priv->membase + UART_IER);
1687
1688         pch_uart_hal_disable_interrupt(priv, PCH_UART_HAL_ALL_INT);
1689
1690         uart_console_write(&priv->port, s, count, pch_console_putchar);
1691
1692         /*
1693          *      Finally, wait for transmitter to become empty
1694          *      and restore the IER
1695          */
1696         wait_for_xmitr(priv, BOTH_EMPTY);
1697         iowrite8(ier, priv->membase + UART_IER);
1698
1699         if (port_locked)
1700                 spin_unlock(&priv->port.lock);
1701         if (priv_locked)
1702                 spin_unlock(&priv->lock);
1703         local_irq_restore(flags);
1704 }
1705
1706 static int __init pch_console_setup(struct console *co, char *options)
1707 {
1708         struct uart_port *port;
1709         int baud = default_baud;
1710         int bits = 8;
1711         int parity = 'n';
1712         int flow = 'n';
1713
1714         /*
1715          * Check whether an invalid uart number has been specified, and
1716          * if so, search for the first available port that does have
1717          * console support.
1718          */
1719         if (co->index >= PCH_UART_NR)
1720                 co->index = 0;
1721         port = &pch_uart_ports[co->index]->port;
1722
1723         if (!port || (!port->iobase && !port->membase))
1724                 return -ENODEV;
1725
1726         port->uartclk = pch_uart_get_uartclk();
1727
1728         if (options)
1729                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1730
1731         return uart_set_options(port, co, baud, parity, bits, flow);
1732 }
1733
1734 static struct uart_driver pch_uart_driver;
1735
1736 static struct console pch_console = {
1737         .name           = PCH_UART_DRIVER_DEVICE,
1738         .write          = pch_console_write,
1739         .device         = uart_console_device,
1740         .setup          = pch_console_setup,
1741         .flags          = CON_PRINTBUFFER | CON_ANYTIME,
1742         .index          = -1,
1743         .data           = &pch_uart_driver,
1744 };
1745
1746 #define PCH_CONSOLE     (&pch_console)
1747 #else
1748 #define PCH_CONSOLE     NULL
1749 #endif  /* CONFIG_SERIAL_PCH_UART_CONSOLE */
1750
1751 static struct uart_driver pch_uart_driver = {
1752         .owner = THIS_MODULE,
1753         .driver_name = KBUILD_MODNAME,
1754         .dev_name = PCH_UART_DRIVER_DEVICE,
1755         .major = 0,
1756         .minor = 0,
1757         .nr = PCH_UART_NR,
1758         .cons = PCH_CONSOLE,
1759 };
1760
1761 static struct eg20t_port *pch_uart_init_port(struct pci_dev *pdev,
1762                                              const struct pci_device_id *id)
1763 {
1764         struct eg20t_port *priv;
1765         int ret;
1766         unsigned int iobase;
1767         unsigned int mapbase;
1768         unsigned char *rxbuf;
1769         int fifosize;
1770         int port_type;
1771         struct pch_uart_driver_data *board;
1772 #ifdef CONFIG_DEBUG_FS
1773         char name[32];  /* for debugfs file name */
1774 #endif
1775
1776         board = &drv_dat[id->driver_data];
1777         port_type = board->port_type;
1778
1779         priv = kzalloc(sizeof(struct eg20t_port), GFP_KERNEL);
1780         if (priv == NULL)
1781                 goto init_port_alloc_err;
1782
1783         rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
1784         if (!rxbuf)
1785                 goto init_port_free_txbuf;
1786
1787         switch (port_type) {
1788         case PORT_UNKNOWN:
1789                 fifosize = 256; /* EG20T/ML7213: UART0 */
1790                 break;
1791         case PORT_8250:
1792                 fifosize = 64; /* EG20T:UART1~3  ML7213: UART1~2*/
1793                 break;
1794         default:
1795                 dev_err(&pdev->dev, "Invalid Port Type(=%d)\n", port_type);
1796                 goto init_port_hal_free;
1797         }
1798
1799         pci_enable_msi(pdev);
1800         pci_set_master(pdev);
1801
1802         spin_lock_init(&priv->lock);
1803
1804         iobase = pci_resource_start(pdev, 0);
1805         mapbase = pci_resource_start(pdev, 1);
1806         priv->mapbase = mapbase;
1807         priv->iobase = iobase;
1808         priv->pdev = pdev;
1809         priv->tx_empty = 1;
1810         priv->rxbuf.buf = rxbuf;
1811         priv->rxbuf.size = PAGE_SIZE;
1812
1813         priv->fifo_size = fifosize;
1814         priv->uartclk = pch_uart_get_uartclk();
1815         priv->port_type = PORT_MAX_8250 + port_type + 1;
1816         priv->port.dev = &pdev->dev;
1817         priv->port.iobase = iobase;
1818         priv->port.membase = NULL;
1819         priv->port.mapbase = mapbase;
1820         priv->port.irq = pdev->irq;
1821         priv->port.iotype = UPIO_PORT;
1822         priv->port.ops = &pch_uart_ops;
1823         priv->port.flags = UPF_BOOT_AUTOCONF;
1824         priv->port.fifosize = fifosize;
1825         priv->port.line = board->line_no;
1826         priv->trigger = PCH_UART_HAL_TRIGGER_M;
1827
1828         snprintf(priv->irq_name, IRQ_NAME_SIZE,
1829                  KBUILD_MODNAME ":" PCH_UART_DRIVER_DEVICE "%d",
1830                  priv->port.line);
1831
1832         spin_lock_init(&priv->port.lock);
1833
1834         pci_set_drvdata(pdev, priv);
1835         priv->trigger_level = 1;
1836         priv->fcr = 0;
1837
1838         if (pdev->dev.of_node)
1839                 of_property_read_u32(pdev->dev.of_node, "clock-frequency"
1840                                          , &user_uartclk);
1841
1842 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1843         pch_uart_ports[board->line_no] = priv;
1844 #endif
1845         ret = uart_add_one_port(&pch_uart_driver, &priv->port);
1846         if (ret < 0)
1847                 goto init_port_hal_free;
1848
1849 #ifdef CONFIG_DEBUG_FS
1850         snprintf(name, sizeof(name), "uart%d_regs", board->line_no);
1851         priv->debugfs = debugfs_create_file(name, S_IFREG | S_IRUGO,
1852                                 NULL, priv, &port_regs_ops);
1853 #endif
1854
1855         return priv;
1856
1857 init_port_hal_free:
1858 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1859         pch_uart_ports[board->line_no] = NULL;
1860 #endif
1861         free_page((unsigned long)rxbuf);
1862 init_port_free_txbuf:
1863         kfree(priv);
1864 init_port_alloc_err:
1865
1866         return NULL;
1867 }
1868
1869 static void pch_uart_exit_port(struct eg20t_port *priv)
1870 {
1871
1872 #ifdef CONFIG_DEBUG_FS
1873         if (priv->debugfs)
1874                 debugfs_remove(priv->debugfs);
1875 #endif
1876         uart_remove_one_port(&pch_uart_driver, &priv->port);
1877         free_page((unsigned long)priv->rxbuf.buf);
1878 }
1879
1880 static void pch_uart_pci_remove(struct pci_dev *pdev)
1881 {
1882         struct eg20t_port *priv = pci_get_drvdata(pdev);
1883
1884         pci_disable_msi(pdev);
1885
1886 #ifdef CONFIG_SERIAL_PCH_UART_CONSOLE
1887         pch_uart_ports[priv->port.line] = NULL;
1888 #endif
1889         pch_uart_exit_port(priv);
1890         pci_disable_device(pdev);
1891         kfree(priv);
1892         return;
1893 }
1894 #ifdef CONFIG_PM
1895 static int pch_uart_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1896 {
1897         struct eg20t_port *priv = pci_get_drvdata(pdev);
1898
1899         uart_suspend_port(&pch_uart_driver, &priv->port);
1900
1901         pci_save_state(pdev);
1902         pci_set_power_state(pdev, pci_choose_state(pdev, state));
1903         return 0;
1904 }
1905
1906 static int pch_uart_pci_resume(struct pci_dev *pdev)
1907 {
1908         struct eg20t_port *priv = pci_get_drvdata(pdev);
1909         int ret;
1910
1911         pci_set_power_state(pdev, PCI_D0);
1912         pci_restore_state(pdev);
1913
1914         ret = pci_enable_device(pdev);
1915         if (ret) {
1916                 dev_err(&pdev->dev,
1917                 "%s-pci_enable_device failed(ret=%d) ", __func__, ret);
1918                 return ret;
1919         }
1920
1921         uart_resume_port(&pch_uart_driver, &priv->port);
1922
1923         return 0;
1924 }
1925 #else
1926 #define pch_uart_pci_suspend NULL
1927 #define pch_uart_pci_resume NULL
1928 #endif
1929
1930 static const struct pci_device_id pch_uart_pci_id[] = {
1931         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8811),
1932          .driver_data = pch_et20t_uart0},
1933         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8812),
1934          .driver_data = pch_et20t_uart1},
1935         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8813),
1936          .driver_data = pch_et20t_uart2},
1937         {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x8814),
1938          .driver_data = pch_et20t_uart3},
1939         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8027),
1940          .driver_data = pch_ml7213_uart0},
1941         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8028),
1942          .driver_data = pch_ml7213_uart1},
1943         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
1944          .driver_data = pch_ml7213_uart2},
1945         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
1946          .driver_data = pch_ml7223_uart0},
1947         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
1948          .driver_data = pch_ml7223_uart1},
1949         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8811),
1950          .driver_data = pch_ml7831_uart0},
1951         {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8812),
1952          .driver_data = pch_ml7831_uart1},
1953         {0,},
1954 };
1955
1956 static int pch_uart_pci_probe(struct pci_dev *pdev,
1957                                         const struct pci_device_id *id)
1958 {
1959         int ret;
1960         struct eg20t_port *priv;
1961
1962         ret = pci_enable_device(pdev);
1963         if (ret < 0)
1964                 goto probe_error;
1965
1966         priv = pch_uart_init_port(pdev, id);
1967         if (!priv) {
1968                 ret = -EBUSY;
1969                 goto probe_disable_device;
1970         }
1971         pci_set_drvdata(pdev, priv);
1972
1973         return ret;
1974
1975 probe_disable_device:
1976         pci_disable_msi(pdev);
1977         pci_disable_device(pdev);
1978 probe_error:
1979         return ret;
1980 }
1981
1982 static struct pci_driver pch_uart_pci_driver = {
1983         .name = "pch_uart",
1984         .id_table = pch_uart_pci_id,
1985         .probe = pch_uart_pci_probe,
1986         .remove = pch_uart_pci_remove,
1987         .suspend = pch_uart_pci_suspend,
1988         .resume = pch_uart_pci_resume,
1989 };
1990
1991 static int __init pch_uart_module_init(void)
1992 {
1993         int ret;
1994
1995         /* register as UART driver */
1996         ret = uart_register_driver(&pch_uart_driver);
1997         if (ret < 0)
1998                 return ret;
1999
2000         /* register as PCI driver */
2001         ret = pci_register_driver(&pch_uart_pci_driver);
2002         if (ret < 0)
2003                 uart_unregister_driver(&pch_uart_driver);
2004
2005         return ret;
2006 }
2007 module_init(pch_uart_module_init);
2008
2009 static void __exit pch_uart_module_exit(void)
2010 {
2011         pci_unregister_driver(&pch_uart_pci_driver);
2012         uart_unregister_driver(&pch_uart_driver);
2013 }
2014 module_exit(pch_uart_module_exit);
2015
2016 MODULE_LICENSE("GPL v2");
2017 MODULE_DESCRIPTION("Intel EG20T PCH UART PCI Driver");
2018 MODULE_DEVICE_TABLE(pci, pch_uart_pci_id);
2019
2020 module_param(default_baud, uint, S_IRUGO);
2021 MODULE_PARM_DESC(default_baud,
2022                  "Default BAUD for initial driver state and console (default 9600)");
2023 module_param(user_uartclk, uint, S_IRUGO);
2024 MODULE_PARM_DESC(user_uartclk,
2025                  "Override UART default or board specific UART clock");