drivers/tty/serial/qcom_geni_serial.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
   3
   4 #include <linux/clk.h>
   5 #include <linux/console.h>
   6 #include <linux/io.h>
   7 #include <linux/iopoll.h>
   8 #include <linux/module.h>
   9 #include <linux/of.h>
  10 #include <linux/of_device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/qcom-geni-se.h>
  13 #include <linux/serial.h>
  14 #include <linux/serial_core.h>
  15 #include <linux/slab.h>
  16 #include <linux/tty.h>
  17 #include <linux/tty_flip.h>
  18
  19 /* UART specific GENI registers */
  20 #define SE_UART_LOOPBACK_CFG            0x22c
  21 #define SE_UART_TX_TRANS_CFG            0x25c
  22 #define SE_UART_TX_WORD_LEN             0x268
  23 #define SE_UART_TX_STOP_BIT_LEN         0x26c
  24 #define SE_UART_TX_TRANS_LEN            0x270
  25 #define SE_UART_RX_TRANS_CFG            0x280
  26 #define SE_UART_RX_WORD_LEN             0x28c
  27 #define SE_UART_RX_STALE_CNT            0x294
  28 #define SE_UART_TX_PARITY_CFG           0x2a4
  29 #define SE_UART_RX_PARITY_CFG           0x2a8
  30 #define SE_UART_MANUAL_RFR              0x2ac
  31
  32 /* SE_UART_TRANS_CFG */
  33 #define UART_TX_PAR_EN          BIT(0)
  34 #define UART_CTS_MASK           BIT(1)
  35
  36 /* SE_UART_TX_WORD_LEN */
  37 #define TX_WORD_LEN_MSK         GENMASK(9, 0)
  38
  39 /* SE_UART_TX_STOP_BIT_LEN */
  40 #define TX_STOP_BIT_LEN_MSK     GENMASK(23, 0)
  41 #define TX_STOP_BIT_LEN_1       0
  42 #define TX_STOP_BIT_LEN_1_5     1
  43 #define TX_STOP_BIT_LEN_2       2
  44
  45 /* SE_UART_TX_TRANS_LEN */
  46 #define TX_TRANS_LEN_MSK        GENMASK(23, 0)
  47
  48 /* SE_UART_RX_TRANS_CFG */
  49 #define UART_RX_INS_STATUS_BIT  BIT(2)
  50 #define UART_RX_PAR_EN          BIT(3)
  51
  52 /* SE_UART_RX_WORD_LEN */
  53 #define RX_WORD_LEN_MASK        GENMASK(9, 0)
  54
  55 /* SE_UART_RX_STALE_CNT */
  56 #define RX_STALE_CNT            GENMASK(23, 0)
  57
  58 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
  59 #define PAR_CALC_EN             BIT(0)
  60 #define PAR_MODE_MSK            GENMASK(2, 1)
  61 #define PAR_MODE_SHFT           1
  62 #define PAR_EVEN                0x00
  63 #define PAR_ODD                 0x01
  64 #define PAR_SPACE               0x10
  65 #define PAR_MARK                0x11
  66
  67 /* SE_UART_MANUAL_RFR register fields */
  68 #define UART_MANUAL_RFR_EN      BIT(31)
  69 #define UART_RFR_NOT_READY      BIT(1)
  70 #define UART_RFR_READY          BIT(0)
  71
  72 /* UART M_CMD OP codes */
  73 #define UART_START_TX           0x1
  74 #define UART_START_BREAK        0x4
  75 #define UART_STOP_BREAK         0x5
  76 /* UART S_CMD OP codes */
  77 #define UART_START_READ         0x1
  78 #define UART_PARAM              0x1
  79
  80 #define UART_OVERSAMPLING       32
  81 #define STALE_TIMEOUT           16
  82 #define DEFAULT_BITS_PER_CHAR   10
  83 #define GENI_UART_CONS_PORTS    1
  84 #define GENI_UART_PORTS         3
  85 #define DEF_FIFO_DEPTH_WORDS    16
  86 #define DEF_TX_WM               2
  87 #define DEF_FIFO_WIDTH_BITS     32
  88 #define UART_RX_WM              2
  89 #define MAX_LOOPBACK_CFG        3
  90
  91 #ifdef CONFIG_CONSOLE_POLL
  92 #define RX_BYTES_PW 1
  93 #else
  94 #define RX_BYTES_PW 4
  95 #endif
  96
  97 struct qcom_geni_serial_port {
  98         struct uart_port uport;
  99         struct geni_se se;
 100         char name[20];
 101         u32 tx_fifo_depth;
 102         u32 tx_fifo_width;
 103         u32 rx_fifo_depth;
 104         bool setup;
 105         int (*handle_rx)(struct uart_port *uport, u32 bytes, bool drop);
 106         unsigned int baud;
 107         unsigned int tx_bytes_pw;
 108         unsigned int rx_bytes_pw;
 109         u32 *rx_fifo;
 110         u32 loopback;
 111         bool brk;
 112
 113         unsigned int tx_remaining;
 114 };
 115
 116 static const struct uart_ops qcom_geni_console_pops;
 117 static const struct uart_ops qcom_geni_uart_pops;
 118 static struct uart_driver qcom_geni_console_driver;
 119 static struct uart_driver qcom_geni_uart_driver;
 120 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop);
 121 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop);
 122 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *port);
 123 static void qcom_geni_serial_stop_rx(struct uart_port *uport);
 124 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop);
 125
 126 static const unsigned long root_freq[] = {7372800, 14745600, 19200000, 29491200,
 127                                         32000000, 48000000, 64000000, 80000000,
 128                                         96000000, 100000000, 102400000,
 129                                         112000000, 120000000, 128000000};
 130
 131 #define to_dev_port(ptr, member) \
 132                 container_of(ptr, struct qcom_geni_serial_port, member)
 133
 134 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
 135         [0] = {
 136                 .uport = {
 137                                 .iotype = UPIO_MEM,
 138                                 .ops = &qcom_geni_uart_pops,
 139                                 .flags = UPF_BOOT_AUTOCONF,
 140                                 .line = 0,
 141                 },
 142         },
 143         [1] = {
 144                 .uport = {
 145                                 .iotype = UPIO_MEM,
 146                                 .ops = &qcom_geni_uart_pops,
 147                                 .flags = UPF_BOOT_AUTOCONF,
 148                                 .line = 1,
 149                 },
 150         },
 151         [2] = {
 152                 .uport = {
 153                                 .iotype = UPIO_MEM,
 154                                 .ops = &qcom_geni_uart_pops,
 155                                 .flags = UPF_BOOT_AUTOCONF,
 156                                 .line = 2,
 157                 },
 158         },
 159 };
 160
 161 static ssize_t loopback_show(struct device *dev,
 162                                 struct device_attribute *attr, char *buf)
 163 {
 164         struct platform_device *pdev = to_platform_device(dev);
 165         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
 166
 167         return snprintf(buf, sizeof(u32), "%d\n", port->loopback);
 168 }
 169
 170 static ssize_t loopback_store(struct device *dev,
 171                                 struct device_attribute *attr, const char *buf,
 172                                 size_t size)
 173 {
 174         struct platform_device *pdev = to_platform_device(dev);
 175         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
 176         u32 loopback;
 177
 178         if (kstrtoint(buf, 0, &loopback) || loopback > MAX_LOOPBACK_CFG) {
 179                 dev_err(dev, "Invalid input\n");
 180                 return -EINVAL;
 181         }
 182         port->loopback = loopback;
 183         return size;
 184 }
 185 static DEVICE_ATTR_RW(loopback);
 186
 187 static struct qcom_geni_serial_port qcom_geni_console_port = {
 188         .uport = {
 189                 .iotype = UPIO_MEM,
 190                 .ops = &qcom_geni_console_pops,
 191                 .flags = UPF_BOOT_AUTOCONF,
 192                 .line = 0,
 193         },
 194 };
 195
 196 static int qcom_geni_serial_request_port(struct uart_port *uport)
 197 {
 198         struct platform_device *pdev = to_platform_device(uport->dev);
 199         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 200         struct resource *res;
 201
 202         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 203         uport->membase = devm_ioremap_resource(&pdev->dev, res);
 204         if (IS_ERR(uport->membase))
 205                 return PTR_ERR(uport->membase);
 206         port->se.base = uport->membase;
 207         return 0;
 208 }
 209
 210 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
 211 {
 212         if (cfg_flags & UART_CONFIG_TYPE) {
 213                 uport->type = PORT_MSM;
 214                 qcom_geni_serial_request_port(uport);
 215         }
 216 }
 217
 218 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
 219 {
 220         unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
 221         u32 geni_ios;
 222
 223         if (uart_console(uport)) {
 224                 mctrl |= TIOCM_CTS;
 225         } else {
 226                 geni_ios = readl(uport->membase + SE_GENI_IOS);
 227                 if (!(geni_ios & IO2_DATA_IN))
 228                         mctrl |= TIOCM_CTS;
 229         }
 230
 231         return mctrl;
 232 }
 233
 234 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
 235                                                         unsigned int mctrl)
 236 {
 237         u32 uart_manual_rfr = 0;
 238
 239         if (uart_console(uport))
 240                 return;
 241
 242         if (!(mctrl & TIOCM_RTS))
 243                 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
 244         writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
 245 }
 246
 247 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
 248 {
 249         return "MSM";
 250 }
 251
 252 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
 253 {
 254         struct qcom_geni_serial_port *port;
 255         int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
 256
 257         if (line < 0 || line >= nr_ports)
 258                 return ERR_PTR(-ENXIO);
 259
 260         port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
 261         return port;
 262 }
 263
 264 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
 265                                 int offset, int field, bool set)
 266 {
 267         u32 reg;
 268         struct qcom_geni_serial_port *port;
 269         unsigned int baud;
 270         unsigned int fifo_bits;
 271         unsigned long timeout_us = 20000;
 272
 273         if (uport->private_data) {
 274                 port = to_dev_port(uport, uport);
 275                 baud = port->baud;
 276                 if (!baud)
 277                         baud = 115200;
 278                 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
 279                 /*
 280                  * Total polling iterations based on FIFO worth of bytes to be
 281                  * sent at current baud. Add a little fluff to the wait.
 282                  */
 283                 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
 284         }
 285
 286         /*
 287          * Use custom implementation instead of readl_poll_atomic since ktimer
 288          * is not ready at the time of early console.
 289          */
 290         timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
 291         while (timeout_us) {
 292                 reg = readl(uport->membase + offset);
 293                 if ((bool)(reg & field) == set)
 294                         return true;
 295                 udelay(10);
 296                 timeout_us -= 10;
 297         }
 298         return false;
 299 }
 300
 301 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
 302 {
 303         u32 m_cmd;
 304
 305         writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
 306         m_cmd = UART_START_TX << M_OPCODE_SHFT;
 307         writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
 308 }
 309
 310 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
 311 {
 312         int done;
 313         u32 irq_clear = M_CMD_DONE_EN;
 314
 315         done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 316                                                 M_CMD_DONE_EN, true);
 317         if (!done) {
 318                 writel(M_GENI_CMD_ABORT, uport->membase +
 319                                                 SE_GENI_M_CMD_CTRL_REG);
 320                 irq_clear |= M_CMD_ABORT_EN;
 321                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 322                                                         M_CMD_ABORT_EN, true);
 323         }
 324         writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
 325 }
 326
 327 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
 328 {
 329         u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
 330
 331         writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
 332         qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
 333                                         S_GENI_CMD_ABORT, false);
 334         writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
 335         writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
 336 }
 337
 338 #ifdef CONFIG_CONSOLE_POLL
 339 static int qcom_geni_serial_get_char(struct uart_port *uport)
 340 {
 341         u32 rx_fifo;
 342         u32 status;
 343
 344         status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 345         writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 346
 347         status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 348         writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 349
 350         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 351         if (!(status & RX_FIFO_WC_MSK))
 352                 return NO_POLL_CHAR;
 353
 354         rx_fifo = readl(uport->membase + SE_GENI_RX_FIFOn);
 355         return rx_fifo & 0xff;
 356 }
 357
 358 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
 359                                                         unsigned char c)
 360 {
 361         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 362         qcom_geni_serial_setup_tx(uport, 1);
 363         WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 364                                                 M_TX_FIFO_WATERMARK_EN, true));
 365         writel(c, uport->membase + SE_GENI_TX_FIFOn);
 366         writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 367         qcom_geni_serial_poll_tx_done(uport);
 368 }
 369 #endif
 370
 371 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
 372 static void qcom_geni_serial_wr_char(struct uart_port *uport, int ch)
 373 {
 374         writel(ch, uport->membase + SE_GENI_TX_FIFOn);
 375 }
 376
 377 static void
 378 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
 379                                  unsigned int count)
 380 {
 381         int i;
 382         u32 bytes_to_send = count;
 383
 384         for (i = 0; i < count; i++) {
 385                 /*
 386                  * uart_console_write() adds a carriage return for each newline.
 387                  * Account for additional bytes to be written.
 388                  */
 389                 if (s[i] == '\n')
 390                         bytes_to_send++;
 391         }
 392
 393         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 394         qcom_geni_serial_setup_tx(uport, bytes_to_send);
 395         for (i = 0; i < count; ) {
 396                 size_t chars_to_write = 0;
 397                 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
 398
 399                 /*
 400                  * If the WM bit never set, then the Tx state machine is not
 401                  * in a valid state, so break, cancel/abort any existing
 402                  * command. Unfortunately the current data being written is
 403                  * lost.
 404                  */
 405                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 406                                                 M_TX_FIFO_WATERMARK_EN, true))
 407                         break;
 408                 chars_to_write = min_t(size_t, count - i, avail / 2);
 409                 uart_console_write(uport, s + i, chars_to_write,
 410                                                 qcom_geni_serial_wr_char);
 411                 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
 412                                                         SE_GENI_M_IRQ_CLEAR);
 413                 i += chars_to_write;
 414         }
 415         qcom_geni_serial_poll_tx_done(uport);
 416 }
 417
 418 static void qcom_geni_serial_console_write(struct console *co, const char *s,
 419                               unsigned int count)
 420 {
 421         struct uart_port *uport;
 422         struct qcom_geni_serial_port *port;
 423         bool locked = true;
 424         unsigned long flags;
 425         u32 geni_status;
 426         u32 irq_en;
 427
 428         WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
 429
 430         port = get_port_from_line(co->index, true);
 431         if (IS_ERR(port))
 432                 return;
 433
 434         uport = &port->uport;
 435         if (oops_in_progress)
 436                 locked = spin_trylock_irqsave(&uport->lock, flags);
 437         else
 438                 spin_lock_irqsave(&uport->lock, flags);
 439
 440         geni_status = readl(uport->membase + SE_GENI_STATUS);
 441
 442         /* Cancel the current write to log the fault */
 443         if (!locked) {
 444                 geni_se_cancel_m_cmd(&port->se);
 445                 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 446                                                 M_CMD_CANCEL_EN, true)) {
 447                         geni_se_abort_m_cmd(&port->se);
 448                         qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 449                                                         M_CMD_ABORT_EN, true);
 450                         writel(M_CMD_ABORT_EN, uport->membase +
 451                                                         SE_GENI_M_IRQ_CLEAR);
 452                 }
 453                 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 454         } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
 455                 /*
 456                  * It seems we can't interrupt existing transfers if all data
 457                  * has been sent, in which case we need to look for done first.
 458                  */
 459                 qcom_geni_serial_poll_tx_done(uport);
 460
 461                 if (uart_circ_chars_pending(&uport->state->xmit)) {
 462                         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 463                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 464                                         uport->membase + SE_GENI_M_IRQ_EN);
 465                 }
 466         }
 467
 468         __qcom_geni_serial_console_write(uport, s, count);
 469
 470         if (port->tx_remaining)
 471                 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
 472
 473         if (locked)
 474                 spin_unlock_irqrestore(&uport->lock, flags);
 475 }
 476
 477 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 478 {
 479         u32 i;
 480         unsigned char buf[sizeof(u32)];
 481         struct tty_port *tport;
 482         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 483
 484         tport = &uport->state->port;
 485         for (i = 0; i < bytes; ) {
 486                 int c;
 487                 int chunk = min_t(int, bytes - i, port->rx_bytes_pw);
 488
 489                 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
 490                 i += chunk;
 491                 if (drop)
 492                         continue;
 493
 494                 for (c = 0; c < chunk; c++) {
 495                         int sysrq;
 496
 497                         uport->icount.rx++;
 498                         if (port->brk && buf[c] == 0) {
 499                                 port->brk = false;
 500                                 if (uart_handle_break(uport))
 501                                         continue;
 502                         }
 503
 504                         sysrq = uart_handle_sysrq_char(uport, buf[c]);
 505                         if (!sysrq)
 506                                 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
 507                 }
 508         }
 509         if (!drop)
 510                 tty_flip_buffer_push(tport);
 511         return 0;
 512 }
 513 #else
 514 static int handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
 515 {
 516         return -EPERM;
 517 }
 518
 519 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
 520
 521 static int handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
 522 {
 523         unsigned char *buf;
 524         struct tty_port *tport;
 525         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 526         u32 num_bytes_pw = port->tx_fifo_width / BITS_PER_BYTE;
 527         u32 words = ALIGN(bytes, num_bytes_pw) / num_bytes_pw;
 528         int ret;
 529
 530         tport = &uport->state->port;
 531         ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, port->rx_fifo, words);
 532         if (drop)
 533                 return 0;
 534
 535         buf = (unsigned char *)port->rx_fifo;
 536         ret = tty_insert_flip_string(tport, buf, bytes);
 537         if (ret != bytes) {
 538                 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
 539                                 __func__, ret, bytes);
 540                 WARN_ON_ONCE(1);
 541         }
 542         uport->icount.rx += ret;
 543         tty_flip_buffer_push(tport);
 544         return ret;
 545 }
 546
 547 static void qcom_geni_serial_start_tx(struct uart_port *uport)
 548 {
 549         u32 irq_en;
 550         u32 status;
 551
 552         status = readl(uport->membase + SE_GENI_STATUS);
 553         if (status & M_GENI_CMD_ACTIVE)
 554                 return;
 555
 556         if (!qcom_geni_serial_tx_empty(uport))
 557                 return;
 558
 559         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 560         irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
 561
 562         writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
 563         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 564 }
 565
 566 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
 567 {
 568         u32 irq_en;
 569         u32 status;
 570         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 571
 572         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 573         irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
 574         writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
 575         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 576         status = readl(uport->membase + SE_GENI_STATUS);
 577         /* Possible stop tx is called multiple times. */
 578         if (!(status & M_GENI_CMD_ACTIVE))
 579                 return;
 580
 581         geni_se_cancel_m_cmd(&port->se);
 582         if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 583                                                 M_CMD_CANCEL_EN, true)) {
 584                 geni_se_abort_m_cmd(&port->se);
 585                 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
 586                                                 M_CMD_ABORT_EN, true);
 587                 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 588         }
 589         writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
 590 }
 591
 592 static void qcom_geni_serial_start_rx(struct uart_port *uport)
 593 {
 594         u32 irq_en;
 595         u32 status;
 596         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 597
 598         status = readl(uport->membase + SE_GENI_STATUS);
 599         if (status & S_GENI_CMD_ACTIVE)
 600                 qcom_geni_serial_stop_rx(uport);
 601
 602         geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
 603
 604         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 605         irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
 606         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 607
 608         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 609         irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
 610         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 611 }
 612
 613 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
 614 {
 615         u32 irq_en;
 616         u32 status;
 617         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 618         u32 s_irq_status;
 619
 620         irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
 621         irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
 622         writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
 623
 624         irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 625         irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
 626         writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
 627
 628         status = readl(uport->membase + SE_GENI_STATUS);
 629         /* Possible stop rx is called multiple times. */
 630         if (!(status & S_GENI_CMD_ACTIVE))
 631                 return;
 632
 633         geni_se_cancel_s_cmd(&port->se);
 634         qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
 635                                         S_CMD_CANCEL_EN, true);
 636         /*
 637          * If timeout occurs secondary engine remains active
 638          * and Abort sequence is executed.
 639          */
 640         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 641         /* Flush the Rx buffer */
 642         if (s_irq_status & S_RX_FIFO_LAST_EN)
 643                 qcom_geni_serial_handle_rx(uport, true);
 644         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 645
 646         status = readl(uport->membase + SE_GENI_STATUS);
 647         if (status & S_GENI_CMD_ACTIVE)
 648                 qcom_geni_serial_abort_rx(uport);
 649 }
 650
 651 static void qcom_geni_serial_handle_rx(struct uart_port *uport, bool drop)
 652 {
 653         u32 status;
 654         u32 word_cnt;
 655         u32 last_word_byte_cnt;
 656         u32 last_word_partial;
 657         u32 total_bytes;
 658         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 659
 660         status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
 661         word_cnt = status & RX_FIFO_WC_MSK;
 662         last_word_partial = status & RX_LAST;
 663         last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
 664                                                 RX_LAST_BYTE_VALID_SHFT;
 665
 666         if (!word_cnt)
 667                 return;
 668         total_bytes = port->rx_bytes_pw * (word_cnt - 1);
 669         if (last_word_partial && last_word_byte_cnt)
 670                 total_bytes += last_word_byte_cnt;
 671         else
 672                 total_bytes += port->rx_bytes_pw;
 673         port->handle_rx(uport, total_bytes, drop);
 674 }
 675
 676 static void qcom_geni_serial_handle_tx(struct uart_port *uport, bool done,
 677                 bool active)
 678 {
 679         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 680         struct circ_buf *xmit = &uport->state->xmit;
 681         size_t avail;
 682         size_t remaining;
 683         size_t pending;
 684         int i;
 685         u32 status;
 686         u32 irq_en;
 687         unsigned int chunk;
 688         int tail;
 689
 690         status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
 691
 692         /* Complete the current tx command before taking newly added data */
 693         if (active)
 694                 pending = port->tx_remaining;
 695         else
 696                 pending = uart_circ_chars_pending(xmit);
 697
 698         /* All data has been transmitted and acknowledged as received */
 699         if (!pending && !status && done) {
 700                 qcom_geni_serial_stop_tx(uport);
 701                 goto out_write_wakeup;
 702         }
 703
 704         avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
 705         avail *= port->tx_bytes_pw;
 706
 707         tail = xmit->tail;
 708         chunk = min(avail, pending);
 709         if (!chunk)
 710                 goto out_write_wakeup;
 711
 712         if (!port->tx_remaining) {
 713                 qcom_geni_serial_setup_tx(uport, pending);
 714                 port->tx_remaining = pending;
 715
 716                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 717                 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
 718                         writel(irq_en | M_TX_FIFO_WATERMARK_EN,
 719                                         uport->membase + SE_GENI_M_IRQ_EN);
 720         }
 721
 722         remaining = chunk;
 723         for (i = 0; i < chunk; ) {
 724                 unsigned int tx_bytes;
 725                 u8 buf[sizeof(u32)];
 726                 int c;
 727
 728                 memset(buf, 0, ARRAY_SIZE(buf));
 729                 tx_bytes = min_t(size_t, remaining, port->tx_bytes_pw);
 730
 731                 for (c = 0; c < tx_bytes ; c++) {
 732                         buf[c] = xmit->buf[tail++];
 733                         tail &= UART_XMIT_SIZE - 1;
 734                 }
 735
 736                 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
 737
 738                 i += tx_bytes;
 739                 uport->icount.tx += tx_bytes;
 740                 remaining -= tx_bytes;
 741                 port->tx_remaining -= tx_bytes;
 742         }
 743
 744         xmit->tail = tail;
 745
 746         /*
 747          * The tx fifo watermark is level triggered and latched. Though we had
 748          * cleared it in qcom_geni_serial_isr it will have already reasserted
 749          * so we must clear it again here after our writes.
 750          */
 751         writel(M_TX_FIFO_WATERMARK_EN,
 752                         uport->membase + SE_GENI_M_IRQ_CLEAR);
 753
 754 out_write_wakeup:
 755         if (!port->tx_remaining) {
 756                 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 757                 if (irq_en & M_TX_FIFO_WATERMARK_EN)
 758                         writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
 759                                         uport->membase + SE_GENI_M_IRQ_EN);
 760         }
 761
 762         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 763                 uart_write_wakeup(uport);
 764 }
 765
 766 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
 767 {
 768         unsigned int m_irq_status;
 769         unsigned int s_irq_status;
 770         unsigned int geni_status;
 771         struct uart_port *uport = dev;
 772         unsigned long flags;
 773         unsigned int m_irq_en;
 774         bool drop_rx = false;
 775         struct tty_port *tport = &uport->state->port;
 776         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 777
 778         if (uport->suspended)
 779                 return IRQ_NONE;
 780
 781         spin_lock_irqsave(&uport->lock, flags);
 782         m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
 783         s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
 784         geni_status = readl(uport->membase + SE_GENI_STATUS);
 785         m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
 786         writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
 787         writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
 788
 789         if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
 790                 goto out_unlock;
 791
 792         if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
 793                 uport->icount.overrun++;
 794                 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
 795         }
 796
 797         if (m_irq_status & m_irq_en & (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
 798                 qcom_geni_serial_handle_tx(uport, m_irq_status & M_CMD_DONE_EN,
 799                                         geni_status & M_GENI_CMD_ACTIVE);
 800
 801         if (s_irq_status & S_GP_IRQ_0_EN || s_irq_status & S_GP_IRQ_1_EN) {
 802                 if (s_irq_status & S_GP_IRQ_0_EN)
 803                         uport->icount.parity++;
 804                 drop_rx = true;
 805         } else if (s_irq_status & S_GP_IRQ_2_EN ||
 806                                         s_irq_status & S_GP_IRQ_3_EN) {
 807                 uport->icount.brk++;
 808                 port->brk = true;
 809         }
 810
 811         if (s_irq_status & S_RX_FIFO_WATERMARK_EN ||
 812                                         s_irq_status & S_RX_FIFO_LAST_EN)
 813                 qcom_geni_serial_handle_rx(uport, drop_rx);
 814
 815 out_unlock:
 816         spin_unlock_irqrestore(&uport->lock, flags);
 817         return IRQ_HANDLED;
 818 }
 819
 820 static void get_tx_fifo_size(struct qcom_geni_serial_port *port)
 821 {
 822         struct uart_port *uport;
 823
 824         uport = &port->uport;
 825         port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
 826         port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
 827         port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
 828         uport->fifosize =
 829                 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
 830 }
 831
 832
 833 static void qcom_geni_serial_shutdown(struct uart_port *uport)
 834 {
 835         unsigned long flags;
 836
 837         /* Stop the console before stopping the current tx */
 838         if (uart_console(uport))
 839                 console_stop(uport->cons);
 840
 841         free_irq(uport->irq, uport);
 842         spin_lock_irqsave(&uport->lock, flags);
 843         qcom_geni_serial_stop_tx(uport);
 844         qcom_geni_serial_stop_rx(uport);
 845         spin_unlock_irqrestore(&uport->lock, flags);
 846 }
 847
 848 static int qcom_geni_serial_port_setup(struct uart_port *uport)
 849 {
 850         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 851         unsigned int rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
 852         u32 proto;
 853
 854         if (uart_console(uport))
 855                 port->tx_bytes_pw = 1;
 856         else
 857                 port->tx_bytes_pw = 4;
 858         port->rx_bytes_pw = RX_BYTES_PW;
 859
 860         proto = geni_se_read_proto(&port->se);
 861         if (proto != GENI_SE_UART) {
 862                 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
 863                 return -ENXIO;
 864         }
 865
 866         qcom_geni_serial_stop_rx(uport);
 867
 868         get_tx_fifo_size(port);
 869
 870         writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
 871         /*
 872          * Make an unconditional cancel on the main sequencer to reset
 873          * it else we could end up in data loss scenarios.
 874          */
 875         if (uart_console(uport))
 876                 qcom_geni_serial_poll_tx_done(uport);
 877         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->tx_bytes_pw,
 878                                                 false, true, false);
 879         geni_se_config_packing(&port->se, BITS_PER_BYTE, port->rx_bytes_pw,
 880                                                 false, false, true);
 881         geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
 882         geni_se_select_mode(&port->se, GENI_SE_FIFO);
 883         if (!uart_console(uport)) {
 884                 port->rx_fifo = devm_kcalloc(uport->dev,
 885                         port->rx_fifo_depth, sizeof(u32), GFP_KERNEL);
 886                 if (!port->rx_fifo)
 887                         return -ENOMEM;
 888         }
 889         port->setup = true;
 890
 891         return 0;
 892 }
 893
 894 static int qcom_geni_serial_startup(struct uart_port *uport)
 895 {
 896         int ret;
 897         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 898
 899         scnprintf(port->name, sizeof(port->name),
 900                   "qcom_serial_%s%d",
 901                 (uart_console(uport) ? "console" : "uart"), uport->line);
 902
 903         if (!port->setup) {
 904                 ret = qcom_geni_serial_port_setup(uport);
 905                 if (ret)
 906                         return ret;
 907         }
 908
 909         ret = request_irq(uport->irq, qcom_geni_serial_isr, IRQF_TRIGGER_HIGH,
 910                                                         port->name, uport);
 911         if (ret)
 912                 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
 913         return ret;
 914 }
 915
 916 static unsigned long get_clk_cfg(unsigned long clk_freq)
 917 {
 918         int i;
 919
 920         for (i = 0; i < ARRAY_SIZE(root_freq); i++) {
 921                 if (!(root_freq[i] % clk_freq))
 922                         return root_freq[i];
 923         }
 924         return 0;
 925 }
 926
 927 static unsigned long get_clk_div_rate(unsigned int baud, unsigned int *clk_div)
 928 {
 929         unsigned long ser_clk;
 930         unsigned long desired_clk;
 931
 932         desired_clk = baud * UART_OVERSAMPLING;
 933         ser_clk = get_clk_cfg(desired_clk);
 934         if (!ser_clk) {
 935                 pr_err("%s: Can't find matching DFS entry for baud %d\n",
 936                                                                 __func__, baud);
 937                 return ser_clk;
 938         }
 939
 940         *clk_div = ser_clk / desired_clk;
 941         return ser_clk;
 942 }
 943
 944 static void qcom_geni_serial_set_termios(struct uart_port *uport,
 945                                 struct ktermios *termios, struct ktermios *old)
 946 {
 947         unsigned int baud;
 948         unsigned int bits_per_char;
 949         unsigned int tx_trans_cfg;
 950         unsigned int tx_parity_cfg;
 951         unsigned int rx_trans_cfg;
 952         unsigned int rx_parity_cfg;
 953         unsigned int stop_bit_len;
 954         unsigned int clk_div;
 955         unsigned long ser_clk_cfg;
 956         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
 957         unsigned long clk_rate;
 958
 959         qcom_geni_serial_stop_rx(uport);
 960         /* baud rate */
 961         baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
 962         port->baud = baud;
 963         clk_rate = get_clk_div_rate(baud, &clk_div);
 964         if (!clk_rate)
 965                 goto out_restart_rx;
 966
 967         uport->uartclk = clk_rate;
 968         clk_set_rate(port->se.clk, clk_rate);
 969         ser_clk_cfg = SER_CLK_EN;
 970         ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
 971
 972         /* parity */
 973         tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
 974         tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
 975         rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
 976         rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
 977         if (termios->c_cflag & PARENB) {
 978                 tx_trans_cfg |= UART_TX_PAR_EN;
 979                 rx_trans_cfg |= UART_RX_PAR_EN;
 980                 tx_parity_cfg |= PAR_CALC_EN;
 981                 rx_parity_cfg |= PAR_CALC_EN;
 982                 if (termios->c_cflag & PARODD) {
 983                         tx_parity_cfg |= PAR_ODD;
 984                         rx_parity_cfg |= PAR_ODD;
 985                 } else if (termios->c_cflag & CMSPAR) {
 986                         tx_parity_cfg |= PAR_SPACE;
 987                         rx_parity_cfg |= PAR_SPACE;
 988                 } else {
 989                         tx_parity_cfg |= PAR_EVEN;
 990                         rx_parity_cfg |= PAR_EVEN;
 991                 }
 992         } else {
 993                 tx_trans_cfg &= ~UART_TX_PAR_EN;
 994                 rx_trans_cfg &= ~UART_RX_PAR_EN;
 995                 tx_parity_cfg &= ~PAR_CALC_EN;
 996                 rx_parity_cfg &= ~PAR_CALC_EN;
 997         }
 998
 999         /* bits per char */
1000         switch (termios->c_cflag & CSIZE) {
1001         case CS5:
1002                 bits_per_char = 5;
1003                 break;
1004         case CS6:
1005                 bits_per_char = 6;
1006                 break;
1007         case CS7:
1008                 bits_per_char = 7;
1009                 break;
1010         case CS8:
1011         default:
1012                 bits_per_char = 8;
1013                 break;
1014         }
1015
1016         /* stop bits */
1017         if (termios->c_cflag & CSTOPB)
1018                 stop_bit_len = TX_STOP_BIT_LEN_2;
1019         else
1020                 stop_bit_len = TX_STOP_BIT_LEN_1;
1021
1022         /* flow control, clear the CTS_MASK bit if using flow control. */
1023         if (termios->c_cflag & CRTSCTS)
1024                 tx_trans_cfg &= ~UART_CTS_MASK;
1025         else
1026                 tx_trans_cfg |= UART_CTS_MASK;
1027
1028         if (baud)
1029                 uart_update_timeout(uport, termios->c_cflag, baud);
1030
1031         if (!uart_console(uport))
1032                 writel(port->loopback,
1033                                 uport->membase + SE_UART_LOOPBACK_CFG);
1034         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1035         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1036         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1037         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1038         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1039         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1040         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1041         writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1042         writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1043 out_restart_rx:
1044         qcom_geni_serial_start_rx(uport);
1045 }
1046
1047 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
1048 {
1049         return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
1050 }
1051
1052 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
1053 static int qcom_geni_console_setup(struct console *co, char *options)
1054 {
1055         struct uart_port *uport;
1056         struct qcom_geni_serial_port *port;
1057         int baud = 9600;
1058         int bits = 8;
1059         int parity = 'n';
1060         int flow = 'n';
1061         int ret;
1062
1063         if (co->index >= GENI_UART_CONS_PORTS  || co->index < 0)
1064                 return -ENXIO;
1065
1066         port = get_port_from_line(co->index, true);
1067         if (IS_ERR(port)) {
1068                 pr_err("Invalid line %d\n", co->index);
1069                 return PTR_ERR(port);
1070         }
1071
1072         uport = &port->uport;
1073
1074         if (unlikely(!uport->membase))
1075                 return -ENXIO;
1076
1077         if (!port->setup) {
1078                 ret = qcom_geni_serial_port_setup(uport);
1079                 if (ret)
1080                         return ret;
1081         }
1082
1083         if (options)
1084                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1085
1086         return uart_set_options(uport, co, baud, parity, bits, flow);
1087 }
1088
1089 static void qcom_geni_serial_earlycon_write(struct console *con,
1090                                         const char *s, unsigned int n)
1091 {
1092         struct earlycon_device *dev = con->data;
1093
1094         __qcom_geni_serial_console_write(&dev->port, s, n);
1095 }
1096
1097 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1098                                                                 const char *opt)
1099 {
1100         struct uart_port *uport = &dev->port;
1101         u32 tx_trans_cfg;
1102         u32 tx_parity_cfg = 0;  /* Disable Tx Parity */
1103         u32 rx_trans_cfg = 0;
1104         u32 rx_parity_cfg = 0;  /* Disable Rx Parity */
1105         u32 stop_bit_len = 0;   /* Default stop bit length - 1 bit */
1106         u32 bits_per_char;
1107         struct geni_se se;
1108
1109         if (!uport->membase)
1110                 return -EINVAL;
1111
1112         memset(&se, 0, sizeof(se));
1113         se.base = uport->membase;
1114         if (geni_se_read_proto(&se) != GENI_SE_UART)
1115                 return -ENXIO;
1116         /*
1117          * Ignore Flow control.
1118          * n = 8.
1119          */
1120         tx_trans_cfg = UART_CTS_MASK;
1121         bits_per_char = BITS_PER_BYTE;
1122
1123         /*
1124          * Make an unconditional cancel on the main sequencer to reset
1125          * it else we could end up in data loss scenarios.
1126          */
1127         qcom_geni_serial_poll_tx_done(uport);
1128         qcom_geni_serial_abort_rx(uport);
1129         geni_se_config_packing(&se, BITS_PER_BYTE, 1, false, true, false);
1130         geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1131         geni_se_select_mode(&se, GENI_SE_FIFO);
1132
1133         writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1134         writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1135         writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1136         writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1137         writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1138         writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1139         writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1140
1141         dev->con->write = qcom_geni_serial_earlycon_write;
1142         dev->con->setup = NULL;
1143         return 0;
1144 }
1145 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1146                                 qcom_geni_serial_earlycon_setup);
1147
1148 static int __init console_register(struct uart_driver *drv)
1149 {
1150         return uart_register_driver(drv);
1151 }
1152
1153 static void console_unregister(struct uart_driver *drv)
1154 {
1155         uart_unregister_driver(drv);
1156 }
1157
1158 static struct console cons_ops = {
1159         .name = "ttyMSM",
1160         .write = qcom_geni_serial_console_write,
1161         .device = uart_console_device,
1162         .setup = qcom_geni_console_setup,
1163         .flags = CON_PRINTBUFFER,
1164         .index = -1,
1165         .data = &qcom_geni_console_driver,
1166 };
1167
1168 static struct uart_driver qcom_geni_console_driver = {
1169         .owner = THIS_MODULE,
1170         .driver_name = "qcom_geni_console",
1171         .dev_name = "ttyMSM",
1172         .nr =  GENI_UART_CONS_PORTS,
1173         .cons = &cons_ops,
1174 };
1175 #else
1176 static int console_register(struct uart_driver *drv)
1177 {
1178         return 0;
1179 }
1180
1181 static void console_unregister(struct uart_driver *drv)
1182 {
1183 }
1184 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1185
1186 static struct uart_driver qcom_geni_uart_driver = {
1187         .owner = THIS_MODULE,
1188         .driver_name = "qcom_geni_uart",
1189         .dev_name = "ttyHS",
1190         .nr =  GENI_UART_PORTS,
1191 };
1192
1193 static void qcom_geni_serial_pm(struct uart_port *uport,
1194                 unsigned int new_state, unsigned int old_state)
1195 {
1196         struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
1197
1198         /* If we've never been called, treat it as off */
1199         if (old_state == UART_PM_STATE_UNDEFINED)
1200                 old_state = UART_PM_STATE_OFF;
1201
1202         if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
1203                 geni_se_resources_on(&port->se);
1204         else if (new_state == UART_PM_STATE_OFF &&
1205                         old_state == UART_PM_STATE_ON)
1206                 geni_se_resources_off(&port->se);
1207 }
1208
1209 static const struct uart_ops qcom_geni_console_pops = {
1210         .tx_empty = qcom_geni_serial_tx_empty,
1211         .stop_tx = qcom_geni_serial_stop_tx,
1212         .start_tx = qcom_geni_serial_start_tx,
1213         .stop_rx = qcom_geni_serial_stop_rx,
1214         .set_termios = qcom_geni_serial_set_termios,
1215         .startup = qcom_geni_serial_startup,
1216         .request_port = qcom_geni_serial_request_port,
1217         .config_port = qcom_geni_serial_config_port,
1218         .shutdown = qcom_geni_serial_shutdown,
1219         .type = qcom_geni_serial_get_type,
1220         .set_mctrl = qcom_geni_serial_set_mctrl,
1221         .get_mctrl = qcom_geni_serial_get_mctrl,
1222 #ifdef CONFIG_CONSOLE_POLL
1223         .poll_get_char  = qcom_geni_serial_get_char,
1224         .poll_put_char  = qcom_geni_serial_poll_put_char,
1225 #endif
1226         .pm = qcom_geni_serial_pm,
1227 };
1228
1229 static const struct uart_ops qcom_geni_uart_pops = {
1230         .tx_empty = qcom_geni_serial_tx_empty,
1231         .stop_tx = qcom_geni_serial_stop_tx,
1232         .start_tx = qcom_geni_serial_start_tx,
1233         .stop_rx = qcom_geni_serial_stop_rx,
1234         .set_termios = qcom_geni_serial_set_termios,
1235         .startup = qcom_geni_serial_startup,
1236         .request_port = qcom_geni_serial_request_port,
1237         .config_port = qcom_geni_serial_config_port,
1238         .shutdown = qcom_geni_serial_shutdown,
1239         .type = qcom_geni_serial_get_type,
1240         .set_mctrl = qcom_geni_serial_set_mctrl,
1241         .get_mctrl = qcom_geni_serial_get_mctrl,
1242         .pm = qcom_geni_serial_pm,
1243 };
1244
1245 static int qcom_geni_serial_probe(struct platform_device *pdev)
1246 {
1247         int ret = 0;
1248         int line = -1;
1249         struct qcom_geni_serial_port *port;
1250         struct uart_port *uport;
1251         struct resource *res;
1252         int irq;
1253         bool console = false;
1254         struct uart_driver *drv;
1255
1256         if (of_device_is_compatible(pdev->dev.of_node, "qcom,geni-debug-uart"))
1257                 console = true;
1258
1259         if (pdev->dev.of_node) {
1260                 if (console) {
1261                         drv = &qcom_geni_console_driver;
1262                         line = of_alias_get_id(pdev->dev.of_node, "serial");
1263                 } else {
1264                         drv = &qcom_geni_uart_driver;
1265                         line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1266                 }
1267         }
1268
1269         port = get_port_from_line(line, console);
1270         if (IS_ERR(port)) {
1271                 dev_err(&pdev->dev, "Invalid line %d\n", line);
1272                 return PTR_ERR(port);
1273         }
1274
1275         uport = &port->uport;
1276         /* Don't allow 2 drivers to access the same port */
1277         if (uport->private_data)
1278                 return -ENODEV;
1279
1280         uport->dev = &pdev->dev;
1281         port->se.dev = &pdev->dev;
1282         port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1283         port->se.clk = devm_clk_get(&pdev->dev, "se");
1284         if (IS_ERR(port->se.clk)) {
1285                 ret = PTR_ERR(port->se.clk);
1286                 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1287                 return ret;
1288         }
1289
1290         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291         if (!res)
1292                 return -EINVAL;
1293         uport->mapbase = res->start;
1294
1295         port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1296         port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1297         port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1298
1299         irq = platform_get_irq(pdev, 0);
1300         if (irq < 0) {
1301                 dev_err(&pdev->dev, "Failed to get IRQ %d\n", irq);
1302                 return irq;
1303         }
1304         uport->irq = irq;
1305
1306         uport->private_data = drv;
1307         platform_set_drvdata(pdev, port);
1308         port->handle_rx = console ? handle_rx_console : handle_rx_uart;
1309         if (!console)
1310                 device_create_file(uport->dev, &dev_attr_loopback);
1311         return uart_add_one_port(drv, uport);
1312 }
1313
1314 static int qcom_geni_serial_remove(struct platform_device *pdev)
1315 {
1316         struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1317         struct uart_driver *drv = port->uport.private_data;
1318
1319         uart_remove_one_port(drv, &port->uport);
1320         return 0;
1321 }
1322
1323 static int __maybe_unused qcom_geni_serial_sys_suspend_noirq(struct device *dev)
1324 {
1325         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1326         struct uart_port *uport = &port->uport;
1327
1328         if (uart_console(uport)) {
1329                 uart_suspend_port(uport->private_data, uport);
1330         } else {
1331                 struct uart_state *state = uport->state;
1332                 /*
1333                  * If the port is open, deny system suspend.
1334                  */
1335                 if (state->pm_state == UART_PM_STATE_ON)
1336                         return -EBUSY;
1337         }
1338
1339         return 0;
1340 }
1341
1342 static int __maybe_unused qcom_geni_serial_sys_resume_noirq(struct device *dev)
1343 {
1344         struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1345         struct uart_port *uport = &port->uport;
1346
1347         if (uart_console(uport) &&
1348                         console_suspend_enabled && uport->suspended) {
1349                 uart_resume_port(uport->private_data, uport);
1350                 /*
1351                  * uart_suspend_port() invokes port shutdown which in turn
1352                  * frees the irq. uart_resume_port invokes port startup which
1353                  * performs request_irq. The request_irq auto-enables the IRQ.
1354                  * In addition, resume_noirq implicitly enables the IRQ and
1355                  * leads to an unbalanced IRQ enable warning. Disable the IRQ
1356                  * before returning so that the warning is suppressed.
1357                  */
1358                 disable_irq(uport->irq);
1359         }
1360         return 0;
1361 }
1362
1363 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1364         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_geni_serial_sys_suspend_noirq,
1365                                         qcom_geni_serial_sys_resume_noirq)
1366 };
1367
1368 static const struct of_device_id qcom_geni_serial_match_table[] = {
1369         { .compatible = "qcom,geni-debug-uart", },
1370         { .compatible = "qcom,geni-uart", },
1371         {}
1372 };
1373 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1374
1375 static struct platform_driver qcom_geni_serial_platform_driver = {
1376         .remove = qcom_geni_serial_remove,
1377         .probe = qcom_geni_serial_probe,
1378         .driver = {
1379                 .name = "qcom_geni_serial",
1380                 .of_match_table = qcom_geni_serial_match_table,
1381                 .pm = &qcom_geni_serial_pm_ops,
1382         },
1383 };
1384
1385 static int __init qcom_geni_serial_init(void)
1386 {
1387         int ret;
1388
1389         ret = console_register(&qcom_geni_console_driver);
1390         if (ret)
1391                 return ret;
1392
1393         ret = uart_register_driver(&qcom_geni_uart_driver);
1394         if (ret) {
1395                 console_unregister(&qcom_geni_console_driver);
1396                 return ret;
1397         }
1398
1399         ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1400         if (ret) {
1401                 console_unregister(&qcom_geni_console_driver);
1402                 uart_unregister_driver(&qcom_geni_uart_driver);
1403         }
1404         return ret;
1405 }
1406 module_init(qcom_geni_serial_init);
1407
1408 static void __exit qcom_geni_serial_exit(void)
1409 {
1410         platform_driver_unregister(&qcom_geni_serial_platform_driver);
1411         console_unregister(&qcom_geni_console_driver);
1412         uart_unregister_driver(&qcom_geni_uart_driver);
1413 }
1414 module_exit(qcom_geni_serial_exit);
1415
1416 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1417 MODULE_LICENSE("GPL v2");