drivers/tty/serial/samsung.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver core for Samsung SoC onboard UARTs.
   4  *
   5  * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
   6  *      http://armlinux.simtec.co.uk/
   7 */
   8
   9 /* Hote on 2410 error handling
  10  *
  11  * The s3c2410 manual has a love/hate affair with the contents of the
  12  * UERSTAT register in the UART blocks, and keeps marking some of the
  13  * error bits as reserved. Having checked with the s3c2410x01,
  14  * it copes with BREAKs properly, so I am happy to ignore the RESERVED
  15  * feature from the latter versions of the manual.
  16  *
  17  * If it becomes aparrent that latter versions of the 2410 remove these
  18  * bits, then action will have to be taken to differentiate the versions
  19  * and change the policy on BREAK
  20  *
  21  * BJD, 04-Nov-2004
  22 */
  23
  24 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  25 #define SUPPORT_SYSRQ
  26 #endif
  27
  28 #include <linux/dmaengine.h>
  29 #include <linux/dma-mapping.h>
  30 #include <linux/slab.h>
  31 #include <linux/module.h>
  32 #include <linux/ioport.h>
  33 #include <linux/io.h>
  34 #include <linux/platform_device.h>
  35 #include <linux/init.h>
  36 #include <linux/sysrq.h>
  37 #include <linux/console.h>
  38 #include <linux/tty.h>
  39 #include <linux/tty_flip.h>
  40 #include <linux/serial_core.h>
  41 #include <linux/serial.h>
  42 #include <linux/serial_s3c.h>
  43 #include <linux/delay.h>
  44 #include <linux/clk.h>
  45 #include <linux/cpufreq.h>
  46 #include <linux/of.h>
  47
  48 #include <asm/irq.h>
  49
  50 #include "samsung.h"
  51
  52 #if     defined(CONFIG_SERIAL_SAMSUNG_DEBUG) && \
  53         !defined(MODULE)
  54
  55 extern void printascii(const char *);
  56
  57 __printf(1, 2)
  58 static void dbg(const char *fmt, ...)
  59 {
  60         va_list va;
  61         char buff[256];
  62
  63         va_start(va, fmt);
  64         vscnprintf(buff, sizeof(buff), fmt, va);
  65         va_end(va);
  66
  67         printascii(buff);
  68 }
  69
  70 #else
  71 #define dbg(fmt, ...) do { if (0) no_printk(fmt, ##__VA_ARGS__); } while (0)
  72 #endif
  73
  74 /* UART name and device definitions */
  75
  76 #define S3C24XX_SERIAL_NAME     "ttySAC"
  77 #define S3C24XX_SERIAL_MAJOR    204
  78 #define S3C24XX_SERIAL_MINOR    64
  79
  80 #define S3C24XX_TX_PIO                  1
  81 #define S3C24XX_TX_DMA                  2
  82 #define S3C24XX_RX_PIO                  1
  83 #define S3C24XX_RX_DMA                  2
  84 /* macros to change one thing to another */
  85
  86 #define tx_enabled(port) ((port)->unused[0])
  87 #define rx_enabled(port) ((port)->unused[1])
  88
  89 /* flag to ignore all characters coming in */
  90 #define RXSTAT_DUMMY_READ (0x10000000)
  91
  92 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
  93 {
  94         return container_of(port, struct s3c24xx_uart_port, port);
  95 }
  96
  97 /* translate a port to the device name */
  98
  99 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
 100 {
 101         return to_platform_device(port->dev)->name;
 102 }
 103
 104 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
 105 {
 106         return rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE;
 107 }
 108
 109 /*
 110  * s3c64xx and later SoC's include the interrupt mask and status registers in
 111  * the controller itself, unlike the s3c24xx SoC's which have these registers
 112  * in the interrupt controller. Check if the port type is s3c64xx or higher.
 113  */
 114 static int s3c24xx_serial_has_interrupt_mask(struct uart_port *port)
 115 {
 116         return to_ourport(port)->info->type == PORT_S3C6400;
 117 }
 118
 119 static void s3c24xx_serial_rx_enable(struct uart_port *port)
 120 {
 121         unsigned long flags;
 122         unsigned int ucon, ufcon;
 123         int count = 10000;
 124
 125         spin_lock_irqsave(&port->lock, flags);
 126
 127         while (--count && !s3c24xx_serial_txempty_nofifo(port))
 128                 udelay(100);
 129
 130         ufcon = rd_regl(port, S3C2410_UFCON);
 131         ufcon |= S3C2410_UFCON_RESETRX;
 132         wr_regl(port, S3C2410_UFCON, ufcon);
 133
 134         ucon = rd_regl(port, S3C2410_UCON);
 135         ucon |= S3C2410_UCON_RXIRQMODE;
 136         wr_regl(port, S3C2410_UCON, ucon);
 137
 138         rx_enabled(port) = 1;
 139         spin_unlock_irqrestore(&port->lock, flags);
 140 }
 141
 142 static void s3c24xx_serial_rx_disable(struct uart_port *port)
 143 {
 144         unsigned long flags;
 145         unsigned int ucon;
 146
 147         spin_lock_irqsave(&port->lock, flags);
 148
 149         ucon = rd_regl(port, S3C2410_UCON);
 150         ucon &= ~S3C2410_UCON_RXIRQMODE;
 151         wr_regl(port, S3C2410_UCON, ucon);
 152
 153         rx_enabled(port) = 0;
 154         spin_unlock_irqrestore(&port->lock, flags);
 155 }
 156
 157 static void s3c24xx_serial_stop_tx(struct uart_port *port)
 158 {
 159         struct s3c24xx_uart_port *ourport = to_ourport(port);
 160         struct s3c24xx_uart_dma *dma = ourport->dma;
 161         struct circ_buf *xmit = &port->state->xmit;
 162         struct dma_tx_state state;
 163         int count;
 164
 165         if (!tx_enabled(port))
 166                 return;
 167
 168         if (s3c24xx_serial_has_interrupt_mask(port))
 169                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 170         else
 171                 disable_irq_nosync(ourport->tx_irq);
 172
 173         if (dma && dma->tx_chan && ourport->tx_in_progress == S3C24XX_TX_DMA) {
 174                 dmaengine_pause(dma->tx_chan);
 175                 dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 176                 dmaengine_terminate_all(dma->tx_chan);
 177                 dma_sync_single_for_cpu(ourport->port.dev,
 178                         dma->tx_transfer_addr, dma->tx_size, DMA_TO_DEVICE);
 179                 async_tx_ack(dma->tx_desc);
 180                 count = dma->tx_bytes_requested - state.residue;
 181                 xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 182                 port->icount.tx += count;
 183         }
 184
 185         tx_enabled(port) = 0;
 186         ourport->tx_in_progress = 0;
 187
 188         if (port->flags & UPF_CONS_FLOW)
 189                 s3c24xx_serial_rx_enable(port);
 190
 191         ourport->tx_mode = 0;
 192 }
 193
 194 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport);
 195
 196 static void s3c24xx_serial_tx_dma_complete(void *args)
 197 {
 198         struct s3c24xx_uart_port *ourport = args;
 199         struct uart_port *port = &ourport->port;
 200         struct circ_buf *xmit = &port->state->xmit;
 201         struct s3c24xx_uart_dma *dma = ourport->dma;
 202         struct dma_tx_state state;
 203         unsigned long flags;
 204         int count;
 205
 206
 207         dmaengine_tx_status(dma->tx_chan, dma->tx_cookie, &state);
 208         count = dma->tx_bytes_requested - state.residue;
 209         async_tx_ack(dma->tx_desc);
 210
 211         dma_sync_single_for_cpu(ourport->port.dev, dma->tx_transfer_addr,
 212                                 dma->tx_size, DMA_TO_DEVICE);
 213
 214         spin_lock_irqsave(&port->lock, flags);
 215
 216         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 217         port->icount.tx += count;
 218         ourport->tx_in_progress = 0;
 219
 220         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 221                 uart_write_wakeup(port);
 222
 223         s3c24xx_serial_start_next_tx(ourport);
 224         spin_unlock_irqrestore(&port->lock, flags);
 225 }
 226
 227 static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
 228 {
 229         struct uart_port *port = &ourport->port;
 230         u32 ucon;
 231
 232         /* Mask Tx interrupt */
 233         if (s3c24xx_serial_has_interrupt_mask(port))
 234                 s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
 235         else
 236                 disable_irq_nosync(ourport->tx_irq);
 237
 238         /* Enable tx dma mode */
 239         ucon = rd_regl(port, S3C2410_UCON);
 240         ucon &= ~(S3C64XX_UCON_TXBURST_MASK | S3C64XX_UCON_TXMODE_MASK);
 241         ucon |= S3C64XX_UCON_TXBURST_1;
 242         ucon |= S3C64XX_UCON_TXMODE_DMA;
 243         wr_regl(port,  S3C2410_UCON, ucon);
 244
 245         ourport->tx_mode = S3C24XX_TX_DMA;
 246 }
 247
 248 static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
 249 {
 250         struct uart_port *port = &ourport->port;
 251         u32 ucon, ufcon;
 252
 253         /* Set ufcon txtrig */
 254         ourport->tx_in_progress = S3C24XX_TX_PIO;
 255         ufcon = rd_regl(port, S3C2410_UFCON);
 256         wr_regl(port,  S3C2410_UFCON, ufcon);
 257
 258         /* Enable tx pio mode */
 259         ucon = rd_regl(port, S3C2410_UCON);
 260         ucon &= ~(S3C64XX_UCON_TXMODE_MASK);
 261         ucon |= S3C64XX_UCON_TXMODE_CPU;
 262         wr_regl(port,  S3C2410_UCON, ucon);
 263
 264         /* Unmask Tx interrupt */
 265         if (s3c24xx_serial_has_interrupt_mask(port))
 266                 s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
 267                                   S3C64XX_UINTM);
 268         else
 269                 enable_irq(ourport->tx_irq);
 270
 271         ourport->tx_mode = S3C24XX_TX_PIO;
 272 }
 273
 274 static void s3c24xx_serial_start_tx_pio(struct s3c24xx_uart_port *ourport)
 275 {
 276         if (ourport->tx_mode != S3C24XX_TX_PIO)
 277                 enable_tx_pio(ourport);
 278 }
 279
 280 static int s3c24xx_serial_start_tx_dma(struct s3c24xx_uart_port *ourport,
 281                                       unsigned int count)
 282 {
 283         struct uart_port *port = &ourport->port;
 284         struct circ_buf *xmit = &port->state->xmit;
 285         struct s3c24xx_uart_dma *dma = ourport->dma;
 286
 287
 288         if (ourport->tx_mode != S3C24XX_TX_DMA)
 289                 enable_tx_dma(ourport);
 290
 291         dma->tx_size = count & ~(dma_get_cache_alignment() - 1);
 292         dma->tx_transfer_addr = dma->tx_addr + xmit->tail;
 293
 294         dma_sync_single_for_device(ourport->port.dev, dma->tx_transfer_addr,
 295                                 dma->tx_size, DMA_TO_DEVICE);
 296
 297         dma->tx_desc = dmaengine_prep_slave_single(dma->tx_chan,
 298                                 dma->tx_transfer_addr, dma->tx_size,
 299                                 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 300         if (!dma->tx_desc) {
 301                 dev_err(ourport->port.dev, "Unable to get desc for Tx\n");
 302                 return -EIO;
 303         }
 304
 305         dma->tx_desc->callback = s3c24xx_serial_tx_dma_complete;
 306         dma->tx_desc->callback_param = ourport;
 307         dma->tx_bytes_requested = dma->tx_size;
 308
 309         ourport->tx_in_progress = S3C24XX_TX_DMA;
 310         dma->tx_cookie = dmaengine_submit(dma->tx_desc);
 311         dma_async_issue_pending(dma->tx_chan);
 312         return 0;
 313 }
 314
 315 static void s3c24xx_serial_start_next_tx(struct s3c24xx_uart_port *ourport)
 316 {
 317         struct uart_port *port = &ourport->port;
 318         struct circ_buf *xmit = &port->state->xmit;
 319         unsigned long count;
 320
 321         /* Get data size up to the end of buffer */
 322         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 323
 324         if (!count) {
 325                 s3c24xx_serial_stop_tx(port);
 326                 return;
 327         }
 328
 329         if (!ourport->dma || !ourport->dma->tx_chan ||
 330             count < ourport->min_dma_size ||
 331             xmit->tail & (dma_get_cache_alignment() - 1))
 332                 s3c24xx_serial_start_tx_pio(ourport);
 333         else
 334                 s3c24xx_serial_start_tx_dma(ourport, count);
 335 }
 336
 337 static void s3c24xx_serial_start_tx(struct uart_port *port)
 338 {
 339         struct s3c24xx_uart_port *ourport = to_ourport(port);
 340         struct circ_buf *xmit = &port->state->xmit;
 341
 342         if (!tx_enabled(port)) {
 343                 if (port->flags & UPF_CONS_FLOW)
 344                         s3c24xx_serial_rx_disable(port);
 345
 346                 tx_enabled(port) = 1;
 347                 if (!ourport->dma || !ourport->dma->tx_chan)
 348                         s3c24xx_serial_start_tx_pio(ourport);
 349         }
 350
 351         if (ourport->dma && ourport->dma->tx_chan) {
 352                 if (!uart_circ_empty(xmit) && !ourport->tx_in_progress)
 353                         s3c24xx_serial_start_next_tx(ourport);
 354         }
 355 }
 356
 357 static void s3c24xx_uart_copy_rx_to_tty(struct s3c24xx_uart_port *ourport,
 358                 struct tty_port *tty, int count)
 359 {
 360         struct s3c24xx_uart_dma *dma = ourport->dma;
 361         int copied;
 362
 363         if (!count)
 364                 return;
 365
 366         dma_sync_single_for_cpu(ourport->port.dev, dma->rx_addr,
 367                                 dma->rx_size, DMA_FROM_DEVICE);
 368
 369         ourport->port.icount.rx += count;
 370         if (!tty) {
 371                 dev_err(ourport->port.dev, "No tty port\n");
 372                 return;
 373         }
 374         copied = tty_insert_flip_string(tty,
 375                         ((unsigned char *)(ourport->dma->rx_buf)), count);
 376         if (copied != count) {
 377                 WARN_ON(1);
 378                 dev_err(ourport->port.dev, "RxData copy to tty layer failed\n");
 379         }
 380 }
 381
 382 static void s3c24xx_serial_stop_rx(struct uart_port *port)
 383 {
 384         struct s3c24xx_uart_port *ourport = to_ourport(port);
 385         struct s3c24xx_uart_dma *dma = ourport->dma;
 386         struct tty_port *t = &port->state->port;
 387         struct dma_tx_state state;
 388         enum dma_status dma_status;
 389         unsigned int received;
 390
 391         if (rx_enabled(port)) {
 392                 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
 393                 if (s3c24xx_serial_has_interrupt_mask(port))
 394                         s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
 395                                         S3C64XX_UINTM);
 396                 else
 397                         disable_irq_nosync(ourport->rx_irq);
 398                 rx_enabled(port) = 0;
 399         }
 400         if (dma && dma->rx_chan) {
 401                 dmaengine_pause(dma->tx_chan);
 402                 dma_status = dmaengine_tx_status(dma->rx_chan,
 403                                 dma->rx_cookie, &state);
 404                 if (dma_status == DMA_IN_PROGRESS ||
 405                         dma_status == DMA_PAUSED) {
 406                         received = dma->rx_bytes_requested - state.residue;
 407                         dmaengine_terminate_all(dma->rx_chan);
 408                         s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 409                 }
 410         }
 411 }
 412
 413 static inline struct s3c24xx_uart_info
 414         *s3c24xx_port_to_info(struct uart_port *port)
 415 {
 416         return to_ourport(port)->info;
 417 }
 418
 419 static inline struct s3c2410_uartcfg
 420         *s3c24xx_port_to_cfg(struct uart_port *port)
 421 {
 422         struct s3c24xx_uart_port *ourport;
 423
 424         if (port->dev == NULL)
 425                 return NULL;
 426
 427         ourport = container_of(port, struct s3c24xx_uart_port, port);
 428         return ourport->cfg;
 429 }
 430
 431 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
 432                                      unsigned long ufstat)
 433 {
 434         struct s3c24xx_uart_info *info = ourport->info;
 435
 436         if (ufstat & info->rx_fifofull)
 437                 return ourport->port.fifosize;
 438
 439         return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
 440 }
 441
 442 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport);
 443 static void s3c24xx_serial_rx_dma_complete(void *args)
 444 {
 445         struct s3c24xx_uart_port *ourport = args;
 446         struct uart_port *port = &ourport->port;
 447
 448         struct s3c24xx_uart_dma *dma = ourport->dma;
 449         struct tty_port *t = &port->state->port;
 450         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 451
 452         struct dma_tx_state state;
 453         unsigned long flags;
 454         int received;
 455
 456         dmaengine_tx_status(dma->rx_chan,  dma->rx_cookie, &state);
 457         received  = dma->rx_bytes_requested - state.residue;
 458         async_tx_ack(dma->rx_desc);
 459
 460         spin_lock_irqsave(&port->lock, flags);
 461
 462         if (received)
 463                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 464
 465         if (tty) {
 466                 tty_flip_buffer_push(t);
 467                 tty_kref_put(tty);
 468         }
 469
 470         s3c64xx_start_rx_dma(ourport);
 471
 472         spin_unlock_irqrestore(&port->lock, flags);
 473 }
 474
 475 static void s3c64xx_start_rx_dma(struct s3c24xx_uart_port *ourport)
 476 {
 477         struct s3c24xx_uart_dma *dma = ourport->dma;
 478
 479         dma_sync_single_for_device(ourport->port.dev, dma->rx_addr,
 480                                 dma->rx_size, DMA_FROM_DEVICE);
 481
 482         dma->rx_desc = dmaengine_prep_slave_single(dma->rx_chan,
 483                                 dma->rx_addr, dma->rx_size, DMA_DEV_TO_MEM,
 484                                 DMA_PREP_INTERRUPT);
 485         if (!dma->rx_desc) {
 486                 dev_err(ourport->port.dev, "Unable to get desc for Rx\n");
 487                 return;
 488         }
 489
 490         dma->rx_desc->callback = s3c24xx_serial_rx_dma_complete;
 491         dma->rx_desc->callback_param = ourport;
 492         dma->rx_bytes_requested = dma->rx_size;
 493
 494         dma->rx_cookie = dmaengine_submit(dma->rx_desc);
 495         dma_async_issue_pending(dma->rx_chan);
 496 }
 497
 498 /* ? - where has parity gone?? */
 499 #define S3C2410_UERSTAT_PARITY (0x1000)
 500
 501 static void enable_rx_dma(struct s3c24xx_uart_port *ourport)
 502 {
 503         struct uart_port *port = &ourport->port;
 504         unsigned int ucon;
 505
 506         /* set Rx mode to DMA mode */
 507         ucon = rd_regl(port, S3C2410_UCON);
 508         ucon &= ~(S3C64XX_UCON_RXBURST_MASK |
 509                         S3C64XX_UCON_TIMEOUT_MASK |
 510                         S3C64XX_UCON_EMPTYINT_EN |
 511                         S3C64XX_UCON_DMASUS_EN |
 512                         S3C64XX_UCON_TIMEOUT_EN |
 513                         S3C64XX_UCON_RXMODE_MASK);
 514         ucon |= S3C64XX_UCON_RXBURST_1 |
 515                         0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 516                         S3C64XX_UCON_EMPTYINT_EN |
 517                         S3C64XX_UCON_TIMEOUT_EN |
 518                         S3C64XX_UCON_RXMODE_DMA;
 519         wr_regl(port, S3C2410_UCON, ucon);
 520
 521         ourport->rx_mode = S3C24XX_RX_DMA;
 522 }
 523
 524 static void enable_rx_pio(struct s3c24xx_uart_port *ourport)
 525 {
 526         struct uart_port *port = &ourport->port;
 527         unsigned int ucon;
 528
 529         /* set Rx mode to DMA mode */
 530         ucon = rd_regl(port, S3C2410_UCON);
 531         ucon &= ~(S3C64XX_UCON_TIMEOUT_MASK |
 532                         S3C64XX_UCON_EMPTYINT_EN |
 533                         S3C64XX_UCON_DMASUS_EN |
 534                         S3C64XX_UCON_TIMEOUT_EN |
 535                         S3C64XX_UCON_RXMODE_MASK);
 536         ucon |= 0xf << S3C64XX_UCON_TIMEOUT_SHIFT |
 537                         S3C64XX_UCON_TIMEOUT_EN |
 538                         S3C64XX_UCON_RXMODE_CPU;
 539         wr_regl(port, S3C2410_UCON, ucon);
 540
 541         ourport->rx_mode = S3C24XX_RX_PIO;
 542 }
 543
 544 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport);
 545
 546 static irqreturn_t s3c24xx_serial_rx_chars_dma(void *dev_id)
 547 {
 548         unsigned int utrstat, ufstat, received;
 549         struct s3c24xx_uart_port *ourport = dev_id;
 550         struct uart_port *port = &ourport->port;
 551         struct s3c24xx_uart_dma *dma = ourport->dma;
 552         struct tty_struct *tty = tty_port_tty_get(&ourport->port.state->port);
 553         struct tty_port *t = &port->state->port;
 554         unsigned long flags;
 555         struct dma_tx_state state;
 556
 557         utrstat = rd_regl(port, S3C2410_UTRSTAT);
 558         ufstat = rd_regl(port, S3C2410_UFSTAT);
 559
 560         spin_lock_irqsave(&port->lock, flags);
 561
 562         if (!(utrstat & S3C2410_UTRSTAT_TIMEOUT)) {
 563                 s3c64xx_start_rx_dma(ourport);
 564                 if (ourport->rx_mode == S3C24XX_RX_PIO)
 565                         enable_rx_dma(ourport);
 566                 goto finish;
 567         }
 568
 569         if (ourport->rx_mode == S3C24XX_RX_DMA) {
 570                 dmaengine_pause(dma->rx_chan);
 571                 dmaengine_tx_status(dma->rx_chan, dma->rx_cookie, &state);
 572                 dmaengine_terminate_all(dma->rx_chan);
 573                 received = dma->rx_bytes_requested - state.residue;
 574                 s3c24xx_uart_copy_rx_to_tty(ourport, t, received);
 575
 576                 enable_rx_pio(ourport);
 577         }
 578
 579         s3c24xx_serial_rx_drain_fifo(ourport);
 580
 581         if (tty) {
 582                 tty_flip_buffer_push(t);
 583                 tty_kref_put(tty);
 584         }
 585
 586         wr_regl(port, S3C2410_UTRSTAT, S3C2410_UTRSTAT_TIMEOUT);
 587
 588 finish:
 589         spin_unlock_irqrestore(&port->lock, flags);
 590
 591         return IRQ_HANDLED;
 592 }
 593
 594 static void s3c24xx_serial_rx_drain_fifo(struct s3c24xx_uart_port *ourport)
 595 {
 596         struct uart_port *port = &ourport->port;
 597         unsigned int ufcon, ch, flag, ufstat, uerstat;
 598         unsigned int fifocnt = 0;
 599         int max_count = port->fifosize;
 600
 601         while (max_count-- > 0) {
 602                 /*
 603                  * Receive all characters known to be in FIFO
 604                  * before reading FIFO level again
 605                  */
 606                 if (fifocnt == 0) {
 607                         ufstat = rd_regl(port, S3C2410_UFSTAT);
 608                         fifocnt = s3c24xx_serial_rx_fifocnt(ourport, ufstat);
 609                         if (fifocnt == 0)
 610                                 break;
 611                 }
 612                 fifocnt--;
 613
 614                 uerstat = rd_regl(port, S3C2410_UERSTAT);
 615                 ch = rd_regb(port, S3C2410_URXH);
 616
 617                 if (port->flags & UPF_CONS_FLOW) {
 618                         int txe = s3c24xx_serial_txempty_nofifo(port);
 619
 620                         if (rx_enabled(port)) {
 621                                 if (!txe) {
 622                                         rx_enabled(port) = 0;
 623                                         continue;
 624                                 }
 625                         } else {
 626                                 if (txe) {
 627                                         ufcon = rd_regl(port, S3C2410_UFCON);
 628                                         ufcon |= S3C2410_UFCON_RESETRX;
 629                                         wr_regl(port, S3C2410_UFCON, ufcon);
 630                                         rx_enabled(port) = 1;
 631                                         return;
 632                                 }
 633                                 continue;
 634                         }
 635                 }
 636
 637                 /* insert the character into the buffer */
 638
 639                 flag = TTY_NORMAL;
 640                 port->icount.rx++;
 641
 642                 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
 643                         dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
 644                             ch, uerstat);
 645
 646                         /* check for break */
 647                         if (uerstat & S3C2410_UERSTAT_BREAK) {
 648                                 dbg("break!\n");
 649                                 port->icount.brk++;
 650                                 if (uart_handle_break(port))
 651                                         continue; /* Ignore character */
 652                         }
 653
 654                         if (uerstat & S3C2410_UERSTAT_FRAME)
 655                                 port->icount.frame++;
 656                         if (uerstat & S3C2410_UERSTAT_OVERRUN)
 657                                 port->icount.overrun++;
 658
 659                         uerstat &= port->read_status_mask;
 660
 661                         if (uerstat & S3C2410_UERSTAT_BREAK)
 662                                 flag = TTY_BREAK;
 663                         else if (uerstat & S3C2410_UERSTAT_PARITY)
 664                                 flag = TTY_PARITY;
 665                         else if (uerstat & (S3C2410_UERSTAT_FRAME |
 666                                             S3C2410_UERSTAT_OVERRUN))
 667                                 flag = TTY_FRAME;
 668                 }
 669
 670                 if (uart_handle_sysrq_char(port, ch))
 671                         continue; /* Ignore character */
 672
 673                 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN,
 674                                  ch, flag);
 675         }
 676
 677         tty_flip_buffer_push(&port->state->port);
 678 }
 679
 680 static irqreturn_t s3c24xx_serial_rx_chars_pio(void *dev_id)
 681 {
 682         struct s3c24xx_uart_port *ourport = dev_id;
 683         struct uart_port *port = &ourport->port;
 684         unsigned long flags;
 685
 686         spin_lock_irqsave(&port->lock, flags);
 687         s3c24xx_serial_rx_drain_fifo(ourport);
 688         spin_unlock_irqrestore(&port->lock, flags);
 689
 690         return IRQ_HANDLED;
 691 }
 692
 693
 694 static irqreturn_t s3c24xx_serial_rx_chars(int irq, void *dev_id)
 695 {
 696         struct s3c24xx_uart_port *ourport = dev_id;
 697
 698         if (ourport->dma && ourport->dma->rx_chan)
 699                 return s3c24xx_serial_rx_chars_dma(dev_id);
 700         return s3c24xx_serial_rx_chars_pio(dev_id);
 701 }
 702
 703 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
 704 {
 705         struct s3c24xx_uart_port *ourport = id;
 706         struct uart_port *port = &ourport->port;
 707         struct circ_buf *xmit = &port->state->xmit;
 708         unsigned long flags;
 709         int count, dma_count = 0;
 710
 711         spin_lock_irqsave(&port->lock, flags);
 712
 713         count = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
 714
 715         if (ourport->dma && ourport->dma->tx_chan &&
 716             count >= ourport->min_dma_size) {
 717                 int align = dma_get_cache_alignment() -
 718                         (xmit->tail & (dma_get_cache_alignment() - 1));
 719                 if (count-align >= ourport->min_dma_size) {
 720                         dma_count = count-align;
 721                         count = align;
 722                 }
 723         }
 724
 725         if (port->x_char) {
 726                 wr_regb(port, S3C2410_UTXH, port->x_char);
 727                 port->icount.tx++;
 728                 port->x_char = 0;
 729                 goto out;
 730         }
 731
 732         /* if there isn't anything more to transmit, or the uart is now
 733          * stopped, disable the uart and exit
 734         */
 735
 736         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 737                 s3c24xx_serial_stop_tx(port);
 738                 goto out;
 739         }
 740
 741         /* try and drain the buffer... */
 742
 743         if (count > port->fifosize) {
 744                 count = port->fifosize;
 745                 dma_count = 0;
 746         }
 747
 748         while (!uart_circ_empty(xmit) && count > 0) {
 749                 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
 750                         break;
 751
 752                 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
 753                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 754                 port->icount.tx++;
 755                 count--;
 756         }
 757
 758         if (!count && dma_count) {
 759                 s3c24xx_serial_start_tx_dma(ourport, dma_count);
 760                 goto out;
 761         }
 762
 763         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 764                 uart_write_wakeup(port);
 765
 766         if (uart_circ_empty(xmit))
 767                 s3c24xx_serial_stop_tx(port);
 768
 769 out:
 770         spin_unlock_irqrestore(&port->lock, flags);
 771         return IRQ_HANDLED;
 772 }
 773
 774 /* interrupt handler for s3c64xx and later SoC's.*/
 775 static irqreturn_t s3c64xx_serial_handle_irq(int irq, void *id)
 776 {
 777         struct s3c24xx_uart_port *ourport = id;
 778         struct uart_port *port = &ourport->port;
 779         unsigned int pend = rd_regl(port, S3C64XX_UINTP);
 780         irqreturn_t ret = IRQ_HANDLED;
 781
 782         if (pend & S3C64XX_UINTM_RXD_MSK) {
 783                 ret = s3c24xx_serial_rx_chars(irq, id);
 784                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_RXD_MSK);
 785         }
 786         if (pend & S3C64XX_UINTM_TXD_MSK) {
 787                 ret = s3c24xx_serial_tx_chars(irq, id);
 788                 wr_regl(port, S3C64XX_UINTP, S3C64XX_UINTM_TXD_MSK);
 789         }
 790         return ret;
 791 }
 792
 793 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
 794 {
 795         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
 796         unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
 797         unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
 798
 799         if (ufcon & S3C2410_UFCON_FIFOMODE) {
 800                 if ((ufstat & info->tx_fifomask) != 0 ||
 801                     (ufstat & info->tx_fifofull))
 802                         return 0;
 803
 804                 return 1;
 805         }
 806
 807         return s3c24xx_serial_txempty_nofifo(port);
 808 }
 809
 810 /* no modem control lines */
 811 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
 812 {
 813         unsigned int umstat = rd_regb(port, S3C2410_UMSTAT);
 814
 815         if (umstat & S3C2410_UMSTAT_CTS)
 816                 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 817         else
 818                 return TIOCM_CAR | TIOCM_DSR;
 819 }
 820
 821 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
 822 {
 823         unsigned int umcon = rd_regl(port, S3C2410_UMCON);
 824
 825         if (mctrl & TIOCM_RTS)
 826                 umcon |= S3C2410_UMCOM_RTS_LOW;
 827         else
 828                 umcon &= ~S3C2410_UMCOM_RTS_LOW;
 829
 830         wr_regl(port, S3C2410_UMCON, umcon);
 831 }
 832
 833 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
 834 {
 835         unsigned long flags;
 836         unsigned int ucon;
 837
 838         spin_lock_irqsave(&port->lock, flags);
 839
 840         ucon = rd_regl(port, S3C2410_UCON);
 841
 842         if (break_state)
 843                 ucon |= S3C2410_UCON_SBREAK;
 844         else
 845                 ucon &= ~S3C2410_UCON_SBREAK;
 846
 847         wr_regl(port, S3C2410_UCON, ucon);
 848
 849         spin_unlock_irqrestore(&port->lock, flags);
 850 }
 851
 852 static int s3c24xx_serial_request_dma(struct s3c24xx_uart_port *p)
 853 {
 854         struct s3c24xx_uart_dma *dma = p->dma;
 855         struct dma_slave_caps dma_caps;
 856         const char *reason = NULL;
 857         int ret;
 858
 859         /* Default slave configuration parameters */
 860         dma->rx_conf.direction          = DMA_DEV_TO_MEM;
 861         dma->rx_conf.src_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 862         dma->rx_conf.src_addr           = p->port.mapbase + S3C2410_URXH;
 863         dma->rx_conf.src_maxburst       = 1;
 864
 865         dma->tx_conf.direction          = DMA_MEM_TO_DEV;
 866         dma->tx_conf.dst_addr_width     = DMA_SLAVE_BUSWIDTH_1_BYTE;
 867         dma->tx_conf.dst_addr           = p->port.mapbase + S3C2410_UTXH;
 868         dma->tx_conf.dst_maxburst       = 1;
 869
 870         dma->rx_chan = dma_request_chan(p->port.dev, "rx");
 871
 872         if (IS_ERR(dma->rx_chan)) {
 873                 reason = "DMA RX channel request failed";
 874                 ret = PTR_ERR(dma->rx_chan);
 875                 goto err_warn;
 876         }
 877
 878         ret = dma_get_slave_caps(dma->rx_chan, &dma_caps);
 879         if (ret < 0 ||
 880             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
 881                 reason = "insufficient DMA RX engine capabilities";
 882                 ret = -EOPNOTSUPP;
 883                 goto err_release_rx;
 884         }
 885
 886         dmaengine_slave_config(dma->rx_chan, &dma->rx_conf);
 887
 888         dma->tx_chan = dma_request_chan(p->port.dev, "tx");
 889         if (IS_ERR(dma->tx_chan)) {
 890                 reason = "DMA TX channel request failed";
 891                 ret = PTR_ERR(dma->tx_chan);
 892                 goto err_release_rx;
 893         }
 894
 895         ret = dma_get_slave_caps(dma->tx_chan, &dma_caps);
 896         if (ret < 0 ||
 897             dma_caps.residue_granularity < DMA_RESIDUE_GRANULARITY_BURST) {
 898                 reason = "insufficient DMA TX engine capabilities";
 899                 ret = -EOPNOTSUPP;
 900                 goto err_release_tx;
 901         }
 902
 903         dmaengine_slave_config(dma->tx_chan, &dma->tx_conf);
 904
 905         /* RX buffer */
 906         dma->rx_size = PAGE_SIZE;
 907
 908         dma->rx_buf = kmalloc(dma->rx_size, GFP_KERNEL);
 909         if (!dma->rx_buf) {
 910                 ret = -ENOMEM;
 911                 goto err_release_tx;
 912         }
 913
 914         dma->rx_addr = dma_map_single(p->port.dev, dma->rx_buf,
 915                                 dma->rx_size, DMA_FROM_DEVICE);
 916         if (dma_mapping_error(p->port.dev, dma->rx_addr)) {
 917                 reason = "DMA mapping error for RX buffer";
 918                 ret = -EIO;
 919                 goto err_free_rx;
 920         }
 921
 922         /* TX buffer */
 923         dma->tx_addr = dma_map_single(p->port.dev, p->port.state->xmit.buf,
 924                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 925         if (dma_mapping_error(p->port.dev, dma->tx_addr)) {
 926                 reason = "DMA mapping error for TX buffer";
 927                 ret = -EIO;
 928                 goto err_unmap_rx;
 929         }
 930
 931         return 0;
 932
 933 err_unmap_rx:
 934         dma_unmap_single(p->port.dev, dma->rx_addr, dma->rx_size,
 935                          DMA_FROM_DEVICE);
 936 err_free_rx:
 937         kfree(dma->rx_buf);
 938 err_release_tx:
 939         dma_release_channel(dma->tx_chan);
 940 err_release_rx:
 941         dma_release_channel(dma->rx_chan);
 942 err_warn:
 943         if (reason)
 944                 dev_warn(p->port.dev, "%s, DMA will not be used\n", reason);
 945         return ret;
 946 }
 947
 948 static void s3c24xx_serial_release_dma(struct s3c24xx_uart_port *p)
 949 {
 950         struct s3c24xx_uart_dma *dma = p->dma;
 951
 952         if (dma->rx_chan) {
 953                 dmaengine_terminate_all(dma->rx_chan);
 954                 dma_unmap_single(p->port.dev, dma->rx_addr,
 955                                 dma->rx_size, DMA_FROM_DEVICE);
 956                 kfree(dma->rx_buf);
 957                 dma_release_channel(dma->rx_chan);
 958                 dma->rx_chan = NULL;
 959         }
 960
 961         if (dma->tx_chan) {
 962                 dmaengine_terminate_all(dma->tx_chan);
 963                 dma_unmap_single(p->port.dev, dma->tx_addr,
 964                                 UART_XMIT_SIZE, DMA_TO_DEVICE);
 965                 dma_release_channel(dma->tx_chan);
 966                 dma->tx_chan = NULL;
 967         }
 968 }
 969
 970 static void s3c24xx_serial_shutdown(struct uart_port *port)
 971 {
 972         struct s3c24xx_uart_port *ourport = to_ourport(port);
 973
 974         if (ourport->tx_claimed) {
 975                 if (!s3c24xx_serial_has_interrupt_mask(port))
 976                         free_irq(ourport->tx_irq, ourport);
 977                 tx_enabled(port) = 0;
 978                 ourport->tx_claimed = 0;
 979                 ourport->tx_mode = 0;
 980         }
 981
 982         if (ourport->rx_claimed) {
 983                 if (!s3c24xx_serial_has_interrupt_mask(port))
 984                         free_irq(ourport->rx_irq, ourport);
 985                 ourport->rx_claimed = 0;
 986                 rx_enabled(port) = 0;
 987         }
 988
 989         /* Clear pending interrupts and mask all interrupts */
 990         if (s3c24xx_serial_has_interrupt_mask(port)) {
 991                 free_irq(port->irq, ourport);
 992
 993                 wr_regl(port, S3C64XX_UINTP, 0xf);
 994                 wr_regl(port, S3C64XX_UINTM, 0xf);
 995         }
 996
 997         if (ourport->dma)
 998                 s3c24xx_serial_release_dma(ourport);
 999
1000         ourport->tx_in_progress = 0;
1001 }
1002
1003 static int s3c24xx_serial_startup(struct uart_port *port)
1004 {
1005         struct s3c24xx_uart_port *ourport = to_ourport(port);
1006         int ret;
1007
1008         dbg("s3c24xx_serial_startup: port=%p (%08llx,%p)\n",
1009             port, (unsigned long long)port->mapbase, port->membase);
1010
1011         rx_enabled(port) = 1;
1012
1013         ret = request_irq(ourport->rx_irq, s3c24xx_serial_rx_chars, 0,
1014                           s3c24xx_serial_portname(port), ourport);
1015
1016         if (ret != 0) {
1017                 dev_err(port->dev, "cannot get irq %d\n", ourport->rx_irq);
1018                 return ret;
1019         }
1020
1021         ourport->rx_claimed = 1;
1022
1023         dbg("requesting tx irq...\n");
1024
1025         tx_enabled(port) = 1;
1026
1027         ret = request_irq(ourport->tx_irq, s3c24xx_serial_tx_chars, 0,
1028                           s3c24xx_serial_portname(port), ourport);
1029
1030         if (ret) {
1031                 dev_err(port->dev, "cannot get irq %d\n", ourport->tx_irq);
1032                 goto err;
1033         }
1034
1035         ourport->tx_claimed = 1;
1036
1037         dbg("s3c24xx_serial_startup ok\n");
1038
1039         /* the port reset code should have done the correct
1040          * register setup for the port controls */
1041
1042         return ret;
1043
1044 err:
1045         s3c24xx_serial_shutdown(port);
1046         return ret;
1047 }
1048
1049 static int s3c64xx_serial_startup(struct uart_port *port)
1050 {
1051         struct s3c24xx_uart_port *ourport = to_ourport(port);
1052         unsigned long flags;
1053         unsigned int ufcon;
1054         int ret;
1055
1056         dbg("s3c64xx_serial_startup: port=%p (%08llx,%p)\n",
1057             port, (unsigned long long)port->mapbase, port->membase);
1058
1059         wr_regl(port, S3C64XX_UINTM, 0xf);
1060         if (ourport->dma) {
1061                 ret = s3c24xx_serial_request_dma(ourport);
1062                 if (ret < 0) {
1063                         devm_kfree(port->dev, ourport->dma);
1064                         ourport->dma = NULL;
1065                 }
1066         }
1067
1068         ret = request_irq(port->irq, s3c64xx_serial_handle_irq, IRQF_SHARED,
1069                           s3c24xx_serial_portname(port), ourport);
1070         if (ret) {
1071                 dev_err(port->dev, "cannot get irq %d\n", port->irq);
1072                 return ret;
1073         }
1074
1075         /* For compatibility with s3c24xx Soc's */
1076         rx_enabled(port) = 1;
1077         ourport->rx_claimed = 1;
1078         tx_enabled(port) = 0;
1079         ourport->tx_claimed = 1;
1080
1081         spin_lock_irqsave(&port->lock, flags);
1082
1083         ufcon = rd_regl(port, S3C2410_UFCON);
1084         ufcon |= S3C2410_UFCON_RESETRX | S5PV210_UFCON_RXTRIG8;
1085         if (!uart_console(port))
1086                 ufcon |= S3C2410_UFCON_RESETTX;
1087         wr_regl(port, S3C2410_UFCON, ufcon);
1088
1089         enable_rx_pio(ourport);
1090
1091         spin_unlock_irqrestore(&port->lock, flags);
1092
1093         /* Enable Rx Interrupt */
1094         s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
1095
1096         dbg("s3c64xx_serial_startup ok\n");
1097         return ret;
1098 }
1099
1100 /* power power management control */
1101
1102 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
1103                               unsigned int old)
1104 {
1105         struct s3c24xx_uart_port *ourport = to_ourport(port);
1106         int timeout = 10000;
1107
1108         ourport->pm_level = level;
1109
1110         switch (level) {
1111         case 3:
1112                 while (--timeout && !s3c24xx_serial_txempty_nofifo(port))
1113                         udelay(100);
1114
1115                 if (!IS_ERR(ourport->baudclk))
1116                         clk_disable_unprepare(ourport->baudclk);
1117
1118                 clk_disable_unprepare(ourport->clk);
1119                 break;
1120
1121         case 0:
1122                 clk_prepare_enable(ourport->clk);
1123
1124                 if (!IS_ERR(ourport->baudclk))
1125                         clk_prepare_enable(ourport->baudclk);
1126
1127                 break;
1128         default:
1129                 dev_err(port->dev, "s3c24xx_serial: unknown pm %d\n", level);
1130         }
1131 }
1132
1133 /* baud rate calculation
1134  *
1135  * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
1136  * of different sources, including the peripheral clock ("pclk") and an
1137  * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
1138  * with a programmable extra divisor.
1139  *
1140  * The following code goes through the clock sources, and calculates the
1141  * baud clocks (and the resultant actual baud rates) and then tries to
1142  * pick the closest one and select that.
1143  *
1144 */
1145
1146 #define MAX_CLK_NAME_LENGTH 15
1147
1148 static inline int s3c24xx_serial_getsource(struct uart_port *port)
1149 {
1150         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1151         unsigned int ucon;
1152
1153         if (info->num_clks == 1)
1154                 return 0;
1155
1156         ucon = rd_regl(port, S3C2410_UCON);
1157         ucon &= info->clksel_mask;
1158         return ucon >> info->clksel_shift;
1159 }
1160
1161 static void s3c24xx_serial_setsource(struct uart_port *port,
1162                         unsigned int clk_sel)
1163 {
1164         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1165         unsigned int ucon;
1166
1167         if (info->num_clks == 1)
1168                 return;
1169
1170         ucon = rd_regl(port, S3C2410_UCON);
1171         if ((ucon & info->clksel_mask) >> info->clksel_shift == clk_sel)
1172                 return;
1173
1174         ucon &= ~info->clksel_mask;
1175         ucon |= clk_sel << info->clksel_shift;
1176         wr_regl(port, S3C2410_UCON, ucon);
1177 }
1178
1179 static unsigned int s3c24xx_serial_getclk(struct s3c24xx_uart_port *ourport,
1180                         unsigned int req_baud, struct clk **best_clk,
1181                         unsigned int *clk_num)
1182 {
1183         struct s3c24xx_uart_info *info = ourport->info;
1184         struct clk *clk;
1185         unsigned long rate;
1186         unsigned int cnt, baud, quot, best_quot = 0;
1187         char clkname[MAX_CLK_NAME_LENGTH];
1188         int calc_deviation, deviation = (1 << 30) - 1;
1189
1190         for (cnt = 0; cnt < info->num_clks; cnt++) {
1191                 /* Keep selected clock if provided */
1192                 if (ourport->cfg->clk_sel &&
1193                         !(ourport->cfg->clk_sel & (1 << cnt)))
1194                         continue;
1195
1196                 sprintf(clkname, "clk_uart_baud%d", cnt);
1197                 clk = clk_get(ourport->port.dev, clkname);
1198                 if (IS_ERR(clk))
1199                         continue;
1200
1201                 rate = clk_get_rate(clk);
1202                 if (!rate)
1203                         continue;
1204
1205                 if (ourport->info->has_divslot) {
1206                         unsigned long div = rate / req_baud;
1207
1208                         /* The UDIVSLOT register on the newer UARTs allows us to
1209                          * get a divisor adjustment of 1/16th on the baud clock.
1210                          *
1211                          * We don't keep the UDIVSLOT value (the 16ths we
1212                          * calculated by not multiplying the baud by 16) as it
1213                          * is easy enough to recalculate.
1214                          */
1215
1216                         quot = div / 16;
1217                         baud = rate / div;
1218                 } else {
1219                         quot = (rate + (8 * req_baud)) / (16 * req_baud);
1220                         baud = rate / (quot * 16);
1221                 }
1222                 quot--;
1223
1224                 calc_deviation = req_baud - baud;
1225                 if (calc_deviation < 0)
1226                         calc_deviation = -calc_deviation;
1227
1228                 if (calc_deviation < deviation) {
1229                         *best_clk = clk;
1230                         best_quot = quot;
1231                         *clk_num = cnt;
1232                         deviation = calc_deviation;
1233                 }
1234         }
1235
1236         return best_quot;
1237 }
1238
1239 /* udivslot_table[]
1240  *
1241  * This table takes the fractional value of the baud divisor and gives
1242  * the recommended setting for the UDIVSLOT register.
1243  */
1244 static u16 udivslot_table[16] = {
1245         [0] = 0x0000,
1246         [1] = 0x0080,
1247         [2] = 0x0808,
1248         [3] = 0x0888,
1249         [4] = 0x2222,
1250         [5] = 0x4924,
1251         [6] = 0x4A52,
1252         [7] = 0x54AA,
1253         [8] = 0x5555,
1254         [9] = 0xD555,
1255         [10] = 0xD5D5,
1256         [11] = 0xDDD5,
1257         [12] = 0xDDDD,
1258         [13] = 0xDFDD,
1259         [14] = 0xDFDF,
1260         [15] = 0xFFDF,
1261 };
1262
1263 static void s3c24xx_serial_set_termios(struct uart_port *port,
1264                                        struct ktermios *termios,
1265                                        struct ktermios *old)
1266 {
1267         struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
1268         struct s3c24xx_uart_port *ourport = to_ourport(port);
1269         struct clk *clk = ERR_PTR(-EINVAL);
1270         unsigned long flags;
1271         unsigned int baud, quot, clk_sel = 0;
1272         unsigned int ulcon;
1273         unsigned int umcon;
1274         unsigned int udivslot = 0;
1275
1276         /*
1277          * We don't support modem control lines.
1278          */
1279         termios->c_cflag &= ~(HUPCL | CMSPAR);
1280         termios->c_cflag |= CLOCAL;
1281
1282         /*
1283          * Ask the core to calculate the divisor for us.
1284          */
1285
1286         baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
1287         quot = s3c24xx_serial_getclk(ourport, baud, &clk, &clk_sel);
1288         if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
1289                 quot = port->custom_divisor;
1290         if (IS_ERR(clk))
1291                 return;
1292
1293         /* check to see if we need  to change clock source */
1294
1295         if (ourport->baudclk != clk) {
1296                 clk_prepare_enable(clk);
1297
1298                 s3c24xx_serial_setsource(port, clk_sel);
1299
1300                 if (!IS_ERR(ourport->baudclk)) {
1301                         clk_disable_unprepare(ourport->baudclk);
1302                         ourport->baudclk = ERR_PTR(-EINVAL);
1303                 }
1304
1305                 ourport->baudclk = clk;
1306                 ourport->baudclk_rate = clk ? clk_get_rate(clk) : 0;
1307         }
1308
1309         if (ourport->info->has_divslot) {
1310                 unsigned int div = ourport->baudclk_rate / baud;
1311
1312                 if (cfg->has_fracval) {
1313                         udivslot = (div & 15);
1314                         dbg("fracval = %04x\n", udivslot);
1315                 } else {
1316                         udivslot = udivslot_table[div & 15];
1317                         dbg("udivslot = %04x (div %d)\n", udivslot, div & 15);
1318                 }
1319         }
1320
1321         switch (termios->c_cflag & CSIZE) {
1322         case CS5:
1323                 dbg("config: 5bits/char\n");
1324                 ulcon = S3C2410_LCON_CS5;
1325                 break;
1326         case CS6:
1327                 dbg("config: 6bits/char\n");
1328                 ulcon = S3C2410_LCON_CS6;
1329                 break;
1330         case CS7:
1331                 dbg("config: 7bits/char\n");
1332                 ulcon = S3C2410_LCON_CS7;
1333                 break;
1334         case CS8:
1335         default:
1336                 dbg("config: 8bits/char\n");
1337                 ulcon = S3C2410_LCON_CS8;
1338                 break;
1339         }
1340
1341         /* preserve original lcon IR settings */
1342         ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
1343
1344         if (termios->c_cflag & CSTOPB)
1345                 ulcon |= S3C2410_LCON_STOPB;
1346
1347         if (termios->c_cflag & PARENB) {
1348                 if (termios->c_cflag & PARODD)
1349                         ulcon |= S3C2410_LCON_PODD;
1350                 else
1351                         ulcon |= S3C2410_LCON_PEVEN;
1352         } else {
1353                 ulcon |= S3C2410_LCON_PNONE;
1354         }
1355
1356         spin_lock_irqsave(&port->lock, flags);
1357
1358         dbg("setting ulcon to %08x, brddiv to %d, udivslot %08x\n",
1359             ulcon, quot, udivslot);
1360
1361         wr_regl(port, S3C2410_ULCON, ulcon);
1362         wr_regl(port, S3C2410_UBRDIV, quot);
1363
1364         port->status &= ~UPSTAT_AUTOCTS;
1365
1366         umcon = rd_regl(port, S3C2410_UMCON);
1367         if (termios->c_cflag & CRTSCTS) {
1368                 umcon |= S3C2410_UMCOM_AFC;
1369                 /* Disable RTS when RX FIFO contains 63 bytes */
1370                 umcon &= ~S3C2412_UMCON_AFC_8;
1371                 port->status = UPSTAT_AUTOCTS;
1372         } else {
1373                 umcon &= ~S3C2410_UMCOM_AFC;
1374         }
1375         wr_regl(port, S3C2410_UMCON, umcon);
1376
1377         if (ourport->info->has_divslot)
1378                 wr_regl(port, S3C2443_DIVSLOT, udivslot);
1379
1380         dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
1381             rd_regl(port, S3C2410_ULCON),
1382             rd_regl(port, S3C2410_UCON),
1383             rd_regl(port, S3C2410_UFCON));
1384
1385         /*
1386          * Update the per-port timeout.
1387          */
1388         uart_update_timeout(port, termios->c_cflag, baud);
1389
1390         /*
1391          * Which character status flags are we interested in?
1392          */
1393         port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
1394         if (termios->c_iflag & INPCK)
1395                 port->read_status_mask |= S3C2410_UERSTAT_FRAME |
1396                         S3C2410_UERSTAT_PARITY;
1397         /*
1398          * Which character status flags should we ignore?
1399          */
1400         port->ignore_status_mask = 0;
1401         if (termios->c_iflag & IGNPAR)
1402                 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
1403         if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
1404                 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
1405
1406         /*
1407          * Ignore all characters if CREAD is not set.
1408          */
1409         if ((termios->c_cflag & CREAD) == 0)
1410                 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
1411
1412         spin_unlock_irqrestore(&port->lock, flags);
1413 }
1414
1415 static const char *s3c24xx_serial_type(struct uart_port *port)
1416 {
1417         switch (port->type) {
1418         case PORT_S3C2410:
1419                 return "S3C2410";
1420         case PORT_S3C2440:
1421                 return "S3C2440";
1422         case PORT_S3C2412:
1423                 return "S3C2412";
1424         case PORT_S3C6400:
1425                 return "S3C6400/10";
1426         default:
1427                 return NULL;
1428         }
1429 }
1430
1431 #define MAP_SIZE (0x100)
1432
1433 static void s3c24xx_serial_release_port(struct uart_port *port)
1434 {
1435         release_mem_region(port->mapbase, MAP_SIZE);
1436 }
1437
1438 static int s3c24xx_serial_request_port(struct uart_port *port)
1439 {
1440         const char *name = s3c24xx_serial_portname(port);
1441         return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
1442 }
1443
1444 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
1445 {
1446         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1447
1448         if (flags & UART_CONFIG_TYPE &&
1449             s3c24xx_serial_request_port(port) == 0)
1450                 port->type = info->type;
1451 }
1452
1453 /*
1454  * verify the new serial_struct (for TIOCSSERIAL).
1455  */
1456 static int
1457 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
1458 {
1459         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1460
1461         if (ser->type != PORT_UNKNOWN && ser->type != info->type)
1462                 return -EINVAL;
1463
1464         return 0;
1465 }
1466
1467
1468 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1469
1470 static struct console s3c24xx_serial_console;
1471
1472 static int __init s3c24xx_serial_console_init(void)
1473 {
1474         register_console(&s3c24xx_serial_console);
1475         return 0;
1476 }
1477 console_initcall(s3c24xx_serial_console_init);
1478
1479 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
1480 #else
1481 #define S3C24XX_SERIAL_CONSOLE NULL
1482 #endif
1483
1484 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1485 static int s3c24xx_serial_get_poll_char(struct uart_port *port);
1486 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
1487                          unsigned char c);
1488 #endif
1489
1490 static struct uart_ops s3c24xx_serial_ops = {
1491         .pm             = s3c24xx_serial_pm,
1492         .tx_empty       = s3c24xx_serial_tx_empty,
1493         .get_mctrl      = s3c24xx_serial_get_mctrl,
1494         .set_mctrl      = s3c24xx_serial_set_mctrl,
1495         .stop_tx        = s3c24xx_serial_stop_tx,
1496         .start_tx       = s3c24xx_serial_start_tx,
1497         .stop_rx        = s3c24xx_serial_stop_rx,
1498         .break_ctl      = s3c24xx_serial_break_ctl,
1499         .startup        = s3c24xx_serial_startup,
1500         .shutdown       = s3c24xx_serial_shutdown,
1501         .set_termios    = s3c24xx_serial_set_termios,
1502         .type           = s3c24xx_serial_type,
1503         .release_port   = s3c24xx_serial_release_port,
1504         .request_port   = s3c24xx_serial_request_port,
1505         .config_port    = s3c24xx_serial_config_port,
1506         .verify_port    = s3c24xx_serial_verify_port,
1507 #if defined(CONFIG_SERIAL_SAMSUNG_CONSOLE) && defined(CONFIG_CONSOLE_POLL)
1508         .poll_get_char = s3c24xx_serial_get_poll_char,
1509         .poll_put_char = s3c24xx_serial_put_poll_char,
1510 #endif
1511 };
1512
1513 static struct uart_driver s3c24xx_uart_drv = {
1514         .owner          = THIS_MODULE,
1515         .driver_name    = "s3c2410_serial",
1516         .nr             = CONFIG_SERIAL_SAMSUNG_UARTS,
1517         .cons           = S3C24XX_SERIAL_CONSOLE,
1518         .dev_name       = S3C24XX_SERIAL_NAME,
1519         .major          = S3C24XX_SERIAL_MAJOR,
1520         .minor          = S3C24XX_SERIAL_MINOR,
1521 };
1522
1523 #define __PORT_LOCK_UNLOCKED(i) \
1524         __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[i].port.lock)
1525 static struct s3c24xx_uart_port
1526 s3c24xx_serial_ports[CONFIG_SERIAL_SAMSUNG_UARTS] = {
1527         [0] = {
1528                 .port = {
1529                         .lock           = __PORT_LOCK_UNLOCKED(0),
1530                         .iotype         = UPIO_MEM,
1531                         .uartclk        = 0,
1532                         .fifosize       = 16,
1533                         .ops            = &s3c24xx_serial_ops,
1534                         .flags          = UPF_BOOT_AUTOCONF,
1535                         .line           = 0,
1536                 }
1537         },
1538         [1] = {
1539                 .port = {
1540                         .lock           = __PORT_LOCK_UNLOCKED(1),
1541                         .iotype         = UPIO_MEM,
1542                         .uartclk        = 0,
1543                         .fifosize       = 16,
1544                         .ops            = &s3c24xx_serial_ops,
1545                         .flags          = UPF_BOOT_AUTOCONF,
1546                         .line           = 1,
1547                 }
1548         },
1549 #if CONFIG_SERIAL_SAMSUNG_UARTS > 2
1550
1551         [2] = {
1552                 .port = {
1553                         .lock           = __PORT_LOCK_UNLOCKED(2),
1554                         .iotype         = UPIO_MEM,
1555                         .uartclk        = 0,
1556                         .fifosize       = 16,
1557                         .ops            = &s3c24xx_serial_ops,
1558                         .flags          = UPF_BOOT_AUTOCONF,
1559                         .line           = 2,
1560                 }
1561         },
1562 #endif
1563 #if CONFIG_SERIAL_SAMSUNG_UARTS > 3
1564         [3] = {
1565                 .port = {
1566                         .lock           = __PORT_LOCK_UNLOCKED(3),
1567                         .iotype         = UPIO_MEM,
1568                         .uartclk        = 0,
1569                         .fifosize       = 16,
1570                         .ops            = &s3c24xx_serial_ops,
1571                         .flags          = UPF_BOOT_AUTOCONF,
1572                         .line           = 3,
1573                 }
1574         }
1575 #endif
1576 };
1577 #undef __PORT_LOCK_UNLOCKED
1578
1579 /* s3c24xx_serial_resetport
1580  *
1581  * reset the fifos and other the settings.
1582 */
1583
1584 static void s3c24xx_serial_resetport(struct uart_port *port,
1585                                    struct s3c2410_uartcfg *cfg)
1586 {
1587         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1588         unsigned long ucon = rd_regl(port, S3C2410_UCON);
1589         unsigned int ucon_mask;
1590
1591         ucon_mask = info->clksel_mask;
1592         if (info->type == PORT_S3C2440)
1593                 ucon_mask |= S3C2440_UCON0_DIVMASK;
1594
1595         ucon &= ucon_mask;
1596         wr_regl(port, S3C2410_UCON,  ucon | cfg->ucon);
1597
1598         /* reset both fifos */
1599         wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1600         wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1601
1602         /* some delay is required after fifo reset */
1603         udelay(1);
1604 }
1605
1606
1607 #ifdef CONFIG_ARM_S3C24XX_CPUFREQ
1608
1609 static int s3c24xx_serial_cpufreq_transition(struct notifier_block *nb,
1610                                              unsigned long val, void *data)
1611 {
1612         struct s3c24xx_uart_port *port;
1613         struct uart_port *uport;
1614
1615         port = container_of(nb, struct s3c24xx_uart_port, freq_transition);
1616         uport = &port->port;
1617
1618         /* check to see if port is enabled */
1619
1620         if (port->pm_level != 0)
1621                 return 0;
1622
1623         /* try and work out if the baudrate is changing, we can detect
1624          * a change in rate, but we do not have support for detecting
1625          * a disturbance in the clock-rate over the change.
1626          */
1627
1628         if (IS_ERR(port->baudclk))
1629                 goto exit;
1630
1631         if (port->baudclk_rate == clk_get_rate(port->baudclk))
1632                 goto exit;
1633
1634         if (val == CPUFREQ_PRECHANGE) {
1635                 /* we should really shut the port down whilst the
1636                  * frequency change is in progress. */
1637
1638         } else if (val == CPUFREQ_POSTCHANGE) {
1639                 struct ktermios *termios;
1640                 struct tty_struct *tty;
1641
1642                 if (uport->state == NULL)
1643                         goto exit;
1644
1645                 tty = uport->state->port.tty;
1646
1647                 if (tty == NULL)
1648                         goto exit;
1649
1650                 termios = &tty->termios;
1651
1652                 if (termios == NULL) {
1653                         dev_warn(uport->dev, "%s: no termios?\n", __func__);
1654                         goto exit;
1655                 }
1656
1657                 s3c24xx_serial_set_termios(uport, termios, NULL);
1658         }
1659
1660 exit:
1661         return 0;
1662 }
1663
1664 static inline int
1665 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1666 {
1667         port->freq_transition.notifier_call = s3c24xx_serial_cpufreq_transition;
1668
1669         return cpufreq_register_notifier(&port->freq_transition,
1670                                          CPUFREQ_TRANSITION_NOTIFIER);
1671 }
1672
1673 static inline void
1674 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1675 {
1676         cpufreq_unregister_notifier(&port->freq_transition,
1677                                     CPUFREQ_TRANSITION_NOTIFIER);
1678 }
1679
1680 #else
1681 static inline int
1682 s3c24xx_serial_cpufreq_register(struct s3c24xx_uart_port *port)
1683 {
1684         return 0;
1685 }
1686
1687 static inline void
1688 s3c24xx_serial_cpufreq_deregister(struct s3c24xx_uart_port *port)
1689 {
1690 }
1691 #endif
1692
1693 /* s3c24xx_serial_init_port
1694  *
1695  * initialise a single serial port from the platform device given
1696  */
1697
1698 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1699                                     struct platform_device *platdev)
1700 {
1701         struct uart_port *port = &ourport->port;
1702         struct s3c2410_uartcfg *cfg = ourport->cfg;
1703         struct resource *res;
1704         int ret;
1705
1706         dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1707
1708         if (platdev == NULL)
1709                 return -ENODEV;
1710
1711         if (port->mapbase != 0)
1712                 return -EINVAL;
1713
1714         /* setup info for port */
1715         port->dev       = &platdev->dev;
1716
1717         /* Startup sequence is different for s3c64xx and higher SoC's */
1718         if (s3c24xx_serial_has_interrupt_mask(port))
1719                 s3c24xx_serial_ops.startup = s3c64xx_serial_startup;
1720
1721         port->uartclk = 1;
1722
1723         if (cfg->uart_flags & UPF_CONS_FLOW) {
1724                 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1725                 port->flags |= UPF_CONS_FLOW;
1726         }
1727
1728         /* sort our the physical and virtual addresses for each UART */
1729
1730         res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1731         if (res == NULL) {
1732                 dev_err(port->dev, "failed to find memory resource for uart\n");
1733                 return -EINVAL;
1734         }
1735
1736         dbg("resource %pR)\n", res);
1737
1738         port->membase = devm_ioremap(port->dev, res->start, resource_size(res));
1739         if (!port->membase) {
1740                 dev_err(port->dev, "failed to remap controller address\n");
1741                 return -EBUSY;
1742         }
1743
1744         port->mapbase = res->start;
1745         ret = platform_get_irq(platdev, 0);
1746         if (ret < 0)
1747                 port->irq = 0;
1748         else {
1749                 port->irq = ret;
1750                 ourport->rx_irq = ret;
1751                 ourport->tx_irq = ret + 1;
1752         }
1753
1754         if (!s3c24xx_serial_has_interrupt_mask(port)) {
1755                 ret = platform_get_irq(platdev, 1);
1756                 if (ret > 0)
1757                         ourport->tx_irq = ret;
1758         }
1759         /*
1760          * DMA is currently supported only on DT platforms, if DMA properties
1761          * are specified.
1762          */
1763         if (platdev->dev.of_node && of_find_property(platdev->dev.of_node,
1764                                                      "dmas", NULL)) {
1765                 ourport->dma = devm_kzalloc(port->dev,
1766                                             sizeof(*ourport->dma),
1767                                             GFP_KERNEL);
1768                 if (!ourport->dma) {
1769                         ret = -ENOMEM;
1770                         goto err;
1771                 }
1772         }
1773
1774         ourport->clk    = clk_get(&platdev->dev, "uart");
1775         if (IS_ERR(ourport->clk)) {
1776                 pr_err("%s: Controller clock not found\n",
1777                                 dev_name(&platdev->dev));
1778                 ret = PTR_ERR(ourport->clk);
1779                 goto err;
1780         }
1781
1782         ret = clk_prepare_enable(ourport->clk);
1783         if (ret) {
1784                 pr_err("uart: clock failed to prepare+enable: %d\n", ret);
1785                 clk_put(ourport->clk);
1786                 goto err;
1787         }
1788
1789         /* Keep all interrupts masked and cleared */
1790         if (s3c24xx_serial_has_interrupt_mask(port)) {
1791                 wr_regl(port, S3C64XX_UINTM, 0xf);
1792                 wr_regl(port, S3C64XX_UINTP, 0xf);
1793                 wr_regl(port, S3C64XX_UINTSP, 0xf);
1794         }
1795
1796         dbg("port: map=%pa, mem=%p, irq=%d (%d,%d), clock=%u\n",
1797             &port->mapbase, port->membase, port->irq,
1798             ourport->rx_irq, ourport->tx_irq, port->uartclk);
1799
1800         /* reset the fifos (and setup the uart) */
1801         s3c24xx_serial_resetport(port, cfg);
1802
1803         return 0;
1804
1805 err:
1806         port->mapbase = 0;
1807         return ret;
1808 }
1809
1810 /* Device driver serial port probe */
1811
1812 static const struct of_device_id s3c24xx_uart_dt_match[];
1813 static int probe_index;
1814
1815 static inline struct s3c24xx_serial_drv_data *s3c24xx_get_driver_data(
1816                         struct platform_device *pdev)
1817 {
1818 #ifdef CONFIG_OF
1819         if (pdev->dev.of_node) {
1820                 const struct of_device_id *match;
1821                 match = of_match_node(s3c24xx_uart_dt_match, pdev->dev.of_node);
1822                 return (struct s3c24xx_serial_drv_data *)match->data;
1823         }
1824 #endif
1825         return (struct s3c24xx_serial_drv_data *)
1826                         platform_get_device_id(pdev)->driver_data;
1827 }
1828
1829 static int s3c24xx_serial_probe(struct platform_device *pdev)
1830 {
1831         struct device_node *np = pdev->dev.of_node;
1832         struct s3c24xx_uart_port *ourport;
1833         int index = probe_index;
1834         int ret;
1835
1836         if (np) {
1837                 ret = of_alias_get_id(np, "serial");
1838                 if (ret >= 0)
1839                         index = ret;
1840         }
1841
1842         dbg("s3c24xx_serial_probe(%p) %d\n", pdev, index);
1843
1844         if (index >= ARRAY_SIZE(s3c24xx_serial_ports)) {
1845                 dev_err(&pdev->dev, "serial%d out of range\n", index);
1846                 return -EINVAL;
1847         }
1848         ourport = &s3c24xx_serial_ports[index];
1849
1850         ourport->drv_data = s3c24xx_get_driver_data(pdev);
1851         if (!ourport->drv_data) {
1852                 dev_err(&pdev->dev, "could not find driver data\n");
1853                 return -ENODEV;
1854         }
1855
1856         ourport->baudclk = ERR_PTR(-EINVAL);
1857         ourport->info = ourport->drv_data->info;
1858         ourport->cfg = (dev_get_platdata(&pdev->dev)) ?
1859                         dev_get_platdata(&pdev->dev) :
1860                         ourport->drv_data->def_cfg;
1861
1862         if (np)
1863                 of_property_read_u32(np,
1864                         "samsung,uart-fifosize", &ourport->port.fifosize);
1865
1866         if (ourport->drv_data->fifosize[index])
1867                 ourport->port.fifosize = ourport->drv_data->fifosize[index];
1868         else if (ourport->info->fifosize)
1869                 ourport->port.fifosize = ourport->info->fifosize;
1870
1871         /*
1872          * DMA transfers must be aligned at least to cache line size,
1873          * so find minimal transfer size suitable for DMA mode
1874          */
1875         ourport->min_dma_size = max_t(int, ourport->port.fifosize,
1876                                     dma_get_cache_alignment());
1877
1878         dbg("%s: initialising port %p...\n", __func__, ourport);
1879
1880         ret = s3c24xx_serial_init_port(ourport, pdev);
1881         if (ret < 0)
1882                 return ret;
1883
1884         if (!s3c24xx_uart_drv.state) {
1885                 ret = uart_register_driver(&s3c24xx_uart_drv);
1886                 if (ret < 0) {
1887                         pr_err("Failed to register Samsung UART driver\n");
1888                         return ret;
1889                 }
1890         }
1891
1892         dbg("%s: adding port\n", __func__);
1893         uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1894         platform_set_drvdata(pdev, &ourport->port);
1895
1896         /*
1897          * Deactivate the clock enabled in s3c24xx_serial_init_port here,
1898          * so that a potential re-enablement through the pm-callback overlaps
1899          * and keeps the clock enabled in this case.
1900          */
1901         clk_disable_unprepare(ourport->clk);
1902
1903         ret = s3c24xx_serial_cpufreq_register(ourport);
1904         if (ret < 0)
1905                 dev_err(&pdev->dev, "failed to add cpufreq notifier\n");
1906
1907         probe_index++;
1908
1909         return 0;
1910 }
1911
1912 static int s3c24xx_serial_remove(struct platform_device *dev)
1913 {
1914         struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1915
1916         if (port) {
1917                 s3c24xx_serial_cpufreq_deregister(to_ourport(port));
1918                 uart_remove_one_port(&s3c24xx_uart_drv, port);
1919         }
1920
1921         uart_unregister_driver(&s3c24xx_uart_drv);
1922
1923         return 0;
1924 }
1925
1926 /* UART power management code */
1927 #ifdef CONFIG_PM_SLEEP
1928 static int s3c24xx_serial_suspend(struct device *dev)
1929 {
1930         struct uart_port *port = s3c24xx_dev_to_port(dev);
1931
1932         if (port)
1933                 uart_suspend_port(&s3c24xx_uart_drv, port);
1934
1935         return 0;
1936 }
1937
1938 static int s3c24xx_serial_resume(struct device *dev)
1939 {
1940         struct uart_port *port = s3c24xx_dev_to_port(dev);
1941         struct s3c24xx_uart_port *ourport = to_ourport(port);
1942
1943         if (port) {
1944                 clk_prepare_enable(ourport->clk);
1945                 if (!IS_ERR(ourport->baudclk))
1946                         clk_prepare_enable(ourport->baudclk);
1947                 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1948                 if (!IS_ERR(ourport->baudclk))
1949                         clk_disable_unprepare(ourport->baudclk);
1950                 clk_disable_unprepare(ourport->clk);
1951
1952                 uart_resume_port(&s3c24xx_uart_drv, port);
1953         }
1954
1955         return 0;
1956 }
1957
1958 static int s3c24xx_serial_resume_noirq(struct device *dev)
1959 {
1960         struct uart_port *port = s3c24xx_dev_to_port(dev);
1961         struct s3c24xx_uart_port *ourport = to_ourport(port);
1962
1963         if (port) {
1964                 /* restore IRQ mask */
1965                 if (s3c24xx_serial_has_interrupt_mask(port)) {
1966                         unsigned int uintm = 0xf;
1967                         if (tx_enabled(port))
1968                                 uintm &= ~S3C64XX_UINTM_TXD_MSK;
1969                         if (rx_enabled(port))
1970                                 uintm &= ~S3C64XX_UINTM_RXD_MSK;
1971                         clk_prepare_enable(ourport->clk);
1972                         if (!IS_ERR(ourport->baudclk))
1973                                 clk_prepare_enable(ourport->baudclk);
1974                         wr_regl(port, S3C64XX_UINTM, uintm);
1975                         if (!IS_ERR(ourport->baudclk))
1976                                 clk_disable_unprepare(ourport->baudclk);
1977                         clk_disable_unprepare(ourport->clk);
1978                 }
1979         }
1980
1981         return 0;
1982 }
1983
1984 static const struct dev_pm_ops s3c24xx_serial_pm_ops = {
1985         .suspend = s3c24xx_serial_suspend,
1986         .resume = s3c24xx_serial_resume,
1987         .resume_noirq = s3c24xx_serial_resume_noirq,
1988 };
1989 #define SERIAL_SAMSUNG_PM_OPS   (&s3c24xx_serial_pm_ops)
1990
1991 #else /* !CONFIG_PM_SLEEP */
1992
1993 #define SERIAL_SAMSUNG_PM_OPS   NULL
1994 #endif /* CONFIG_PM_SLEEP */
1995
1996 /* Console code */
1997
1998 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
1999
2000 static struct uart_port *cons_uart;
2001
2002 static int
2003 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
2004 {
2005         struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
2006         unsigned long ufstat, utrstat;
2007
2008         if (ufcon & S3C2410_UFCON_FIFOMODE) {
2009                 /* fifo mode - check amount of data in fifo registers... */
2010
2011                 ufstat = rd_regl(port, S3C2410_UFSTAT);
2012                 return (ufstat & info->tx_fifofull) ? 0 : 1;
2013         }
2014
2015         /* in non-fifo mode, we go and use the tx buffer empty */
2016
2017         utrstat = rd_regl(port, S3C2410_UTRSTAT);
2018         return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
2019 }
2020
2021 static bool
2022 s3c24xx_port_configured(unsigned int ucon)
2023 {
2024         /* consider the serial port configured if the tx/rx mode set */
2025         return (ucon & 0xf) != 0;
2026 }
2027
2028 #ifdef CONFIG_CONSOLE_POLL
2029 /*
2030  * Console polling routines for writing and reading from the uart while
2031  * in an interrupt or debug context.
2032  */
2033
2034 static int s3c24xx_serial_get_poll_char(struct uart_port *port)
2035 {
2036         struct s3c24xx_uart_port *ourport = to_ourport(port);
2037         unsigned int ufstat;
2038
2039         ufstat = rd_regl(port, S3C2410_UFSTAT);
2040         if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
2041                 return NO_POLL_CHAR;
2042
2043         return rd_regb(port, S3C2410_URXH);
2044 }
2045
2046 static void s3c24xx_serial_put_poll_char(struct uart_port *port,
2047                 unsigned char c)
2048 {
2049         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2050         unsigned int ucon = rd_regl(port, S3C2410_UCON);
2051
2052         /* not possible to xmit on unconfigured port */
2053         if (!s3c24xx_port_configured(ucon))
2054                 return;
2055
2056         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2057                 cpu_relax();
2058         wr_regb(port, S3C2410_UTXH, c);
2059 }
2060
2061 #endif /* CONFIG_CONSOLE_POLL */
2062
2063 static void
2064 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
2065 {
2066         unsigned int ufcon = rd_regl(port, S3C2410_UFCON);
2067
2068         while (!s3c24xx_serial_console_txrdy(port, ufcon))
2069                 cpu_relax();
2070         wr_regb(port, S3C2410_UTXH, ch);
2071 }
2072
2073 static void
2074 s3c24xx_serial_console_write(struct console *co, const char *s,
2075                              unsigned int count)
2076 {
2077         unsigned int ucon = rd_regl(cons_uart, S3C2410_UCON);
2078
2079         /* not possible to xmit on unconfigured port */
2080         if (!s3c24xx_port_configured(ucon))
2081                 return;
2082
2083         uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
2084 }
2085
2086 static void __init
2087 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
2088                            int *parity, int *bits)
2089 {
2090         struct clk *clk;
2091         unsigned int ulcon;
2092         unsigned int ucon;
2093         unsigned int ubrdiv;
2094         unsigned long rate;
2095         unsigned int clk_sel;
2096         char clk_name[MAX_CLK_NAME_LENGTH];
2097
2098         ulcon  = rd_regl(port, S3C2410_ULCON);
2099         ucon   = rd_regl(port, S3C2410_UCON);
2100         ubrdiv = rd_regl(port, S3C2410_UBRDIV);
2101
2102         dbg("s3c24xx_serial_get_options: port=%p\n"
2103             "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
2104             port, ulcon, ucon, ubrdiv);
2105
2106         if (s3c24xx_port_configured(ucon)) {
2107                 switch (ulcon & S3C2410_LCON_CSMASK) {
2108                 case S3C2410_LCON_CS5:
2109                         *bits = 5;
2110                         break;
2111                 case S3C2410_LCON_CS6:
2112                         *bits = 6;
2113                         break;
2114                 case S3C2410_LCON_CS7:
2115                         *bits = 7;
2116                         break;
2117                 case S3C2410_LCON_CS8:
2118                 default:
2119                         *bits = 8;
2120                         break;
2121                 }
2122
2123                 switch (ulcon & S3C2410_LCON_PMASK) {
2124                 case S3C2410_LCON_PEVEN:
2125                         *parity = 'e';
2126                         break;
2127
2128                 case S3C2410_LCON_PODD:
2129                         *parity = 'o';
2130                         break;
2131
2132                 case S3C2410_LCON_PNONE:
2133                 default:
2134                         *parity = 'n';
2135                 }
2136
2137                 /* now calculate the baud rate */
2138
2139                 clk_sel = s3c24xx_serial_getsource(port);
2140                 sprintf(clk_name, "clk_uart_baud%d", clk_sel);
2141
2142                 clk = clk_get(port->dev, clk_name);
2143                 if (!IS_ERR(clk))
2144                         rate = clk_get_rate(clk);
2145                 else
2146                         rate = 1;
2147
2148                 *baud = rate / (16 * (ubrdiv + 1));
2149                 dbg("calculated baud %d\n", *baud);
2150         }
2151
2152 }
2153
2154 static int __init
2155 s3c24xx_serial_console_setup(struct console *co, char *options)
2156 {
2157         struct uart_port *port;
2158         int baud = 9600;
2159         int bits = 8;
2160         int parity = 'n';
2161         int flow = 'n';
2162
2163         dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
2164             co, co->index, options);
2165
2166         /* is this a valid port */
2167
2168         if (co->index == -1 || co->index >= CONFIG_SERIAL_SAMSUNG_UARTS)
2169                 co->index = 0;
2170
2171         port = &s3c24xx_serial_ports[co->index].port;
2172
2173         /* is the port configured? */
2174
2175         if (port->mapbase == 0x0)
2176                 return -ENODEV;
2177
2178         cons_uart = port;
2179
2180         dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
2181
2182         /*
2183          * Check whether an invalid uart number has been specified, and
2184          * if so, search for the first available port that does have
2185          * console support.
2186          */
2187         if (options)
2188                 uart_parse_options(options, &baud, &parity, &bits, &flow);
2189         else
2190                 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
2191
2192         dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
2193
2194         return uart_set_options(port, co, baud, parity, bits, flow);
2195 }
2196
2197 static struct console s3c24xx_serial_console = {
2198         .name           = S3C24XX_SERIAL_NAME,
2199         .device         = uart_console_device,
2200         .flags          = CON_PRINTBUFFER,
2201         .index          = -1,
2202         .write          = s3c24xx_serial_console_write,
2203         .setup          = s3c24xx_serial_console_setup,
2204         .data           = &s3c24xx_uart_drv,
2205 };
2206 #endif /* CONFIG_SERIAL_SAMSUNG_CONSOLE */
2207
2208 #ifdef CONFIG_CPU_S3C2410
2209 static struct s3c24xx_serial_drv_data s3c2410_serial_drv_data = {
2210         .info = &(struct s3c24xx_uart_info) {
2211                 .name           = "Samsung S3C2410 UART",
2212                 .type           = PORT_S3C2410,
2213                 .fifosize       = 16,
2214                 .rx_fifomask    = S3C2410_UFSTAT_RXMASK,
2215                 .rx_fifoshift   = S3C2410_UFSTAT_RXSHIFT,
2216                 .rx_fifofull    = S3C2410_UFSTAT_RXFULL,
2217                 .tx_fifofull    = S3C2410_UFSTAT_TXFULL,
2218                 .tx_fifomask    = S3C2410_UFSTAT_TXMASK,
2219                 .tx_fifoshift   = S3C2410_UFSTAT_TXSHIFT,
2220                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2221                 .num_clks       = 2,
2222                 .clksel_mask    = S3C2410_UCON_CLKMASK,
2223                 .clksel_shift   = S3C2410_UCON_CLKSHIFT,
2224         },
2225         .def_cfg = &(struct s3c2410_uartcfg) {
2226                 .ucon           = S3C2410_UCON_DEFAULT,
2227                 .ufcon          = S3C2410_UFCON_DEFAULT,
2228         },
2229 };
2230 #define S3C2410_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2410_serial_drv_data)
2231 #else
2232 #define S3C2410_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2233 #endif
2234
2235 #ifdef CONFIG_CPU_S3C2412
2236 static struct s3c24xx_serial_drv_data s3c2412_serial_drv_data = {
2237         .info = &(struct s3c24xx_uart_info) {
2238                 .name           = "Samsung S3C2412 UART",
2239                 .type           = PORT_S3C2412,
2240                 .fifosize       = 64,
2241                 .has_divslot    = 1,
2242                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2243                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2244                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2245                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2246                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2247                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2248                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2249                 .num_clks       = 4,
2250                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2251                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2252         },
2253         .def_cfg = &(struct s3c2410_uartcfg) {
2254                 .ucon           = S3C2410_UCON_DEFAULT,
2255                 .ufcon          = S3C2410_UFCON_DEFAULT,
2256         },
2257 };
2258 #define S3C2412_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2412_serial_drv_data)
2259 #else
2260 #define S3C2412_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2261 #endif
2262
2263 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2416) || \
2264         defined(CONFIG_CPU_S3C2443) || defined(CONFIG_CPU_S3C2442)
2265 static struct s3c24xx_serial_drv_data s3c2440_serial_drv_data = {
2266         .info = &(struct s3c24xx_uart_info) {
2267                 .name           = "Samsung S3C2440 UART",
2268                 .type           = PORT_S3C2440,
2269                 .fifosize       = 64,
2270                 .has_divslot    = 1,
2271                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2272                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2273                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2274                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2275                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2276                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2277                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2278                 .num_clks       = 4,
2279                 .clksel_mask    = S3C2412_UCON_CLKMASK,
2280                 .clksel_shift   = S3C2412_UCON_CLKSHIFT,
2281         },
2282         .def_cfg = &(struct s3c2410_uartcfg) {
2283                 .ucon           = S3C2410_UCON_DEFAULT,
2284                 .ufcon          = S3C2410_UFCON_DEFAULT,
2285         },
2286 };
2287 #define S3C2440_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c2440_serial_drv_data)
2288 #else
2289 #define S3C2440_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2290 #endif
2291
2292 #if defined(CONFIG_CPU_S3C6400) || defined(CONFIG_CPU_S3C6410)
2293 static struct s3c24xx_serial_drv_data s3c6400_serial_drv_data = {
2294         .info = &(struct s3c24xx_uart_info) {
2295                 .name           = "Samsung S3C6400 UART",
2296                 .type           = PORT_S3C6400,
2297                 .fifosize       = 64,
2298                 .has_divslot    = 1,
2299                 .rx_fifomask    = S3C2440_UFSTAT_RXMASK,
2300                 .rx_fifoshift   = S3C2440_UFSTAT_RXSHIFT,
2301                 .rx_fifofull    = S3C2440_UFSTAT_RXFULL,
2302                 .tx_fifofull    = S3C2440_UFSTAT_TXFULL,
2303                 .tx_fifomask    = S3C2440_UFSTAT_TXMASK,
2304                 .tx_fifoshift   = S3C2440_UFSTAT_TXSHIFT,
2305                 .def_clk_sel    = S3C2410_UCON_CLKSEL2,
2306                 .num_clks       = 4,
2307                 .clksel_mask    = S3C6400_UCON_CLKMASK,
2308                 .clksel_shift   = S3C6400_UCON_CLKSHIFT,
2309         },
2310         .def_cfg = &(struct s3c2410_uartcfg) {
2311                 .ucon           = S3C2410_UCON_DEFAULT,
2312                 .ufcon          = S3C2410_UFCON_DEFAULT,
2313         },
2314 };
2315 #define S3C6400_SERIAL_DRV_DATA ((kernel_ulong_t)&s3c6400_serial_drv_data)
2316 #else
2317 #define S3C6400_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2318 #endif
2319
2320 #ifdef CONFIG_CPU_S5PV210
2321 static struct s3c24xx_serial_drv_data s5pv210_serial_drv_data = {
2322         .info = &(struct s3c24xx_uart_info) {
2323                 .name           = "Samsung S5PV210 UART",
2324                 .type           = PORT_S3C6400,
2325                 .has_divslot    = 1,
2326                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,
2327                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,
2328                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,
2329                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,
2330                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,
2331                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,
2332                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,
2333                 .num_clks       = 2,
2334                 .clksel_mask    = S5PV210_UCON_CLKMASK,
2335                 .clksel_shift   = S5PV210_UCON_CLKSHIFT,
2336         },
2337         .def_cfg = &(struct s3c2410_uartcfg) {
2338                 .ucon           = S5PV210_UCON_DEFAULT,
2339                 .ufcon          = S5PV210_UFCON_DEFAULT,
2340         },
2341         .fifosize = { 256, 64, 16, 16 },
2342 };
2343 #define S5PV210_SERIAL_DRV_DATA ((kernel_ulong_t)&s5pv210_serial_drv_data)
2344 #else
2345 #define S5PV210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2346 #endif
2347
2348 #if defined(CONFIG_ARCH_EXYNOS)
2349 #define EXYNOS_COMMON_SERIAL_DRV_DATA                           \
2350         .info = &(struct s3c24xx_uart_info) {                   \
2351                 .name           = "Samsung Exynos UART",        \
2352                 .type           = PORT_S3C6400,                 \
2353                 .has_divslot    = 1,                            \
2354                 .rx_fifomask    = S5PV210_UFSTAT_RXMASK,        \
2355                 .rx_fifoshift   = S5PV210_UFSTAT_RXSHIFT,       \
2356                 .rx_fifofull    = S5PV210_UFSTAT_RXFULL,        \
2357                 .tx_fifofull    = S5PV210_UFSTAT_TXFULL,        \
2358                 .tx_fifomask    = S5PV210_UFSTAT_TXMASK,        \
2359                 .tx_fifoshift   = S5PV210_UFSTAT_TXSHIFT,       \
2360                 .def_clk_sel    = S3C2410_UCON_CLKSEL0,         \
2361                 .num_clks       = 1,                            \
2362                 .clksel_mask    = 0,                            \
2363                 .clksel_shift   = 0,                            \
2364         },                                                      \
2365         .def_cfg = &(struct s3c2410_uartcfg) {                  \
2366                 .ucon           = S5PV210_UCON_DEFAULT,         \
2367                 .ufcon          = S5PV210_UFCON_DEFAULT,        \
2368                 .has_fracval    = 1,                            \
2369         }                                                       \
2370
2371 static struct s3c24xx_serial_drv_data exynos4210_serial_drv_data = {
2372         EXYNOS_COMMON_SERIAL_DRV_DATA,
2373         .fifosize = { 256, 64, 16, 16 },
2374 };
2375
2376 static struct s3c24xx_serial_drv_data exynos5433_serial_drv_data = {
2377         EXYNOS_COMMON_SERIAL_DRV_DATA,
2378         .fifosize = { 64, 256, 16, 256 },
2379 };
2380
2381 #define EXYNOS4210_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos4210_serial_drv_data)
2382 #define EXYNOS5433_SERIAL_DRV_DATA ((kernel_ulong_t)&exynos5433_serial_drv_data)
2383 #else
2384 #define EXYNOS4210_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2385 #define EXYNOS5433_SERIAL_DRV_DATA (kernel_ulong_t)NULL
2386 #endif
2387
2388 static const struct platform_device_id s3c24xx_serial_driver_ids[] = {
2389         {
2390                 .name           = "s3c2410-uart",
2391                 .driver_data    = S3C2410_SERIAL_DRV_DATA,
2392         }, {
2393                 .name           = "s3c2412-uart",
2394                 .driver_data    = S3C2412_SERIAL_DRV_DATA,
2395         }, {
2396                 .name           = "s3c2440-uart",
2397                 .driver_data    = S3C2440_SERIAL_DRV_DATA,
2398         }, {
2399                 .name           = "s3c6400-uart",
2400                 .driver_data    = S3C6400_SERIAL_DRV_DATA,
2401         }, {
2402                 .name           = "s5pv210-uart",
2403                 .driver_data    = S5PV210_SERIAL_DRV_DATA,
2404         }, {
2405                 .name           = "exynos4210-uart",
2406                 .driver_data    = EXYNOS4210_SERIAL_DRV_DATA,
2407         }, {
2408                 .name           = "exynos5433-uart",
2409                 .driver_data    = EXYNOS5433_SERIAL_DRV_DATA,
2410         },
2411         { },
2412 };
2413 MODULE_DEVICE_TABLE(platform, s3c24xx_serial_driver_ids);
2414
2415 #ifdef CONFIG_OF
2416 static const struct of_device_id s3c24xx_uart_dt_match[] = {
2417         { .compatible = "samsung,s3c2410-uart",
2418                 .data = (void *)S3C2410_SERIAL_DRV_DATA },
2419         { .compatible = "samsung,s3c2412-uart",
2420                 .data = (void *)S3C2412_SERIAL_DRV_DATA },
2421         { .compatible = "samsung,s3c2440-uart",
2422                 .data = (void *)S3C2440_SERIAL_DRV_DATA },
2423         { .compatible = "samsung,s3c6400-uart",
2424                 .data = (void *)S3C6400_SERIAL_DRV_DATA },
2425         { .compatible = "samsung,s5pv210-uart",
2426                 .data = (void *)S5PV210_SERIAL_DRV_DATA },
2427         { .compatible = "samsung,exynos4210-uart",
2428                 .data = (void *)EXYNOS4210_SERIAL_DRV_DATA },
2429         { .compatible = "samsung,exynos5433-uart",
2430                 .data = (void *)EXYNOS5433_SERIAL_DRV_DATA },
2431         {},
2432 };
2433 MODULE_DEVICE_TABLE(of, s3c24xx_uart_dt_match);
2434 #endif
2435
2436 static struct platform_driver samsung_serial_driver = {
2437         .probe          = s3c24xx_serial_probe,
2438         .remove         = s3c24xx_serial_remove,
2439         .id_table       = s3c24xx_serial_driver_ids,
2440         .driver         = {
2441                 .name   = "samsung-uart",
2442                 .pm     = SERIAL_SAMSUNG_PM_OPS,
2443                 .of_match_table = of_match_ptr(s3c24xx_uart_dt_match),
2444         },
2445 };
2446
2447 module_platform_driver(samsung_serial_driver);
2448
2449 #ifdef CONFIG_SERIAL_SAMSUNG_CONSOLE
2450 /*
2451  * Early console.
2452  */
2453
2454 struct samsung_early_console_data {
2455         u32 txfull_mask;
2456 };
2457
2458 static void samsung_early_busyuart(struct uart_port *port)
2459 {
2460         while (!(readl(port->membase + S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXFE))
2461                 ;
2462 }
2463
2464 static void samsung_early_busyuart_fifo(struct uart_port *port)
2465 {
2466         struct samsung_early_console_data *data = port->private_data;
2467
2468         while (readl(port->membase + S3C2410_UFSTAT) & data->txfull_mask)
2469                 ;
2470 }
2471
2472 static void samsung_early_putc(struct uart_port *port, int c)
2473 {
2474         if (readl(port->membase + S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE)
2475                 samsung_early_busyuart_fifo(port);
2476         else
2477                 samsung_early_busyuart(port);
2478
2479         writeb(c, port->membase + S3C2410_UTXH);
2480 }
2481
2482 static void samsung_early_write(struct console *con, const char *s, unsigned n)
2483 {
2484         struct earlycon_device *dev = con->data;
2485
2486         uart_console_write(&dev->port, s, n, samsung_early_putc);
2487 }
2488
2489 static int __init samsung_early_console_setup(struct earlycon_device *device,
2490                                               const char *opt)
2491 {
2492         if (!device->port.membase)
2493                 return -ENODEV;
2494
2495         device->con->write = samsung_early_write;
2496         return 0;
2497 }
2498
2499 /* S3C2410 */
2500 static struct samsung_early_console_data s3c2410_early_console_data = {
2501         .txfull_mask = S3C2410_UFSTAT_TXFULL,
2502 };
2503
2504 static int __init s3c2410_early_console_setup(struct earlycon_device *device,
2505                                               const char *opt)
2506 {
2507         device->port.private_data = &s3c2410_early_console_data;
2508         return samsung_early_console_setup(device, opt);
2509 }
2510 OF_EARLYCON_DECLARE(s3c2410, "samsung,s3c2410-uart",
2511                         s3c2410_early_console_setup);
2512
2513 /* S3C2412, S3C2440, S3C64xx */
2514 static struct samsung_early_console_data s3c2440_early_console_data = {
2515         .txfull_mask = S3C2440_UFSTAT_TXFULL,
2516 };
2517
2518 static int __init s3c2440_early_console_setup(struct earlycon_device *device,
2519                                               const char *opt)
2520 {
2521         device->port.private_data = &s3c2440_early_console_data;
2522         return samsung_early_console_setup(device, opt);
2523 }
2524 OF_EARLYCON_DECLARE(s3c2412, "samsung,s3c2412-uart",
2525                         s3c2440_early_console_setup);
2526 OF_EARLYCON_DECLARE(s3c2440, "samsung,s3c2440-uart",
2527                         s3c2440_early_console_setup);
2528 OF_EARLYCON_DECLARE(s3c6400, "samsung,s3c6400-uart",
2529                         s3c2440_early_console_setup);
2530
2531 /* S5PV210, EXYNOS */
2532 static struct samsung_early_console_data s5pv210_early_console_data = {
2533         .txfull_mask = S5PV210_UFSTAT_TXFULL,
2534 };
2535
2536 static int __init s5pv210_early_console_setup(struct earlycon_device *device,
2537                                               const char *opt)
2538 {
2539         device->port.private_data = &s5pv210_early_console_data;
2540         return samsung_early_console_setup(device, opt);
2541 }
2542 OF_EARLYCON_DECLARE(s5pv210, "samsung,s5pv210-uart",
2543                         s5pv210_early_console_setup);
2544 OF_EARLYCON_DECLARE(exynos4210, "samsung,exynos4210-uart",
2545                         s5pv210_early_console_setup);
2546 #endif
2547
2548 MODULE_ALIAS("platform:samsung-uart");
2549 MODULE_DESCRIPTION("Samsung SoC Serial port driver");
2550 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
2551 MODULE_LICENSE("GPL v2");