drivers/tty/serial/stm32-usart.c

   1 /*
   2  * Copyright (C) Maxime Coquelin 2015
   3  * Copyright (C) STMicroelectronics SA 2017
   4  * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   5  *           Gerald Baeza <gerald.baeza@st.com>
   6  * License terms:  GNU General Public License (GPL), version 2
   7  *
   8  * Inspired by st-asc.c from STMicroelectronics (c)
   9  */
  10
  11 #if defined(CONFIG_SERIAL_STM32_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  12 #define SUPPORT_SYSRQ
  13 #endif
  14
  15 #include <linux/clk.h>
  16 #include <linux/console.h>
  17 #include <linux/delay.h>
  18 #include <linux/dma-direction.h>
  19 #include <linux/dmaengine.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/irq.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/pm_wakeirq.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/serial.h>
  32 #include <linux/spinlock.h>
  33 #include <linux/sysrq.h>
  34 #include <linux/tty_flip.h>
  35 #include <linux/tty.h>
  36
  37 #include "stm32-usart.h"
  38
  39 static void stm32_stop_tx(struct uart_port *port);
  40 static void stm32_transmit_chars(struct uart_port *port);
  41
  42 static inline struct stm32_port *to_stm32_port(struct uart_port *port)
  43 {
  44         return container_of(port, struct stm32_port, port);
  45 }
  46
  47 static void stm32_set_bits(struct uart_port *port, u32 reg, u32 bits)
  48 {
  49         u32 val;
  50
  51         val = readl_relaxed(port->membase + reg);
  52         val |= bits;
  53         writel_relaxed(val, port->membase + reg);
  54 }
  55
  56 static void stm32_clr_bits(struct uart_port *port, u32 reg, u32 bits)
  57 {
  58         u32 val;
  59
  60         val = readl_relaxed(port->membase + reg);
  61         val &= ~bits;
  62         writel_relaxed(val, port->membase + reg);
  63 }
  64
  65 static int stm32_pending_rx(struct uart_port *port, u32 *sr, int *last_res,
  66                             bool threaded)
  67 {
  68         struct stm32_port *stm32_port = to_stm32_port(port);
  69         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  70         enum dma_status status;
  71         struct dma_tx_state state;
  72
  73         *sr = readl_relaxed(port->membase + ofs->isr);
  74
  75         if (threaded && stm32_port->rx_ch) {
  76                 status = dmaengine_tx_status(stm32_port->rx_ch,
  77                                              stm32_port->rx_ch->cookie,
  78                                              &state);
  79                 if ((status == DMA_IN_PROGRESS) &&
  80                     (*last_res != state.residue))
  81                         return 1;
  82                 else
  83                         return 0;
  84         } else if (*sr & USART_SR_RXNE) {
  85                 return 1;
  86         }
  87         return 0;
  88 }
  89
  90 static unsigned long
  91 stm32_get_char(struct uart_port *port, u32 *sr, int *last_res)
  92 {
  93         struct stm32_port *stm32_port = to_stm32_port(port);
  94         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
  95         unsigned long c;
  96
  97         if (stm32_port->rx_ch) {
  98                 c = stm32_port->rx_buf[RX_BUF_L - (*last_res)--];
  99                 if ((*last_res) == 0)
 100                         *last_res = RX_BUF_L;
 101                 return c;
 102         } else {
 103                 return readl_relaxed(port->membase + ofs->rdr);
 104         }
 105 }
 106
 107 static void stm32_receive_chars(struct uart_port *port, bool threaded)
 108 {
 109         struct tty_port *tport = &port->state->port;
 110         struct stm32_port *stm32_port = to_stm32_port(port);
 111         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 112         unsigned long c;
 113         u32 sr;
 114         char flag;
 115
 116         if (irqd_is_wakeup_set(irq_get_irq_data(port->irq)))
 117                 pm_wakeup_event(tport->tty->dev, 0);
 118
 119         while (stm32_pending_rx(port, &sr, &stm32_port->last_res, threaded)) {
 120                 sr |= USART_SR_DUMMY_RX;
 121                 flag = TTY_NORMAL;
 122
 123                 /*
 124                  * Status bits has to be cleared before reading the RDR:
 125                  * In FIFO mode, reading the RDR will pop the next data
 126                  * (if any) along with its status bits into the SR.
 127                  * Not doing so leads to misalignement between RDR and SR,
 128                  * and clear status bits of the next rx data.
 129                  *
 130                  * Clear errors flags for stm32f7 and stm32h7 compatible
 131                  * devices. On stm32f4 compatible devices, the error bit is
 132                  * cleared by the sequence [read SR - read DR].
 133                  */
 134                 if ((sr & USART_SR_ERR_MASK) && ofs->icr != UNDEF_REG)
 135                         writel_relaxed(sr & USART_SR_ERR_MASK,
 136                                        port->membase + ofs->icr);
 137
 138                 c = stm32_get_char(port, &sr, &stm32_port->last_res);
 139                 port->icount.rx++;
 140                 if (sr & USART_SR_ERR_MASK) {
 141                         if (sr & USART_SR_ORE) {
 142                                 port->icount.overrun++;
 143                         } else if (sr & USART_SR_PE) {
 144                                 port->icount.parity++;
 145                         } else if (sr & USART_SR_FE) {
 146                                 /* Break detection if character is null */
 147                                 if (!c) {
 148                                         port->icount.brk++;
 149                                         if (uart_handle_break(port))
 150                                                 continue;
 151                                 } else {
 152                                         port->icount.frame++;
 153                                 }
 154                         }
 155
 156                         sr &= port->read_status_mask;
 157
 158                         if (sr & USART_SR_PE) {
 159                                 flag = TTY_PARITY;
 160                         } else if (sr & USART_SR_FE) {
 161                                 if (!c)
 162                                         flag = TTY_BREAK;
 163                                 else
 164                                         flag = TTY_FRAME;
 165                         }
 166                 }
 167
 168                 if (uart_handle_sysrq_char(port, c))
 169                         continue;
 170                 uart_insert_char(port, sr, USART_SR_ORE, c, flag);
 171         }
 172
 173         spin_unlock(&port->lock);
 174         tty_flip_buffer_push(tport);
 175         spin_lock(&port->lock);
 176 }
 177
 178 static void stm32_tx_dma_complete(void *arg)
 179 {
 180         struct uart_port *port = arg;
 181         struct stm32_port *stm32port = to_stm32_port(port);
 182         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 183
 184         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 185         stm32port->tx_dma_busy = false;
 186
 187         /* Let's see if we have pending data to send */
 188         stm32_transmit_chars(port);
 189 }
 190
 191 static void stm32_transmit_chars_pio(struct uart_port *port)
 192 {
 193         struct stm32_port *stm32_port = to_stm32_port(port);
 194         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 195         struct circ_buf *xmit = &port->state->xmit;
 196         unsigned int isr;
 197         int ret;
 198
 199         if (stm32_port->tx_dma_busy) {
 200                 stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 201                 stm32_port->tx_dma_busy = false;
 202         }
 203
 204         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 205                                                 isr,
 206                                                 (isr & USART_SR_TXE),
 207                                                 10, 100000);
 208
 209         if (ret)
 210                 dev_err(port->dev, "tx empty not set\n");
 211
 212         stm32_set_bits(port, ofs->cr1, USART_CR1_TXEIE);
 213
 214         writel_relaxed(xmit->buf[xmit->tail], port->membase + ofs->tdr);
 215         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 216         port->icount.tx++;
 217 }
 218
 219 static void stm32_transmit_chars_dma(struct uart_port *port)
 220 {
 221         struct stm32_port *stm32port = to_stm32_port(port);
 222         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 223         struct circ_buf *xmit = &port->state->xmit;
 224         struct dma_async_tx_descriptor *desc = NULL;
 225         dma_cookie_t cookie;
 226         unsigned int count, i;
 227
 228         if (stm32port->tx_dma_busy)
 229                 return;
 230
 231         stm32port->tx_dma_busy = true;
 232
 233         count = uart_circ_chars_pending(xmit);
 234
 235         if (count > TX_BUF_L)
 236                 count = TX_BUF_L;
 237
 238         if (xmit->tail < xmit->head) {
 239                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], count);
 240         } else {
 241                 size_t one = UART_XMIT_SIZE - xmit->tail;
 242                 size_t two;
 243
 244                 if (one > count)
 245                         one = count;
 246                 two = count - one;
 247
 248                 memcpy(&stm32port->tx_buf[0], &xmit->buf[xmit->tail], one);
 249                 if (two)
 250                         memcpy(&stm32port->tx_buf[one], &xmit->buf[0], two);
 251         }
 252
 253         desc = dmaengine_prep_slave_single(stm32port->tx_ch,
 254                                            stm32port->tx_dma_buf,
 255                                            count,
 256                                            DMA_MEM_TO_DEV,
 257                                            DMA_PREP_INTERRUPT);
 258
 259         if (!desc) {
 260                 for (i = count; i > 0; i--)
 261                         stm32_transmit_chars_pio(port);
 262                 return;
 263         }
 264
 265         desc->callback = stm32_tx_dma_complete;
 266         desc->callback_param = port;
 267
 268         /* Push current DMA TX transaction in the pending queue */
 269         cookie = dmaengine_submit(desc);
 270
 271         /* Issue pending DMA TX requests */
 272         dma_async_issue_pending(stm32port->tx_ch);
 273
 274         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 275
 276         xmit->tail = (xmit->tail + count) & (UART_XMIT_SIZE - 1);
 277         port->icount.tx += count;
 278 }
 279
 280 static void stm32_transmit_chars(struct uart_port *port)
 281 {
 282         struct stm32_port *stm32_port = to_stm32_port(port);
 283         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 284         struct circ_buf *xmit = &port->state->xmit;
 285
 286         if (port->x_char) {
 287                 if (stm32_port->tx_dma_busy)
 288                         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 289                 writel_relaxed(port->x_char, port->membase + ofs->tdr);
 290                 port->x_char = 0;
 291                 port->icount.tx++;
 292                 if (stm32_port->tx_dma_busy)
 293                         stm32_set_bits(port, ofs->cr3, USART_CR3_DMAT);
 294                 return;
 295         }
 296
 297         if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
 298                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 299                 return;
 300         }
 301
 302         if (ofs->icr == UNDEF_REG)
 303                 stm32_clr_bits(port, ofs->isr, USART_SR_TC);
 304         else
 305                 writel_relaxed(USART_ICR_TCCF, port->membase + ofs->icr);
 306
 307         if (stm32_port->tx_ch)
 308                 stm32_transmit_chars_dma(port);
 309         else
 310                 stm32_transmit_chars_pio(port);
 311
 312         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 313                 uart_write_wakeup(port);
 314
 315         if (uart_circ_empty(xmit))
 316                 stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 317 }
 318
 319 static irqreturn_t stm32_interrupt(int irq, void *ptr)
 320 {
 321         struct uart_port *port = ptr;
 322         struct stm32_port *stm32_port = to_stm32_port(port);
 323         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 324         u32 sr;
 325
 326         spin_lock(&port->lock);
 327
 328         sr = readl_relaxed(port->membase + ofs->isr);
 329
 330         if ((sr & USART_SR_WUF) && (ofs->icr != UNDEF_REG))
 331                 writel_relaxed(USART_ICR_WUCF,
 332                                port->membase + ofs->icr);
 333
 334         if ((sr & USART_SR_RXNE) && !(stm32_port->rx_ch))
 335                 stm32_receive_chars(port, false);
 336
 337         if ((sr & USART_SR_TXE) && !(stm32_port->tx_ch))
 338                 stm32_transmit_chars(port);
 339
 340         spin_unlock(&port->lock);
 341
 342         if (stm32_port->rx_ch)
 343                 return IRQ_WAKE_THREAD;
 344         else
 345                 return IRQ_HANDLED;
 346 }
 347
 348 static irqreturn_t stm32_threaded_interrupt(int irq, void *ptr)
 349 {
 350         struct uart_port *port = ptr;
 351         struct stm32_port *stm32_port = to_stm32_port(port);
 352
 353         spin_lock(&port->lock);
 354
 355         if (stm32_port->rx_ch)
 356                 stm32_receive_chars(port, true);
 357
 358         spin_unlock(&port->lock);
 359
 360         return IRQ_HANDLED;
 361 }
 362
 363 static unsigned int stm32_tx_empty(struct uart_port *port)
 364 {
 365         struct stm32_port *stm32_port = to_stm32_port(port);
 366         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 367
 368         if (readl_relaxed(port->membase + ofs->isr) & USART_SR_TC)
 369                 return TIOCSER_TEMT;
 370
 371         return 0;
 372 }
 373
 374 static void stm32_set_mctrl(struct uart_port *port, unsigned int mctrl)
 375 {
 376         struct stm32_port *stm32_port = to_stm32_port(port);
 377         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 378
 379         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 380                 stm32_set_bits(port, ofs->cr3, USART_CR3_RTSE);
 381         else
 382                 stm32_clr_bits(port, ofs->cr3, USART_CR3_RTSE);
 383 }
 384
 385 static unsigned int stm32_get_mctrl(struct uart_port *port)
 386 {
 387         /* This routine is used to get signals of: DCD, DSR, RI, and CTS */
 388         return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
 389 }
 390
 391 /* Transmit stop */
 392 static void stm32_stop_tx(struct uart_port *port)
 393 {
 394         struct stm32_port *stm32_port = to_stm32_port(port);
 395         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 396
 397         stm32_clr_bits(port, ofs->cr1, USART_CR1_TXEIE);
 398 }
 399
 400 /* There are probably characters waiting to be transmitted. */
 401 static void stm32_start_tx(struct uart_port *port)
 402 {
 403         struct circ_buf *xmit = &port->state->xmit;
 404
 405         if (uart_circ_empty(xmit) && !port->x_char)
 406                 return;
 407
 408         stm32_transmit_chars(port);
 409 }
 410
 411 /* Throttle the remote when input buffer is about to overflow. */
 412 static void stm32_throttle(struct uart_port *port)
 413 {
 414         struct stm32_port *stm32_port = to_stm32_port(port);
 415         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 416         unsigned long flags;
 417
 418         spin_lock_irqsave(&port->lock, flags);
 419         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 420         spin_unlock_irqrestore(&port->lock, flags);
 421 }
 422
 423 /* Unthrottle the remote, the input buffer can now accept data. */
 424 static void stm32_unthrottle(struct uart_port *port)
 425 {
 426         struct stm32_port *stm32_port = to_stm32_port(port);
 427         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 428         unsigned long flags;
 429
 430         spin_lock_irqsave(&port->lock, flags);
 431         stm32_set_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 432         spin_unlock_irqrestore(&port->lock, flags);
 433 }
 434
 435 /* Receive stop */
 436 static void stm32_stop_rx(struct uart_port *port)
 437 {
 438         struct stm32_port *stm32_port = to_stm32_port(port);
 439         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 440
 441         stm32_clr_bits(port, ofs->cr1, USART_CR1_RXNEIE);
 442 }
 443
 444 /* Handle breaks - ignored by us */
 445 static void stm32_break_ctl(struct uart_port *port, int break_state)
 446 {
 447 }
 448
 449 static int stm32_startup(struct uart_port *port)
 450 {
 451         struct stm32_port *stm32_port = to_stm32_port(port);
 452         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 453         const char *name = to_platform_device(port->dev)->name;
 454         u32 val;
 455         int ret;
 456
 457         ret = request_threaded_irq(port->irq, stm32_interrupt,
 458                                    stm32_threaded_interrupt,
 459                                    IRQF_NO_SUSPEND, name, port);
 460         if (ret)
 461                 return ret;
 462
 463         val = USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 464         if (stm32_port->fifoen)
 465                 val |= USART_CR1_FIFOEN;
 466         stm32_set_bits(port, ofs->cr1, val);
 467
 468         return 0;
 469 }
 470
 471 static void stm32_shutdown(struct uart_port *port)
 472 {
 473         struct stm32_port *stm32_port = to_stm32_port(port);
 474         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 475         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 476         u32 val, isr;
 477         int ret;
 478
 479         val = USART_CR1_TXEIE | USART_CR1_RXNEIE | USART_CR1_TE | USART_CR1_RE;
 480         val |= BIT(cfg->uart_enable_bit);
 481         if (stm32_port->fifoen)
 482                 val |= USART_CR1_FIFOEN;
 483
 484         ret = readl_relaxed_poll_timeout(port->membase + ofs->isr,
 485                                          isr, (isr & USART_SR_TC),
 486                                          10, 100000);
 487
 488         if (ret)
 489                 dev_err(port->dev, "transmission complete not set\n");
 490
 491         stm32_clr_bits(port, ofs->cr1, val);
 492
 493         free_irq(port->irq, port);
 494 }
 495
 496 static void stm32_set_termios(struct uart_port *port, struct ktermios *termios,
 497                             struct ktermios *old)
 498 {
 499         struct stm32_port *stm32_port = to_stm32_port(port);
 500         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 501         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 502         unsigned int baud;
 503         u32 usartdiv, mantissa, fraction, oversampling;
 504         tcflag_t cflag = termios->c_cflag;
 505         u32 cr1, cr2, cr3, isr;
 506         unsigned long flags;
 507         int ret;
 508
 509         if (!stm32_port->hw_flow_control)
 510                 cflag &= ~CRTSCTS;
 511
 512         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 8);
 513
 514         spin_lock_irqsave(&port->lock, flags);
 515
 516         ret = readl_relaxed_poll_timeout_atomic(port->membase + ofs->isr,
 517                                                 isr,
 518                                                 (isr & USART_SR_TC),
 519                                                 10, 100000);
 520
 521         /* Send the TC error message only when ISR_TC is not set. */
 522         if (ret)
 523                 dev_err(port->dev, "Transmission is not complete\n");
 524
 525         /* Stop serial port and reset value */
 526         writel_relaxed(0, port->membase + ofs->cr1);
 527
 528         cr1 = USART_CR1_TE | USART_CR1_RE | USART_CR1_RXNEIE;
 529         cr1 |= BIT(cfg->uart_enable_bit);
 530         if (stm32_port->fifoen)
 531                 cr1 |= USART_CR1_FIFOEN;
 532         cr2 = 0;
 533         cr3 = 0;
 534
 535         if (cflag & CSTOPB)
 536                 cr2 |= USART_CR2_STOP_2B;
 537
 538         if (cflag & PARENB) {
 539                 cr1 |= USART_CR1_PCE;
 540                 if ((cflag & CSIZE) == CS8) {
 541                         if (cfg->has_7bits_data)
 542                                 cr1 |= USART_CR1_M0;
 543                         else
 544                                 cr1 |= USART_CR1_M;
 545                 }
 546         }
 547
 548         if (cflag & PARODD)
 549                 cr1 |= USART_CR1_PS;
 550
 551         port->status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS);
 552         if (cflag & CRTSCTS) {
 553                 port->status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 554                 cr3 |= USART_CR3_CTSE | USART_CR3_RTSE;
 555         }
 556
 557         usartdiv = DIV_ROUND_CLOSEST(port->uartclk, baud);
 558
 559         /*
 560          * The USART supports 16 or 8 times oversampling.
 561          * By default we prefer 16 times oversampling, so that the receiver
 562          * has a better tolerance to clock deviations.
 563          * 8 times oversampling is only used to achieve higher speeds.
 564          */
 565         if (usartdiv < 16) {
 566                 oversampling = 8;
 567                 stm32_set_bits(port, ofs->cr1, USART_CR1_OVER8);
 568         } else {
 569                 oversampling = 16;
 570                 stm32_clr_bits(port, ofs->cr1, USART_CR1_OVER8);
 571         }
 572
 573         mantissa = (usartdiv / oversampling) << USART_BRR_DIV_M_SHIFT;
 574         fraction = usartdiv % oversampling;
 575         writel_relaxed(mantissa | fraction, port->membase + ofs->brr);
 576
 577         uart_update_timeout(port, cflag, baud);
 578
 579         port->read_status_mask = USART_SR_ORE;
 580         if (termios->c_iflag & INPCK)
 581                 port->read_status_mask |= USART_SR_PE | USART_SR_FE;
 582         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
 583                 port->read_status_mask |= USART_SR_FE;
 584
 585         /* Characters to ignore */
 586         port->ignore_status_mask = 0;
 587         if (termios->c_iflag & IGNPAR)
 588                 port->ignore_status_mask = USART_SR_PE | USART_SR_FE;
 589         if (termios->c_iflag & IGNBRK) {
 590                 port->ignore_status_mask |= USART_SR_FE;
 591                 /*
 592                  * If we're ignoring parity and break indicators,
 593                  * ignore overruns too (for real raw support).
 594                  */
 595                 if (termios->c_iflag & IGNPAR)
 596                         port->ignore_status_mask |= USART_SR_ORE;
 597         }
 598
 599         /* Ignore all characters if CREAD is not set */
 600         if ((termios->c_cflag & CREAD) == 0)
 601                 port->ignore_status_mask |= USART_SR_DUMMY_RX;
 602
 603         if (stm32_port->rx_ch)
 604                 cr3 |= USART_CR3_DMAR;
 605
 606         writel_relaxed(cr3, port->membase + ofs->cr3);
 607         writel_relaxed(cr2, port->membase + ofs->cr2);
 608         writel_relaxed(cr1, port->membase + ofs->cr1);
 609
 610         spin_unlock_irqrestore(&port->lock, flags);
 611 }
 612
 613 static const char *stm32_type(struct uart_port *port)
 614 {
 615         return (port->type == PORT_STM32) ? DRIVER_NAME : NULL;
 616 }
 617
 618 static void stm32_release_port(struct uart_port *port)
 619 {
 620 }
 621
 622 static int stm32_request_port(struct uart_port *port)
 623 {
 624         return 0;
 625 }
 626
 627 static void stm32_config_port(struct uart_port *port, int flags)
 628 {
 629         if (flags & UART_CONFIG_TYPE)
 630                 port->type = PORT_STM32;
 631 }
 632
 633 static int
 634 stm32_verify_port(struct uart_port *port, struct serial_struct *ser)
 635 {
 636         /* No user changeable parameters */
 637         return -EINVAL;
 638 }
 639
 640 static void stm32_pm(struct uart_port *port, unsigned int state,
 641                 unsigned int oldstate)
 642 {
 643         struct stm32_port *stm32port = container_of(port,
 644                         struct stm32_port, port);
 645         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 646         struct stm32_usart_config *cfg = &stm32port->info->cfg;
 647         unsigned long flags = 0;
 648
 649         switch (state) {
 650         case UART_PM_STATE_ON:
 651                 clk_prepare_enable(stm32port->clk);
 652                 break;
 653         case UART_PM_STATE_OFF:
 654                 spin_lock_irqsave(&port->lock, flags);
 655                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
 656                 spin_unlock_irqrestore(&port->lock, flags);
 657                 clk_disable_unprepare(stm32port->clk);
 658                 break;
 659         }
 660 }
 661
 662 static const struct uart_ops stm32_uart_ops = {
 663         .tx_empty       = stm32_tx_empty,
 664         .set_mctrl      = stm32_set_mctrl,
 665         .get_mctrl      = stm32_get_mctrl,
 666         .stop_tx        = stm32_stop_tx,
 667         .start_tx       = stm32_start_tx,
 668         .throttle       = stm32_throttle,
 669         .unthrottle     = stm32_unthrottle,
 670         .stop_rx        = stm32_stop_rx,
 671         .break_ctl      = stm32_break_ctl,
 672         .startup        = stm32_startup,
 673         .shutdown       = stm32_shutdown,
 674         .set_termios    = stm32_set_termios,
 675         .pm             = stm32_pm,
 676         .type           = stm32_type,
 677         .release_port   = stm32_release_port,
 678         .request_port   = stm32_request_port,
 679         .config_port    = stm32_config_port,
 680         .verify_port    = stm32_verify_port,
 681 };
 682
 683 static int stm32_init_port(struct stm32_port *stm32port,
 684                           struct platform_device *pdev)
 685 {
 686         struct uart_port *port = &stm32port->port;
 687         struct resource *res;
 688         int ret;
 689
 690         port->iotype    = UPIO_MEM;
 691         port->flags     = UPF_BOOT_AUTOCONF;
 692         port->ops       = &stm32_uart_ops;
 693         port->dev       = &pdev->dev;
 694         port->irq       = platform_get_irq(pdev, 0);
 695         stm32port->wakeirq = platform_get_irq(pdev, 1);
 696         stm32port->fifoen = stm32port->info->cfg.has_fifo;
 697
 698         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 699         port->membase = devm_ioremap_resource(&pdev->dev, res);
 700         if (IS_ERR(port->membase))
 701                 return PTR_ERR(port->membase);
 702         port->mapbase = res->start;
 703
 704         spin_lock_init(&port->lock);
 705
 706         stm32port->clk = devm_clk_get(&pdev->dev, NULL);
 707         if (IS_ERR(stm32port->clk))
 708                 return PTR_ERR(stm32port->clk);
 709
 710         /* Ensure that clk rate is correct by enabling the clk */
 711         ret = clk_prepare_enable(stm32port->clk);
 712         if (ret)
 713                 return ret;
 714
 715         stm32port->port.uartclk = clk_get_rate(stm32port->clk);
 716         if (!stm32port->port.uartclk) {
 717                 clk_disable_unprepare(stm32port->clk);
 718                 ret = -EINVAL;
 719         }
 720
 721         return ret;
 722 }
 723
 724 static struct stm32_port *stm32_of_get_stm32_port(struct platform_device *pdev)
 725 {
 726         struct device_node *np = pdev->dev.of_node;
 727         int id;
 728
 729         if (!np)
 730                 return NULL;
 731
 732         id = of_alias_get_id(np, "serial");
 733         if (id < 0) {
 734                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", id);
 735                 return NULL;
 736         }
 737
 738         if (WARN_ON(id >= STM32_MAX_PORTS))
 739                 return NULL;
 740
 741         stm32_ports[id].hw_flow_control = of_property_read_bool(np,
 742                                                         "st,hw-flow-ctrl");
 743         stm32_ports[id].port.line = id;
 744         stm32_ports[id].last_res = RX_BUF_L;
 745         return &stm32_ports[id];
 746 }
 747
 748 #ifdef CONFIG_OF
 749 static const struct of_device_id stm32_match[] = {
 750         { .compatible = "st,stm32-usart", .data = &stm32f4_info},
 751         { .compatible = "st,stm32-uart", .data = &stm32f4_info},
 752         { .compatible = "st,stm32f7-usart", .data = &stm32f7_info},
 753         { .compatible = "st,stm32f7-uart", .data = &stm32f7_info},
 754         { .compatible = "st,stm32h7-usart", .data = &stm32h7_info},
 755         { .compatible = "st,stm32h7-uart", .data = &stm32h7_info},
 756         {},
 757 };
 758
 759 MODULE_DEVICE_TABLE(of, stm32_match);
 760 #endif
 761
 762 static int stm32_of_dma_rx_probe(struct stm32_port *stm32port,
 763                                  struct platform_device *pdev)
 764 {
 765         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 766         struct uart_port *port = &stm32port->port;
 767         struct device *dev = &pdev->dev;
 768         struct dma_slave_config config;
 769         struct dma_async_tx_descriptor *desc = NULL;
 770         dma_cookie_t cookie;
 771         int ret;
 772
 773         /* Request DMA RX channel */
 774         stm32port->rx_ch = dma_request_slave_channel(dev, "rx");
 775         if (!stm32port->rx_ch) {
 776                 dev_info(dev, "rx dma alloc failed\n");
 777                 return -ENODEV;
 778         }
 779         stm32port->rx_buf = dma_alloc_coherent(&pdev->dev, RX_BUF_L,
 780                                                  &stm32port->rx_dma_buf,
 781                                                  GFP_KERNEL);
 782         if (!stm32port->rx_buf) {
 783                 ret = -ENOMEM;
 784                 goto alloc_err;
 785         }
 786
 787         /* Configure DMA channel */
 788         memset(&config, 0, sizeof(config));
 789         config.src_addr = port->mapbase + ofs->rdr;
 790         config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 791
 792         ret = dmaengine_slave_config(stm32port->rx_ch, &config);
 793         if (ret < 0) {
 794                 dev_err(dev, "rx dma channel config failed\n");
 795                 ret = -ENODEV;
 796                 goto config_err;
 797         }
 798
 799         /* Prepare a DMA cyclic transaction */
 800         desc = dmaengine_prep_dma_cyclic(stm32port->rx_ch,
 801                                          stm32port->rx_dma_buf,
 802                                          RX_BUF_L, RX_BUF_P, DMA_DEV_TO_MEM,
 803                                          DMA_PREP_INTERRUPT);
 804         if (!desc) {
 805                 dev_err(dev, "rx dma prep cyclic failed\n");
 806                 ret = -ENODEV;
 807                 goto config_err;
 808         }
 809
 810         /* No callback as dma buffer is drained on usart interrupt */
 811         desc->callback = NULL;
 812         desc->callback_param = NULL;
 813
 814         /* Push current DMA transaction in the pending queue */
 815         cookie = dmaengine_submit(desc);
 816
 817         /* Issue pending DMA requests */
 818         dma_async_issue_pending(stm32port->rx_ch);
 819
 820         return 0;
 821
 822 config_err:
 823         dma_free_coherent(&pdev->dev,
 824                           RX_BUF_L, stm32port->rx_buf,
 825                           stm32port->rx_dma_buf);
 826
 827 alloc_err:
 828         dma_release_channel(stm32port->rx_ch);
 829         stm32port->rx_ch = NULL;
 830
 831         return ret;
 832 }
 833
 834 static int stm32_of_dma_tx_probe(struct stm32_port *stm32port,
 835                                  struct platform_device *pdev)
 836 {
 837         struct stm32_usart_offsets *ofs = &stm32port->info->ofs;
 838         struct uart_port *port = &stm32port->port;
 839         struct device *dev = &pdev->dev;
 840         struct dma_slave_config config;
 841         int ret;
 842
 843         stm32port->tx_dma_busy = false;
 844
 845         /* Request DMA TX channel */
 846         stm32port->tx_ch = dma_request_slave_channel(dev, "tx");
 847         if (!stm32port->tx_ch) {
 848                 dev_info(dev, "tx dma alloc failed\n");
 849                 return -ENODEV;
 850         }
 851         stm32port->tx_buf = dma_alloc_coherent(&pdev->dev, TX_BUF_L,
 852                                                  &stm32port->tx_dma_buf,
 853                                                  GFP_KERNEL);
 854         if (!stm32port->tx_buf) {
 855                 ret = -ENOMEM;
 856                 goto alloc_err;
 857         }
 858
 859         /* Configure DMA channel */
 860         memset(&config, 0, sizeof(config));
 861         config.dst_addr = port->mapbase + ofs->tdr;
 862         config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
 863
 864         ret = dmaengine_slave_config(stm32port->tx_ch, &config);
 865         if (ret < 0) {
 866                 dev_err(dev, "tx dma channel config failed\n");
 867                 ret = -ENODEV;
 868                 goto config_err;
 869         }
 870
 871         return 0;
 872
 873 config_err:
 874         dma_free_coherent(&pdev->dev,
 875                           TX_BUF_L, stm32port->tx_buf,
 876                           stm32port->tx_dma_buf);
 877
 878 alloc_err:
 879         dma_release_channel(stm32port->tx_ch);
 880         stm32port->tx_ch = NULL;
 881
 882         return ret;
 883 }
 884
 885 static int stm32_serial_probe(struct platform_device *pdev)
 886 {
 887         const struct of_device_id *match;
 888         struct stm32_port *stm32port;
 889         int ret;
 890
 891         stm32port = stm32_of_get_stm32_port(pdev);
 892         if (!stm32port)
 893                 return -ENODEV;
 894
 895         match = of_match_device(stm32_match, &pdev->dev);
 896         if (match && match->data)
 897                 stm32port->info = (struct stm32_usart_info *)match->data;
 898         else
 899                 return -EINVAL;
 900
 901         ret = stm32_init_port(stm32port, pdev);
 902         if (ret)
 903                 return ret;
 904
 905         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0) {
 906                 ret = device_init_wakeup(&pdev->dev, true);
 907                 if (ret)
 908                         goto err_uninit;
 909
 910                 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
 911                                                     stm32port->wakeirq);
 912                 if (ret)
 913                         goto err_nowup;
 914
 915                 device_set_wakeup_enable(&pdev->dev, false);
 916         }
 917
 918         ret = uart_add_one_port(&stm32_usart_driver, &stm32port->port);
 919         if (ret)
 920                 goto err_wirq;
 921
 922         ret = stm32_of_dma_rx_probe(stm32port, pdev);
 923         if (ret)
 924                 dev_info(&pdev->dev, "interrupt mode used for rx (no dma)\n");
 925
 926         ret = stm32_of_dma_tx_probe(stm32port, pdev);
 927         if (ret)
 928                 dev_info(&pdev->dev, "interrupt mode used for tx (no dma)\n");
 929
 930         platform_set_drvdata(pdev, &stm32port->port);
 931
 932         return 0;
 933
 934 err_wirq:
 935         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
 936                 dev_pm_clear_wake_irq(&pdev->dev);
 937
 938 err_nowup:
 939         if (stm32port->info->cfg.has_wakeup && stm32port->wakeirq >= 0)
 940                 device_init_wakeup(&pdev->dev, false);
 941
 942 err_uninit:
 943         clk_disable_unprepare(stm32port->clk);
 944
 945         return ret;
 946 }
 947
 948 static int stm32_serial_remove(struct platform_device *pdev)
 949 {
 950         struct uart_port *port = platform_get_drvdata(pdev);
 951         struct stm32_port *stm32_port = to_stm32_port(port);
 952         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 953         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
 954
 955         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
 956
 957         if (stm32_port->rx_ch)
 958                 dma_release_channel(stm32_port->rx_ch);
 959
 960         if (stm32_port->rx_dma_buf)
 961                 dma_free_coherent(&pdev->dev,
 962                                   RX_BUF_L, stm32_port->rx_buf,
 963                                   stm32_port->rx_dma_buf);
 964
 965         stm32_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
 966
 967         if (stm32_port->tx_ch)
 968                 dma_release_channel(stm32_port->tx_ch);
 969
 970         if (stm32_port->tx_dma_buf)
 971                 dma_free_coherent(&pdev->dev,
 972                                   TX_BUF_L, stm32_port->tx_buf,
 973                                   stm32_port->tx_dma_buf);
 974
 975         if (cfg->has_wakeup && stm32_port->wakeirq >= 0) {
 976                 dev_pm_clear_wake_irq(&pdev->dev);
 977                 device_init_wakeup(&pdev->dev, false);
 978         }
 979
 980         clk_disable_unprepare(stm32_port->clk);
 981
 982         return uart_remove_one_port(&stm32_usart_driver, port);
 983 }
 984
 985
 986 #ifdef CONFIG_SERIAL_STM32_CONSOLE
 987 static void stm32_console_putchar(struct uart_port *port, int ch)
 988 {
 989         struct stm32_port *stm32_port = to_stm32_port(port);
 990         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
 991
 992         while (!(readl_relaxed(port->membase + ofs->isr) & USART_SR_TXE))
 993                 cpu_relax();
 994
 995         writel_relaxed(ch, port->membase + ofs->tdr);
 996 }
 997
 998 static void stm32_console_write(struct console *co, const char *s, unsigned cnt)
 999 {
1000         struct uart_port *port = &stm32_ports[co->index].port;
1001         struct stm32_port *stm32_port = to_stm32_port(port);
1002         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1003         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1004         unsigned long flags;
1005         u32 old_cr1, new_cr1;
1006         int locked = 1;
1007
1008         local_irq_save(flags);
1009         if (port->sysrq)
1010                 locked = 0;
1011         else if (oops_in_progress)
1012                 locked = spin_trylock(&port->lock);
1013         else
1014                 spin_lock(&port->lock);
1015
1016         /* Save and disable interrupts, enable the transmitter */
1017         old_cr1 = readl_relaxed(port->membase + ofs->cr1);
1018         new_cr1 = old_cr1 & ~USART_CR1_IE_MASK;
1019         new_cr1 |=  USART_CR1_TE | BIT(cfg->uart_enable_bit);
1020         writel_relaxed(new_cr1, port->membase + ofs->cr1);
1021
1022         uart_console_write(port, s, cnt, stm32_console_putchar);
1023
1024         /* Restore interrupt state */
1025         writel_relaxed(old_cr1, port->membase + ofs->cr1);
1026
1027         if (locked)
1028                 spin_unlock(&port->lock);
1029         local_irq_restore(flags);
1030 }
1031
1032 static int stm32_console_setup(struct console *co, char *options)
1033 {
1034         struct stm32_port *stm32port;
1035         int baud = 9600;
1036         int bits = 8;
1037         int parity = 'n';
1038         int flow = 'n';
1039
1040         if (co->index >= STM32_MAX_PORTS)
1041                 return -ENODEV;
1042
1043         stm32port = &stm32_ports[co->index];
1044
1045         /*
1046          * This driver does not support early console initialization
1047          * (use ARM early printk support instead), so we only expect
1048          * this to be called during the uart port registration when the
1049          * driver gets probed and the port should be mapped at that point.
1050          */
1051         if (stm32port->port.mapbase == 0 || stm32port->port.membase == NULL)
1052                 return -ENXIO;
1053
1054         if (options)
1055                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1056
1057         return uart_set_options(&stm32port->port, co, baud, parity, bits, flow);
1058 }
1059
1060 static struct console stm32_console = {
1061         .name           = STM32_SERIAL_NAME,
1062         .device         = uart_console_device,
1063         .write          = stm32_console_write,
1064         .setup          = stm32_console_setup,
1065         .flags          = CON_PRINTBUFFER,
1066         .index          = -1,
1067         .data           = &stm32_usart_driver,
1068 };
1069
1070 #define STM32_SERIAL_CONSOLE (&stm32_console)
1071
1072 #else
1073 #define STM32_SERIAL_CONSOLE NULL
1074 #endif /* CONFIG_SERIAL_STM32_CONSOLE */
1075
1076 static struct uart_driver stm32_usart_driver = {
1077         .driver_name    = DRIVER_NAME,
1078         .dev_name       = STM32_SERIAL_NAME,
1079         .major          = 0,
1080         .minor          = 0,
1081         .nr             = STM32_MAX_PORTS,
1082         .cons           = STM32_SERIAL_CONSOLE,
1083 };
1084
1085 #ifdef CONFIG_PM_SLEEP
1086 static void stm32_serial_enable_wakeup(struct uart_port *port, bool enable)
1087 {
1088         struct stm32_port *stm32_port = to_stm32_port(port);
1089         struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
1090         struct stm32_usart_config *cfg = &stm32_port->info->cfg;
1091         u32 val;
1092
1093         if (!cfg->has_wakeup || stm32_port->wakeirq < 0)
1094                 return;
1095
1096         if (enable) {
1097                 stm32_clr_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1098                 stm32_set_bits(port, ofs->cr1, USART_CR1_UESM);
1099                 val = readl_relaxed(port->membase + ofs->cr3);
1100                 val &= ~USART_CR3_WUS_MASK;
1101                 /* Enable Wake up interrupt from low power on start bit */
1102                 val |= USART_CR3_WUS_START_BIT | USART_CR3_WUFIE;
1103                 writel_relaxed(val, port->membase + ofs->cr3);
1104                 stm32_set_bits(port, ofs->cr1, BIT(cfg->uart_enable_bit));
1105         } else {
1106                 stm32_clr_bits(port, ofs->cr1, USART_CR1_UESM);
1107         }
1108 }
1109
1110 static int stm32_serial_suspend(struct device *dev)
1111 {
1112         struct uart_port *port = dev_get_drvdata(dev);
1113
1114         uart_suspend_port(&stm32_usart_driver, port);
1115
1116         if (device_may_wakeup(dev))
1117                 stm32_serial_enable_wakeup(port, true);
1118         else
1119                 stm32_serial_enable_wakeup(port, false);
1120
1121         return 0;
1122 }
1123
1124 static int stm32_serial_resume(struct device *dev)
1125 {
1126         struct uart_port *port = dev_get_drvdata(dev);
1127
1128         if (device_may_wakeup(dev))
1129                 stm32_serial_enable_wakeup(port, false);
1130
1131         return uart_resume_port(&stm32_usart_driver, port);
1132 }
1133 #endif /* CONFIG_PM_SLEEP */
1134
1135 static const struct dev_pm_ops stm32_serial_pm_ops = {
1136         SET_SYSTEM_SLEEP_PM_OPS(stm32_serial_suspend, stm32_serial_resume)
1137 };
1138
1139 static struct platform_driver stm32_serial_driver = {
1140         .probe          = stm32_serial_probe,
1141         .remove         = stm32_serial_remove,
1142         .driver = {
1143                 .name   = DRIVER_NAME,
1144                 .pm     = &stm32_serial_pm_ops,
1145                 .of_match_table = of_match_ptr(stm32_match),
1146         },
1147 };
1148
1149 static int __init usart_init(void)
1150 {
1151         static char banner[] __initdata = "STM32 USART driver initialized";
1152         int ret;
1153
1154         pr_info("%s\n", banner);
1155
1156         ret = uart_register_driver(&stm32_usart_driver);
1157         if (ret)
1158                 return ret;
1159
1160         ret = platform_driver_register(&stm32_serial_driver);
1161         if (ret)
1162                 uart_unregister_driver(&stm32_usart_driver);
1163
1164         return ret;
1165 }
1166
1167 static void __exit usart_exit(void)
1168 {
1169         platform_driver_unregister(&stm32_serial_driver);
1170         uart_unregister_driver(&stm32_usart_driver);
1171 }
1172
1173 module_init(usart_init);
1174 module_exit(usart_exit);
1175
1176 MODULE_ALIAS("platform:" DRIVER_NAME);
1177 MODULE_DESCRIPTION("STMicroelectronics STM32 serial port driver");
1178 MODULE_LICENSE("GPL v2");