2 * Cadence UART driver (found in Xilinx Zynq)
4 * 2011 - 2014 (C) Xilinx Inc.
6 * This program is free software; you can redistribute it
7 * and/or modify it under the terms of the GNU General Public
8 * License as published by the Free Software Foundation;
9 * either version 2 of the License, or (at your option) any
12 * This driver has originally been pushed by Xilinx using a Zynq-branding. This
13 * still shows in the naming of this file, the kconfig symbols and some symbols
17 #if defined(CONFIG_SERIAL_XILINX_PS_UART_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #include <linux/platform_device.h>
22 #include <linux/serial.h>
23 #include <linux/console.h>
24 #include <linux/serial_core.h>
25 #include <linux/slab.h>
26 #include <linux/tty.h>
27 #include <linux/tty_flip.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
32 #include <linux/module.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/iopoll.h>
36 #define CDNS_UART_TTY_NAME "ttyPS"
37 #define CDNS_UART_NAME "xuartps"
38 #define CDNS_UART_MAJOR 0 /* use dynamic node allocation */
39 #define CDNS_UART_MINOR 0 /* works best with devtmpfs */
40 #define CDNS_UART_NR_PORTS 2
41 #define CDNS_UART_FIFO_SIZE 64 /* FIFO size */
42 #define CDNS_UART_REGISTER_SPACE 0x1000
43 #define TX_TIMEOUT 500000
45 /* Rx Trigger level */
46 static int rx_trigger_level = 56;
47 module_param(rx_trigger_level, uint, S_IRUGO);
48 MODULE_PARM_DESC(rx_trigger_level, "Rx trigger level, 1-63 bytes");
51 static int rx_timeout = 10;
52 module_param(rx_timeout, uint, S_IRUGO);
53 MODULE_PARM_DESC(rx_timeout, "Rx timeout, 1-255");
55 /* Register offsets for the UART. */
56 #define CDNS_UART_CR 0x00 /* Control Register */
57 #define CDNS_UART_MR 0x04 /* Mode Register */
58 #define CDNS_UART_IER 0x08 /* Interrupt Enable */
59 #define CDNS_UART_IDR 0x0C /* Interrupt Disable */
60 #define CDNS_UART_IMR 0x10 /* Interrupt Mask */
61 #define CDNS_UART_ISR 0x14 /* Interrupt Status */
62 #define CDNS_UART_BAUDGEN 0x18 /* Baud Rate Generator */
63 #define CDNS_UART_RXTOUT 0x1C /* RX Timeout */
64 #define CDNS_UART_RXWM 0x20 /* RX FIFO Trigger Level */
65 #define CDNS_UART_MODEMCR 0x24 /* Modem Control */
66 #define CDNS_UART_MODEMSR 0x28 /* Modem Status */
67 #define CDNS_UART_SR 0x2C /* Channel Status */
68 #define CDNS_UART_FIFO 0x30 /* FIFO */
69 #define CDNS_UART_BAUDDIV 0x34 /* Baud Rate Divider */
70 #define CDNS_UART_FLOWDEL 0x38 /* Flow Delay */
71 #define CDNS_UART_IRRX_PWIDTH 0x3C /* IR Min Received Pulse Width */
72 #define CDNS_UART_IRTX_PWIDTH 0x40 /* IR Transmitted pulse Width */
73 #define CDNS_UART_TXWM 0x44 /* TX FIFO Trigger Level */
74 #define CDNS_UART_RXBS 0x48 /* RX FIFO byte status register */
76 /* Control Register Bit Definitions */
77 #define CDNS_UART_CR_STOPBRK 0x00000100 /* Stop TX break */
78 #define CDNS_UART_CR_STARTBRK 0x00000080 /* Set TX break */
79 #define CDNS_UART_CR_TX_DIS 0x00000020 /* TX disabled. */
80 #define CDNS_UART_CR_TX_EN 0x00000010 /* TX enabled */
81 #define CDNS_UART_CR_RX_DIS 0x00000008 /* RX disabled. */
82 #define CDNS_UART_CR_RX_EN 0x00000004 /* RX enabled */
83 #define CDNS_UART_CR_TXRST 0x00000002 /* TX logic reset */
84 #define CDNS_UART_CR_RXRST 0x00000001 /* RX logic reset */
85 #define CDNS_UART_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
86 #define CDNS_UART_RXBS_PARITY 0x00000001 /* Parity error status */
87 #define CDNS_UART_RXBS_FRAMING 0x00000002 /* Framing error status */
88 #define CDNS_UART_RXBS_BRK 0x00000004 /* Overrun error status */
92 * The mode register (MR) defines the mode of transfer as well as the data
93 * format. If this register is modified during transmission or reception,
94 * data validity cannot be guaranteed.
96 #define CDNS_UART_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
97 #define CDNS_UART_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
98 #define CDNS_UART_MR_CHMODE_NORM 0x00000000 /* Normal mode */
99 #define CDNS_UART_MR_CHMODE_MASK 0x00000300 /* Mask for mode bits */
101 #define CDNS_UART_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
102 #define CDNS_UART_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
104 #define CDNS_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
105 #define CDNS_UART_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
106 #define CDNS_UART_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
107 #define CDNS_UART_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
108 #define CDNS_UART_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
110 #define CDNS_UART_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
111 #define CDNS_UART_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
112 #define CDNS_UART_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
115 * Interrupt Registers:
116 * Interrupt control logic uses the interrupt enable register (IER) and the
117 * interrupt disable register (IDR) to set the value of the bits in the
118 * interrupt mask register (IMR). The IMR determines whether to pass an
119 * interrupt to the interrupt status register (ISR).
120 * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
121 * interrupt. IMR and ISR are read only, and IER and IDR are write only.
122 * Reading either IER or IDR returns 0x00.
123 * All four registers have the same bit definitions.
125 #define CDNS_UART_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
126 #define CDNS_UART_IXR_PARITY 0x00000080 /* Parity error interrupt */
127 #define CDNS_UART_IXR_FRAMING 0x00000040 /* Framing error interrupt */
128 #define CDNS_UART_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
129 #define CDNS_UART_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
130 #define CDNS_UART_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
131 #define CDNS_UART_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
132 #define CDNS_UART_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
133 #define CDNS_UART_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
134 #define CDNS_UART_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
135 #define CDNS_UART_IXR_RXMASK 0x000021e7 /* Valid RX bit mask */
138 * Do not enable parity error interrupt for the following
139 * reason: When parity error interrupt is enabled, each Rx
140 * parity error always results in 2 events. The first one
141 * being parity error interrupt and the second one with a
142 * proper Rx interrupt with the incoming data. Disabling
143 * parity error interrupt ensures better handling of parity
144 * error events. With this change, for a parity error case, we
145 * get a Rx interrupt with parity error set in ISR register
146 * and we still handle parity errors in the desired way.
149 #define CDNS_UART_RX_IRQS (CDNS_UART_IXR_FRAMING | \
150 CDNS_UART_IXR_OVERRUN | \
151 CDNS_UART_IXR_RXTRIG | \
154 /* Goes in read_status_mask for break detection as the HW doesn't do it*/
155 #define CDNS_UART_IXR_BRK 0x00002000
157 #define CDNS_UART_RXBS_SUPPORT BIT(1)
159 * Modem Control register:
160 * The read/write Modem Control register controls the interface with the modem
161 * or data set, or a peripheral device emulating a modem.
163 #define CDNS_UART_MODEMCR_FCM 0x00000020 /* Automatic flow control mode */
164 #define CDNS_UART_MODEMCR_RTS 0x00000002 /* Request to send output control */
165 #define CDNS_UART_MODEMCR_DTR 0x00000001 /* Data Terminal Ready */
168 * Channel Status Register:
169 * The channel status register (CSR) is provided to enable the control logic
170 * to monitor the status of bits in the channel interrupt status register,
171 * even if these are masked out by the interrupt mask register.
173 #define CDNS_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
174 #define CDNS_UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
175 #define CDNS_UART_SR_TXFULL 0x00000010 /* TX FIFO full */
176 #define CDNS_UART_SR_RXTRIG 0x00000001 /* Rx Trigger */
178 /* baud dividers min/max values */
179 #define CDNS_UART_BDIV_MIN 4
180 #define CDNS_UART_BDIV_MAX 255
181 #define CDNS_UART_CD_MAX 65535
182 #define UART_AUTOSUSPEND_TIMEOUT 3000
185 * struct cdns_uart - device data
186 * @port: Pointer to the UART port
187 * @uartclk: Reference clock
189 * @baud: Current baud rate
190 * @clk_rate_change_nb: Notifier block for clock changes
191 * @quirks: Flags for RXBS support.
194 struct uart_port *port;
198 struct notifier_block clk_rate_change_nb;
201 struct cdns_platform_data {
204 #define to_cdns_uart(_nb) container_of(_nb, struct cdns_uart, \
208 * cdns_uart_handle_rx - Handle the received bytes along with Rx errors.
209 * @dev_id: Id of the UART port
210 * @isrstatus: The interrupt status register value as read
213 static void cdns_uart_handle_rx(void *dev_id, unsigned int isrstatus)
215 struct uart_port *port = (struct uart_port *)dev_id;
216 struct cdns_uart *cdns_uart = port->private_data;
218 unsigned int rxbs_status = 0;
219 unsigned int status_mask;
220 unsigned int framerrprocessed = 0;
221 char status = TTY_NORMAL;
222 bool is_rxbs_support;
224 is_rxbs_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
226 while ((readl(port->membase + CDNS_UART_SR) &
227 CDNS_UART_SR_RXEMPTY) != CDNS_UART_SR_RXEMPTY) {
229 rxbs_status = readl(port->membase + CDNS_UART_RXBS);
230 data = readl(port->membase + CDNS_UART_FIFO);
233 * There is no hardware break detection in Zynq, so we interpret
234 * framing error with all-zeros data as a break sequence.
235 * Most of the time, there's another non-zero byte at the
236 * end of the sequence.
238 if (!is_rxbs_support && (isrstatus & CDNS_UART_IXR_FRAMING)) {
240 port->read_status_mask |= CDNS_UART_IXR_BRK;
241 framerrprocessed = 1;
245 if (is_rxbs_support && (rxbs_status & CDNS_UART_RXBS_BRK)) {
248 if (uart_handle_break(port))
252 isrstatus &= port->read_status_mask;
253 isrstatus &= ~port->ignore_status_mask;
254 status_mask = port->read_status_mask;
255 status_mask &= ~port->ignore_status_mask;
258 (port->read_status_mask & CDNS_UART_IXR_BRK)) {
259 port->read_status_mask &= ~CDNS_UART_IXR_BRK;
261 if (uart_handle_break(port))
265 if (uart_handle_sysrq_char(port, data))
268 if (is_rxbs_support) {
269 if ((rxbs_status & CDNS_UART_RXBS_PARITY)
270 && (status_mask & CDNS_UART_IXR_PARITY)) {
271 port->icount.parity++;
274 if ((rxbs_status & CDNS_UART_RXBS_FRAMING)
275 && (status_mask & CDNS_UART_IXR_PARITY)) {
276 port->icount.frame++;
280 if (isrstatus & CDNS_UART_IXR_PARITY) {
281 port->icount.parity++;
284 if ((isrstatus & CDNS_UART_IXR_FRAMING) &&
286 port->icount.frame++;
290 if (isrstatus & CDNS_UART_IXR_OVERRUN) {
291 port->icount.overrun++;
292 tty_insert_flip_char(&port->state->port, 0,
295 tty_insert_flip_char(&port->state->port, data, status);
298 spin_unlock(&port->lock);
299 tty_flip_buffer_push(&port->state->port);
300 spin_lock(&port->lock);
304 * cdns_uart_handle_tx - Handle the bytes to be Txed.
305 * @dev_id: Id of the UART port
308 static void cdns_uart_handle_tx(void *dev_id)
310 struct uart_port *port = (struct uart_port *)dev_id;
311 unsigned int numbytes;
313 if (uart_circ_empty(&port->state->xmit)) {
314 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IDR);
316 numbytes = port->fifosize;
317 while (numbytes && !uart_circ_empty(&port->state->xmit) &&
318 !(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXFULL)) {
320 * Get the data from the UART circular buffer
321 * and write it to the cdns_uart's TX_FIFO
325 port->state->xmit.buf[port->state->xmit.
326 tail], port->membase + CDNS_UART_FIFO);
331 * Adjust the tail of the UART buffer and wrap
332 * the buffer if it reaches limit.
334 port->state->xmit.tail =
335 (port->state->xmit.tail + 1) &
336 (UART_XMIT_SIZE - 1);
341 if (uart_circ_chars_pending(
342 &port->state->xmit) < WAKEUP_CHARS)
343 uart_write_wakeup(port);
348 * cdns_uart_isr - Interrupt handler
350 * @dev_id: Id of the port
354 static irqreturn_t cdns_uart_isr(int irq, void *dev_id)
356 struct uart_port *port = (struct uart_port *)dev_id;
357 unsigned int isrstatus;
359 spin_lock(&port->lock);
361 /* Read the interrupt status register to determine which
362 * interrupt(s) is/are active and clear them.
364 isrstatus = readl(port->membase + CDNS_UART_ISR);
365 writel(isrstatus, port->membase + CDNS_UART_ISR);
367 if (isrstatus & CDNS_UART_IXR_TXEMPTY) {
368 cdns_uart_handle_tx(dev_id);
369 isrstatus &= ~CDNS_UART_IXR_TXEMPTY;
373 * Skip RX processing if RX is disabled as RXEMPTY will never be set
374 * as read bytes will not be removed from the FIFO.
376 if (isrstatus & CDNS_UART_IXR_RXMASK &&
377 !(readl(port->membase + CDNS_UART_CR) & CDNS_UART_CR_RX_DIS))
378 cdns_uart_handle_rx(dev_id, isrstatus);
380 spin_unlock(&port->lock);
385 * cdns_uart_calc_baud_divs - Calculate baud rate divisors
386 * @clk: UART module input clock
387 * @baud: Desired baud rate
388 * @rbdiv: BDIV value (return value)
389 * @rcd: CD value (return value)
390 * @div8: Value for clk_sel bit in mod (return value)
391 * Return: baud rate, requested baud when possible, or actual baud when there
392 * was too much error, zero if no valid divisors are found.
394 * Formula to obtain baud rate is
395 * baud_tx/rx rate = clk/CD * (BDIV + 1)
396 * input_clk = (Uart User Defined Clock or Apb Clock)
397 * depends on UCLKEN in MR Reg
398 * clk = input_clk or input_clk/8;
399 * depends on CLKS in MR reg
400 * CD and BDIV depends on values in
401 * baud rate generate register
402 * baud rate clock divisor register
404 static unsigned int cdns_uart_calc_baud_divs(unsigned int clk,
405 unsigned int baud, u32 *rbdiv, u32 *rcd, int *div8)
408 unsigned int calc_baud;
409 unsigned int bestbaud = 0;
410 unsigned int bauderror;
411 unsigned int besterror = ~0;
413 if (baud < clk / ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX)) {
420 for (bdiv = CDNS_UART_BDIV_MIN; bdiv <= CDNS_UART_BDIV_MAX; bdiv++) {
421 cd = DIV_ROUND_CLOSEST(clk, baud * (bdiv + 1));
422 if (cd < 1 || cd > CDNS_UART_CD_MAX)
425 calc_baud = clk / (cd * (bdiv + 1));
427 if (baud > calc_baud)
428 bauderror = baud - calc_baud;
430 bauderror = calc_baud - baud;
432 if (besterror > bauderror) {
435 bestbaud = calc_baud;
436 besterror = bauderror;
439 /* use the values when percent error is acceptable */
440 if (((besterror * 100) / baud) < 3)
447 * cdns_uart_set_baud_rate - Calculate and set the baud rate
448 * @port: Handle to the uart port structure
449 * @baud: Baud rate to set
450 * Return: baud rate, requested baud when possible, or actual baud when there
451 * was too much error, zero if no valid divisors are found.
453 static unsigned int cdns_uart_set_baud_rate(struct uart_port *port,
456 unsigned int calc_baud;
457 u32 cd = 0, bdiv = 0;
460 struct cdns_uart *cdns_uart = port->private_data;
462 calc_baud = cdns_uart_calc_baud_divs(port->uartclk, baud, &bdiv, &cd,
465 /* Write new divisors to hardware */
466 mreg = readl(port->membase + CDNS_UART_MR);
468 mreg |= CDNS_UART_MR_CLKSEL;
470 mreg &= ~CDNS_UART_MR_CLKSEL;
471 writel(mreg, port->membase + CDNS_UART_MR);
472 writel(cd, port->membase + CDNS_UART_BAUDGEN);
473 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
474 cdns_uart->baud = baud;
479 #ifdef CONFIG_COMMON_CLK
481 * cdns_uart_clk_notitifer_cb - Clock notifier callback
482 * @nb: Notifier block
483 * @event: Notify event
484 * @data: Notifier data
485 * Return: NOTIFY_OK or NOTIFY_DONE on success, NOTIFY_BAD on error.
487 static int cdns_uart_clk_notifier_cb(struct notifier_block *nb,
488 unsigned long event, void *data)
491 struct uart_port *port;
493 struct clk_notifier_data *ndata = data;
494 unsigned long flags = 0;
495 struct cdns_uart *cdns_uart = to_cdns_uart(nb);
497 port = cdns_uart->port;
502 case PRE_RATE_CHANGE:
508 * Find out if current baud-rate can be achieved with new clock
511 if (!cdns_uart_calc_baud_divs(ndata->new_rate, cdns_uart->baud,
512 &bdiv, &cd, &div8)) {
513 dev_warn(port->dev, "clock rate change rejected\n");
517 spin_lock_irqsave(&cdns_uart->port->lock, flags);
519 /* Disable the TX and RX to set baud rate */
520 ctrl_reg = readl(port->membase + CDNS_UART_CR);
521 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
522 writel(ctrl_reg, port->membase + CDNS_UART_CR);
524 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
528 case POST_RATE_CHANGE:
530 * Set clk dividers to generate correct baud with new clock
534 spin_lock_irqsave(&cdns_uart->port->lock, flags);
537 port->uartclk = ndata->new_rate;
539 cdns_uart->baud = cdns_uart_set_baud_rate(cdns_uart->port,
542 case ABORT_RATE_CHANGE:
544 spin_lock_irqsave(&cdns_uart->port->lock, flags);
546 /* Set TX/RX Reset */
547 ctrl_reg = readl(port->membase + CDNS_UART_CR);
548 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
549 writel(ctrl_reg, port->membase + CDNS_UART_CR);
551 while (readl(port->membase + CDNS_UART_CR) &
552 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
556 * Clear the RX disable and TX disable bits and then set the TX
557 * enable bit and RX enable bit to enable the transmitter and
560 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
561 ctrl_reg = readl(port->membase + CDNS_UART_CR);
562 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
563 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
564 writel(ctrl_reg, port->membase + CDNS_UART_CR);
566 spin_unlock_irqrestore(&cdns_uart->port->lock, flags);
576 * cdns_uart_start_tx - Start transmitting bytes
577 * @port: Handle to the uart port structure
579 static void cdns_uart_start_tx(struct uart_port *port)
583 if (uart_tx_stopped(port))
587 * Set the TX enable bit and clear the TX disable bit to enable the
590 status = readl(port->membase + CDNS_UART_CR);
591 status &= ~CDNS_UART_CR_TX_DIS;
592 status |= CDNS_UART_CR_TX_EN;
593 writel(status, port->membase + CDNS_UART_CR);
595 if (uart_circ_empty(&port->state->xmit))
598 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_ISR);
600 cdns_uart_handle_tx(port);
602 /* Enable the TX Empty interrupt */
603 writel(CDNS_UART_IXR_TXEMPTY, port->membase + CDNS_UART_IER);
607 * cdns_uart_stop_tx - Stop TX
608 * @port: Handle to the uart port structure
610 static void cdns_uart_stop_tx(struct uart_port *port)
614 regval = readl(port->membase + CDNS_UART_CR);
615 regval |= CDNS_UART_CR_TX_DIS;
616 /* Disable the transmitter */
617 writel(regval, port->membase + CDNS_UART_CR);
621 * cdns_uart_stop_rx - Stop RX
622 * @port: Handle to the uart port structure
624 static void cdns_uart_stop_rx(struct uart_port *port)
628 /* Disable RX IRQs */
629 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IDR);
631 /* Disable the receiver */
632 regval = readl(port->membase + CDNS_UART_CR);
633 regval |= CDNS_UART_CR_RX_DIS;
634 writel(regval, port->membase + CDNS_UART_CR);
638 * cdns_uart_tx_empty - Check whether TX is empty
639 * @port: Handle to the uart port structure
641 * Return: TIOCSER_TEMT on success, 0 otherwise
643 static unsigned int cdns_uart_tx_empty(struct uart_port *port)
647 status = readl(port->membase + CDNS_UART_SR) &
648 CDNS_UART_SR_TXEMPTY;
649 return status ? TIOCSER_TEMT : 0;
653 * cdns_uart_break_ctl - Based on the input ctl we have to start or stop
654 * transmitting char breaks
655 * @port: Handle to the uart port structure
656 * @ctl: Value based on which start or stop decision is taken
658 static void cdns_uart_break_ctl(struct uart_port *port, int ctl)
663 spin_lock_irqsave(&port->lock, flags);
665 status = readl(port->membase + CDNS_UART_CR);
668 writel(CDNS_UART_CR_STARTBRK | status,
669 port->membase + CDNS_UART_CR);
671 if ((status & CDNS_UART_CR_STOPBRK) == 0)
672 writel(CDNS_UART_CR_STOPBRK | status,
673 port->membase + CDNS_UART_CR);
675 spin_unlock_irqrestore(&port->lock, flags);
679 * cdns_uart_set_termios - termios operations, handling data length, parity,
680 * stop bits, flow control, baud rate
681 * @port: Handle to the uart port structure
682 * @termios: Handle to the input termios structure
683 * @old: Values of the previously saved termios structure
685 static void cdns_uart_set_termios(struct uart_port *port,
686 struct ktermios *termios, struct ktermios *old)
688 unsigned int cval = 0;
689 unsigned int baud, minbaud, maxbaud;
691 unsigned int ctrl_reg, mode_reg, val;
694 /* Wait for the transmit FIFO to empty before making changes */
695 if (!(readl(port->membase + CDNS_UART_CR) &
696 CDNS_UART_CR_TX_DIS)) {
697 err = readl_poll_timeout(port->membase + CDNS_UART_SR,
698 val, (val & CDNS_UART_SR_TXEMPTY),
701 dev_err(port->dev, "timed out waiting for tx empty");
705 spin_lock_irqsave(&port->lock, flags);
707 /* Disable the TX and RX to set baud rate */
708 ctrl_reg = readl(port->membase + CDNS_UART_CR);
709 ctrl_reg |= CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS;
710 writel(ctrl_reg, port->membase + CDNS_UART_CR);
713 * Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk
714 * min and max baud should be calculated here based on port->uartclk.
715 * this way we get a valid baud and can safely call set_baud()
717 minbaud = port->uartclk /
718 ((CDNS_UART_BDIV_MAX + 1) * CDNS_UART_CD_MAX * 8);
719 maxbaud = port->uartclk / (CDNS_UART_BDIV_MIN + 1);
720 baud = uart_get_baud_rate(port, termios, old, minbaud, maxbaud);
721 baud = cdns_uart_set_baud_rate(port, baud);
722 if (tty_termios_baud_rate(termios))
723 tty_termios_encode_baud_rate(termios, baud, baud);
725 /* Update the per-port timeout. */
726 uart_update_timeout(port, termios->c_cflag, baud);
728 /* Set TX/RX Reset */
729 ctrl_reg = readl(port->membase + CDNS_UART_CR);
730 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
731 writel(ctrl_reg, port->membase + CDNS_UART_CR);
733 while (readl(port->membase + CDNS_UART_CR) &
734 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
738 * Clear the RX disable and TX disable bits and then set the TX enable
739 * bit and RX enable bit to enable the transmitter and receiver.
741 ctrl_reg = readl(port->membase + CDNS_UART_CR);
742 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
743 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
744 writel(ctrl_reg, port->membase + CDNS_UART_CR);
746 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
748 port->read_status_mask = CDNS_UART_IXR_TXEMPTY | CDNS_UART_IXR_RXTRIG |
749 CDNS_UART_IXR_OVERRUN | CDNS_UART_IXR_TOUT;
750 port->ignore_status_mask = 0;
752 if (termios->c_iflag & INPCK)
753 port->read_status_mask |= CDNS_UART_IXR_PARITY |
754 CDNS_UART_IXR_FRAMING;
756 if (termios->c_iflag & IGNPAR)
757 port->ignore_status_mask |= CDNS_UART_IXR_PARITY |
758 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
760 /* ignore all characters if CREAD is not set */
761 if ((termios->c_cflag & CREAD) == 0)
762 port->ignore_status_mask |= CDNS_UART_IXR_RXTRIG |
763 CDNS_UART_IXR_TOUT | CDNS_UART_IXR_PARITY |
764 CDNS_UART_IXR_FRAMING | CDNS_UART_IXR_OVERRUN;
766 mode_reg = readl(port->membase + CDNS_UART_MR);
768 /* Handling Data Size */
769 switch (termios->c_cflag & CSIZE) {
771 cval |= CDNS_UART_MR_CHARLEN_6_BIT;
774 cval |= CDNS_UART_MR_CHARLEN_7_BIT;
778 cval |= CDNS_UART_MR_CHARLEN_8_BIT;
779 termios->c_cflag &= ~CSIZE;
780 termios->c_cflag |= CS8;
784 /* Handling Parity and Stop Bits length */
785 if (termios->c_cflag & CSTOPB)
786 cval |= CDNS_UART_MR_STOPMODE_2_BIT; /* 2 STOP bits */
788 cval |= CDNS_UART_MR_STOPMODE_1_BIT; /* 1 STOP bit */
790 if (termios->c_cflag & PARENB) {
791 /* Mark or Space parity */
792 if (termios->c_cflag & CMSPAR) {
793 if (termios->c_cflag & PARODD)
794 cval |= CDNS_UART_MR_PARITY_MARK;
796 cval |= CDNS_UART_MR_PARITY_SPACE;
798 if (termios->c_cflag & PARODD)
799 cval |= CDNS_UART_MR_PARITY_ODD;
801 cval |= CDNS_UART_MR_PARITY_EVEN;
804 cval |= CDNS_UART_MR_PARITY_NONE;
806 cval |= mode_reg & 1;
807 writel(cval, port->membase + CDNS_UART_MR);
809 spin_unlock_irqrestore(&port->lock, flags);
813 * cdns_uart_startup - Called when an application opens a cdns_uart port
814 * @port: Handle to the uart port structure
816 * Return: 0 on success, negative errno otherwise
818 static int cdns_uart_startup(struct uart_port *port)
820 struct cdns_uart *cdns_uart = port->private_data;
824 unsigned int status = 0;
826 is_brk_support = cdns_uart->quirks & CDNS_UART_RXBS_SUPPORT;
828 spin_lock_irqsave(&port->lock, flags);
830 /* Disable the TX and RX */
831 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
832 port->membase + CDNS_UART_CR);
834 /* Set the Control Register with TX/RX Enable, TX/RX Reset,
837 writel(CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST,
838 port->membase + CDNS_UART_CR);
840 while (readl(port->membase + CDNS_UART_CR) &
841 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
845 * Clear the RX disable bit and then set the RX enable bit to enable
848 status = readl(port->membase + CDNS_UART_CR);
849 status &= CDNS_UART_CR_RX_DIS;
850 status |= CDNS_UART_CR_RX_EN;
851 writel(status, port->membase + CDNS_UART_CR);
853 /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
856 writel(CDNS_UART_MR_CHMODE_NORM | CDNS_UART_MR_STOPMODE_1_BIT
857 | CDNS_UART_MR_PARITY_NONE | CDNS_UART_MR_CHARLEN_8_BIT,
858 port->membase + CDNS_UART_MR);
861 * Set the RX FIFO Trigger level to use most of the FIFO, but it
862 * can be tuned with a module parameter
864 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
867 * Receive Timeout register is enabled but it
868 * can be tuned with a module parameter
870 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
872 /* Clear out any pending interrupts before enabling them */
873 writel(readl(port->membase + CDNS_UART_ISR),
874 port->membase + CDNS_UART_ISR);
876 spin_unlock_irqrestore(&port->lock, flags);
878 ret = request_irq(port->irq, cdns_uart_isr, 0, CDNS_UART_NAME, port);
880 dev_err(port->dev, "request_irq '%d' failed with %d\n",
885 /* Set the Interrupt Registers with desired interrupts */
887 writel(CDNS_UART_RX_IRQS | CDNS_UART_IXR_BRK,
888 port->membase + CDNS_UART_IER);
890 writel(CDNS_UART_RX_IRQS, port->membase + CDNS_UART_IER);
896 * cdns_uart_shutdown - Called when an application closes a cdns_uart port
897 * @port: Handle to the uart port structure
899 static void cdns_uart_shutdown(struct uart_port *port)
904 spin_lock_irqsave(&port->lock, flags);
906 /* Disable interrupts */
907 status = readl(port->membase + CDNS_UART_IMR);
908 writel(status, port->membase + CDNS_UART_IDR);
909 writel(0xffffffff, port->membase + CDNS_UART_ISR);
911 /* Disable the TX and RX */
912 writel(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS,
913 port->membase + CDNS_UART_CR);
915 spin_unlock_irqrestore(&port->lock, flags);
917 free_irq(port->irq, port);
921 * cdns_uart_type - Set UART type to cdns_uart port
922 * @port: Handle to the uart port structure
924 * Return: string on success, NULL otherwise
926 static const char *cdns_uart_type(struct uart_port *port)
928 return port->type == PORT_XUARTPS ? CDNS_UART_NAME : NULL;
932 * cdns_uart_verify_port - Verify the port params
933 * @port: Handle to the uart port structure
934 * @ser: Handle to the structure whose members are compared
936 * Return: 0 on success, negative errno otherwise.
938 static int cdns_uart_verify_port(struct uart_port *port,
939 struct serial_struct *ser)
941 if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
943 if (port->irq != ser->irq)
945 if (ser->io_type != UPIO_MEM)
947 if (port->iobase != ser->port)
955 * cdns_uart_request_port - Claim the memory region attached to cdns_uart port,
956 * called when the driver adds a cdns_uart port via
957 * uart_add_one_port()
958 * @port: Handle to the uart port structure
960 * Return: 0 on success, negative errno otherwise.
962 static int cdns_uart_request_port(struct uart_port *port)
964 if (!request_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE,
969 port->membase = ioremap(port->mapbase, CDNS_UART_REGISTER_SPACE);
970 if (!port->membase) {
971 dev_err(port->dev, "Unable to map registers\n");
972 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
979 * cdns_uart_release_port - Release UART port
980 * @port: Handle to the uart port structure
982 * Release the memory region attached to a cdns_uart port. Called when the
983 * driver removes a cdns_uart port via uart_remove_one_port().
985 static void cdns_uart_release_port(struct uart_port *port)
987 release_mem_region(port->mapbase, CDNS_UART_REGISTER_SPACE);
988 iounmap(port->membase);
989 port->membase = NULL;
993 * cdns_uart_config_port - Configure UART port
994 * @port: Handle to the uart port structure
997 static void cdns_uart_config_port(struct uart_port *port, int flags)
999 if (flags & UART_CONFIG_TYPE && cdns_uart_request_port(port) == 0)
1000 port->type = PORT_XUARTPS;
1004 * cdns_uart_get_mctrl - Get the modem control state
1005 * @port: Handle to the uart port structure
1007 * Return: the modem control state
1009 static unsigned int cdns_uart_get_mctrl(struct uart_port *port)
1011 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
1014 static void cdns_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1019 val = readl(port->membase + CDNS_UART_MODEMCR);
1020 mode_reg = readl(port->membase + CDNS_UART_MR);
1022 val &= ~(CDNS_UART_MODEMCR_RTS | CDNS_UART_MODEMCR_DTR);
1023 mode_reg &= ~CDNS_UART_MR_CHMODE_MASK;
1025 if (mctrl & TIOCM_RTS)
1026 val |= CDNS_UART_MODEMCR_RTS;
1027 if (mctrl & TIOCM_DTR)
1028 val |= CDNS_UART_MODEMCR_DTR;
1029 if (mctrl & TIOCM_LOOP)
1030 mode_reg |= CDNS_UART_MR_CHMODE_L_LOOP;
1032 mode_reg |= CDNS_UART_MR_CHMODE_NORM;
1034 writel(val, port->membase + CDNS_UART_MODEMCR);
1035 writel(mode_reg, port->membase + CDNS_UART_MR);
1038 #ifdef CONFIG_CONSOLE_POLL
1039 static int cdns_uart_poll_get_char(struct uart_port *port)
1042 unsigned long flags;
1044 spin_lock_irqsave(&port->lock, flags);
1046 /* Check if FIFO is empty */
1047 if (readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_RXEMPTY)
1049 else /* Read a character */
1050 c = (unsigned char) readl(port->membase + CDNS_UART_FIFO);
1052 spin_unlock_irqrestore(&port->lock, flags);
1057 static void cdns_uart_poll_put_char(struct uart_port *port, unsigned char c)
1059 unsigned long flags;
1061 spin_lock_irqsave(&port->lock, flags);
1063 /* Wait until FIFO is empty */
1064 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1067 /* Write a character */
1068 writel(c, port->membase + CDNS_UART_FIFO);
1070 /* Wait until FIFO is empty */
1071 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1074 spin_unlock_irqrestore(&port->lock, flags);
1080 static void cdns_uart_pm(struct uart_port *port, unsigned int state,
1081 unsigned int oldstate)
1084 case UART_PM_STATE_OFF:
1085 pm_runtime_mark_last_busy(port->dev);
1086 pm_runtime_put_autosuspend(port->dev);
1089 pm_runtime_get_sync(port->dev);
1094 static const struct uart_ops cdns_uart_ops = {
1095 .set_mctrl = cdns_uart_set_mctrl,
1096 .get_mctrl = cdns_uart_get_mctrl,
1097 .start_tx = cdns_uart_start_tx,
1098 .stop_tx = cdns_uart_stop_tx,
1099 .stop_rx = cdns_uart_stop_rx,
1100 .tx_empty = cdns_uart_tx_empty,
1101 .break_ctl = cdns_uart_break_ctl,
1102 .set_termios = cdns_uart_set_termios,
1103 .startup = cdns_uart_startup,
1104 .shutdown = cdns_uart_shutdown,
1106 .type = cdns_uart_type,
1107 .verify_port = cdns_uart_verify_port,
1108 .request_port = cdns_uart_request_port,
1109 .release_port = cdns_uart_release_port,
1110 .config_port = cdns_uart_config_port,
1111 #ifdef CONFIG_CONSOLE_POLL
1112 .poll_get_char = cdns_uart_poll_get_char,
1113 .poll_put_char = cdns_uart_poll_put_char,
1117 static struct uart_port cdns_uart_port[CDNS_UART_NR_PORTS];
1120 * cdns_uart_get_port - Configure the port from platform device resource info
1123 * Return: a pointer to a uart_port or NULL for failure
1125 static struct uart_port *cdns_uart_get_port(int id)
1127 struct uart_port *port;
1129 /* Try the given port id if failed use default method */
1130 if (id < CDNS_UART_NR_PORTS && cdns_uart_port[id].mapbase != 0) {
1131 /* Find the next unused port */
1132 for (id = 0; id < CDNS_UART_NR_PORTS; id++)
1133 if (cdns_uart_port[id].mapbase == 0)
1137 if (id >= CDNS_UART_NR_PORTS)
1140 port = &cdns_uart_port[id];
1142 /* At this point, we've got an empty uart_port struct, initialize it */
1143 spin_lock_init(&port->lock);
1144 port->membase = NULL;
1146 port->type = PORT_UNKNOWN;
1147 port->iotype = UPIO_MEM32;
1148 port->flags = UPF_BOOT_AUTOCONF;
1149 port->ops = &cdns_uart_ops;
1150 port->fifosize = CDNS_UART_FIFO_SIZE;
1156 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1158 * cdns_uart_console_wait_tx - Wait for the TX to be full
1159 * @port: Handle to the uart port structure
1161 static void cdns_uart_console_wait_tx(struct uart_port *port)
1163 while (!(readl(port->membase + CDNS_UART_SR) & CDNS_UART_SR_TXEMPTY))
1168 * cdns_uart_console_putchar - write the character to the FIFO buffer
1169 * @port: Handle to the uart port structure
1170 * @ch: Character to be written
1172 static void cdns_uart_console_putchar(struct uart_port *port, int ch)
1174 cdns_uart_console_wait_tx(port);
1175 writel(ch, port->membase + CDNS_UART_FIFO);
1178 static void cdns_early_write(struct console *con, const char *s,
1181 struct earlycon_device *dev = con->data;
1183 uart_console_write(&dev->port, s, n, cdns_uart_console_putchar);
1186 static int __init cdns_early_console_setup(struct earlycon_device *device,
1189 struct uart_port *port = &device->port;
1194 /* initialise control register */
1195 writel(CDNS_UART_CR_TX_EN|CDNS_UART_CR_TXRST|CDNS_UART_CR_RXRST,
1196 port->membase + CDNS_UART_CR);
1198 /* only set baud if specified on command line - otherwise
1199 * assume it has been initialized by a boot loader.
1202 u32 cd = 0, bdiv = 0;
1206 cdns_uart_calc_baud_divs(port->uartclk, device->baud,
1208 mr = CDNS_UART_MR_PARITY_NONE;
1210 mr |= CDNS_UART_MR_CLKSEL;
1212 writel(mr, port->membase + CDNS_UART_MR);
1213 writel(cd, port->membase + CDNS_UART_BAUDGEN);
1214 writel(bdiv, port->membase + CDNS_UART_BAUDDIV);
1217 device->con->write = cdns_early_write;
1221 OF_EARLYCON_DECLARE(cdns, "xlnx,xuartps", cdns_early_console_setup);
1222 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p8", cdns_early_console_setup);
1223 OF_EARLYCON_DECLARE(cdns, "cdns,uart-r1p12", cdns_early_console_setup);
1224 OF_EARLYCON_DECLARE(cdns, "xlnx,zynqmp-uart", cdns_early_console_setup);
1227 * cdns_uart_console_write - perform write operation
1228 * @co: Console handle
1229 * @s: Pointer to character array
1230 * @count: No of characters
1232 static void cdns_uart_console_write(struct console *co, const char *s,
1235 struct uart_port *port = &cdns_uart_port[co->index];
1236 unsigned long flags;
1237 unsigned int imr, ctrl;
1242 else if (oops_in_progress)
1243 locked = spin_trylock_irqsave(&port->lock, flags);
1245 spin_lock_irqsave(&port->lock, flags);
1247 /* save and disable interrupt */
1248 imr = readl(port->membase + CDNS_UART_IMR);
1249 writel(imr, port->membase + CDNS_UART_IDR);
1252 * Make sure that the tx part is enabled. Set the TX enable bit and
1253 * clear the TX disable bit to enable the transmitter.
1255 ctrl = readl(port->membase + CDNS_UART_CR);
1256 ctrl &= ~CDNS_UART_CR_TX_DIS;
1257 ctrl |= CDNS_UART_CR_TX_EN;
1258 writel(ctrl, port->membase + CDNS_UART_CR);
1260 uart_console_write(port, s, count, cdns_uart_console_putchar);
1261 cdns_uart_console_wait_tx(port);
1263 writel(ctrl, port->membase + CDNS_UART_CR);
1265 /* restore interrupt state */
1266 writel(imr, port->membase + CDNS_UART_IER);
1269 spin_unlock_irqrestore(&port->lock, flags);
1273 * cdns_uart_console_setup - Initialize the uart to default config
1274 * @co: Console handle
1275 * @options: Initial settings of uart
1277 * Return: 0 on success, negative errno otherwise.
1279 static int cdns_uart_console_setup(struct console *co, char *options)
1281 struct uart_port *port = &cdns_uart_port[co->index];
1286 unsigned long time_out;
1288 if (co->index < 0 || co->index >= CDNS_UART_NR_PORTS)
1291 if (!port->membase) {
1292 pr_debug("console on " CDNS_UART_TTY_NAME "%i not present\n",
1298 uart_parse_options(options, &baud, &parity, &bits, &flow);
1300 /* Wait for tx_empty before setting up the console */
1301 time_out = jiffies + usecs_to_jiffies(TX_TIMEOUT);
1303 while (time_before(jiffies, time_out) &&
1304 cdns_uart_tx_empty(port) != TIOCSER_TEMT)
1307 return uart_set_options(port, co, baud, parity, bits, flow);
1310 static struct uart_driver cdns_uart_uart_driver;
1312 static struct console cdns_uart_console = {
1313 .name = CDNS_UART_TTY_NAME,
1314 .write = cdns_uart_console_write,
1315 .device = uart_console_device,
1316 .setup = cdns_uart_console_setup,
1317 .flags = CON_PRINTBUFFER,
1318 .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
1319 .data = &cdns_uart_uart_driver,
1323 * cdns_uart_console_init - Initialization call
1325 * Return: 0 on success, negative errno otherwise
1327 static int __init cdns_uart_console_init(void)
1329 register_console(&cdns_uart_console);
1333 console_initcall(cdns_uart_console_init);
1335 #endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
1337 static struct uart_driver cdns_uart_uart_driver = {
1338 .owner = THIS_MODULE,
1339 .driver_name = CDNS_UART_NAME,
1340 .dev_name = CDNS_UART_TTY_NAME,
1341 .major = CDNS_UART_MAJOR,
1342 .minor = CDNS_UART_MINOR,
1343 .nr = CDNS_UART_NR_PORTS,
1344 #ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
1345 .cons = &cdns_uart_console,
1349 #ifdef CONFIG_PM_SLEEP
1351 * cdns_uart_suspend - suspend event
1352 * @device: Pointer to the device structure
1356 static int cdns_uart_suspend(struct device *device)
1358 struct uart_port *port = dev_get_drvdata(device);
1361 may_wake = device_may_wakeup(device);
1363 if (console_suspend_enabled && may_wake) {
1364 unsigned long flags = 0;
1366 spin_lock_irqsave(&port->lock, flags);
1367 /* Empty the receive FIFO 1st before making changes */
1368 while (!(readl(port->membase + CDNS_UART_SR) &
1369 CDNS_UART_SR_RXEMPTY))
1370 readl(port->membase + CDNS_UART_FIFO);
1371 /* set RX trigger level to 1 */
1372 writel(1, port->membase + CDNS_UART_RXWM);
1373 /* disable RX timeout interrups */
1374 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IDR);
1375 spin_unlock_irqrestore(&port->lock, flags);
1379 * Call the API provided in serial_core.c file which handles
1382 return uart_suspend_port(&cdns_uart_uart_driver, port);
1386 * cdns_uart_resume - Resume after a previous suspend
1387 * @device: Pointer to the device structure
1391 static int cdns_uart_resume(struct device *device)
1393 struct uart_port *port = dev_get_drvdata(device);
1394 unsigned long flags = 0;
1398 may_wake = device_may_wakeup(device);
1400 if (console_suspend_enabled && !may_wake) {
1401 struct cdns_uart *cdns_uart = port->private_data;
1403 clk_enable(cdns_uart->pclk);
1404 clk_enable(cdns_uart->uartclk);
1406 spin_lock_irqsave(&port->lock, flags);
1408 /* Set TX/RX Reset */
1409 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1410 ctrl_reg |= CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST;
1411 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1412 while (readl(port->membase + CDNS_UART_CR) &
1413 (CDNS_UART_CR_TXRST | CDNS_UART_CR_RXRST))
1416 /* restore rx timeout value */
1417 writel(rx_timeout, port->membase + CDNS_UART_RXTOUT);
1419 ctrl_reg = readl(port->membase + CDNS_UART_CR);
1420 ctrl_reg &= ~(CDNS_UART_CR_TX_DIS | CDNS_UART_CR_RX_DIS);
1421 ctrl_reg |= CDNS_UART_CR_TX_EN | CDNS_UART_CR_RX_EN;
1422 writel(ctrl_reg, port->membase + CDNS_UART_CR);
1424 clk_disable(cdns_uart->uartclk);
1425 clk_disable(cdns_uart->pclk);
1426 spin_unlock_irqrestore(&port->lock, flags);
1428 spin_lock_irqsave(&port->lock, flags);
1429 /* restore original rx trigger level */
1430 writel(rx_trigger_level, port->membase + CDNS_UART_RXWM);
1431 /* enable RX timeout interrupt */
1432 writel(CDNS_UART_IXR_TOUT, port->membase + CDNS_UART_IER);
1433 spin_unlock_irqrestore(&port->lock, flags);
1436 return uart_resume_port(&cdns_uart_uart_driver, port);
1438 #endif /* ! CONFIG_PM_SLEEP */
1439 static int __maybe_unused cdns_runtime_suspend(struct device *dev)
1441 struct platform_device *pdev = to_platform_device(dev);
1442 struct uart_port *port = platform_get_drvdata(pdev);
1443 struct cdns_uart *cdns_uart = port->private_data;
1445 clk_disable(cdns_uart->uartclk);
1446 clk_disable(cdns_uart->pclk);
1450 static int __maybe_unused cdns_runtime_resume(struct device *dev)
1452 struct platform_device *pdev = to_platform_device(dev);
1453 struct uart_port *port = platform_get_drvdata(pdev);
1454 struct cdns_uart *cdns_uart = port->private_data;
1456 clk_enable(cdns_uart->pclk);
1457 clk_enable(cdns_uart->uartclk);
1461 static const struct dev_pm_ops cdns_uart_dev_pm_ops = {
1462 SET_SYSTEM_SLEEP_PM_OPS(cdns_uart_suspend, cdns_uart_resume)
1463 SET_RUNTIME_PM_OPS(cdns_runtime_suspend,
1464 cdns_runtime_resume, NULL)
1467 static const struct cdns_platform_data zynqmp_uart_def = {
1468 .quirks = CDNS_UART_RXBS_SUPPORT, };
1470 /* Match table for of_platform binding */
1471 static const struct of_device_id cdns_uart_of_match[] = {
1472 { .compatible = "xlnx,xuartps", },
1473 { .compatible = "cdns,uart-r1p8", },
1474 { .compatible = "cdns,uart-r1p12", .data = &zynqmp_uart_def },
1475 { .compatible = "xlnx,zynqmp-uart", .data = &zynqmp_uart_def },
1478 MODULE_DEVICE_TABLE(of, cdns_uart_of_match);
1481 * cdns_uart_probe - Platform driver probe
1482 * @pdev: Pointer to the platform device structure
1484 * Return: 0 on success, negative errno otherwise
1486 static int cdns_uart_probe(struct platform_device *pdev)
1489 struct uart_port *port;
1490 struct resource *res;
1491 struct cdns_uart *cdns_uart_data;
1492 const struct of_device_id *match;
1494 cdns_uart_data = devm_kzalloc(&pdev->dev, sizeof(*cdns_uart_data),
1496 if (!cdns_uart_data)
1499 match = of_match_node(cdns_uart_of_match, pdev->dev.of_node);
1500 if (match && match->data) {
1501 const struct cdns_platform_data *data = match->data;
1503 cdns_uart_data->quirks = data->quirks;
1506 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "pclk");
1507 if (IS_ERR(cdns_uart_data->pclk)) {
1508 cdns_uart_data->pclk = devm_clk_get(&pdev->dev, "aper_clk");
1509 if (!IS_ERR(cdns_uart_data->pclk))
1510 dev_err(&pdev->dev, "clock name 'aper_clk' is deprecated.\n");
1512 if (IS_ERR(cdns_uart_data->pclk)) {
1513 dev_err(&pdev->dev, "pclk clock not found.\n");
1514 return PTR_ERR(cdns_uart_data->pclk);
1517 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "uart_clk");
1518 if (IS_ERR(cdns_uart_data->uartclk)) {
1519 cdns_uart_data->uartclk = devm_clk_get(&pdev->dev, "ref_clk");
1520 if (!IS_ERR(cdns_uart_data->uartclk))
1521 dev_err(&pdev->dev, "clock name 'ref_clk' is deprecated.\n");
1523 if (IS_ERR(cdns_uart_data->uartclk)) {
1524 dev_err(&pdev->dev, "uart_clk clock not found.\n");
1525 return PTR_ERR(cdns_uart_data->uartclk);
1528 rc = clk_prepare_enable(cdns_uart_data->pclk);
1530 dev_err(&pdev->dev, "Unable to enable pclk clock.\n");
1533 rc = clk_prepare_enable(cdns_uart_data->uartclk);
1535 dev_err(&pdev->dev, "Unable to enable device clock.\n");
1536 goto err_out_clk_dis_pclk;
1539 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1542 goto err_out_clk_disable;
1545 irq = platform_get_irq(pdev, 0);
1548 goto err_out_clk_disable;
1551 #ifdef CONFIG_COMMON_CLK
1552 cdns_uart_data->clk_rate_change_nb.notifier_call =
1553 cdns_uart_clk_notifier_cb;
1554 if (clk_notifier_register(cdns_uart_data->uartclk,
1555 &cdns_uart_data->clk_rate_change_nb))
1556 dev_warn(&pdev->dev, "Unable to register clock notifier.\n");
1558 /* Look for a serialN alias */
1559 id = of_alias_get_id(pdev->dev.of_node, "serial");
1563 /* Initialize the port structure */
1564 port = cdns_uart_get_port(id);
1567 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
1569 goto err_out_notif_unreg;
1573 * Register the port.
1574 * This function also registers this device with the tty layer
1575 * and triggers invocation of the config_port() entry point.
1577 port->mapbase = res->start;
1579 port->dev = &pdev->dev;
1580 port->uartclk = clk_get_rate(cdns_uart_data->uartclk);
1581 port->private_data = cdns_uart_data;
1582 cdns_uart_data->port = port;
1583 platform_set_drvdata(pdev, port);
1585 pm_runtime_use_autosuspend(&pdev->dev);
1586 pm_runtime_set_autosuspend_delay(&pdev->dev, UART_AUTOSUSPEND_TIMEOUT);
1587 pm_runtime_set_active(&pdev->dev);
1588 pm_runtime_enable(&pdev->dev);
1590 rc = uart_add_one_port(&cdns_uart_uart_driver, port);
1593 "uart_add_one_port() failed; err=%i\n", rc);
1594 goto err_out_pm_disable;
1600 pm_runtime_disable(&pdev->dev);
1601 pm_runtime_set_suspended(&pdev->dev);
1602 pm_runtime_dont_use_autosuspend(&pdev->dev);
1603 err_out_notif_unreg:
1604 #ifdef CONFIG_COMMON_CLK
1605 clk_notifier_unregister(cdns_uart_data->uartclk,
1606 &cdns_uart_data->clk_rate_change_nb);
1608 err_out_clk_disable:
1609 clk_disable_unprepare(cdns_uart_data->uartclk);
1610 err_out_clk_dis_pclk:
1611 clk_disable_unprepare(cdns_uart_data->pclk);
1617 * cdns_uart_remove - called when the platform driver is unregistered
1618 * @pdev: Pointer to the platform device structure
1620 * Return: 0 on success, negative errno otherwise
1622 static int cdns_uart_remove(struct platform_device *pdev)
1624 struct uart_port *port = platform_get_drvdata(pdev);
1625 struct cdns_uart *cdns_uart_data = port->private_data;
1628 /* Remove the cdns_uart port from the serial core */
1629 #ifdef CONFIG_COMMON_CLK
1630 clk_notifier_unregister(cdns_uart_data->uartclk,
1631 &cdns_uart_data->clk_rate_change_nb);
1633 rc = uart_remove_one_port(&cdns_uart_uart_driver, port);
1635 clk_disable_unprepare(cdns_uart_data->uartclk);
1636 clk_disable_unprepare(cdns_uart_data->pclk);
1637 pm_runtime_disable(&pdev->dev);
1638 pm_runtime_set_suspended(&pdev->dev);
1639 pm_runtime_dont_use_autosuspend(&pdev->dev);
1643 static struct platform_driver cdns_uart_platform_driver = {
1644 .probe = cdns_uart_probe,
1645 .remove = cdns_uart_remove,
1647 .name = CDNS_UART_NAME,
1648 .of_match_table = cdns_uart_of_match,
1649 .pm = &cdns_uart_dev_pm_ops,
1650 .suppress_bind_attrs = IS_BUILTIN(CONFIG_SERIAL_XILINX_PS_UART),
1654 static int __init cdns_uart_init(void)
1658 /* Register the cdns_uart driver with the serial core */
1659 retval = uart_register_driver(&cdns_uart_uart_driver);
1663 /* Register the platform driver */
1664 retval = platform_driver_register(&cdns_uart_platform_driver);
1666 uart_unregister_driver(&cdns_uart_uart_driver);
1671 static void __exit cdns_uart_exit(void)
1673 /* Unregister the platform driver */
1674 platform_driver_unregister(&cdns_uart_platform_driver);
1676 /* Unregister the cdns_uart driver */
1677 uart_unregister_driver(&cdns_uart_uart_driver);
1680 module_init(cdns_uart_init);
1681 module_exit(cdns_uart_exit);
1683 MODULE_DESCRIPTION("Driver for Cadence UART");
1684 MODULE_AUTHOR("Xilinx Inc.");
1685 MODULE_LICENSE("GPL");