GNU Linux-libre 4.9.309-gnu1
[releases.git] / drivers / tty / serial / zs.c
1 /*
2  * zs.c: Serial port driver for IOASIC DECstations.
3  *
4  * Derived from drivers/sbus/char/sunserial.c by Paul Mackerras.
5  * Derived from drivers/macintosh/macserial.c by Harald Koerfgen.
6  *
7  * DECstation changes
8  * Copyright (C) 1998-2000 Harald Koerfgen
9  * Copyright (C) 2000, 2001, 2002, 2003, 2004, 2005, 2007  Maciej W. Rozycki
10  *
11  * For the rest of the code the original Copyright applies:
12  * Copyright (C) 1996 Paul Mackerras (Paul.Mackerras@cs.anu.edu.au)
13  * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
14  *
15  *
16  * Note: for IOASIC systems the wiring is as follows:
17  *
18  * mouse/keyboard:
19  * DIN-7 MJ-4  signal        SCC
20  * 2     1     TxD       <-  A.TxD
21  * 3     4     RxD       ->  A.RxD
22  *
23  * EIA-232/EIA-423:
24  * DB-25 MMJ-6 signal        SCC
25  * 2     2     TxD       <-  B.TxD
26  * 3     5     RxD       ->  B.RxD
27  * 4           RTS       <- ~A.RTS
28  * 5           CTS       -> ~B.CTS
29  * 6     6     DSR       -> ~A.SYNC
30  * 8           CD        -> ~B.DCD
31  * 12          DSRS(DCE) -> ~A.CTS  (*)
32  * 15          TxC       ->  B.TxC
33  * 17          RxC       ->  B.RxC
34  * 20    1     DTR       <- ~A.DTR
35  * 22          RI        -> ~A.DCD
36  * 23          DSRS(DTE) <- ~B.RTS
37  *
38  * (*) EIA-232 defines the signal at this pin to be SCD, while DSRS(DCE)
39  *     is shared with DSRS(DTE) at pin 23.
40  *
41  * As you can immediately notice the wiring of the RTS, DTR and DSR signals
42  * is a bit odd.  This makes the handling of port B unnecessarily
43  * complicated and prevents the use of some automatic modes of operation.
44  */
45
46 #if defined(CONFIG_SERIAL_ZS_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
47 #define SUPPORT_SYSRQ
48 #endif
49
50 #include <linux/bug.h>
51 #include <linux/console.h>
52 #include <linux/delay.h>
53 #include <linux/errno.h>
54 #include <linux/init.h>
55 #include <linux/interrupt.h>
56 #include <linux/io.h>
57 #include <linux/ioport.h>
58 #include <linux/irqflags.h>
59 #include <linux/kernel.h>
60 #include <linux/module.h>
61 #include <linux/major.h>
62 #include <linux/serial.h>
63 #include <linux/serial_core.h>
64 #include <linux/spinlock.h>
65 #include <linux/sysrq.h>
66 #include <linux/tty.h>
67 #include <linux/tty_flip.h>
68 #include <linux/types.h>
69
70 #include <linux/atomic.h>
71
72 #include <asm/dec/interrupts.h>
73 #include <asm/dec/ioasic_addrs.h>
74 #include <asm/dec/system.h>
75
76 #include "zs.h"
77
78
79 MODULE_AUTHOR("Maciej W. Rozycki <macro@linux-mips.org>");
80 MODULE_DESCRIPTION("DECstation Z85C30 serial driver");
81 MODULE_LICENSE("GPL");
82
83
84 static char zs_name[] __initdata = "DECstation Z85C30 serial driver version ";
85 static char zs_version[] __initdata = "0.10";
86
87 /*
88  * It would be nice to dynamically allocate everything that
89  * depends on ZS_NUM_SCCS, so we could support any number of
90  * Z85C30s, but for now...
91  */
92 #define ZS_NUM_SCCS     2               /* Max # of ZS chips supported.  */
93 #define ZS_NUM_CHAN     2               /* 2 channels per chip.  */
94 #define ZS_CHAN_A       0               /* Index of the channel A.  */
95 #define ZS_CHAN_B       1               /* Index of the channel B.  */
96 #define ZS_CHAN_IO_SIZE 8               /* IOMEM space size.  */
97 #define ZS_CHAN_IO_STRIDE 4             /* Register alignment.  */
98 #define ZS_CHAN_IO_OFFSET 1             /* The SCC resides on the high byte
99                                            of the 16-bit IOBUS.  */
100 #define ZS_CLOCK        7372800         /* Z85C30 PCLK input clock rate.  */
101
102 #define to_zport(uport) container_of(uport, struct zs_port, port)
103
104 struct zs_parms {
105         resource_size_t scc[ZS_NUM_SCCS];
106         int irq[ZS_NUM_SCCS];
107 };
108
109 static struct zs_scc zs_sccs[ZS_NUM_SCCS];
110
111 static u8 zs_init_regs[ZS_NUM_REGS] __initdata = {
112         0,                              /* write 0 */
113         PAR_SPEC,                       /* write 1 */
114         0,                              /* write 2 */
115         0,                              /* write 3 */
116         X16CLK | SB1,                   /* write 4 */
117         0,                              /* write 5 */
118         0, 0, 0,                        /* write 6, 7, 8 */
119         MIE | DLC | NV,                 /* write 9 */
120         NRZ,                            /* write 10 */
121         TCBR | RCBR,                    /* write 11 */
122         0, 0,                           /* BRG time constant, write 12 + 13 */
123         BRSRC | BRENABL,                /* write 14 */
124         0,                              /* write 15 */
125 };
126
127 /*
128  * Debugging.
129  */
130 #undef ZS_DEBUG_REGS
131
132
133 /*
134  * Reading and writing Z85C30 registers.
135  */
136 static void recovery_delay(void)
137 {
138         udelay(2);
139 }
140
141 static u8 read_zsreg(struct zs_port *zport, int reg)
142 {
143         void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
144         u8 retval;
145
146         if (reg != 0) {
147                 writeb(reg & 0xf, control);
148                 fast_iob();
149                 recovery_delay();
150         }
151         retval = readb(control);
152         recovery_delay();
153         return retval;
154 }
155
156 static void write_zsreg(struct zs_port *zport, int reg, u8 value)
157 {
158         void __iomem *control = zport->port.membase + ZS_CHAN_IO_OFFSET;
159
160         if (reg != 0) {
161                 writeb(reg & 0xf, control);
162                 fast_iob(); recovery_delay();
163         }
164         writeb(value, control);
165         fast_iob();
166         recovery_delay();
167         return;
168 }
169
170 static u8 read_zsdata(struct zs_port *zport)
171 {
172         void __iomem *data = zport->port.membase +
173                              ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
174         u8 retval;
175
176         retval = readb(data);
177         recovery_delay();
178         return retval;
179 }
180
181 static void write_zsdata(struct zs_port *zport, u8 value)
182 {
183         void __iomem *data = zport->port.membase +
184                              ZS_CHAN_IO_STRIDE + ZS_CHAN_IO_OFFSET;
185
186         writeb(value, data);
187         fast_iob();
188         recovery_delay();
189         return;
190 }
191
192 #ifdef ZS_DEBUG_REGS
193 void zs_dump(void)
194 {
195         struct zs_port *zport;
196         int i, j;
197
198         for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
199                 zport = &zs_sccs[i / ZS_NUM_CHAN].zport[i % ZS_NUM_CHAN];
200
201                 if (!zport->scc)
202                         continue;
203
204                 for (j = 0; j < 16; j++)
205                         printk("W%-2d = 0x%02x\t", j, zport->regs[j]);
206                 printk("\n");
207                 for (j = 0; j < 16; j++)
208                         printk("R%-2d = 0x%02x\t", j, read_zsreg(zport, j));
209                 printk("\n\n");
210         }
211 }
212 #endif
213
214
215 static void zs_spin_lock_cond_irq(spinlock_t *lock, int irq)
216 {
217         if (irq)
218                 spin_lock_irq(lock);
219         else
220                 spin_lock(lock);
221 }
222
223 static void zs_spin_unlock_cond_irq(spinlock_t *lock, int irq)
224 {
225         if (irq)
226                 spin_unlock_irq(lock);
227         else
228                 spin_unlock(lock);
229 }
230
231 static int zs_receive_drain(struct zs_port *zport)
232 {
233         int loops = 10000;
234
235         while ((read_zsreg(zport, R0) & Rx_CH_AV) && --loops)
236                 read_zsdata(zport);
237         return loops;
238 }
239
240 static int zs_transmit_drain(struct zs_port *zport, int irq)
241 {
242         struct zs_scc *scc = zport->scc;
243         int loops = 10000;
244
245         while (!(read_zsreg(zport, R0) & Tx_BUF_EMP) && --loops) {
246                 zs_spin_unlock_cond_irq(&scc->zlock, irq);
247                 udelay(2);
248                 zs_spin_lock_cond_irq(&scc->zlock, irq);
249         }
250         return loops;
251 }
252
253 static int zs_line_drain(struct zs_port *zport, int irq)
254 {
255         struct zs_scc *scc = zport->scc;
256         int loops = 10000;
257
258         while (!(read_zsreg(zport, R1) & ALL_SNT) && --loops) {
259                 zs_spin_unlock_cond_irq(&scc->zlock, irq);
260                 udelay(2);
261                 zs_spin_lock_cond_irq(&scc->zlock, irq);
262         }
263         return loops;
264 }
265
266
267 static void load_zsregs(struct zs_port *zport, u8 *regs, int irq)
268 {
269         /* Let the current transmission finish.  */
270         zs_line_drain(zport, irq);
271         /* Load 'em up.  */
272         write_zsreg(zport, R3, regs[3] & ~RxENABLE);
273         write_zsreg(zport, R5, regs[5] & ~TxENAB);
274         write_zsreg(zport, R4, regs[4]);
275         write_zsreg(zport, R9, regs[9]);
276         write_zsreg(zport, R1, regs[1]);
277         write_zsreg(zport, R2, regs[2]);
278         write_zsreg(zport, R10, regs[10]);
279         write_zsreg(zport, R14, regs[14] & ~BRENABL);
280         write_zsreg(zport, R11, regs[11]);
281         write_zsreg(zport, R12, regs[12]);
282         write_zsreg(zport, R13, regs[13]);
283         write_zsreg(zport, R14, regs[14]);
284         write_zsreg(zport, R15, regs[15]);
285         if (regs[3] & RxENABLE)
286                 write_zsreg(zport, R3, regs[3]);
287         if (regs[5] & TxENAB)
288                 write_zsreg(zport, R5, regs[5]);
289         return;
290 }
291
292
293 /*
294  * Status handling routines.
295  */
296
297 /*
298  * zs_tx_empty() -- get the transmitter empty status
299  *
300  * Purpose: Let user call ioctl() to get info when the UART physically
301  *          is emptied.  On bus types like RS485, the transmitter must
302  *          release the bus after transmitting.  This must be done when
303  *          the transmit shift register is empty, not be done when the
304  *          transmit holding register is empty.  This functionality
305  *          allows an RS485 driver to be written in user space.
306  */
307 static unsigned int zs_tx_empty(struct uart_port *uport)
308 {
309         struct zs_port *zport = to_zport(uport);
310         struct zs_scc *scc = zport->scc;
311         unsigned long flags;
312         u8 status;
313
314         spin_lock_irqsave(&scc->zlock, flags);
315         status = read_zsreg(zport, R1);
316         spin_unlock_irqrestore(&scc->zlock, flags);
317
318         return status & ALL_SNT ? TIOCSER_TEMT : 0;
319 }
320
321 static unsigned int zs_raw_get_ab_mctrl(struct zs_port *zport_a,
322                                         struct zs_port *zport_b)
323 {
324         u8 status_a, status_b;
325         unsigned int mctrl;
326
327         status_a = read_zsreg(zport_a, R0);
328         status_b = read_zsreg(zport_b, R0);
329
330         mctrl = ((status_b & CTS) ? TIOCM_CTS : 0) |
331                 ((status_b & DCD) ? TIOCM_CAR : 0) |
332                 ((status_a & DCD) ? TIOCM_RNG : 0) |
333                 ((status_a & SYNC_HUNT) ? TIOCM_DSR : 0);
334
335         return mctrl;
336 }
337
338 static unsigned int zs_raw_get_mctrl(struct zs_port *zport)
339 {
340         struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
341
342         return zport != zport_a ? zs_raw_get_ab_mctrl(zport_a, zport) : 0;
343 }
344
345 static unsigned int zs_raw_xor_mctrl(struct zs_port *zport)
346 {
347         struct zs_port *zport_a = &zport->scc->zport[ZS_CHAN_A];
348         unsigned int mmask, mctrl, delta;
349         u8 mask_a, mask_b;
350
351         if (zport == zport_a)
352                 return 0;
353
354         mask_a = zport_a->regs[15];
355         mask_b = zport->regs[15];
356
357         mmask = ((mask_b & CTSIE) ? TIOCM_CTS : 0) |
358                 ((mask_b & DCDIE) ? TIOCM_CAR : 0) |
359                 ((mask_a & DCDIE) ? TIOCM_RNG : 0) |
360                 ((mask_a & SYNCIE) ? TIOCM_DSR : 0);
361
362         mctrl = zport->mctrl;
363         if (mmask) {
364                 mctrl &= ~mmask;
365                 mctrl |= zs_raw_get_ab_mctrl(zport_a, zport) & mmask;
366         }
367
368         delta = mctrl ^ zport->mctrl;
369         if (delta)
370                 zport->mctrl = mctrl;
371
372         return delta;
373 }
374
375 static unsigned int zs_get_mctrl(struct uart_port *uport)
376 {
377         struct zs_port *zport = to_zport(uport);
378         struct zs_scc *scc = zport->scc;
379         unsigned int mctrl;
380
381         spin_lock(&scc->zlock);
382         mctrl = zs_raw_get_mctrl(zport);
383         spin_unlock(&scc->zlock);
384
385         return mctrl;
386 }
387
388 static void zs_set_mctrl(struct uart_port *uport, unsigned int mctrl)
389 {
390         struct zs_port *zport = to_zport(uport);
391         struct zs_scc *scc = zport->scc;
392         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
393         u8 oldloop, newloop;
394
395         spin_lock(&scc->zlock);
396         if (zport != zport_a) {
397                 if (mctrl & TIOCM_DTR)
398                         zport_a->regs[5] |= DTR;
399                 else
400                         zport_a->regs[5] &= ~DTR;
401                 if (mctrl & TIOCM_RTS)
402                         zport_a->regs[5] |= RTS;
403                 else
404                         zport_a->regs[5] &= ~RTS;
405                 write_zsreg(zport_a, R5, zport_a->regs[5]);
406         }
407
408         /* Rarely modified, so don't poke at hardware unless necessary. */
409         oldloop = zport->regs[14];
410         newloop = oldloop;
411         if (mctrl & TIOCM_LOOP)
412                 newloop |= LOOPBAK;
413         else
414                 newloop &= ~LOOPBAK;
415         if (newloop != oldloop) {
416                 zport->regs[14] = newloop;
417                 write_zsreg(zport, R14, zport->regs[14]);
418         }
419         spin_unlock(&scc->zlock);
420 }
421
422 static void zs_raw_stop_tx(struct zs_port *zport)
423 {
424         write_zsreg(zport, R0, RES_Tx_P);
425         zport->tx_stopped = 1;
426 }
427
428 static void zs_stop_tx(struct uart_port *uport)
429 {
430         struct zs_port *zport = to_zport(uport);
431         struct zs_scc *scc = zport->scc;
432
433         spin_lock(&scc->zlock);
434         zs_raw_stop_tx(zport);
435         spin_unlock(&scc->zlock);
436 }
437
438 static void zs_raw_transmit_chars(struct zs_port *);
439
440 static void zs_start_tx(struct uart_port *uport)
441 {
442         struct zs_port *zport = to_zport(uport);
443         struct zs_scc *scc = zport->scc;
444
445         spin_lock(&scc->zlock);
446         if (zport->tx_stopped) {
447                 zs_transmit_drain(zport, 0);
448                 zport->tx_stopped = 0;
449                 zs_raw_transmit_chars(zport);
450         }
451         spin_unlock(&scc->zlock);
452 }
453
454 static void zs_stop_rx(struct uart_port *uport)
455 {
456         struct zs_port *zport = to_zport(uport);
457         struct zs_scc *scc = zport->scc;
458         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
459
460         spin_lock(&scc->zlock);
461         zport->regs[15] &= ~BRKIE;
462         zport->regs[1] &= ~(RxINT_MASK | TxINT_ENAB);
463         zport->regs[1] |= RxINT_DISAB;
464
465         if (zport != zport_a) {
466                 /* A-side DCD tracks RI and SYNC tracks DSR.  */
467                 zport_a->regs[15] &= ~(DCDIE | SYNCIE);
468                 write_zsreg(zport_a, R15, zport_a->regs[15]);
469                 if (!(zport_a->regs[15] & BRKIE)) {
470                         zport_a->regs[1] &= ~EXT_INT_ENAB;
471                         write_zsreg(zport_a, R1, zport_a->regs[1]);
472                 }
473
474                 /* This-side DCD tracks DCD and CTS tracks CTS.  */
475                 zport->regs[15] &= ~(DCDIE | CTSIE);
476                 zport->regs[1] &= ~EXT_INT_ENAB;
477         } else {
478                 /* DCD tracks RI and SYNC tracks DSR for the B side.  */
479                 if (!(zport->regs[15] & (DCDIE | SYNCIE)))
480                         zport->regs[1] &= ~EXT_INT_ENAB;
481         }
482
483         write_zsreg(zport, R15, zport->regs[15]);
484         write_zsreg(zport, R1, zport->regs[1]);
485         spin_unlock(&scc->zlock);
486 }
487
488 static void zs_enable_ms(struct uart_port *uport)
489 {
490         struct zs_port *zport = to_zport(uport);
491         struct zs_scc *scc = zport->scc;
492         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
493
494         if (zport == zport_a)
495                 return;
496
497         spin_lock(&scc->zlock);
498
499         /* Clear Ext interrupts if not being handled already.  */
500         if (!(zport_a->regs[1] & EXT_INT_ENAB))
501                 write_zsreg(zport_a, R0, RES_EXT_INT);
502
503         /* A-side DCD tracks RI and SYNC tracks DSR.  */
504         zport_a->regs[1] |= EXT_INT_ENAB;
505         zport_a->regs[15] |= DCDIE | SYNCIE;
506
507         /* This-side DCD tracks DCD and CTS tracks CTS.  */
508         zport->regs[15] |= DCDIE | CTSIE;
509
510         zs_raw_xor_mctrl(zport);
511
512         write_zsreg(zport_a, R1, zport_a->regs[1]);
513         write_zsreg(zport_a, R15, zport_a->regs[15]);
514         write_zsreg(zport, R15, zport->regs[15]);
515         spin_unlock(&scc->zlock);
516 }
517
518 static void zs_break_ctl(struct uart_port *uport, int break_state)
519 {
520         struct zs_port *zport = to_zport(uport);
521         struct zs_scc *scc = zport->scc;
522         unsigned long flags;
523
524         spin_lock_irqsave(&scc->zlock, flags);
525         if (break_state == -1)
526                 zport->regs[5] |= SND_BRK;
527         else
528                 zport->regs[5] &= ~SND_BRK;
529         write_zsreg(zport, R5, zport->regs[5]);
530         spin_unlock_irqrestore(&scc->zlock, flags);
531 }
532
533
534 /*
535  * Interrupt handling routines.
536  */
537 #define Rx_BRK 0x0100                   /* BREAK event software flag.  */
538 #define Rx_SYS 0x0200                   /* SysRq event software flag.  */
539
540 static void zs_receive_chars(struct zs_port *zport)
541 {
542         struct uart_port *uport = &zport->port;
543         struct zs_scc *scc = zport->scc;
544         struct uart_icount *icount;
545         unsigned int avail, status, ch, flag;
546         int count;
547
548         for (count = 16; count; count--) {
549                 spin_lock(&scc->zlock);
550                 avail = read_zsreg(zport, R0) & Rx_CH_AV;
551                 spin_unlock(&scc->zlock);
552                 if (!avail)
553                         break;
554
555                 spin_lock(&scc->zlock);
556                 status = read_zsreg(zport, R1) & (Rx_OVR | FRM_ERR | PAR_ERR);
557                 ch = read_zsdata(zport);
558                 spin_unlock(&scc->zlock);
559
560                 flag = TTY_NORMAL;
561
562                 icount = &uport->icount;
563                 icount->rx++;
564
565                 /* Handle the null char got when BREAK is removed.  */
566                 if (!ch)
567                         status |= zport->tty_break;
568                 if (unlikely(status &
569                              (Rx_OVR | FRM_ERR | PAR_ERR | Rx_SYS | Rx_BRK))) {
570                         zport->tty_break = 0;
571
572                         /* Reset the error indication.  */
573                         if (status & (Rx_OVR | FRM_ERR | PAR_ERR)) {
574                                 spin_lock(&scc->zlock);
575                                 write_zsreg(zport, R0, ERR_RES);
576                                 spin_unlock(&scc->zlock);
577                         }
578
579                         if (status & (Rx_SYS | Rx_BRK)) {
580                                 icount->brk++;
581                                 /* SysRq discards the null char.  */
582                                 if (status & Rx_SYS)
583                                         continue;
584                         } else if (status & FRM_ERR)
585                                 icount->frame++;
586                         else if (status & PAR_ERR)
587                                 icount->parity++;
588                         if (status & Rx_OVR)
589                                 icount->overrun++;
590
591                         status &= uport->read_status_mask;
592                         if (status & Rx_BRK)
593                                 flag = TTY_BREAK;
594                         else if (status & FRM_ERR)
595                                 flag = TTY_FRAME;
596                         else if (status & PAR_ERR)
597                                 flag = TTY_PARITY;
598                 }
599
600                 if (uart_handle_sysrq_char(uport, ch))
601                         continue;
602
603                 uart_insert_char(uport, status, Rx_OVR, ch, flag);
604         }
605
606         tty_flip_buffer_push(&uport->state->port);
607 }
608
609 static void zs_raw_transmit_chars(struct zs_port *zport)
610 {
611         struct circ_buf *xmit = &zport->port.state->xmit;
612
613         /* XON/XOFF chars.  */
614         if (zport->port.x_char) {
615                 write_zsdata(zport, zport->port.x_char);
616                 zport->port.icount.tx++;
617                 zport->port.x_char = 0;
618                 return;
619         }
620
621         /* If nothing to do or stopped or hardware stopped.  */
622         if (uart_circ_empty(xmit) || uart_tx_stopped(&zport->port)) {
623                 zs_raw_stop_tx(zport);
624                 return;
625         }
626
627         /* Send char.  */
628         write_zsdata(zport, xmit->buf[xmit->tail]);
629         xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
630         zport->port.icount.tx++;
631
632         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
633                 uart_write_wakeup(&zport->port);
634
635         /* Are we are done?  */
636         if (uart_circ_empty(xmit))
637                 zs_raw_stop_tx(zport);
638 }
639
640 static void zs_transmit_chars(struct zs_port *zport)
641 {
642         struct zs_scc *scc = zport->scc;
643
644         spin_lock(&scc->zlock);
645         zs_raw_transmit_chars(zport);
646         spin_unlock(&scc->zlock);
647 }
648
649 static void zs_status_handle(struct zs_port *zport, struct zs_port *zport_a)
650 {
651         struct uart_port *uport = &zport->port;
652         struct zs_scc *scc = zport->scc;
653         unsigned int delta;
654         u8 status, brk;
655
656         spin_lock(&scc->zlock);
657
658         /* Get status from Read Register 0.  */
659         status = read_zsreg(zport, R0);
660
661         if (zport->regs[15] & BRKIE) {
662                 brk = status & BRK_ABRT;
663                 if (brk && !zport->brk) {
664                         spin_unlock(&scc->zlock);
665                         if (uart_handle_break(uport))
666                                 zport->tty_break = Rx_SYS;
667                         else
668                                 zport->tty_break = Rx_BRK;
669                         spin_lock(&scc->zlock);
670                 }
671                 zport->brk = brk;
672         }
673
674         if (zport != zport_a) {
675                 delta = zs_raw_xor_mctrl(zport);
676                 spin_unlock(&scc->zlock);
677
678                 if (delta & TIOCM_CTS)
679                         uart_handle_cts_change(uport,
680                                                zport->mctrl & TIOCM_CTS);
681                 if (delta & TIOCM_CAR)
682                         uart_handle_dcd_change(uport,
683                                                zport->mctrl & TIOCM_CAR);
684                 if (delta & TIOCM_RNG)
685                         uport->icount.dsr++;
686                 if (delta & TIOCM_DSR)
687                         uport->icount.rng++;
688
689                 if (delta)
690                         wake_up_interruptible(&uport->state->port.delta_msr_wait);
691
692                 spin_lock(&scc->zlock);
693         }
694
695         /* Clear the status condition...  */
696         write_zsreg(zport, R0, RES_EXT_INT);
697
698         spin_unlock(&scc->zlock);
699 }
700
701 /*
702  * This is the Z85C30 driver's generic interrupt routine.
703  */
704 static irqreturn_t zs_interrupt(int irq, void *dev_id)
705 {
706         struct zs_scc *scc = dev_id;
707         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
708         struct zs_port *zport_b = &scc->zport[ZS_CHAN_B];
709         irqreturn_t status = IRQ_NONE;
710         u8 zs_intreg;
711         int count;
712
713         /*
714          * NOTE: The read register 3, which holds the irq status,
715          *       does so for both channels on each chip.  Although
716          *       the status value itself must be read from the A
717          *       channel and is only valid when read from channel A.
718          *       Yes... broken hardware...
719          */
720         for (count = 16; count; count--) {
721                 spin_lock(&scc->zlock);
722                 zs_intreg = read_zsreg(zport_a, R3);
723                 spin_unlock(&scc->zlock);
724                 if (!zs_intreg)
725                         break;
726
727                 /*
728                  * We do not like losing characters, so we prioritise
729                  * interrupt sources a little bit differently than
730                  * the SCC would, was it allowed to.
731                  */
732                 if (zs_intreg & CHBRxIP)
733                         zs_receive_chars(zport_b);
734                 if (zs_intreg & CHARxIP)
735                         zs_receive_chars(zport_a);
736                 if (zs_intreg & CHBEXT)
737                         zs_status_handle(zport_b, zport_a);
738                 if (zs_intreg & CHAEXT)
739                         zs_status_handle(zport_a, zport_a);
740                 if (zs_intreg & CHBTxIP)
741                         zs_transmit_chars(zport_b);
742                 if (zs_intreg & CHATxIP)
743                         zs_transmit_chars(zport_a);
744
745                 status = IRQ_HANDLED;
746         }
747
748         return status;
749 }
750
751
752 /*
753  * Finally, routines used to initialize the serial port.
754  */
755 static int zs_startup(struct uart_port *uport)
756 {
757         struct zs_port *zport = to_zport(uport);
758         struct zs_scc *scc = zport->scc;
759         unsigned long flags;
760         int irq_guard;
761         int ret;
762
763         irq_guard = atomic_add_return(1, &scc->irq_guard);
764         if (irq_guard == 1) {
765                 ret = request_irq(zport->port.irq, zs_interrupt,
766                                   IRQF_SHARED, "scc", scc);
767                 if (ret) {
768                         atomic_add(-1, &scc->irq_guard);
769                         printk(KERN_ERR "zs: can't get irq %d\n",
770                                zport->port.irq);
771                         return ret;
772                 }
773         }
774
775         spin_lock_irqsave(&scc->zlock, flags);
776
777         /* Clear the receive FIFO.  */
778         zs_receive_drain(zport);
779
780         /* Clear the interrupt registers.  */
781         write_zsreg(zport, R0, ERR_RES);
782         write_zsreg(zport, R0, RES_Tx_P);
783         /* But Ext only if not being handled already.  */
784         if (!(zport->regs[1] & EXT_INT_ENAB))
785                 write_zsreg(zport, R0, RES_EXT_INT);
786
787         /* Finally, enable sequencing and interrupts.  */
788         zport->regs[1] &= ~RxINT_MASK;
789         zport->regs[1] |= RxINT_ALL | TxINT_ENAB | EXT_INT_ENAB;
790         zport->regs[3] |= RxENABLE;
791         zport->regs[15] |= BRKIE;
792         write_zsreg(zport, R1, zport->regs[1]);
793         write_zsreg(zport, R3, zport->regs[3]);
794         write_zsreg(zport, R5, zport->regs[5]);
795         write_zsreg(zport, R15, zport->regs[15]);
796
797         /* Record the current state of RR0.  */
798         zport->mctrl = zs_raw_get_mctrl(zport);
799         zport->brk = read_zsreg(zport, R0) & BRK_ABRT;
800
801         zport->tx_stopped = 1;
802
803         spin_unlock_irqrestore(&scc->zlock, flags);
804
805         return 0;
806 }
807
808 static void zs_shutdown(struct uart_port *uport)
809 {
810         struct zs_port *zport = to_zport(uport);
811         struct zs_scc *scc = zport->scc;
812         unsigned long flags;
813         int irq_guard;
814
815         spin_lock_irqsave(&scc->zlock, flags);
816
817         zport->regs[3] &= ~RxENABLE;
818         write_zsreg(zport, R5, zport->regs[5]);
819         write_zsreg(zport, R3, zport->regs[3]);
820
821         spin_unlock_irqrestore(&scc->zlock, flags);
822
823         irq_guard = atomic_add_return(-1, &scc->irq_guard);
824         if (!irq_guard)
825                 free_irq(zport->port.irq, scc);
826 }
827
828
829 static void zs_reset(struct zs_port *zport)
830 {
831         struct zs_scc *scc = zport->scc;
832         int irq;
833         unsigned long flags;
834
835         spin_lock_irqsave(&scc->zlock, flags);
836         irq = !irqs_disabled_flags(flags);
837         if (!scc->initialised) {
838                 /* Reset the pointer first, just in case...  */
839                 read_zsreg(zport, R0);
840                 /* And let the current transmission finish.  */
841                 zs_line_drain(zport, irq);
842                 write_zsreg(zport, R9, FHWRES);
843                 udelay(10);
844                 write_zsreg(zport, R9, 0);
845                 scc->initialised = 1;
846         }
847         load_zsregs(zport, zport->regs, irq);
848         spin_unlock_irqrestore(&scc->zlock, flags);
849 }
850
851 static void zs_set_termios(struct uart_port *uport, struct ktermios *termios,
852                            struct ktermios *old_termios)
853 {
854         struct zs_port *zport = to_zport(uport);
855         struct zs_scc *scc = zport->scc;
856         struct zs_port *zport_a = &scc->zport[ZS_CHAN_A];
857         int irq;
858         unsigned int baud, brg;
859         unsigned long flags;
860
861         spin_lock_irqsave(&scc->zlock, flags);
862         irq = !irqs_disabled_flags(flags);
863
864         /* Byte size.  */
865         zport->regs[3] &= ~RxNBITS_MASK;
866         zport->regs[5] &= ~TxNBITS_MASK;
867         switch (termios->c_cflag & CSIZE) {
868         case CS5:
869                 zport->regs[3] |= Rx5;
870                 zport->regs[5] |= Tx5;
871                 break;
872         case CS6:
873                 zport->regs[3] |= Rx6;
874                 zport->regs[5] |= Tx6;
875                 break;
876         case CS7:
877                 zport->regs[3] |= Rx7;
878                 zport->regs[5] |= Tx7;
879                 break;
880         case CS8:
881         default:
882                 zport->regs[3] |= Rx8;
883                 zport->regs[5] |= Tx8;
884                 break;
885         }
886
887         /* Parity and stop bits.  */
888         zport->regs[4] &= ~(XCLK_MASK | SB_MASK | PAR_ENA | PAR_EVEN);
889         if (termios->c_cflag & CSTOPB)
890                 zport->regs[4] |= SB2;
891         else
892                 zport->regs[4] |= SB1;
893         if (termios->c_cflag & PARENB)
894                 zport->regs[4] |= PAR_ENA;
895         if (!(termios->c_cflag & PARODD))
896                 zport->regs[4] |= PAR_EVEN;
897         switch (zport->clk_mode) {
898         case 64:
899                 zport->regs[4] |= X64CLK;
900                 break;
901         case 32:
902                 zport->regs[4] |= X32CLK;
903                 break;
904         case 16:
905                 zport->regs[4] |= X16CLK;
906                 break;
907         case 1:
908                 zport->regs[4] |= X1CLK;
909                 break;
910         default:
911                 BUG();
912         }
913
914         baud = uart_get_baud_rate(uport, termios, old_termios, 0,
915                                   uport->uartclk / zport->clk_mode / 4);
916
917         brg = ZS_BPS_TO_BRG(baud, uport->uartclk / zport->clk_mode);
918         zport->regs[12] = brg & 0xff;
919         zport->regs[13] = (brg >> 8) & 0xff;
920
921         uart_update_timeout(uport, termios->c_cflag, baud);
922
923         uport->read_status_mask = Rx_OVR;
924         if (termios->c_iflag & INPCK)
925                 uport->read_status_mask |= FRM_ERR | PAR_ERR;
926         if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
927                 uport->read_status_mask |= Rx_BRK;
928
929         uport->ignore_status_mask = 0;
930         if (termios->c_iflag & IGNPAR)
931                 uport->ignore_status_mask |= FRM_ERR | PAR_ERR;
932         if (termios->c_iflag & IGNBRK) {
933                 uport->ignore_status_mask |= Rx_BRK;
934                 if (termios->c_iflag & IGNPAR)
935                         uport->ignore_status_mask |= Rx_OVR;
936         }
937
938         if (termios->c_cflag & CREAD)
939                 zport->regs[3] |= RxENABLE;
940         else
941                 zport->regs[3] &= ~RxENABLE;
942
943         if (zport != zport_a) {
944                 if (!(termios->c_cflag & CLOCAL)) {
945                         zport->regs[15] |= DCDIE;
946                 } else
947                         zport->regs[15] &= ~DCDIE;
948                 if (termios->c_cflag & CRTSCTS) {
949                         zport->regs[15] |= CTSIE;
950                 } else
951                         zport->regs[15] &= ~CTSIE;
952                 zs_raw_xor_mctrl(zport);
953         }
954
955         /* Load up the new values.  */
956         load_zsregs(zport, zport->regs, irq);
957
958         spin_unlock_irqrestore(&scc->zlock, flags);
959 }
960
961 /*
962  * Hack alert!
963  * Required solely so that the initial PROM-based console
964  * works undisturbed in parallel with this one.
965  */
966 static void zs_pm(struct uart_port *uport, unsigned int state,
967                   unsigned int oldstate)
968 {
969         struct zs_port *zport = to_zport(uport);
970
971         if (state < 3)
972                 zport->regs[5] |= TxENAB;
973         else
974                 zport->regs[5] &= ~TxENAB;
975         write_zsreg(zport, R5, zport->regs[5]);
976 }
977
978
979 static const char *zs_type(struct uart_port *uport)
980 {
981         return "Z85C30 SCC";
982 }
983
984 static void zs_release_port(struct uart_port *uport)
985 {
986         iounmap(uport->membase);
987         uport->membase = 0;
988         release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
989 }
990
991 static int zs_map_port(struct uart_port *uport)
992 {
993         if (!uport->membase)
994                 uport->membase = ioremap_nocache(uport->mapbase,
995                                                  ZS_CHAN_IO_SIZE);
996         if (!uport->membase) {
997                 printk(KERN_ERR "zs: Cannot map MMIO\n");
998                 return -ENOMEM;
999         }
1000         return 0;
1001 }
1002
1003 static int zs_request_port(struct uart_port *uport)
1004 {
1005         int ret;
1006
1007         if (!request_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE, "scc")) {
1008                 printk(KERN_ERR "zs: Unable to reserve MMIO resource\n");
1009                 return -EBUSY;
1010         }
1011         ret = zs_map_port(uport);
1012         if (ret) {
1013                 release_mem_region(uport->mapbase, ZS_CHAN_IO_SIZE);
1014                 return ret;
1015         }
1016         return 0;
1017 }
1018
1019 static void zs_config_port(struct uart_port *uport, int flags)
1020 {
1021         struct zs_port *zport = to_zport(uport);
1022
1023         if (flags & UART_CONFIG_TYPE) {
1024                 if (zs_request_port(uport))
1025                         return;
1026
1027                 uport->type = PORT_ZS;
1028
1029                 zs_reset(zport);
1030         }
1031 }
1032
1033 static int zs_verify_port(struct uart_port *uport, struct serial_struct *ser)
1034 {
1035         struct zs_port *zport = to_zport(uport);
1036         int ret = 0;
1037
1038         if (ser->type != PORT_UNKNOWN && ser->type != PORT_ZS)
1039                 ret = -EINVAL;
1040         if (ser->irq != uport->irq)
1041                 ret = -EINVAL;
1042         if (ser->baud_base != uport->uartclk / zport->clk_mode / 4)
1043                 ret = -EINVAL;
1044         return ret;
1045 }
1046
1047
1048 static struct uart_ops zs_ops = {
1049         .tx_empty       = zs_tx_empty,
1050         .set_mctrl      = zs_set_mctrl,
1051         .get_mctrl      = zs_get_mctrl,
1052         .stop_tx        = zs_stop_tx,
1053         .start_tx       = zs_start_tx,
1054         .stop_rx        = zs_stop_rx,
1055         .enable_ms      = zs_enable_ms,
1056         .break_ctl      = zs_break_ctl,
1057         .startup        = zs_startup,
1058         .shutdown       = zs_shutdown,
1059         .set_termios    = zs_set_termios,
1060         .pm             = zs_pm,
1061         .type           = zs_type,
1062         .release_port   = zs_release_port,
1063         .request_port   = zs_request_port,
1064         .config_port    = zs_config_port,
1065         .verify_port    = zs_verify_port,
1066 };
1067
1068 /*
1069  * Initialize Z85C30 port structures.
1070  */
1071 static int __init zs_probe_sccs(void)
1072 {
1073         static int probed;
1074         struct zs_parms zs_parms;
1075         int chip, side, irq;
1076         int n_chips = 0;
1077         int i;
1078
1079         if (probed)
1080                 return 0;
1081
1082         irq = dec_interrupt[DEC_IRQ_SCC0];
1083         if (irq >= 0) {
1084                 zs_parms.scc[n_chips] = IOASIC_SCC0;
1085                 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC0];
1086                 n_chips++;
1087         }
1088         irq = dec_interrupt[DEC_IRQ_SCC1];
1089         if (irq >= 0) {
1090                 zs_parms.scc[n_chips] = IOASIC_SCC1;
1091                 zs_parms.irq[n_chips] = dec_interrupt[DEC_IRQ_SCC1];
1092                 n_chips++;
1093         }
1094         if (!n_chips)
1095                 return -ENXIO;
1096
1097         probed = 1;
1098
1099         for (chip = 0; chip < n_chips; chip++) {
1100                 spin_lock_init(&zs_sccs[chip].zlock);
1101                 for (side = 0; side < ZS_NUM_CHAN; side++) {
1102                         struct zs_port *zport = &zs_sccs[chip].zport[side];
1103                         struct uart_port *uport = &zport->port;
1104
1105                         zport->scc      = &zs_sccs[chip];
1106                         zport->clk_mode = 16;
1107
1108                         uport->irq      = zs_parms.irq[chip];
1109                         uport->uartclk  = ZS_CLOCK;
1110                         uport->fifosize = 1;
1111                         uport->iotype   = UPIO_MEM;
1112                         uport->flags    = UPF_BOOT_AUTOCONF;
1113                         uport->ops      = &zs_ops;
1114                         uport->line     = chip * ZS_NUM_CHAN + side;
1115                         uport->mapbase  = dec_kn_slot_base +
1116                                           zs_parms.scc[chip] +
1117                                           (side ^ ZS_CHAN_B) * ZS_CHAN_IO_SIZE;
1118
1119                         for (i = 0; i < ZS_NUM_REGS; i++)
1120                                 zport->regs[i] = zs_init_regs[i];
1121                 }
1122         }
1123
1124         return 0;
1125 }
1126
1127
1128 #ifdef CONFIG_SERIAL_ZS_CONSOLE
1129 static void zs_console_putchar(struct uart_port *uport, int ch)
1130 {
1131         struct zs_port *zport = to_zport(uport);
1132         struct zs_scc *scc = zport->scc;
1133         int irq;
1134         unsigned long flags;
1135
1136         spin_lock_irqsave(&scc->zlock, flags);
1137         irq = !irqs_disabled_flags(flags);
1138         if (zs_transmit_drain(zport, irq))
1139                 write_zsdata(zport, ch);
1140         spin_unlock_irqrestore(&scc->zlock, flags);
1141 }
1142
1143 /*
1144  * Print a string to the serial port trying not to disturb
1145  * any possible real use of the port...
1146  */
1147 static void zs_console_write(struct console *co, const char *s,
1148                              unsigned int count)
1149 {
1150         int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1151         struct zs_port *zport = &zs_sccs[chip].zport[side];
1152         struct zs_scc *scc = zport->scc;
1153         unsigned long flags;
1154         u8 txint, txenb;
1155         int irq;
1156
1157         /* Disable transmit interrupts and enable the transmitter. */
1158         spin_lock_irqsave(&scc->zlock, flags);
1159         txint = zport->regs[1];
1160         txenb = zport->regs[5];
1161         if (txint & TxINT_ENAB) {
1162                 zport->regs[1] = txint & ~TxINT_ENAB;
1163                 write_zsreg(zport, R1, zport->regs[1]);
1164         }
1165         if (!(txenb & TxENAB)) {
1166                 zport->regs[5] = txenb | TxENAB;
1167                 write_zsreg(zport, R5, zport->regs[5]);
1168         }
1169         spin_unlock_irqrestore(&scc->zlock, flags);
1170
1171         uart_console_write(&zport->port, s, count, zs_console_putchar);
1172
1173         /* Restore transmit interrupts and the transmitter enable. */
1174         spin_lock_irqsave(&scc->zlock, flags);
1175         irq = !irqs_disabled_flags(flags);
1176         zs_line_drain(zport, irq);
1177         if (!(txenb & TxENAB)) {
1178                 zport->regs[5] &= ~TxENAB;
1179                 write_zsreg(zport, R5, zport->regs[5]);
1180         }
1181         if (txint & TxINT_ENAB) {
1182                 zport->regs[1] |= TxINT_ENAB;
1183                 write_zsreg(zport, R1, zport->regs[1]);
1184
1185                 /* Resume any transmission as the TxIP bit won't be set.  */
1186                 if (!zport->tx_stopped)
1187                         zs_raw_transmit_chars(zport);
1188         }
1189         spin_unlock_irqrestore(&scc->zlock, flags);
1190 }
1191
1192 /*
1193  * Setup serial console baud/bits/parity.  We do two things here:
1194  * - construct a cflag setting for the first uart_open()
1195  * - initialise the serial port
1196  * Return non-zero if we didn't find a serial port.
1197  */
1198 static int __init zs_console_setup(struct console *co, char *options)
1199 {
1200         int chip = co->index / ZS_NUM_CHAN, side = co->index % ZS_NUM_CHAN;
1201         struct zs_port *zport = &zs_sccs[chip].zport[side];
1202         struct uart_port *uport = &zport->port;
1203         int baud = 9600;
1204         int bits = 8;
1205         int parity = 'n';
1206         int flow = 'n';
1207         int ret;
1208
1209         ret = zs_map_port(uport);
1210         if (ret)
1211                 return ret;
1212
1213         zs_reset(zport);
1214         zs_pm(uport, 0, -1);
1215
1216         if (options)
1217                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1218         return uart_set_options(uport, co, baud, parity, bits, flow);
1219 }
1220
1221 static struct uart_driver zs_reg;
1222 static struct console zs_console = {
1223         .name   = "ttyS",
1224         .write  = zs_console_write,
1225         .device = uart_console_device,
1226         .setup  = zs_console_setup,
1227         .flags  = CON_PRINTBUFFER,
1228         .index  = -1,
1229         .data   = &zs_reg,
1230 };
1231
1232 /*
1233  *      Register console.
1234  */
1235 static int __init zs_serial_console_init(void)
1236 {
1237         int ret;
1238
1239         ret = zs_probe_sccs();
1240         if (ret)
1241                 return ret;
1242         register_console(&zs_console);
1243
1244         return 0;
1245 }
1246
1247 console_initcall(zs_serial_console_init);
1248
1249 #define SERIAL_ZS_CONSOLE       &zs_console
1250 #else
1251 #define SERIAL_ZS_CONSOLE       NULL
1252 #endif /* CONFIG_SERIAL_ZS_CONSOLE */
1253
1254 static struct uart_driver zs_reg = {
1255         .owner                  = THIS_MODULE,
1256         .driver_name            = "serial",
1257         .dev_name               = "ttyS",
1258         .major                  = TTY_MAJOR,
1259         .minor                  = 64,
1260         .nr                     = ZS_NUM_SCCS * ZS_NUM_CHAN,
1261         .cons                   = SERIAL_ZS_CONSOLE,
1262 };
1263
1264 /* zs_init inits the driver. */
1265 static int __init zs_init(void)
1266 {
1267         int i, ret;
1268
1269         pr_info("%s%s\n", zs_name, zs_version);
1270
1271         /* Find out how many Z85C30 SCCs we have.  */
1272         ret = zs_probe_sccs();
1273         if (ret)
1274                 return ret;
1275
1276         ret = uart_register_driver(&zs_reg);
1277         if (ret)
1278                 return ret;
1279
1280         for (i = 0; i < ZS_NUM_SCCS * ZS_NUM_CHAN; i++) {
1281                 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1282                 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1283                 struct uart_port *uport = &zport->port;
1284
1285                 if (zport->scc)
1286                         uart_add_one_port(&zs_reg, uport);
1287         }
1288
1289         return 0;
1290 }
1291
1292 static void __exit zs_exit(void)
1293 {
1294         int i;
1295
1296         for (i = ZS_NUM_SCCS * ZS_NUM_CHAN - 1; i >= 0; i--) {
1297                 struct zs_scc *scc = &zs_sccs[i / ZS_NUM_CHAN];
1298                 struct zs_port *zport = &scc->zport[i % ZS_NUM_CHAN];
1299                 struct uart_port *uport = &zport->port;
1300
1301                 if (zport->scc)
1302                         uart_remove_one_port(&zs_reg, uport);
1303         }
1304
1305         uart_unregister_driver(&zs_reg);
1306 }
1307
1308 module_init(zs_init);
1309 module_exit(zs_exit);