2 * core.c - ChipIdea USB IP core family device controller
4 * Copyright (C) 2008 Chipidea - MIPS Technologies, Inc. All rights reserved.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 * Description: ChipIdea USB IP core family device controller
16 * This driver is composed of several blocks:
17 * - HW: hardware interface
18 * - DBG: debug facilities (optional)
20 * - ISR: interrupts handling
21 * - ENDPT: endpoint operations (Gadget API)
22 * - GADGET: gadget operations (Gadget API)
23 * - BUS: bus glue code, bus abstraction layer
26 * - STALL_IN: non-empty bulk-in pipes cannot be halted
27 * if defined mass storage compliance succeeds but with warnings
31 * if undefined usbtest 13 fails
32 * - TRACE: enable function tracing (depends on DEBUG)
35 * - Chapter 9 & Mass Storage Compliance with Gadget File Storage
36 * - Chapter 9 Compliance with Gadget Zero (STALL_IN undefined)
37 * - Normal & LPM support
40 * - OK: 0-12, 13 (STALL_IN defined) & 14
41 * - Not Supported: 15 & 16 (ISO)
44 * - Suspend & Remote Wakeup
46 #include <linux/delay.h>
47 #include <linux/device.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/extcon.h>
50 #include <linux/phy/phy.h>
51 #include <linux/platform_device.h>
52 #include <linux/module.h>
53 #include <linux/idr.h>
54 #include <linux/interrupt.h>
56 #include <linux/kernel.h>
57 #include <linux/slab.h>
58 #include <linux/pm_runtime.h>
59 #include <linux/usb/ch9.h>
60 #include <linux/usb/gadget.h>
61 #include <linux/usb/otg.h>
62 #include <linux/usb/chipidea.h>
63 #include <linux/usb/of.h>
65 #include <linux/regulator/consumer.h>
66 #include <linux/usb/ehci_def.h>
75 /* Controller register map */
76 static const u8 ci_regs_nolpm[] = {
77 [CAP_CAPLENGTH] = 0x00U,
78 [CAP_HCCPARAMS] = 0x08U,
79 [CAP_DCCPARAMS] = 0x24U,
80 [CAP_TESTMODE] = 0x38U,
84 [OP_DEVICEADDR] = 0x14U,
85 [OP_ENDPTLISTADDR] = 0x18U,
87 [OP_BURSTSIZE] = 0x20U,
88 [OP_ULPI_VIEWPORT] = 0x30U,
93 [OP_ENDPTSETUPSTAT] = 0x6CU,
94 [OP_ENDPTPRIME] = 0x70U,
95 [OP_ENDPTFLUSH] = 0x74U,
96 [OP_ENDPTSTAT] = 0x78U,
97 [OP_ENDPTCOMPLETE] = 0x7CU,
98 [OP_ENDPTCTRL] = 0x80U,
101 static const u8 ci_regs_lpm[] = {
102 [CAP_CAPLENGTH] = 0x00U,
103 [CAP_HCCPARAMS] = 0x08U,
104 [CAP_DCCPARAMS] = 0x24U,
105 [CAP_TESTMODE] = 0xFCU,
108 [OP_USBINTR] = 0x08U,
109 [OP_DEVICEADDR] = 0x14U,
110 [OP_ENDPTLISTADDR] = 0x18U,
112 [OP_BURSTSIZE] = 0x20U,
113 [OP_ULPI_VIEWPORT] = 0x30U,
117 [OP_USBMODE] = 0xC8U,
118 [OP_ENDPTSETUPSTAT] = 0xD8U,
119 [OP_ENDPTPRIME] = 0xDCU,
120 [OP_ENDPTFLUSH] = 0xE0U,
121 [OP_ENDPTSTAT] = 0xE4U,
122 [OP_ENDPTCOMPLETE] = 0xE8U,
123 [OP_ENDPTCTRL] = 0xECU,
126 static void hw_alloc_regmap(struct ci_hdrc *ci, bool is_lpm)
130 for (i = 0; i < OP_ENDPTCTRL; i++)
131 ci->hw_bank.regmap[i] =
132 (i <= CAP_LAST ? ci->hw_bank.cap : ci->hw_bank.op) +
133 (is_lpm ? ci_regs_lpm[i] : ci_regs_nolpm[i]);
135 for (; i <= OP_LAST; i++)
136 ci->hw_bank.regmap[i] = ci->hw_bank.op +
137 4 * (i - OP_ENDPTCTRL) +
139 ? ci_regs_lpm[OP_ENDPTCTRL]
140 : ci_regs_nolpm[OP_ENDPTCTRL]);
144 static enum ci_revision ci_get_revision(struct ci_hdrc *ci)
146 int ver = hw_read_id_reg(ci, ID_ID, VERSION) >> __ffs(VERSION);
147 enum ci_revision rev = CI_REVISION_UNKNOWN;
150 rev = hw_read_id_reg(ci, ID_ID, REVISION)
152 rev += CI_REVISION_20;
153 } else if (ver == 0x0) {
154 rev = CI_REVISION_1X;
161 * hw_read_intr_enable: returns interrupt enable register
163 * @ci: the controller
165 * This function returns register data
167 u32 hw_read_intr_enable(struct ci_hdrc *ci)
169 return hw_read(ci, OP_USBINTR, ~0);
173 * hw_read_intr_status: returns interrupt status register
175 * @ci: the controller
177 * This function returns register data
179 u32 hw_read_intr_status(struct ci_hdrc *ci)
181 return hw_read(ci, OP_USBSTS, ~0);
185 * hw_port_test_set: writes port test mode (execute without interruption)
188 * This function returns an error code
190 int hw_port_test_set(struct ci_hdrc *ci, u8 mode)
192 const u8 TEST_MODE_MAX = 7;
194 if (mode > TEST_MODE_MAX)
197 hw_write(ci, OP_PORTSC, PORTSC_PTC, mode << __ffs(PORTSC_PTC));
202 * hw_port_test_get: reads port test mode value
204 * @ci: the controller
206 * This function returns port test mode value
208 u8 hw_port_test_get(struct ci_hdrc *ci)
210 return hw_read(ci, OP_PORTSC, PORTSC_PTC) >> __ffs(PORTSC_PTC);
213 static void hw_wait_phy_stable(void)
216 * The phy needs some delay to output the stable status from low
217 * power mode. And for OTGSC, the status inputs are debounced
218 * using a 1 ms time constant, so, delay 2ms for controller to get
219 * the stable status, like vbus and id when the phy leaves low power.
221 usleep_range(2000, 2500);
224 /* The PHY enters/leaves low power mode */
225 static void ci_hdrc_enter_lpm(struct ci_hdrc *ci, bool enable)
227 enum ci_hw_regs reg = ci->hw_bank.lpm ? OP_DEVLC : OP_PORTSC;
228 bool lpm = !!(hw_read(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm)));
231 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
232 PORTSC_PHCD(ci->hw_bank.lpm));
233 else if (!enable && lpm)
234 hw_write(ci, reg, PORTSC_PHCD(ci->hw_bank.lpm),
238 static int hw_device_init(struct ci_hdrc *ci, void __iomem *base)
242 /* bank is a module variable */
243 ci->hw_bank.abs = base;
245 ci->hw_bank.cap = ci->hw_bank.abs;
246 ci->hw_bank.cap += ci->platdata->capoffset;
247 ci->hw_bank.op = ci->hw_bank.cap + (ioread32(ci->hw_bank.cap) & 0xff);
249 hw_alloc_regmap(ci, false);
250 reg = hw_read(ci, CAP_HCCPARAMS, HCCPARAMS_LEN) >>
251 __ffs(HCCPARAMS_LEN);
252 ci->hw_bank.lpm = reg;
254 hw_alloc_regmap(ci, !!reg);
255 ci->hw_bank.size = ci->hw_bank.op - ci->hw_bank.abs;
256 ci->hw_bank.size += OP_LAST;
257 ci->hw_bank.size /= sizeof(u32);
259 reg = hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DEN) >>
260 __ffs(DCCPARAMS_DEN);
261 ci->hw_ep_max = reg * 2; /* cache hw ENDPT_MAX */
263 if (ci->hw_ep_max > ENDPT_MAX)
266 ci_hdrc_enter_lpm(ci, false);
268 /* Disable all interrupts bits */
269 hw_write(ci, OP_USBINTR, 0xffffffff, 0);
271 /* Clear all interrupts status bits*/
272 hw_write(ci, OP_USBSTS, 0xffffffff, 0xffffffff);
274 ci->rev = ci_get_revision(ci);
277 "ChipIdea HDRC found, revision: %d, lpm: %d; cap: %p op: %p\n",
278 ci->rev, ci->hw_bank.lpm, ci->hw_bank.cap, ci->hw_bank.op);
280 /* setup lock mode ? */
282 /* ENDPTSETUPSTAT is '0' by default */
284 /* HCSPARAMS.bf.ppc SHOULD BE zero for device */
289 void hw_phymode_configure(struct ci_hdrc *ci)
291 u32 portsc, lpm, sts = 0;
293 switch (ci->platdata->phy_mode) {
294 case USBPHY_INTERFACE_MODE_UTMI:
295 portsc = PORTSC_PTS(PTS_UTMI);
296 lpm = DEVLC_PTS(PTS_UTMI);
298 case USBPHY_INTERFACE_MODE_UTMIW:
299 portsc = PORTSC_PTS(PTS_UTMI) | PORTSC_PTW;
300 lpm = DEVLC_PTS(PTS_UTMI) | DEVLC_PTW;
302 case USBPHY_INTERFACE_MODE_ULPI:
303 portsc = PORTSC_PTS(PTS_ULPI);
304 lpm = DEVLC_PTS(PTS_ULPI);
306 case USBPHY_INTERFACE_MODE_SERIAL:
307 portsc = PORTSC_PTS(PTS_SERIAL);
308 lpm = DEVLC_PTS(PTS_SERIAL);
311 case USBPHY_INTERFACE_MODE_HSIC:
312 portsc = PORTSC_PTS(PTS_HSIC);
313 lpm = DEVLC_PTS(PTS_HSIC);
319 if (ci->hw_bank.lpm) {
320 hw_write(ci, OP_DEVLC, DEVLC_PTS(7) | DEVLC_PTW, lpm);
322 hw_write(ci, OP_DEVLC, DEVLC_STS, DEVLC_STS);
324 hw_write(ci, OP_PORTSC, PORTSC_PTS(7) | PORTSC_PTW, portsc);
326 hw_write(ci, OP_PORTSC, PORTSC_STS, PORTSC_STS);
329 EXPORT_SYMBOL_GPL(hw_phymode_configure);
332 * _ci_usb_phy_init: initialize phy taking in account both phy and usb_phy
334 * @ci: the controller
336 * This function returns an error code if the phy failed to init
338 static int _ci_usb_phy_init(struct ci_hdrc *ci)
343 ret = phy_init(ci->phy);
347 ret = phy_power_on(ci->phy);
353 ret = usb_phy_init(ci->usb_phy);
360 * _ci_usb_phy_exit: deinitialize phy taking in account both phy and usb_phy
362 * @ci: the controller
364 static void ci_usb_phy_exit(struct ci_hdrc *ci)
366 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
370 phy_power_off(ci->phy);
373 usb_phy_shutdown(ci->usb_phy);
378 * ci_usb_phy_init: initialize phy according to different phy type
379 * @ci: the controller
381 * This function returns an error code if usb_phy_init has failed
383 static int ci_usb_phy_init(struct ci_hdrc *ci)
387 if (ci->platdata->flags & CI_HDRC_OVERRIDE_PHY_CONTROL)
390 switch (ci->platdata->phy_mode) {
391 case USBPHY_INTERFACE_MODE_UTMI:
392 case USBPHY_INTERFACE_MODE_UTMIW:
393 case USBPHY_INTERFACE_MODE_HSIC:
394 ret = _ci_usb_phy_init(ci);
396 hw_wait_phy_stable();
399 hw_phymode_configure(ci);
401 case USBPHY_INTERFACE_MODE_ULPI:
402 case USBPHY_INTERFACE_MODE_SERIAL:
403 hw_phymode_configure(ci);
404 ret = _ci_usb_phy_init(ci);
409 ret = _ci_usb_phy_init(ci);
411 hw_wait_phy_stable();
419 * ci_platform_configure: do controller configure
420 * @ci: the controller
423 void ci_platform_configure(struct ci_hdrc *ci)
425 bool is_device_mode, is_host_mode;
427 is_device_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_DC;
428 is_host_mode = hw_read(ci, OP_USBMODE, USBMODE_CM) == USBMODE_CM_HC;
430 if (is_device_mode) {
431 phy_set_mode(ci->phy, PHY_MODE_USB_DEVICE);
433 if (ci->platdata->flags & CI_HDRC_DISABLE_DEVICE_STREAMING)
434 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
439 phy_set_mode(ci->phy, PHY_MODE_USB_HOST);
441 if (ci->platdata->flags & CI_HDRC_DISABLE_HOST_STREAMING)
442 hw_write(ci, OP_USBMODE, USBMODE_CI_SDIS,
446 if (ci->platdata->flags & CI_HDRC_FORCE_FULLSPEED) {
448 hw_write(ci, OP_DEVLC, DEVLC_PFSC, DEVLC_PFSC);
450 hw_write(ci, OP_PORTSC, PORTSC_PFSC, PORTSC_PFSC);
453 if (ci->platdata->flags & CI_HDRC_SET_NON_ZERO_TTHA)
454 hw_write(ci, OP_TTCTRL, TTCTRL_TTHA_MASK, TTCTRL_TTHA);
456 hw_write(ci, OP_USBCMD, 0xff0000, ci->platdata->itc_setting << 16);
458 if (ci->platdata->flags & CI_HDRC_OVERRIDE_AHB_BURST)
459 hw_write_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK,
460 ci->platdata->ahb_burst_config);
462 /* override burst size, take effect only when ahb_burst_config is 0 */
463 if (!hw_read_id_reg(ci, ID_SBUSCFG, AHBBRST_MASK)) {
464 if (ci->platdata->flags & CI_HDRC_OVERRIDE_TX_BURST)
465 hw_write(ci, OP_BURSTSIZE, TX_BURST_MASK,
466 ci->platdata->tx_burst_size << __ffs(TX_BURST_MASK));
468 if (ci->platdata->flags & CI_HDRC_OVERRIDE_RX_BURST)
469 hw_write(ci, OP_BURSTSIZE, RX_BURST_MASK,
470 ci->platdata->rx_burst_size);
475 * hw_controller_reset: do controller reset
476 * @ci: the controller
478 * This function returns an error code
480 static int hw_controller_reset(struct ci_hdrc *ci)
484 hw_write(ci, OP_USBCMD, USBCMD_RST, USBCMD_RST);
485 while (hw_read(ci, OP_USBCMD, USBCMD_RST)) {
495 * hw_device_reset: resets chip (execute without interruption)
496 * @ci: the controller
498 * This function returns an error code
500 int hw_device_reset(struct ci_hdrc *ci)
504 /* should flush & stop before reset */
505 hw_write(ci, OP_ENDPTFLUSH, ~0, ~0);
506 hw_write(ci, OP_USBCMD, USBCMD_RS, 0);
508 ret = hw_controller_reset(ci);
510 dev_err(ci->dev, "error resetting controller, ret=%d\n", ret);
514 if (ci->platdata->notify_event) {
515 ret = ci->platdata->notify_event(ci,
516 CI_HDRC_CONTROLLER_RESET_EVENT);
521 /* USBMODE should be configured step by step */
522 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_IDLE);
523 hw_write(ci, OP_USBMODE, USBMODE_CM, USBMODE_CM_DC);
525 hw_write(ci, OP_USBMODE, USBMODE_SLOM, USBMODE_SLOM);
527 if (hw_read(ci, OP_USBMODE, USBMODE_CM) != USBMODE_CM_DC) {
528 pr_err("cannot enter in %s device mode", ci_role(ci)->name);
529 pr_err("lpm = %i", ci->hw_bank.lpm);
533 ci_platform_configure(ci);
538 static irqreturn_t ci_irq_handler(int irq, void *data)
540 struct ci_hdrc *ci = data;
541 irqreturn_t ret = IRQ_NONE;
545 disable_irq_nosync(irq);
546 ci->wakeup_int = true;
547 pm_runtime_get(ci->dev);
552 otgsc = hw_read_otgsc(ci, ~0);
553 if (ci_otg_is_fsm_mode(ci)) {
554 ret = ci_otg_fsm_irq(ci);
555 if (ret == IRQ_HANDLED)
561 * Handle id change interrupt, it indicates device/host function
564 if (ci->is_otg && (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS)) {
566 /* Clear ID change irq status */
567 hw_write_otgsc(ci, OTGSC_IDIS, OTGSC_IDIS);
568 ci_otg_queue_work(ci);
573 * Handle vbus change interrupt, it indicates device connection
574 * and disconnection events.
576 if (ci->is_otg && (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS)) {
577 ci->b_sess_valid_event = true;
579 hw_write_otgsc(ci, OTGSC_BSVIS, OTGSC_BSVIS);
580 ci_otg_queue_work(ci);
584 /* Handle device/host interrupt */
585 if (ci->role != CI_ROLE_END)
586 ret = ci_role(ci)->irq(ci);
591 static void ci_irq(struct ci_hdrc *ci)
595 local_irq_save(flags);
596 ci_irq_handler(ci->irq, ci);
597 local_irq_restore(flags);
600 static int ci_cable_notifier(struct notifier_block *nb, unsigned long event,
603 struct ci_hdrc_cable *cbl = container_of(nb, struct ci_hdrc_cable, nb);
604 struct ci_hdrc *ci = cbl->ci;
606 cbl->connected = event;
613 static int ci_get_platdata(struct device *dev,
614 struct ci_hdrc_platform_data *platdata)
616 struct extcon_dev *ext_vbus, *ext_id;
617 struct ci_hdrc_cable *cable;
620 if (!platdata->phy_mode)
621 platdata->phy_mode = of_usb_get_phy_mode(dev->of_node);
623 if (!platdata->dr_mode)
624 platdata->dr_mode = usb_get_dr_mode(dev);
626 if (platdata->dr_mode == USB_DR_MODE_UNKNOWN)
627 platdata->dr_mode = USB_DR_MODE_OTG;
629 if (platdata->dr_mode != USB_DR_MODE_PERIPHERAL) {
630 /* Get the vbus regulator */
631 platdata->reg_vbus = devm_regulator_get(dev, "vbus");
632 if (PTR_ERR(platdata->reg_vbus) == -EPROBE_DEFER) {
633 return -EPROBE_DEFER;
634 } else if (PTR_ERR(platdata->reg_vbus) == -ENODEV) {
635 /* no vbus regulator is needed */
636 platdata->reg_vbus = NULL;
637 } else if (IS_ERR(platdata->reg_vbus)) {
638 dev_err(dev, "Getting regulator error: %ld\n",
639 PTR_ERR(platdata->reg_vbus));
640 return PTR_ERR(platdata->reg_vbus);
642 /* Get TPL support */
643 if (!platdata->tpl_support)
644 platdata->tpl_support =
645 of_usb_host_tpl_support(dev->of_node);
648 if (platdata->dr_mode == USB_DR_MODE_OTG) {
649 /* We can support HNP and SRP of OTG 2.0 */
650 platdata->ci_otg_caps.otg_rev = 0x0200;
651 platdata->ci_otg_caps.hnp_support = true;
652 platdata->ci_otg_caps.srp_support = true;
654 /* Update otg capabilities by DT properties */
655 ret = of_usb_update_otg_caps(dev->of_node,
656 &platdata->ci_otg_caps);
661 if (usb_get_maximum_speed(dev) == USB_SPEED_FULL)
662 platdata->flags |= CI_HDRC_FORCE_FULLSPEED;
664 of_property_read_u32(dev->of_node, "phy-clkgate-delay-us",
665 &platdata->phy_clkgate_delay_us);
667 platdata->itc_setting = 1;
669 of_property_read_u32(dev->of_node, "itc-setting",
670 &platdata->itc_setting);
672 ret = of_property_read_u32(dev->of_node, "ahb-burst-config",
673 &platdata->ahb_burst_config);
675 platdata->flags |= CI_HDRC_OVERRIDE_AHB_BURST;
676 } else if (ret != -EINVAL) {
677 dev_err(dev, "failed to get ahb-burst-config\n");
681 ret = of_property_read_u32(dev->of_node, "tx-burst-size-dword",
682 &platdata->tx_burst_size);
684 platdata->flags |= CI_HDRC_OVERRIDE_TX_BURST;
685 } else if (ret != -EINVAL) {
686 dev_err(dev, "failed to get tx-burst-size-dword\n");
690 ret = of_property_read_u32(dev->of_node, "rx-burst-size-dword",
691 &platdata->rx_burst_size);
693 platdata->flags |= CI_HDRC_OVERRIDE_RX_BURST;
694 } else if (ret != -EINVAL) {
695 dev_err(dev, "failed to get rx-burst-size-dword\n");
699 if (of_find_property(dev->of_node, "non-zero-ttctrl-ttha", NULL))
700 platdata->flags |= CI_HDRC_SET_NON_ZERO_TTHA;
702 ext_id = ERR_PTR(-ENODEV);
703 ext_vbus = ERR_PTR(-ENODEV);
704 if (of_property_read_bool(dev->of_node, "extcon")) {
705 /* Each one of them is not mandatory */
706 ext_vbus = extcon_get_edev_by_phandle(dev, 0);
707 if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV)
708 return PTR_ERR(ext_vbus);
710 ext_id = extcon_get_edev_by_phandle(dev, 1);
711 if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV)
712 return PTR_ERR(ext_id);
715 cable = &platdata->vbus_extcon;
716 cable->nb.notifier_call = ci_cable_notifier;
717 cable->edev = ext_vbus;
719 if (!IS_ERR(ext_vbus)) {
720 ret = extcon_get_state(cable->edev, EXTCON_USB);
722 cable->connected = true;
724 cable->connected = false;
727 cable = &platdata->id_extcon;
728 cable->nb.notifier_call = ci_cable_notifier;
729 cable->edev = ext_id;
731 if (!IS_ERR(ext_id)) {
732 ret = extcon_get_state(cable->edev, EXTCON_USB_HOST);
734 cable->connected = true;
736 cable->connected = false;
741 static int ci_extcon_register(struct ci_hdrc *ci)
743 struct ci_hdrc_cable *id, *vbus;
746 id = &ci->platdata->id_extcon;
748 if (!IS_ERR_OR_NULL(id->edev)) {
749 ret = devm_extcon_register_notifier(ci->dev, id->edev,
750 EXTCON_USB_HOST, &id->nb);
752 dev_err(ci->dev, "register ID failed\n");
757 vbus = &ci->platdata->vbus_extcon;
759 if (!IS_ERR_OR_NULL(vbus->edev)) {
760 ret = devm_extcon_register_notifier(ci->dev, vbus->edev,
761 EXTCON_USB, &vbus->nb);
763 dev_err(ci->dev, "register VBUS failed\n");
771 static DEFINE_IDA(ci_ida);
773 struct platform_device *ci_hdrc_add_device(struct device *dev,
774 struct resource *res, int nres,
775 struct ci_hdrc_platform_data *platdata)
777 struct platform_device *pdev;
780 ret = ci_get_platdata(dev, platdata);
784 id = ida_simple_get(&ci_ida, 0, 0, GFP_KERNEL);
788 pdev = platform_device_alloc("ci_hdrc", id);
794 pdev->dev.parent = dev;
796 ret = platform_device_add_resources(pdev, res, nres);
800 ret = platform_device_add_data(pdev, platdata, sizeof(*platdata));
804 ret = platform_device_add(pdev);
811 platform_device_put(pdev);
813 ida_simple_remove(&ci_ida, id);
816 EXPORT_SYMBOL_GPL(ci_hdrc_add_device);
818 void ci_hdrc_remove_device(struct platform_device *pdev)
821 platform_device_unregister(pdev);
822 ida_simple_remove(&ci_ida, id);
824 EXPORT_SYMBOL_GPL(ci_hdrc_remove_device);
826 static inline void ci_role_destroy(struct ci_hdrc *ci)
828 ci_hdrc_gadget_destroy(ci);
829 ci_hdrc_host_destroy(ci);
830 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
831 ci_hdrc_otg_destroy(ci);
834 static void ci_get_otg_capable(struct ci_hdrc *ci)
836 if (ci->platdata->flags & CI_HDRC_DUAL_ROLE_NOT_OTG)
839 ci->is_otg = (hw_read(ci, CAP_DCCPARAMS,
840 DCCPARAMS_DC | DCCPARAMS_HC)
841 == (DCCPARAMS_DC | DCCPARAMS_HC));
843 dev_dbg(ci->dev, "It is OTG capable controller\n");
844 /* Disable and clear all OTG irq */
845 hw_write_otgsc(ci, OTGSC_INT_EN_BITS | OTGSC_INT_STATUS_BITS,
846 OTGSC_INT_STATUS_BITS);
850 static ssize_t ci_role_show(struct device *dev, struct device_attribute *attr,
853 struct ci_hdrc *ci = dev_get_drvdata(dev);
855 if (ci->role != CI_ROLE_END)
856 return sprintf(buf, "%s\n", ci_role(ci)->name);
861 static ssize_t ci_role_store(struct device *dev,
862 struct device_attribute *attr, const char *buf, size_t n)
864 struct ci_hdrc *ci = dev_get_drvdata(dev);
868 if (!(ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET])) {
869 dev_warn(dev, "Current configuration is not dual-role, quit\n");
873 for (role = CI_ROLE_HOST; role < CI_ROLE_END; role++)
874 if (!strncmp(buf, ci->roles[role]->name,
875 strlen(ci->roles[role]->name)))
878 if (role == CI_ROLE_END || role == ci->role)
881 pm_runtime_get_sync(dev);
882 disable_irq(ci->irq);
884 ret = ci_role_start(ci, role);
885 if (!ret && ci->role == CI_ROLE_GADGET)
886 ci_handle_vbus_change(ci);
888 pm_runtime_put_sync(dev);
890 return (ret == 0) ? n : ret;
892 static DEVICE_ATTR(role, 0644, ci_role_show, ci_role_store);
894 static struct attribute *ci_attrs[] = {
899 static const struct attribute_group ci_attr_group = {
903 static int ci_hdrc_probe(struct platform_device *pdev)
905 struct device *dev = &pdev->dev;
907 struct resource *res;
910 enum usb_dr_mode dr_mode;
912 if (!dev_get_platdata(dev)) {
913 dev_err(dev, "platform data missing\n");
917 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 base = devm_ioremap_resource(dev, res);
920 return PTR_ERR(base);
922 ci = devm_kzalloc(dev, sizeof(*ci), GFP_KERNEL);
926 spin_lock_init(&ci->lock);
928 ci->platdata = dev_get_platdata(dev);
929 ci->imx28_write_fix = !!(ci->platdata->flags &
930 CI_HDRC_IMX28_WRITE_FIX);
931 ci->supports_runtime_pm = !!(ci->platdata->flags &
932 CI_HDRC_SUPPORTS_RUNTIME_PM);
933 platform_set_drvdata(pdev, ci);
935 ret = hw_device_init(ci, base);
937 dev_err(dev, "can't initialize hardware\n");
941 ret = ci_ulpi_init(ci);
945 if (ci->platdata->phy) {
946 ci->phy = ci->platdata->phy;
947 } else if (ci->platdata->usb_phy) {
948 ci->usb_phy = ci->platdata->usb_phy;
950 ci->usb_phy = devm_usb_get_phy_by_phandle(dev->parent, "phys",
952 ci->phy = devm_phy_get(dev->parent, "usb-phy");
954 /* Fallback to grabbing any registered USB2 PHY */
955 if (IS_ERR(ci->usb_phy) &&
956 PTR_ERR(ci->usb_phy) != -EPROBE_DEFER)
957 ci->usb_phy = devm_usb_get_phy(dev->parent,
960 /* if both generic PHY and USB PHY layers aren't enabled */
961 if (PTR_ERR(ci->phy) == -ENOSYS &&
962 PTR_ERR(ci->usb_phy) == -ENXIO) {
967 if (IS_ERR(ci->phy) && IS_ERR(ci->usb_phy)) {
974 else if (IS_ERR(ci->usb_phy))
978 ret = ci_usb_phy_init(ci);
980 dev_err(dev, "unable to init phy: %d\n", ret);
984 ci->hw_bank.phys = res->start;
986 ci->irq = platform_get_irq(pdev, 0);
988 dev_err(dev, "missing IRQ\n");
993 ci_get_otg_capable(ci);
995 dr_mode = ci->platdata->dr_mode;
996 /* initialize role(s) before the interrupt is requested */
997 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
998 ret = ci_hdrc_host_init(ci);
1001 dev_info(dev, "doesn't support host\n");
1007 if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
1008 ret = ci_hdrc_gadget_init(ci);
1011 dev_info(dev, "doesn't support gadget\n");
1017 if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
1018 dev_err(dev, "no supported roles\n");
1023 if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
1024 ret = ci_hdrc_otg_init(ci);
1026 dev_err(dev, "init otg fails, ret = %d\n", ret);
1031 if (ci->roles[CI_ROLE_HOST] && ci->roles[CI_ROLE_GADGET]) {
1033 ci->role = ci_otg_role(ci);
1034 /* Enable ID change irq */
1035 hw_write_otgsc(ci, OTGSC_IDIE, OTGSC_IDIE);
1038 * If the controller is not OTG capable, but support
1039 * role switch, the defalt role is gadget, and the
1040 * user can switch it through debugfs.
1042 ci->role = CI_ROLE_GADGET;
1045 ci->role = ci->roles[CI_ROLE_HOST]
1050 if (!ci_otg_is_fsm_mode(ci)) {
1051 /* only update vbus status for peripheral */
1052 if (ci->role == CI_ROLE_GADGET)
1053 ci_handle_vbus_change(ci);
1055 ret = ci_role_start(ci, ci->role);
1057 dev_err(dev, "can't start %s role\n",
1063 ret = devm_request_irq(dev, ci->irq, ci_irq_handler, IRQF_SHARED,
1064 ci->platdata->name, ci);
1068 ret = ci_extcon_register(ci);
1072 if (ci->supports_runtime_pm) {
1073 pm_runtime_set_active(&pdev->dev);
1074 pm_runtime_enable(&pdev->dev);
1075 pm_runtime_set_autosuspend_delay(&pdev->dev, 2000);
1076 pm_runtime_mark_last_busy(ci->dev);
1077 pm_runtime_use_autosuspend(&pdev->dev);
1080 if (ci_otg_is_fsm_mode(ci))
1081 ci_hdrc_otg_fsm_start(ci);
1083 device_set_wakeup_capable(&pdev->dev, true);
1084 ret = dbg_create_files(ci);
1088 ret = sysfs_create_group(&dev->kobj, &ci_attr_group);
1095 dbg_remove_files(ci);
1097 if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
1098 ci_hdrc_otg_destroy(ci);
1100 ci_hdrc_gadget_destroy(ci);
1102 ci_hdrc_host_destroy(ci);
1104 ci_usb_phy_exit(ci);
1111 static int ci_hdrc_remove(struct platform_device *pdev)
1113 struct ci_hdrc *ci = platform_get_drvdata(pdev);
1115 if (ci->supports_runtime_pm) {
1116 pm_runtime_get_sync(&pdev->dev);
1117 pm_runtime_disable(&pdev->dev);
1118 pm_runtime_put_noidle(&pdev->dev);
1121 dbg_remove_files(ci);
1122 sysfs_remove_group(&ci->dev->kobj, &ci_attr_group);
1123 ci_role_destroy(ci);
1124 ci_hdrc_enter_lpm(ci, true);
1125 ci_usb_phy_exit(ci);
1132 /* Prepare wakeup by SRP before suspend */
1133 static void ci_otg_fsm_suspend_for_srp(struct ci_hdrc *ci)
1135 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1136 !hw_read_otgsc(ci, OTGSC_ID)) {
1137 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_PP,
1139 hw_write(ci, OP_PORTSC, PORTSC_W1C_BITS | PORTSC_WKCN,
1144 /* Handle SRP when wakeup by data pulse */
1145 static void ci_otg_fsm_wakeup_by_srp(struct ci_hdrc *ci)
1147 if ((ci->fsm.otg->state == OTG_STATE_A_IDLE) &&
1148 (ci->fsm.a_bus_drop == 1) && (ci->fsm.a_bus_req == 0)) {
1149 if (!hw_read_otgsc(ci, OTGSC_ID)) {
1150 ci->fsm.a_srp_det = 1;
1151 ci->fsm.a_bus_drop = 0;
1155 ci_otg_queue_work(ci);
1159 static void ci_controller_suspend(struct ci_hdrc *ci)
1161 disable_irq(ci->irq);
1162 ci_hdrc_enter_lpm(ci, true);
1163 if (ci->platdata->phy_clkgate_delay_us)
1164 usleep_range(ci->platdata->phy_clkgate_delay_us,
1165 ci->platdata->phy_clkgate_delay_us + 50);
1166 usb_phy_set_suspend(ci->usb_phy, 1);
1168 enable_irq(ci->irq);
1172 * Handle the wakeup interrupt triggered by extcon connector
1173 * We need to call ci_irq again for extcon since the first
1174 * interrupt (wakeup int) only let the controller be out of
1175 * low power mode, but not handle any interrupts.
1177 static void ci_extcon_wakeup_int(struct ci_hdrc *ci)
1179 struct ci_hdrc_cable *cable_id, *cable_vbus;
1180 u32 otgsc = hw_read_otgsc(ci, ~0);
1182 cable_id = &ci->platdata->id_extcon;
1183 cable_vbus = &ci->platdata->vbus_extcon;
1185 if (!IS_ERR(cable_id->edev) && ci->is_otg &&
1186 (otgsc & OTGSC_IDIE) && (otgsc & OTGSC_IDIS))
1189 if (!IS_ERR(cable_vbus->edev) && ci->is_otg &&
1190 (otgsc & OTGSC_BSVIE) && (otgsc & OTGSC_BSVIS))
1194 static int ci_controller_resume(struct device *dev)
1196 struct ci_hdrc *ci = dev_get_drvdata(dev);
1199 dev_dbg(dev, "at %s\n", __func__);
1206 ci_hdrc_enter_lpm(ci, false);
1208 ret = ci_ulpi_resume(ci);
1213 usb_phy_set_suspend(ci->usb_phy, 0);
1214 usb_phy_set_wakeup(ci->usb_phy, false);
1215 hw_wait_phy_stable();
1219 if (ci->wakeup_int) {
1220 ci->wakeup_int = false;
1221 pm_runtime_mark_last_busy(ci->dev);
1222 pm_runtime_put_autosuspend(ci->dev);
1223 enable_irq(ci->irq);
1224 if (ci_otg_is_fsm_mode(ci))
1225 ci_otg_fsm_wakeup_by_srp(ci);
1226 ci_extcon_wakeup_int(ci);
1232 #ifdef CONFIG_PM_SLEEP
1233 static int ci_suspend(struct device *dev)
1235 struct ci_hdrc *ci = dev_get_drvdata(dev);
1238 flush_workqueue(ci->wq);
1240 * Controller needs to be active during suspend, otherwise the core
1241 * may run resume when the parent is at suspend if other driver's
1242 * suspend fails, it occurs before parent's suspend has not started,
1243 * but the core suspend has finished.
1246 pm_runtime_resume(dev);
1253 if (device_may_wakeup(dev)) {
1254 if (ci_otg_is_fsm_mode(ci))
1255 ci_otg_fsm_suspend_for_srp(ci);
1257 usb_phy_set_wakeup(ci->usb_phy, true);
1258 enable_irq_wake(ci->irq);
1261 ci_controller_suspend(ci);
1266 static int ci_resume(struct device *dev)
1268 struct ci_hdrc *ci = dev_get_drvdata(dev);
1271 if (device_may_wakeup(dev))
1272 disable_irq_wake(ci->irq);
1274 ret = ci_controller_resume(dev);
1278 if (ci->supports_runtime_pm) {
1279 pm_runtime_disable(dev);
1280 pm_runtime_set_active(dev);
1281 pm_runtime_enable(dev);
1286 #endif /* CONFIG_PM_SLEEP */
1288 static int ci_runtime_suspend(struct device *dev)
1290 struct ci_hdrc *ci = dev_get_drvdata(dev);
1292 dev_dbg(dev, "at %s\n", __func__);
1299 if (ci_otg_is_fsm_mode(ci))
1300 ci_otg_fsm_suspend_for_srp(ci);
1302 usb_phy_set_wakeup(ci->usb_phy, true);
1303 ci_controller_suspend(ci);
1308 static int ci_runtime_resume(struct device *dev)
1310 return ci_controller_resume(dev);
1313 #endif /* CONFIG_PM */
1314 static const struct dev_pm_ops ci_pm_ops = {
1315 SET_SYSTEM_SLEEP_PM_OPS(ci_suspend, ci_resume)
1316 SET_RUNTIME_PM_OPS(ci_runtime_suspend, ci_runtime_resume, NULL)
1319 static struct platform_driver ci_hdrc_driver = {
1320 .probe = ci_hdrc_probe,
1321 .remove = ci_hdrc_remove,
1328 static int __init ci_hdrc_platform_register(void)
1330 ci_hdrc_host_driver_init();
1331 return platform_driver_register(&ci_hdrc_driver);
1333 module_init(ci_hdrc_platform_register);
1335 static void __exit ci_hdrc_platform_unregister(void)
1337 platform_driver_unregister(&ci_hdrc_driver);
1339 module_exit(ci_hdrc_platform_unregister);
1341 MODULE_ALIAS("platform:ci_hdrc");
1342 MODULE_LICENSE("GPL v2");
1343 MODULE_AUTHOR("David Lopo <dlopo@chipidea.mips.com>");
1344 MODULE_DESCRIPTION("ChipIdea HDRC Driver");