drivers/usb/dwc2/core_intr.c

   1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
   2 /*
   3  * core_intr.c - DesignWare HS OTG Controller common interrupt handling
   4  *
   5  * Copyright (C) 2004-2013 Synopsys, Inc.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. The names of the above-listed copyright holders may not be used
  17  *    to endorse or promote products derived from this software without
  18  *    specific prior written permission.
  19  *
  20  * ALTERNATIVELY, this software may be distributed under the terms of the
  21  * GNU General Public License ("GPL") as published by the Free Software
  22  * Foundation; either version 2 of the License, or (at your option) any
  23  * later version.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 /*
  39  * This file contains the common interrupt handlers
  40  */
  41 #include <linux/kernel.h>
  42 #include <linux/module.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/spinlock.h>
  45 #include <linux/interrupt.h>
  46 #include <linux/dma-mapping.h>
  47 #include <linux/io.h>
  48 #include <linux/slab.h>
  49 #include <linux/usb.h>
  50
  51 #include <linux/usb/hcd.h>
  52 #include <linux/usb/ch11.h>
  53
  54 #include "core.h"
  55 #include "hcd.h"
  56
  57 static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  58 {
  59         switch (hsotg->op_state) {
  60         case OTG_STATE_A_HOST:
  61                 return "a_host";
  62         case OTG_STATE_A_SUSPEND:
  63                 return "a_suspend";
  64         case OTG_STATE_A_PERIPHERAL:
  65                 return "a_peripheral";
  66         case OTG_STATE_B_PERIPHERAL:
  67                 return "b_peripheral";
  68         case OTG_STATE_B_HOST:
  69                 return "b_host";
  70         default:
  71                 return "unknown";
  72         }
  73 }
  74
  75 /**
  76  * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  77  * When the PRTINT interrupt fires, there are certain status bits in the Host
  78  * Port that needs to get cleared.
  79  *
  80  * @hsotg: Programming view of DWC_otg controller
  81  */
  82 static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  83 {
  84         u32 hprt0 = dwc2_readl(hsotg, HPRT0);
  85
  86         if (hprt0 & HPRT0_ENACHG) {
  87                 hprt0 &= ~HPRT0_ENA;
  88                 dwc2_writel(hsotg, hprt0, HPRT0);
  89         }
  90 }
  91
  92 /**
  93  * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  94  *
  95  * @hsotg: Programming view of DWC_otg controller
  96  */
  97 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  98 {
  99         /* Clear interrupt */
 100         dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
 101
 102         dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
 103                  dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 104 }
 105
 106 /**
 107  * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
 108  * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
 109  *
 110  * @hsotg: Programming view of DWC_otg controller
 111  */
 112 static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
 113 {
 114         u32 gotgint;
 115         u32 gotgctl;
 116         u32 gintmsk;
 117
 118         gotgint = dwc2_readl(hsotg, GOTGINT);
 119         gotgctl = dwc2_readl(hsotg, GOTGCTL);
 120         dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
 121                 dwc2_op_state_str(hsotg));
 122
 123         if (gotgint & GOTGINT_SES_END_DET) {
 124                 dev_dbg(hsotg->dev,
 125                         " ++OTG Interrupt: Session End Detected++ (%s)\n",
 126                         dwc2_op_state_str(hsotg));
 127                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 128
 129                 if (dwc2_is_device_mode(hsotg))
 130                         dwc2_hsotg_disconnect(hsotg);
 131
 132                 if (hsotg->op_state == OTG_STATE_B_HOST) {
 133                         hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 134                 } else {
 135                         /*
 136                          * If not B_HOST and Device HNP still set, HNP did
 137                          * not succeed!
 138                          */
 139                         if (gotgctl & GOTGCTL_DEVHNPEN) {
 140                                 dev_dbg(hsotg->dev, "Session End Detected\n");
 141                                 dev_err(hsotg->dev,
 142                                         "Device Not Connected/Responding!\n");
 143                         }
 144
 145                         /*
 146                          * If Session End Detected the B-Cable has been
 147                          * disconnected
 148                          */
 149                         /* Reset to a clean state */
 150                         hsotg->lx_state = DWC2_L0;
 151                 }
 152
 153                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 154                 gotgctl &= ~GOTGCTL_DEVHNPEN;
 155                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
 156         }
 157
 158         if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
 159                 dev_dbg(hsotg->dev,
 160                         " ++OTG Interrupt: Session Request Success Status Change++\n");
 161                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 162                 if (gotgctl & GOTGCTL_SESREQSCS) {
 163                         if (hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS &&
 164                             hsotg->params.i2c_enable) {
 165                                 hsotg->srp_success = 1;
 166                         } else {
 167                                 /* Clear Session Request */
 168                                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 169                                 gotgctl &= ~GOTGCTL_SESREQ;
 170                                 dwc2_writel(hsotg, gotgctl, GOTGCTL);
 171                         }
 172                 }
 173         }
 174
 175         if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
 176                 /*
 177                  * Print statements during the HNP interrupt handling
 178                  * can cause it to fail
 179                  */
 180                 gotgctl = dwc2_readl(hsotg, GOTGCTL);
 181                 /*
 182                  * WA for 3.00a- HW is not setting cur_mode, even sometimes
 183                  * this does not help
 184                  */
 185                 if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
 186                         udelay(100);
 187                 if (gotgctl & GOTGCTL_HSTNEGSCS) {
 188                         if (dwc2_is_host_mode(hsotg)) {
 189                                 hsotg->op_state = OTG_STATE_B_HOST;
 190                                 /*
 191                                  * Need to disable SOF interrupt immediately.
 192                                  * When switching from device to host, the PCD
 193                                  * interrupt handler won't handle the interrupt
 194                                  * if host mode is already set. The HCD
 195                                  * interrupt handler won't get called if the
 196                                  * HCD state is HALT. This means that the
 197                                  * interrupt does not get handled and Linux
 198                                  * complains loudly.
 199                                  */
 200                                 gintmsk = dwc2_readl(hsotg, GINTMSK);
 201                                 gintmsk &= ~GINTSTS_SOF;
 202                                 dwc2_writel(hsotg, gintmsk, GINTMSK);
 203
 204                                 /*
 205                                  * Call callback function with spin lock
 206                                  * released
 207                                  */
 208                                 spin_unlock(&hsotg->lock);
 209
 210                                 /* Initialize the Core for Host mode */
 211                                 dwc2_hcd_start(hsotg);
 212                                 spin_lock(&hsotg->lock);
 213                                 hsotg->op_state = OTG_STATE_B_HOST;
 214                         }
 215                 } else {
 216                         gotgctl = dwc2_readl(hsotg, GOTGCTL);
 217                         gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
 218                         dwc2_writel(hsotg, gotgctl, GOTGCTL);
 219                         dev_dbg(hsotg->dev, "HNP Failed\n");
 220                         dev_err(hsotg->dev,
 221                                 "Device Not Connected/Responding\n");
 222                 }
 223         }
 224
 225         if (gotgint & GOTGINT_HST_NEG_DET) {
 226                 /*
 227                  * The disconnect interrupt is set at the same time as
 228                  * Host Negotiation Detected. During the mode switch all
 229                  * interrupts are cleared so the disconnect interrupt
 230                  * handler will not get executed.
 231                  */
 232                 dev_dbg(hsotg->dev,
 233                         " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
 234                         (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
 235                 if (dwc2_is_device_mode(hsotg)) {
 236                         dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
 237                                 hsotg->op_state);
 238                         spin_unlock(&hsotg->lock);
 239                         dwc2_hcd_disconnect(hsotg, false);
 240                         spin_lock(&hsotg->lock);
 241                         hsotg->op_state = OTG_STATE_A_PERIPHERAL;
 242                 } else {
 243                         /* Need to disable SOF interrupt immediately */
 244                         gintmsk = dwc2_readl(hsotg, GINTMSK);
 245                         gintmsk &= ~GINTSTS_SOF;
 246                         dwc2_writel(hsotg, gintmsk, GINTMSK);
 247                         spin_unlock(&hsotg->lock);
 248                         dwc2_hcd_start(hsotg);
 249                         spin_lock(&hsotg->lock);
 250                         hsotg->op_state = OTG_STATE_A_HOST;
 251                 }
 252         }
 253
 254         if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
 255                 dev_dbg(hsotg->dev,
 256                         " ++OTG Interrupt: A-Device Timeout Change++\n");
 257         if (gotgint & GOTGINT_DBNCE_DONE)
 258                 dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
 259
 260         /* Clear GOTGINT */
 261         dwc2_writel(hsotg, gotgint, GOTGINT);
 262 }
 263
 264 /**
 265  * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
 266  * Change Interrupt
 267  *
 268  * @hsotg: Programming view of DWC_otg controller
 269  *
 270  * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
 271  * Device to Host Mode transition or a Host to Device Mode transition. This only
 272  * occurs when the cable is connected/removed from the PHY connector.
 273  */
 274 static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
 275 {
 276         u32 gintmsk;
 277
 278         /* Clear interrupt */
 279         dwc2_writel(hsotg, GINTSTS_CONIDSTSCHNG, GINTSTS);
 280
 281         /* Need to disable SOF interrupt immediately */
 282         gintmsk = dwc2_readl(hsotg, GINTMSK);
 283         gintmsk &= ~GINTSTS_SOF;
 284         dwc2_writel(hsotg, gintmsk, GINTMSK);
 285
 286         dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++  (%s)\n",
 287                 dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 288
 289         /*
 290          * Need to schedule a work, as there are possible DELAY function calls.
 291          * Release lock before scheduling workq as it holds spinlock during
 292          * scheduling.
 293          */
 294         if (hsotg->wq_otg) {
 295                 spin_unlock(&hsotg->lock);
 296                 queue_work(hsotg->wq_otg, &hsotg->wf_otg);
 297                 spin_lock(&hsotg->lock);
 298         }
 299 }
 300
 301 /**
 302  * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
 303  * initiating the Session Request Protocol to request the host to turn on bus
 304  * power so a new session can begin
 305  *
 306  * @hsotg: Programming view of DWC_otg controller
 307  *
 308  * This handler responds by turning on bus power. If the DWC_otg controller is
 309  * in low power mode, this handler brings the controller out of low power mode
 310  * before turning on bus power.
 311  */
 312 static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
 313 {
 314         int ret;
 315         u32 hprt0;
 316
 317         /* Clear interrupt */
 318         dwc2_writel(hsotg, GINTSTS_SESSREQINT, GINTSTS);
 319
 320         dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
 321                 hsotg->lx_state);
 322
 323         if (dwc2_is_device_mode(hsotg)) {
 324                 if (hsotg->lx_state == DWC2_L2) {
 325                         ret = dwc2_exit_partial_power_down(hsotg, true);
 326                         if (ret && (ret != -ENOTSUPP))
 327                                 dev_err(hsotg->dev,
 328                                         "exit power_down failed\n");
 329                 }
 330
 331                 /*
 332                  * Report disconnect if there is any previous session
 333                  * established
 334                  */
 335                 dwc2_hsotg_disconnect(hsotg);
 336         } else {
 337                 /* Turn on the port power bit. */
 338                 hprt0 = dwc2_read_hprt0(hsotg);
 339                 hprt0 |= HPRT0_PWR;
 340                 dwc2_writel(hsotg, hprt0, HPRT0);
 341                 /* Connect hcd after port power is set. */
 342                 dwc2_hcd_connect(hsotg);
 343         }
 344 }
 345
 346 /**
 347  * dwc2_wakeup_from_lpm_l1 - Exit the device from LPM L1 state
 348  *
 349  * @hsotg: Programming view of DWC_otg controller
 350  *
 351  */
 352 static void dwc2_wakeup_from_lpm_l1(struct dwc2_hsotg *hsotg)
 353 {
 354         u32 glpmcfg;
 355         u32 i = 0;
 356
 357         if (hsotg->lx_state != DWC2_L1) {
 358                 dev_err(hsotg->dev, "Core isn't in DWC2_L1 state\n");
 359                 return;
 360         }
 361
 362         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 363         if (dwc2_is_device_mode(hsotg)) {
 364                 dev_dbg(hsotg->dev, "Exit from L1 state\n");
 365                 glpmcfg &= ~GLPMCFG_ENBLSLPM;
 366                 glpmcfg &= ~GLPMCFG_HIRD_THRES_EN;
 367                 dwc2_writel(hsotg, glpmcfg, GLPMCFG);
 368
 369                 do {
 370                         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 371
 372                         if (!(glpmcfg & (GLPMCFG_COREL1RES_MASK |
 373                                          GLPMCFG_L1RESUMEOK | GLPMCFG_SLPSTS)))
 374                                 break;
 375
 376                         udelay(1);
 377                 } while (++i < 200);
 378
 379                 if (i == 200) {
 380                         dev_err(hsotg->dev, "Failed to exit L1 sleep state in 200us.\n");
 381                         return;
 382                 }
 383                 dwc2_gadget_init_lpm(hsotg);
 384         } else {
 385                 /* TODO */
 386                 dev_err(hsotg->dev, "Host side LPM is not supported.\n");
 387                 return;
 388         }
 389
 390         /* Change to L0 state */
 391         hsotg->lx_state = DWC2_L0;
 392
 393         /* Inform gadget to exit from L1 */
 394         call_gadget(hsotg, resume);
 395 }
 396
 397 /*
 398  * This interrupt indicates that the DWC_otg controller has detected a
 399  * resume or remote wakeup sequence. If the DWC_otg controller is in
 400  * low power mode, the handler must brings the controller out of low
 401  * power mode. The controller automatically begins resume signaling.
 402  * The handler schedules a time to stop resume signaling.
 403  */
 404 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
 405 {
 406         int ret;
 407
 408         /* Clear interrupt */
 409         dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
 410
 411         dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
 412         dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
 413
 414         if (hsotg->lx_state == DWC2_L1) {
 415                 dwc2_wakeup_from_lpm_l1(hsotg);
 416                 return;
 417         }
 418
 419         if (dwc2_is_device_mode(hsotg)) {
 420                 dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
 421                         dwc2_readl(hsotg, DSTS));
 422                 if (hsotg->lx_state == DWC2_L2) {
 423                         u32 dctl = dwc2_readl(hsotg, DCTL);
 424
 425                         /* Clear Remote Wakeup Signaling */
 426                         dctl &= ~DCTL_RMTWKUPSIG;
 427                         dwc2_writel(hsotg, dctl, DCTL);
 428                         ret = dwc2_exit_partial_power_down(hsotg, true);
 429                         if (ret && (ret != -ENOTSUPP))
 430                                 dev_err(hsotg->dev, "exit power_down failed\n");
 431
 432                         /* Change to L0 state */
 433                         hsotg->lx_state = DWC2_L0;
 434                         call_gadget(hsotg, resume);
 435                 } else {
 436                         /* Change to L0 state */
 437                         hsotg->lx_state = DWC2_L0;
 438                 }
 439         } else {
 440                 if (hsotg->params.power_down)
 441                         return;
 442
 443                 if (hsotg->lx_state != DWC2_L1) {
 444                         u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
 445
 446                         /* Restart the Phy Clock */
 447                         pcgcctl &= ~PCGCTL_STOPPCLK;
 448                         dwc2_writel(hsotg, pcgcctl, PCGCTL);
 449                         mod_timer(&hsotg->wkp_timer,
 450                                   jiffies + msecs_to_jiffies(71));
 451                 } else {
 452                         /* Change to L0 state */
 453                         hsotg->lx_state = DWC2_L0;
 454                 }
 455         }
 456 }
 457
 458 /*
 459  * This interrupt indicates that a device has been disconnected from the
 460  * root port
 461  */
 462 static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
 463 {
 464         dwc2_writel(hsotg, GINTSTS_DISCONNINT, GINTSTS);
 465
 466         dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
 467                 dwc2_is_host_mode(hsotg) ? "Host" : "Device",
 468                 dwc2_op_state_str(hsotg));
 469
 470         if (hsotg->op_state == OTG_STATE_A_HOST)
 471                 dwc2_hcd_disconnect(hsotg, false);
 472 }
 473
 474 /*
 475  * This interrupt indicates that SUSPEND state has been detected on the USB.
 476  *
 477  * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
 478  * to "a_host".
 479  *
 480  * When power management is enabled the core will be put in low power mode.
 481  */
 482 static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
 483 {
 484         u32 dsts;
 485         int ret;
 486
 487         /* Clear interrupt */
 488         dwc2_writel(hsotg, GINTSTS_USBSUSP, GINTSTS);
 489
 490         dev_dbg(hsotg->dev, "USB SUSPEND\n");
 491
 492         if (dwc2_is_device_mode(hsotg)) {
 493                 /*
 494                  * Check the Device status register to determine if the Suspend
 495                  * state is active
 496                  */
 497                 dsts = dwc2_readl(hsotg, DSTS);
 498                 dev_dbg(hsotg->dev, "%s: DSTS=0x%0x\n", __func__, dsts);
 499                 dev_dbg(hsotg->dev,
 500                         "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d HWCFG4.Hibernation=%d\n",
 501                         !!(dsts & DSTS_SUSPSTS),
 502                         hsotg->hw_params.power_optimized,
 503                         hsotg->hw_params.hibernation);
 504
 505                 /* Ignore suspend request before enumeration */
 506                 if (!dwc2_is_device_connected(hsotg)) {
 507                         dev_dbg(hsotg->dev,
 508                                 "ignore suspend request before enumeration\n");
 509                         return;
 510                 }
 511                 if (dsts & DSTS_SUSPSTS) {
 512                         if (hsotg->hw_params.power_optimized) {
 513                                 ret = dwc2_enter_partial_power_down(hsotg);
 514                                 if (ret) {
 515                                         if (ret != -ENOTSUPP)
 516                                                 dev_err(hsotg->dev,
 517                                                         "%s: enter partial_power_down failed\n",
 518                                                         __func__);
 519                                         goto skip_power_saving;
 520                                 }
 521
 522                                 udelay(100);
 523
 524                                 /* Ask phy to be suspended */
 525                                 if (!IS_ERR_OR_NULL(hsotg->uphy))
 526                                         usb_phy_set_suspend(hsotg->uphy, true);
 527                         }
 528
 529                         if (hsotg->hw_params.hibernation) {
 530                                 ret = dwc2_enter_hibernation(hsotg, 0);
 531                                 if (ret && ret != -ENOTSUPP)
 532                                         dev_err(hsotg->dev,
 533                                                 "%s: enter hibernation failed\n",
 534                                                 __func__);
 535                         }
 536 skip_power_saving:
 537                         /*
 538                          * Change to L2 (suspend) state before releasing
 539                          * spinlock
 540                          */
 541                         hsotg->lx_state = DWC2_L2;
 542
 543                         /* Call gadget suspend callback */
 544                         call_gadget(hsotg, suspend);
 545                 }
 546         } else {
 547                 if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
 548                         dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
 549
 550                         /* Change to L2 (suspend) state */
 551                         hsotg->lx_state = DWC2_L2;
 552                         /* Clear the a_peripheral flag, back to a_host */
 553                         spin_unlock(&hsotg->lock);
 554                         dwc2_hcd_start(hsotg);
 555                         spin_lock(&hsotg->lock);
 556                         hsotg->op_state = OTG_STATE_A_HOST;
 557                 }
 558         }
 559 }
 560
 561 /**
 562  * dwc2_handle_lpm_intr - GINTSTS_LPMTRANRCVD Interrupt handler
 563  *
 564  * @hsotg: Programming view of DWC_otg controller
 565  *
 566  */
 567 static void dwc2_handle_lpm_intr(struct dwc2_hsotg *hsotg)
 568 {
 569         u32 glpmcfg;
 570         u32 pcgcctl;
 571         u32 hird;
 572         u32 hird_thres;
 573         u32 hird_thres_en;
 574         u32 enslpm;
 575
 576         /* Clear interrupt */
 577         dwc2_writel(hsotg, GINTSTS_LPMTRANRCVD, GINTSTS);
 578
 579         glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 580
 581         if (!(glpmcfg & GLPMCFG_LPMCAP)) {
 582                 dev_err(hsotg->dev, "Unexpected LPM interrupt\n");
 583                 return;
 584         }
 585
 586         hird = (glpmcfg & GLPMCFG_HIRD_MASK) >> GLPMCFG_HIRD_SHIFT;
 587         hird_thres = (glpmcfg & GLPMCFG_HIRD_THRES_MASK &
 588                         ~GLPMCFG_HIRD_THRES_EN) >> GLPMCFG_HIRD_THRES_SHIFT;
 589         hird_thres_en = glpmcfg & GLPMCFG_HIRD_THRES_EN;
 590         enslpm = glpmcfg & GLPMCFG_ENBLSLPM;
 591
 592         if (dwc2_is_device_mode(hsotg)) {
 593                 dev_dbg(hsotg->dev, "HIRD_THRES_EN = %d\n", hird_thres_en);
 594
 595                 if (hird_thres_en && hird >= hird_thres) {
 596                         dev_dbg(hsotg->dev, "L1 with utmi_l1_suspend_n\n");
 597                 } else if (enslpm) {
 598                         dev_dbg(hsotg->dev, "L1 with utmi_sleep_n\n");
 599                 } else {
 600                         dev_dbg(hsotg->dev, "Entering Sleep with L1 Gating\n");
 601
 602                         pcgcctl = dwc2_readl(hsotg, PCGCTL);
 603                         pcgcctl |= PCGCTL_ENBL_SLEEP_GATING;
 604                         dwc2_writel(hsotg, pcgcctl, PCGCTL);
 605                 }
 606                 /**
 607                  * Examine prt_sleep_sts after TL1TokenTetry period max (10 us)
 608                  */
 609                 udelay(10);
 610
 611                 glpmcfg = dwc2_readl(hsotg, GLPMCFG);
 612
 613                 if (glpmcfg & GLPMCFG_SLPSTS) {
 614                         /* Save the current state */
 615                         hsotg->lx_state = DWC2_L1;
 616                         dev_dbg(hsotg->dev,
 617                                 "Core is in L1 sleep glpmcfg=%08x\n", glpmcfg);
 618
 619                         /* Inform gadget that we are in L1 state */
 620                         call_gadget(hsotg, suspend);
 621                 }
 622         }
 623 }
 624
 625 #define GINTMSK_COMMON  (GINTSTS_WKUPINT | GINTSTS_SESSREQINT |         \
 626                          GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT |        \
 627                          GINTSTS_MODEMIS | GINTSTS_DISCONNINT |         \
 628                          GINTSTS_USBSUSP | GINTSTS_PRTINT |             \
 629                          GINTSTS_LPMTRANRCVD)
 630
 631 /*
 632  * This function returns the Core Interrupt register
 633  */
 634 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
 635 {
 636         u32 gintsts;
 637         u32 gintmsk;
 638         u32 gahbcfg;
 639         u32 gintmsk_common = GINTMSK_COMMON;
 640
 641         gintsts = dwc2_readl(hsotg, GINTSTS);
 642         gintmsk = dwc2_readl(hsotg, GINTMSK);
 643         gahbcfg = dwc2_readl(hsotg, GAHBCFG);
 644
 645         /* If any common interrupts set */
 646         if (gintsts & gintmsk_common)
 647                 dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n",
 648                         gintsts, gintmsk);
 649
 650         if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
 651                 return gintsts & gintmsk & gintmsk_common;
 652         else
 653                 return 0;
 654 }
 655
 656 /**
 657  * dwc_handle_gpwrdn_disc_det() - Handles the gpwrdn disconnect detect.
 658  * Exits hibernation without restoring registers.
 659  *
 660  * @hsotg: Programming view of DWC_otg controller
 661  * @gpwrdn: GPWRDN register
 662  */
 663 static inline void dwc_handle_gpwrdn_disc_det(struct dwc2_hsotg *hsotg,
 664                                               u32 gpwrdn)
 665 {
 666         u32 gpwrdn_tmp;
 667
 668         /* Switch-on voltage to the core */
 669         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 670         gpwrdn_tmp &= ~GPWRDN_PWRDNSWTCH;
 671         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 672         udelay(5);
 673
 674         /* Reset core */
 675         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 676         gpwrdn_tmp &= ~GPWRDN_PWRDNRSTN;
 677         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 678         udelay(5);
 679
 680         /* Disable Power Down Clamp */
 681         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 682         gpwrdn_tmp &= ~GPWRDN_PWRDNCLMP;
 683         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 684         udelay(5);
 685
 686         /* Deassert reset core */
 687         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 688         gpwrdn_tmp |= GPWRDN_PWRDNRSTN;
 689         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 690         udelay(5);
 691
 692         /* Disable PMU interrupt */
 693         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 694         gpwrdn_tmp &= ~GPWRDN_PMUINTSEL;
 695         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 696
 697         /* De-assert Wakeup Logic */
 698         gpwrdn_tmp = dwc2_readl(hsotg, GPWRDN);
 699         gpwrdn_tmp &= ~GPWRDN_PMUACTV;
 700         dwc2_writel(hsotg, gpwrdn_tmp, GPWRDN);
 701
 702         hsotg->hibernated = 0;
 703
 704 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || \
 705         IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
 706         hsotg->bus_suspended = 0;
 707 #endif
 708
 709         if (gpwrdn & GPWRDN_IDSTS) {
 710                 hsotg->op_state = OTG_STATE_B_PERIPHERAL;
 711                 dwc2_core_init(hsotg, false);
 712                 dwc2_enable_global_interrupts(hsotg);
 713                 dwc2_hsotg_core_init_disconnected(hsotg, false);
 714                 dwc2_hsotg_core_connect(hsotg);
 715         } else {
 716                 hsotg->op_state = OTG_STATE_A_HOST;
 717
 718                 /* Initialize the Core for Host mode */
 719                 dwc2_core_init(hsotg, false);
 720                 dwc2_enable_global_interrupts(hsotg);
 721                 dwc2_hcd_start(hsotg);
 722         }
 723 }
 724
 725 /*
 726  * GPWRDN interrupt handler.
 727  *
 728  * The GPWRDN interrupts are those that occur in both Host and
 729  * Device mode while core is in hibernated state.
 730  */
 731 static void dwc2_handle_gpwrdn_intr(struct dwc2_hsotg *hsotg)
 732 {
 733         u32 gpwrdn;
 734         int linestate;
 735
 736         gpwrdn = dwc2_readl(hsotg, GPWRDN);
 737         /* clear all interrupt */
 738         dwc2_writel(hsotg, gpwrdn, GPWRDN);
 739         linestate = (gpwrdn & GPWRDN_LINESTATE_MASK) >> GPWRDN_LINESTATE_SHIFT;
 740         dev_dbg(hsotg->dev,
 741                 "%s: dwc2_handle_gpwrdwn_intr called gpwrdn= %08x\n", __func__,
 742                 gpwrdn);
 743
 744         if ((gpwrdn & GPWRDN_DISCONN_DET) &&
 745             (gpwrdn & GPWRDN_DISCONN_DET_MSK) && !linestate) {
 746                 dev_dbg(hsotg->dev, "%s: GPWRDN_DISCONN_DET\n", __func__);
 747                 /*
 748                  * Call disconnect detect function to exit from
 749                  * hibernation
 750                  */
 751                 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
 752         } else if ((gpwrdn & GPWRDN_LNSTSCHG) &&
 753                    (gpwrdn & GPWRDN_LNSTSCHG_MSK) && linestate) {
 754                 dev_dbg(hsotg->dev, "%s: GPWRDN_LNSTSCHG\n", __func__);
 755                 if (hsotg->hw_params.hibernation &&
 756                     hsotg->hibernated) {
 757                         if (gpwrdn & GPWRDN_IDSTS) {
 758                                 dwc2_exit_hibernation(hsotg, 0, 0, 0);
 759                                 call_gadget(hsotg, resume);
 760                         } else {
 761                                 dwc2_exit_hibernation(hsotg, 1, 0, 1);
 762                         }
 763                 }
 764         } else if ((gpwrdn & GPWRDN_RST_DET) &&
 765                    (gpwrdn & GPWRDN_RST_DET_MSK)) {
 766                 dev_dbg(hsotg->dev, "%s: GPWRDN_RST_DET\n", __func__);
 767                 if (!linestate && (gpwrdn & GPWRDN_BSESSVLD))
 768                         dwc2_exit_hibernation(hsotg, 0, 1, 0);
 769         } else if ((gpwrdn & GPWRDN_STS_CHGINT) &&
 770                    (gpwrdn & GPWRDN_STS_CHGINT_MSK)) {
 771                 dev_dbg(hsotg->dev, "%s: GPWRDN_STS_CHGINT\n", __func__);
 772                 /*
 773                  * As GPWRDN_STS_CHGINT exit from hibernation flow is
 774                  * the same as in GPWRDN_DISCONN_DET flow. Call
 775                  * disconnect detect helper function to exit from
 776                  * hibernation.
 777                  */
 778                 dwc_handle_gpwrdn_disc_det(hsotg, gpwrdn);
 779         }
 780 }
 781
 782 /*
 783  * Common interrupt handler
 784  *
 785  * The common interrupts are those that occur in both Host and Device mode.
 786  * This handler handles the following interrupts:
 787  * - Mode Mismatch Interrupt
 788  * - OTG Interrupt
 789  * - Connector ID Status Change Interrupt
 790  * - Disconnect Interrupt
 791  * - Session Request Interrupt
 792  * - Resume / Remote Wakeup Detected Interrupt
 793  * - Suspend Interrupt
 794  */
 795 irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
 796 {
 797         struct dwc2_hsotg *hsotg = dev;
 798         u32 gintsts;
 799         irqreturn_t retval = IRQ_NONE;
 800
 801         spin_lock(&hsotg->lock);
 802
 803         if (!dwc2_is_controller_alive(hsotg)) {
 804                 dev_warn(hsotg->dev, "Controller is dead\n");
 805                 goto out;
 806         }
 807
 808         /* Reading current frame number value in device or host modes. */
 809         if (dwc2_is_device_mode(hsotg))
 810                 hsotg->frame_number = (dwc2_readl(hsotg, DSTS)
 811                                        & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
 812         else
 813                 hsotg->frame_number = (dwc2_readl(hsotg, HFNUM)
 814                                        & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
 815
 816         gintsts = dwc2_read_common_intr(hsotg);
 817         if (gintsts & ~GINTSTS_PRTINT)
 818                 retval = IRQ_HANDLED;
 819
 820         /* In case of hibernated state gintsts must not work */
 821         if (hsotg->hibernated) {
 822                 dwc2_handle_gpwrdn_intr(hsotg);
 823                 retval = IRQ_HANDLED;
 824                 goto out;
 825         }
 826
 827         if (gintsts & GINTSTS_MODEMIS)
 828                 dwc2_handle_mode_mismatch_intr(hsotg);
 829         if (gintsts & GINTSTS_OTGINT)
 830                 dwc2_handle_otg_intr(hsotg);
 831         if (gintsts & GINTSTS_CONIDSTSCHNG)
 832                 dwc2_handle_conn_id_status_change_intr(hsotg);
 833         if (gintsts & GINTSTS_DISCONNINT)
 834                 dwc2_handle_disconnect_intr(hsotg);
 835         if (gintsts & GINTSTS_SESSREQINT)
 836                 dwc2_handle_session_req_intr(hsotg);
 837         if (gintsts & GINTSTS_WKUPINT)
 838                 dwc2_handle_wakeup_detected_intr(hsotg);
 839         if (gintsts & GINTSTS_USBSUSP)
 840                 dwc2_handle_usb_suspend_intr(hsotg);
 841         if (gintsts & GINTSTS_LPMTRANRCVD)
 842                 dwc2_handle_lpm_intr(hsotg);
 843
 844         if (gintsts & GINTSTS_PRTINT) {
 845                 /*
 846                  * The port interrupt occurs while in device mode with HPRT0
 847                  * Port Enable/Disable
 848                  */
 849                 if (dwc2_is_device_mode(hsotg)) {
 850                         dev_dbg(hsotg->dev,
 851                                 " --Port interrupt received in Device mode--\n");
 852                         dwc2_handle_usb_port_intr(hsotg);
 853                         retval = IRQ_HANDLED;
 854                 }
 855         }
 856
 857 out:
 858         spin_unlock(&hsotg->lock);
 859         return retval;
 860 }