1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * hw.h - DesignWare HS OTG Controller hardware definitions
5 * Copyright 2004-2013 Synopsys, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions, and the following disclaimer,
12 * without modification.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. The names of the above-listed copyright holders may not be used
17 * to endorse or promote products derived from this software without
18 * specific prior written permission.
20 * ALTERNATIVELY, this software may be distributed under the terms of the
21 * GNU General Public License ("GPL") as published by the Free Software
22 * Foundation; either version 2 of the License, or (at your option) any
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 #define HSOTG_REG(x) (x)
43 #define GOTGCTL HSOTG_REG(0x000)
44 #define GOTGCTL_CHIRPEN BIT(27)
45 #define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22)
46 #define GOTGCTL_MULT_VALID_BC_SHIFT 22
47 #define GOTGCTL_OTGVER BIT(20)
48 #define GOTGCTL_BSESVLD BIT(19)
49 #define GOTGCTL_ASESVLD BIT(18)
50 #define GOTGCTL_DBNC_SHORT BIT(17)
51 #define GOTGCTL_CONID_B BIT(16)
52 #define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15)
53 #define GOTGCTL_DEVHNPEN BIT(11)
54 #define GOTGCTL_HSTSETHNPEN BIT(10)
55 #define GOTGCTL_HNPREQ BIT(9)
56 #define GOTGCTL_HSTNEGSCS BIT(8)
57 #define GOTGCTL_SESREQ BIT(1)
58 #define GOTGCTL_SESREQSCS BIT(0)
60 #define GOTGINT HSOTG_REG(0x004)
61 #define GOTGINT_DBNCE_DONE BIT(19)
62 #define GOTGINT_A_DEV_TOUT_CHG BIT(18)
63 #define GOTGINT_HST_NEG_DET BIT(17)
64 #define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9)
65 #define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8)
66 #define GOTGINT_SES_END_DET BIT(2)
68 #define GAHBCFG HSOTG_REG(0x008)
69 #define GAHBCFG_AHB_SINGLE BIT(23)
70 #define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22)
71 #define GAHBCFG_REM_MEM_SUPP BIT(21)
72 #define GAHBCFG_P_TXF_EMP_LVL BIT(8)
73 #define GAHBCFG_NP_TXF_EMP_LVL BIT(7)
74 #define GAHBCFG_DMA_EN BIT(5)
75 #define GAHBCFG_HBSTLEN_MASK (0xf << 1)
76 #define GAHBCFG_HBSTLEN_SHIFT 1
77 #define GAHBCFG_HBSTLEN_SINGLE 0
78 #define GAHBCFG_HBSTLEN_INCR 1
79 #define GAHBCFG_HBSTLEN_INCR4 3
80 #define GAHBCFG_HBSTLEN_INCR8 5
81 #define GAHBCFG_HBSTLEN_INCR16 7
82 #define GAHBCFG_GLBL_INTR_EN BIT(0)
83 #define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \
84 GAHBCFG_NP_TXF_EMP_LVL | \
88 #define GUSBCFG HSOTG_REG(0x00C)
89 #define GUSBCFG_FORCEDEVMODE BIT(30)
90 #define GUSBCFG_FORCEHOSTMODE BIT(29)
91 #define GUSBCFG_TXENDDELAY BIT(28)
92 #define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27)
93 #define GUSBCFG_ICUSBCAP BIT(26)
94 #define GUSBCFG_ULPI_INT_PROT_DIS BIT(25)
95 #define GUSBCFG_INDICATORPASSTHROUGH BIT(24)
96 #define GUSBCFG_INDICATORCOMPLEMENT BIT(23)
97 #define GUSBCFG_TERMSELDLPULSE BIT(22)
98 #define GUSBCFG_ULPI_INT_VBUS_IND BIT(21)
99 #define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20)
100 #define GUSBCFG_ULPI_CLK_SUSP_M BIT(19)
101 #define GUSBCFG_ULPI_AUTO_RES BIT(18)
102 #define GUSBCFG_ULPI_FS_LS BIT(17)
103 #define GUSBCFG_OTG_UTMI_FS_SEL BIT(16)
104 #define GUSBCFG_PHY_LP_CLK_SEL BIT(15)
105 #define GUSBCFG_USBTRDTIM_MASK (0xf << 10)
106 #define GUSBCFG_USBTRDTIM_SHIFT 10
107 #define GUSBCFG_HNPCAP BIT(9)
108 #define GUSBCFG_SRPCAP BIT(8)
109 #define GUSBCFG_DDRSEL BIT(7)
110 #define GUSBCFG_PHYSEL BIT(6)
111 #define GUSBCFG_FSINTF BIT(5)
112 #define GUSBCFG_ULPI_UTMI_SEL BIT(4)
113 #define GUSBCFG_PHYIF16 BIT(3)
114 #define GUSBCFG_PHYIF8 (0 << 3)
115 #define GUSBCFG_TOUTCAL_MASK (0x7 << 0)
116 #define GUSBCFG_TOUTCAL_SHIFT 0
117 #define GUSBCFG_TOUTCAL_LIMIT 0x7
118 #define GUSBCFG_TOUTCAL(_x) ((_x) << 0)
120 #define GRSTCTL HSOTG_REG(0x010)
121 #define GRSTCTL_AHBIDLE BIT(31)
122 #define GRSTCTL_DMAREQ BIT(30)
123 #define GRSTCTL_TXFNUM_MASK (0x1f << 6)
124 #define GRSTCTL_TXFNUM_SHIFT 6
125 #define GRSTCTL_TXFNUM_LIMIT 0x1f
126 #define GRSTCTL_TXFNUM(_x) ((_x) << 6)
127 #define GRSTCTL_TXFFLSH BIT(5)
128 #define GRSTCTL_RXFFLSH BIT(4)
129 #define GRSTCTL_IN_TKNQ_FLSH BIT(3)
130 #define GRSTCTL_FRMCNTRRST BIT(2)
131 #define GRSTCTL_HSFTRST BIT(1)
132 #define GRSTCTL_CSFTRST BIT(0)
134 #define GINTSTS HSOTG_REG(0x014)
135 #define GINTMSK HSOTG_REG(0x018)
136 #define GINTSTS_WKUPINT BIT(31)
137 #define GINTSTS_SESSREQINT BIT(30)
138 #define GINTSTS_DISCONNINT BIT(29)
139 #define GINTSTS_CONIDSTSCHNG BIT(28)
140 #define GINTSTS_LPMTRANRCVD BIT(27)
141 #define GINTSTS_PTXFEMP BIT(26)
142 #define GINTSTS_HCHINT BIT(25)
143 #define GINTSTS_PRTINT BIT(24)
144 #define GINTSTS_RESETDET BIT(23)
145 #define GINTSTS_FET_SUSP BIT(22)
146 #define GINTSTS_INCOMPL_IP BIT(21)
147 #define GINTSTS_INCOMPL_SOOUT BIT(21)
148 #define GINTSTS_INCOMPL_SOIN BIT(20)
149 #define GINTSTS_OEPINT BIT(19)
150 #define GINTSTS_IEPINT BIT(18)
151 #define GINTSTS_EPMIS BIT(17)
152 #define GINTSTS_RESTOREDONE BIT(16)
153 #define GINTSTS_EOPF BIT(15)
154 #define GINTSTS_ISOUTDROP BIT(14)
155 #define GINTSTS_ENUMDONE BIT(13)
156 #define GINTSTS_USBRST BIT(12)
157 #define GINTSTS_USBSUSP BIT(11)
158 #define GINTSTS_ERLYSUSP BIT(10)
159 #define GINTSTS_I2CINT BIT(9)
160 #define GINTSTS_ULPI_CK_INT BIT(8)
161 #define GINTSTS_GOUTNAKEFF BIT(7)
162 #define GINTSTS_GINNAKEFF BIT(6)
163 #define GINTSTS_NPTXFEMP BIT(5)
164 #define GINTSTS_RXFLVL BIT(4)
165 #define GINTSTS_SOF BIT(3)
166 #define GINTSTS_OTGINT BIT(2)
167 #define GINTSTS_MODEMIS BIT(1)
168 #define GINTSTS_CURMODE_HOST BIT(0)
170 #define GRXSTSR HSOTG_REG(0x01C)
171 #define GRXSTSP HSOTG_REG(0x020)
172 #define GRXSTS_FN_MASK (0x7f << 25)
173 #define GRXSTS_FN_SHIFT 25
174 #define GRXSTS_PKTSTS_MASK (0xf << 17)
175 #define GRXSTS_PKTSTS_SHIFT 17
176 #define GRXSTS_PKTSTS_GLOBALOUTNAK 1
177 #define GRXSTS_PKTSTS_OUTRX 2
178 #define GRXSTS_PKTSTS_HCHIN 2
179 #define GRXSTS_PKTSTS_OUTDONE 3
180 #define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3
181 #define GRXSTS_PKTSTS_SETUPDONE 4
182 #define GRXSTS_PKTSTS_DATATOGGLEERR 5
183 #define GRXSTS_PKTSTS_SETUPRX 6
184 #define GRXSTS_PKTSTS_HCHHALTED 7
185 #define GRXSTS_HCHNUM_MASK (0xf << 0)
186 #define GRXSTS_HCHNUM_SHIFT 0
187 #define GRXSTS_DPID_MASK (0x3 << 15)
188 #define GRXSTS_DPID_SHIFT 15
189 #define GRXSTS_BYTECNT_MASK (0x7ff << 4)
190 #define GRXSTS_BYTECNT_SHIFT 4
191 #define GRXSTS_EPNUM_MASK (0xf << 0)
192 #define GRXSTS_EPNUM_SHIFT 0
194 #define GRXFSIZ HSOTG_REG(0x024)
195 #define GRXFSIZ_DEPTH_MASK (0xffff << 0)
196 #define GRXFSIZ_DEPTH_SHIFT 0
198 #define GNPTXFSIZ HSOTG_REG(0x028)
199 /* Use FIFOSIZE_* constants to access this register */
201 #define GNPTXSTS HSOTG_REG(0x02C)
202 #define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24)
203 #define GNPTXSTS_NP_TXQ_TOP_SHIFT 24
204 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16)
205 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16
206 #define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff)
207 #define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0)
208 #define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0
209 #define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff)
211 #define GI2CCTL HSOTG_REG(0x0030)
212 #define GI2CCTL_BSYDNE BIT(31)
213 #define GI2CCTL_RW BIT(30)
214 #define GI2CCTL_I2CDATSE0 BIT(28)
215 #define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26)
216 #define GI2CCTL_I2CDEVADDR_SHIFT 26
217 #define GI2CCTL_I2CSUSPCTL BIT(25)
218 #define GI2CCTL_ACK BIT(24)
219 #define GI2CCTL_I2CEN BIT(23)
220 #define GI2CCTL_ADDR_MASK (0x7f << 16)
221 #define GI2CCTL_ADDR_SHIFT 16
222 #define GI2CCTL_REGADDR_MASK (0xff << 8)
223 #define GI2CCTL_REGADDR_SHIFT 8
224 #define GI2CCTL_RWDATA_MASK (0xff << 0)
225 #define GI2CCTL_RWDATA_SHIFT 0
227 #define GPVNDCTL HSOTG_REG(0x0034)
228 #define GGPIO HSOTG_REG(0x0038)
229 #define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16)
231 #define GUID HSOTG_REG(0x003c)
232 #define GSNPSID HSOTG_REG(0x0040)
233 #define GHWCFG1 HSOTG_REG(0x0044)
234 #define GSNPSID_ID_MASK GENMASK(31, 16)
236 #define GHWCFG2 HSOTG_REG(0x0048)
237 #define GHWCFG2_OTG_ENABLE_IC_USB BIT(31)
238 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26)
239 #define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26
240 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24)
241 #define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24
242 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22)
243 #define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22
244 #define GHWCFG2_MULTI_PROC_INT BIT(20)
245 #define GHWCFG2_DYNAMIC_FIFO BIT(19)
246 #define GHWCFG2_PERIO_EP_SUPPORTED BIT(18)
247 #define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14)
248 #define GHWCFG2_NUM_HOST_CHAN_SHIFT 14
249 #define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10)
250 #define GHWCFG2_NUM_DEV_EP_SHIFT 10
251 #define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8)
252 #define GHWCFG2_FS_PHY_TYPE_SHIFT 8
253 #define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0
254 #define GHWCFG2_FS_PHY_TYPE_DEDICATED 1
255 #define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2
256 #define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3
257 #define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6)
258 #define GHWCFG2_HS_PHY_TYPE_SHIFT 6
259 #define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0
260 #define GHWCFG2_HS_PHY_TYPE_UTMI 1
261 #define GHWCFG2_HS_PHY_TYPE_ULPI 2
262 #define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3
263 #define GHWCFG2_POINT2POINT BIT(5)
264 #define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3)
265 #define GHWCFG2_ARCHITECTURE_SHIFT 3
266 #define GHWCFG2_SLAVE_ONLY_ARCH 0
267 #define GHWCFG2_EXT_DMA_ARCH 1
268 #define GHWCFG2_INT_DMA_ARCH 2
269 #define GHWCFG2_OP_MODE_MASK (0x7 << 0)
270 #define GHWCFG2_OP_MODE_SHIFT 0
271 #define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0
272 #define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1
273 #define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2
274 #define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3
275 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4
276 #define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5
277 #define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6
278 #define GHWCFG2_OP_MODE_UNDEFINED 7
280 #define GHWCFG3 HSOTG_REG(0x004c)
281 #define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16)
282 #define GHWCFG3_DFIFO_DEPTH_SHIFT 16
283 #define GHWCFG3_OTG_LPM_EN BIT(15)
284 #define GHWCFG3_BC_SUPPORT BIT(14)
285 #define GHWCFG3_OTG_ENABLE_HSIC BIT(13)
286 #define GHWCFG3_ADP_SUPP BIT(12)
287 #define GHWCFG3_SYNCH_RESET_TYPE BIT(11)
288 #define GHWCFG3_OPTIONAL_FEATURES BIT(10)
289 #define GHWCFG3_VENDOR_CTRL_IF BIT(9)
290 #define GHWCFG3_I2C BIT(8)
291 #define GHWCFG3_OTG_FUNC BIT(7)
292 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4)
293 #define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4
294 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0)
295 #define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0
297 #define GHWCFG4 HSOTG_REG(0x0050)
298 #define GHWCFG4_DESC_DMA_DYN BIT(31)
299 #define GHWCFG4_DESC_DMA BIT(30)
300 #define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26)
301 #define GHWCFG4_NUM_IN_EPS_SHIFT 26
302 #define GHWCFG4_DED_FIFO_EN BIT(25)
303 #define GHWCFG4_DED_FIFO_SHIFT 25
304 #define GHWCFG4_SESSION_END_FILT_EN BIT(24)
305 #define GHWCFG4_B_VALID_FILT_EN BIT(23)
306 #define GHWCFG4_A_VALID_FILT_EN BIT(22)
307 #define GHWCFG4_VBUS_VALID_FILT_EN BIT(21)
308 #define GHWCFG4_IDDIG_FILT_EN BIT(20)
309 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16)
310 #define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16
311 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14)
312 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14
313 #define GHWCFG4_ACG_SUPPORTED BIT(12)
314 #define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11)
315 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0
316 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1
317 #define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2
318 #define GHWCFG4_XHIBER BIT(7)
319 #define GHWCFG4_HIBER BIT(6)
320 #define GHWCFG4_MIN_AHB_FREQ BIT(5)
321 #define GHWCFG4_POWER_OPTIMIZ BIT(4)
322 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0)
323 #define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0
325 #define GLPMCFG HSOTG_REG(0x0054)
326 #define GLPMCFG_INVSELHSIC BIT(31)
327 #define GLPMCFG_HSICCON BIT(30)
328 #define GLPMCFG_RSTRSLPSTS BIT(29)
329 #define GLPMCFG_ENBESL BIT(28)
330 #define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25)
331 #define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25
332 #define GLPMCFG_SNDLPM BIT(24)
333 #define GLPMCFG_RETRY_CNT_MASK (0x7 << 21)
334 #define GLPMCFG_RETRY_CNT_SHIFT 21
335 #define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17)
336 #define GLPMCFG_LPM_CHNL_INDX_SHIFT 17
337 #define GLPMCFG_L1RESUMEOK BIT(16)
338 #define GLPMCFG_SLPSTS BIT(15)
339 #define GLPMCFG_COREL1RES_MASK (0x3 << 13)
340 #define GLPMCFG_COREL1RES_SHIFT 13
341 #define GLPMCFG_HIRD_THRES_MASK (0x1f << 8)
342 #define GLPMCFG_HIRD_THRES_SHIFT 8
343 #define GLPMCFG_HIRD_THRES_EN (0x10 << 8)
344 #define GLPMCFG_ENBLSLPM BIT(7)
345 #define GLPMCFG_BREMOTEWAKE BIT(6)
346 #define GLPMCFG_HIRD_MASK (0xf << 2)
347 #define GLPMCFG_HIRD_SHIFT 2
348 #define GLPMCFG_APPL1RES BIT(1)
349 #define GLPMCFG_LPMCAP BIT(0)
351 #define GPWRDN HSOTG_REG(0x0058)
352 #define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24)
353 #define GPWRDN_MULT_VAL_ID_BC_SHIFT 24
354 #define GPWRDN_ADP_INT BIT(23)
355 #define GPWRDN_BSESSVLD BIT(22)
356 #define GPWRDN_IDSTS BIT(21)
357 #define GPWRDN_LINESTATE_MASK (0x3 << 19)
358 #define GPWRDN_LINESTATE_SHIFT 19
359 #define GPWRDN_STS_CHGINT_MSK BIT(18)
360 #define GPWRDN_STS_CHGINT BIT(17)
361 #define GPWRDN_SRP_DET_MSK BIT(16)
362 #define GPWRDN_SRP_DET BIT(15)
363 #define GPWRDN_CONNECT_DET_MSK BIT(14)
364 #define GPWRDN_CONNECT_DET BIT(13)
365 #define GPWRDN_DISCONN_DET_MSK BIT(12)
366 #define GPWRDN_DISCONN_DET BIT(11)
367 #define GPWRDN_RST_DET_MSK BIT(10)
368 #define GPWRDN_RST_DET BIT(9)
369 #define GPWRDN_LNSTSCHG_MSK BIT(8)
370 #define GPWRDN_LNSTSCHG BIT(7)
371 #define GPWRDN_DIS_VBUS BIT(6)
372 #define GPWRDN_PWRDNSWTCH BIT(5)
373 #define GPWRDN_PWRDNRSTN BIT(4)
374 #define GPWRDN_PWRDNCLMP BIT(3)
375 #define GPWRDN_RESTORE BIT(2)
376 #define GPWRDN_PMUACTV BIT(1)
377 #define GPWRDN_PMUINTSEL BIT(0)
379 #define GDFIFOCFG HSOTG_REG(0x005c)
380 #define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16)
381 #define GDFIFOCFG_EPINFOBASE_SHIFT 16
382 #define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0)
383 #define GDFIFOCFG_GDFIFOCFG_SHIFT 0
385 #define ADPCTL HSOTG_REG(0x0060)
386 #define ADPCTL_AR_MASK (0x3 << 27)
387 #define ADPCTL_AR_SHIFT 27
388 #define ADPCTL_ADP_TMOUT_INT_MSK BIT(26)
389 #define ADPCTL_ADP_SNS_INT_MSK BIT(25)
390 #define ADPCTL_ADP_PRB_INT_MSK BIT(24)
391 #define ADPCTL_ADP_TMOUT_INT BIT(23)
392 #define ADPCTL_ADP_SNS_INT BIT(22)
393 #define ADPCTL_ADP_PRB_INT BIT(21)
394 #define ADPCTL_ADPENA BIT(20)
395 #define ADPCTL_ADPRES BIT(19)
396 #define ADPCTL_ENASNS BIT(18)
397 #define ADPCTL_ENAPRB BIT(17)
398 #define ADPCTL_RTIM_MASK (0x7ff << 6)
399 #define ADPCTL_RTIM_SHIFT 6
400 #define ADPCTL_PRB_PER_MASK (0x3 << 4)
401 #define ADPCTL_PRB_PER_SHIFT 4
402 #define ADPCTL_PRB_DELTA_MASK (0x3 << 2)
403 #define ADPCTL_PRB_DELTA_SHIFT 2
404 #define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0)
405 #define ADPCTL_PRB_DSCHRG_SHIFT 0
407 #define HPTXFSIZ HSOTG_REG(0x100)
408 /* Use FIFOSIZE_* constants to access this register */
410 #define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4))
411 /* Use FIFOSIZE_* constants to access this register */
413 /* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */
414 #define FIFOSIZE_DEPTH_MASK (0xffff << 16)
415 #define FIFOSIZE_DEPTH_SHIFT 16
416 #define FIFOSIZE_STARTADDR_MASK (0xffff << 0)
417 #define FIFOSIZE_STARTADDR_SHIFT 0
418 #define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff)
420 /* Device mode registers */
422 #define DCFG HSOTG_REG(0x800)
423 #define DCFG_DESCDMA_EN BIT(23)
424 #define DCFG_EPMISCNT_MASK (0x1f << 18)
425 #define DCFG_EPMISCNT_SHIFT 18
426 #define DCFG_EPMISCNT_LIMIT 0x1f
427 #define DCFG_EPMISCNT(_x) ((_x) << 18)
428 #define DCFG_IPG_ISOC_SUPPORDED BIT(17)
429 #define DCFG_PERFRINT_MASK (0x3 << 11)
430 #define DCFG_PERFRINT_SHIFT 11
431 #define DCFG_PERFRINT_LIMIT 0x3
432 #define DCFG_PERFRINT(_x) ((_x) << 11)
433 #define DCFG_DEVADDR_MASK (0x7f << 4)
434 #define DCFG_DEVADDR_SHIFT 4
435 #define DCFG_DEVADDR_LIMIT 0x7f
436 #define DCFG_DEVADDR(_x) ((_x) << 4)
437 #define DCFG_NZ_STS_OUT_HSHK BIT(2)
438 #define DCFG_DEVSPD_MASK (0x3 << 0)
439 #define DCFG_DEVSPD_SHIFT 0
440 #define DCFG_DEVSPD_HS 0
441 #define DCFG_DEVSPD_FS 1
442 #define DCFG_DEVSPD_LS 2
443 #define DCFG_DEVSPD_FS48 3
445 #define DCTL HSOTG_REG(0x804)
446 #define DCTL_PWRONPRGDONE BIT(11)
447 #define DCTL_CGOUTNAK BIT(10)
448 #define DCTL_SGOUTNAK BIT(9)
449 #define DCTL_CGNPINNAK BIT(8)
450 #define DCTL_SGNPINNAK BIT(7)
451 #define DCTL_TSTCTL_MASK (0x7 << 4)
452 #define DCTL_TSTCTL_SHIFT 4
453 #define DCTL_GOUTNAKSTS BIT(3)
454 #define DCTL_GNPINNAKSTS BIT(2)
455 #define DCTL_SFTDISCON BIT(1)
456 #define DCTL_RMTWKUPSIG BIT(0)
458 #define DSTS HSOTG_REG(0x808)
459 #define DSTS_SOFFN_MASK (0x3fff << 8)
460 #define DSTS_SOFFN_SHIFT 8
461 #define DSTS_SOFFN_LIMIT 0x3fff
462 #define DSTS_SOFFN(_x) ((_x) << 8)
463 #define DSTS_ERRATICERR BIT(3)
464 #define DSTS_ENUMSPD_MASK (0x3 << 1)
465 #define DSTS_ENUMSPD_SHIFT 1
466 #define DSTS_ENUMSPD_HS 0
467 #define DSTS_ENUMSPD_FS 1
468 #define DSTS_ENUMSPD_LS 2
469 #define DSTS_ENUMSPD_FS48 3
470 #define DSTS_SUSPSTS BIT(0)
472 #define DIEPMSK HSOTG_REG(0x810)
473 #define DIEPMSK_NAKMSK BIT(13)
474 #define DIEPMSK_BNAININTRMSK BIT(9)
475 #define DIEPMSK_TXFIFOUNDRNMSK BIT(8)
476 #define DIEPMSK_TXFIFOEMPTY BIT(7)
477 #define DIEPMSK_INEPNAKEFFMSK BIT(6)
478 #define DIEPMSK_INTKNEPMISMSK BIT(5)
479 #define DIEPMSK_INTKNTXFEMPMSK BIT(4)
480 #define DIEPMSK_TIMEOUTMSK BIT(3)
481 #define DIEPMSK_AHBERRMSK BIT(2)
482 #define DIEPMSK_EPDISBLDMSK BIT(1)
483 #define DIEPMSK_XFERCOMPLMSK BIT(0)
485 #define DOEPMSK HSOTG_REG(0x814)
486 #define DOEPMSK_BNAMSK BIT(9)
487 #define DOEPMSK_BACK2BACKSETUP BIT(6)
488 #define DOEPMSK_STSPHSERCVDMSK BIT(5)
489 #define DOEPMSK_OUTTKNEPDISMSK BIT(4)
490 #define DOEPMSK_SETUPMSK BIT(3)
491 #define DOEPMSK_AHBERRMSK BIT(2)
492 #define DOEPMSK_EPDISBLDMSK BIT(1)
493 #define DOEPMSK_XFERCOMPLMSK BIT(0)
495 #define DAINT HSOTG_REG(0x818)
496 #define DAINTMSK HSOTG_REG(0x81C)
497 #define DAINT_OUTEP_SHIFT 16
498 #define DAINT_OUTEP(_x) (1 << ((_x) + 16))
499 #define DAINT_INEP(_x) (1 << (_x))
501 #define DTKNQR1 HSOTG_REG(0x820)
502 #define DTKNQR2 HSOTG_REG(0x824)
503 #define DTKNQR3 HSOTG_REG(0x830)
504 #define DTKNQR4 HSOTG_REG(0x834)
505 #define DIEPEMPMSK HSOTG_REG(0x834)
507 #define DVBUSDIS HSOTG_REG(0x828)
508 #define DVBUSPULSE HSOTG_REG(0x82C)
510 #define DIEPCTL0 HSOTG_REG(0x900)
511 #define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20))
513 #define DOEPCTL0 HSOTG_REG(0xB00)
514 #define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20))
517 * bits[29..28] - reserved (no SetD0PID, SetD1PID)
518 * bits[25..22] - should always be zero, this isn't a periodic endpoint
519 * bits[10..0] - MPS setting different for EP0
521 #define D0EPCTL_MPS_MASK (0x3 << 0)
522 #define D0EPCTL_MPS_SHIFT 0
523 #define D0EPCTL_MPS_64 0
524 #define D0EPCTL_MPS_32 1
525 #define D0EPCTL_MPS_16 2
526 #define D0EPCTL_MPS_8 3
528 #define DXEPCTL_EPENA BIT(31)
529 #define DXEPCTL_EPDIS BIT(30)
530 #define DXEPCTL_SETD1PID BIT(29)
531 #define DXEPCTL_SETODDFR BIT(29)
532 #define DXEPCTL_SETD0PID BIT(28)
533 #define DXEPCTL_SETEVENFR BIT(28)
534 #define DXEPCTL_SNAK BIT(27)
535 #define DXEPCTL_CNAK BIT(26)
536 #define DXEPCTL_TXFNUM_MASK (0xf << 22)
537 #define DXEPCTL_TXFNUM_SHIFT 22
538 #define DXEPCTL_TXFNUM_LIMIT 0xf
539 #define DXEPCTL_TXFNUM(_x) ((_x) << 22)
540 #define DXEPCTL_STALL BIT(21)
541 #define DXEPCTL_SNP BIT(20)
542 #define DXEPCTL_EPTYPE_MASK (0x3 << 18)
543 #define DXEPCTL_EPTYPE_CONTROL (0x0 << 18)
544 #define DXEPCTL_EPTYPE_ISO (0x1 << 18)
545 #define DXEPCTL_EPTYPE_BULK (0x2 << 18)
546 #define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18)
548 #define DXEPCTL_NAKSTS BIT(17)
549 #define DXEPCTL_DPID BIT(16)
550 #define DXEPCTL_EOFRNUM BIT(16)
551 #define DXEPCTL_USBACTEP BIT(15)
552 #define DXEPCTL_NEXTEP_MASK (0xf << 11)
553 #define DXEPCTL_NEXTEP_SHIFT 11
554 #define DXEPCTL_NEXTEP_LIMIT 0xf
555 #define DXEPCTL_NEXTEP(_x) ((_x) << 11)
556 #define DXEPCTL_MPS_MASK (0x7ff << 0)
557 #define DXEPCTL_MPS_SHIFT 0
558 #define DXEPCTL_MPS_LIMIT 0x7ff
559 #define DXEPCTL_MPS(_x) ((_x) << 0)
561 #define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20))
562 #define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20))
563 #define DXEPINT_SETUP_RCVD BIT(15)
564 #define DXEPINT_NYETINTRPT BIT(14)
565 #define DXEPINT_NAKINTRPT BIT(13)
566 #define DXEPINT_BBLEERRINTRPT BIT(12)
567 #define DXEPINT_PKTDRPSTS BIT(11)
568 #define DXEPINT_BNAINTR BIT(9)
569 #define DXEPINT_TXFIFOUNDRN BIT(8)
570 #define DXEPINT_OUTPKTERR BIT(8)
571 #define DXEPINT_TXFEMP BIT(7)
572 #define DXEPINT_INEPNAKEFF BIT(6)
573 #define DXEPINT_BACK2BACKSETUP BIT(6)
574 #define DXEPINT_INTKNEPMIS BIT(5)
575 #define DXEPINT_STSPHSERCVD BIT(5)
576 #define DXEPINT_INTKNTXFEMP BIT(4)
577 #define DXEPINT_OUTTKNEPDIS BIT(4)
578 #define DXEPINT_TIMEOUT BIT(3)
579 #define DXEPINT_SETUP BIT(3)
580 #define DXEPINT_AHBERR BIT(2)
581 #define DXEPINT_EPDISBLD BIT(1)
582 #define DXEPINT_XFERCOMPL BIT(0)
584 #define DIEPTSIZ0 HSOTG_REG(0x910)
585 #define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19)
586 #define DIEPTSIZ0_PKTCNT_SHIFT 19
587 #define DIEPTSIZ0_PKTCNT_LIMIT 0x3
588 #define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19)
589 #define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
590 #define DIEPTSIZ0_XFERSIZE_SHIFT 0
591 #define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f
592 #define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0)
594 #define DOEPTSIZ0 HSOTG_REG(0xB10)
595 #define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29)
596 #define DOEPTSIZ0_SUPCNT_SHIFT 29
597 #define DOEPTSIZ0_SUPCNT_LIMIT 0x3
598 #define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29)
599 #define DOEPTSIZ0_PKTCNT BIT(19)
600 #define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0)
601 #define DOEPTSIZ0_XFERSIZE_SHIFT 0
603 #define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20))
604 #define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20))
605 #define DXEPTSIZ_MC_MASK (0x3 << 29)
606 #define DXEPTSIZ_MC_SHIFT 29
607 #define DXEPTSIZ_MC_LIMIT 0x3
608 #define DXEPTSIZ_MC(_x) ((_x) << 29)
609 #define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19)
610 #define DXEPTSIZ_PKTCNT_SHIFT 19
611 #define DXEPTSIZ_PKTCNT_LIMIT 0x3ff
612 #define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff)
613 #define DXEPTSIZ_PKTCNT(_x) ((_x) << 19)
614 #define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0)
615 #define DXEPTSIZ_XFERSIZE_SHIFT 0
616 #define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff
617 #define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff)
618 #define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0)
620 #define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20))
621 #define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20))
623 #define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20))
625 #define PCGCTL HSOTG_REG(0x0e00)
626 #define PCGCTL_IF_DEV_MODE BIT(31)
627 #define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29)
628 #define PCGCTL_P2HD_PRT_SPD_SHIFT 29
629 #define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27)
630 #define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27
631 #define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20)
632 #define PCGCTL_MAC_DEV_ADDR_SHIFT 20
633 #define PCGCTL_MAX_TERMSEL BIT(19)
634 #define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17)
635 #define PCGCTL_MAX_XCVRSELECT_SHIFT 17
636 #define PCGCTL_PORT_POWER BIT(16)
637 #define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14)
638 #define PCGCTL_PRT_CLK_SEL_SHIFT 14
639 #define PCGCTL_ESS_REG_RESTORED BIT(13)
640 #define PCGCTL_EXTND_HIBER_SWITCH BIT(12)
641 #define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11)
642 #define PCGCTL_ENBL_EXTND_HIBER BIT(10)
643 #define PCGCTL_RESTOREMODE BIT(9)
644 #define PCGCTL_RESETAFTSUSP BIT(8)
645 #define PCGCTL_DEEP_SLEEP BIT(7)
646 #define PCGCTL_PHY_IN_SLEEP BIT(6)
647 #define PCGCTL_ENBL_SLEEP_GATING BIT(5)
648 #define PCGCTL_RSTPDWNMODULE BIT(3)
649 #define PCGCTL_PWRCLMP BIT(2)
650 #define PCGCTL_GATEHCLK BIT(1)
651 #define PCGCTL_STOPPCLK BIT(0)
653 #define PCGCCTL1 HSOTG_REG(0xe04)
654 #define PCGCCTL1_TIMER (0x3 << 1)
655 #define PCGCCTL1_GATEEN BIT(0)
657 #define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
659 /* Host Mode Registers */
661 #define HCFG HSOTG_REG(0x0400)
662 #define HCFG_MODECHTIMEN BIT(31)
663 #define HCFG_PERSCHEDENA BIT(26)
664 #define HCFG_FRLISTEN_MASK (0x3 << 24)
665 #define HCFG_FRLISTEN_SHIFT 24
666 #define HCFG_FRLISTEN_8 (0 << 24)
667 #define FRLISTEN_8_SIZE 8
668 #define HCFG_FRLISTEN_16 BIT(24)
669 #define FRLISTEN_16_SIZE 16
670 #define HCFG_FRLISTEN_32 (2 << 24)
671 #define FRLISTEN_32_SIZE 32
672 #define HCFG_FRLISTEN_64 (3 << 24)
673 #define FRLISTEN_64_SIZE 64
674 #define HCFG_DESCDMA BIT(23)
675 #define HCFG_RESVALID_MASK (0xff << 8)
676 #define HCFG_RESVALID_SHIFT 8
677 #define HCFG_ENA32KHZ BIT(7)
678 #define HCFG_FSLSSUPP BIT(2)
679 #define HCFG_FSLSPCLKSEL_MASK (0x3 << 0)
680 #define HCFG_FSLSPCLKSEL_SHIFT 0
681 #define HCFG_FSLSPCLKSEL_30_60_MHZ 0
682 #define HCFG_FSLSPCLKSEL_48_MHZ 1
683 #define HCFG_FSLSPCLKSEL_6_MHZ 2
685 #define HFIR HSOTG_REG(0x0404)
686 #define HFIR_FRINT_MASK (0xffff << 0)
687 #define HFIR_FRINT_SHIFT 0
688 #define HFIR_RLDCTRL BIT(16)
690 #define HFNUM HSOTG_REG(0x0408)
691 #define HFNUM_FRREM_MASK (0xffff << 16)
692 #define HFNUM_FRREM_SHIFT 16
693 #define HFNUM_FRNUM_MASK (0xffff << 0)
694 #define HFNUM_FRNUM_SHIFT 0
695 #define HFNUM_MAX_FRNUM 0x3fff
697 #define HPTXSTS HSOTG_REG(0x0410)
698 #define TXSTS_QTOP_ODD BIT(31)
699 #define TXSTS_QTOP_CHNEP_MASK (0xf << 27)
700 #define TXSTS_QTOP_CHNEP_SHIFT 27
701 #define TXSTS_QTOP_TOKEN_MASK (0x3 << 25)
702 #define TXSTS_QTOP_TOKEN_SHIFT 25
703 #define TXSTS_QTOP_TERMINATE BIT(24)
704 #define TXSTS_QSPCAVAIL_MASK (0xff << 16)
705 #define TXSTS_QSPCAVAIL_SHIFT 16
706 #define TXSTS_FSPCAVAIL_MASK (0xffff << 0)
707 #define TXSTS_FSPCAVAIL_SHIFT 0
709 #define HAINT HSOTG_REG(0x0414)
710 #define HAINTMSK HSOTG_REG(0x0418)
711 #define HFLBADDR HSOTG_REG(0x041c)
713 #define HPRT0 HSOTG_REG(0x0440)
714 #define HPRT0_SPD_MASK (0x3 << 17)
715 #define HPRT0_SPD_SHIFT 17
716 #define HPRT0_SPD_HIGH_SPEED 0
717 #define HPRT0_SPD_FULL_SPEED 1
718 #define HPRT0_SPD_LOW_SPEED 2
719 #define HPRT0_TSTCTL_MASK (0xf << 13)
720 #define HPRT0_TSTCTL_SHIFT 13
721 #define HPRT0_PWR BIT(12)
722 #define HPRT0_LNSTS_MASK (0x3 << 10)
723 #define HPRT0_LNSTS_SHIFT 10
724 #define HPRT0_RST BIT(8)
725 #define HPRT0_SUSP BIT(7)
726 #define HPRT0_RES BIT(6)
727 #define HPRT0_OVRCURRCHG BIT(5)
728 #define HPRT0_OVRCURRACT BIT(4)
729 #define HPRT0_ENACHG BIT(3)
730 #define HPRT0_ENA BIT(2)
731 #define HPRT0_CONNDET BIT(1)
732 #define HPRT0_CONNSTS BIT(0)
734 #define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch))
735 #define HCCHAR_CHENA BIT(31)
736 #define HCCHAR_CHDIS BIT(30)
737 #define HCCHAR_ODDFRM BIT(29)
738 #define HCCHAR_DEVADDR_MASK (0x7f << 22)
739 #define HCCHAR_DEVADDR_SHIFT 22
740 #define HCCHAR_MULTICNT_MASK (0x3 << 20)
741 #define HCCHAR_MULTICNT_SHIFT 20
742 #define HCCHAR_EPTYPE_MASK (0x3 << 18)
743 #define HCCHAR_EPTYPE_SHIFT 18
744 #define HCCHAR_LSPDDEV BIT(17)
745 #define HCCHAR_EPDIR BIT(15)
746 #define HCCHAR_EPNUM_MASK (0xf << 11)
747 #define HCCHAR_EPNUM_SHIFT 11
748 #define HCCHAR_MPS_MASK (0x7ff << 0)
749 #define HCCHAR_MPS_SHIFT 0
751 #define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch))
752 #define HCSPLT_SPLTENA BIT(31)
753 #define HCSPLT_COMPSPLT BIT(16)
754 #define HCSPLT_XACTPOS_MASK (0x3 << 14)
755 #define HCSPLT_XACTPOS_SHIFT 14
756 #define HCSPLT_XACTPOS_MID 0
757 #define HCSPLT_XACTPOS_END 1
758 #define HCSPLT_XACTPOS_BEGIN 2
759 #define HCSPLT_XACTPOS_ALL 3
760 #define HCSPLT_HUBADDR_MASK (0x7f << 7)
761 #define HCSPLT_HUBADDR_SHIFT 7
762 #define HCSPLT_PRTADDR_MASK (0x7f << 0)
763 #define HCSPLT_PRTADDR_SHIFT 0
765 #define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch))
766 #define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch))
767 #define HCINTMSK_RESERVED14_31 (0x3ffff << 14)
768 #define HCINTMSK_FRM_LIST_ROLL BIT(13)
769 #define HCINTMSK_XCS_XACT BIT(12)
770 #define HCINTMSK_BNA BIT(11)
771 #define HCINTMSK_DATATGLERR BIT(10)
772 #define HCINTMSK_FRMOVRUN BIT(9)
773 #define HCINTMSK_BBLERR BIT(8)
774 #define HCINTMSK_XACTERR BIT(7)
775 #define HCINTMSK_NYET BIT(6)
776 #define HCINTMSK_ACK BIT(5)
777 #define HCINTMSK_NAK BIT(4)
778 #define HCINTMSK_STALL BIT(3)
779 #define HCINTMSK_AHBERR BIT(2)
780 #define HCINTMSK_CHHLTD BIT(1)
781 #define HCINTMSK_XFERCOMPL BIT(0)
783 #define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch))
784 #define TSIZ_DOPNG BIT(31)
785 #define TSIZ_SC_MC_PID_MASK (0x3 << 29)
786 #define TSIZ_SC_MC_PID_SHIFT 29
787 #define TSIZ_SC_MC_PID_DATA0 0
788 #define TSIZ_SC_MC_PID_DATA2 1
789 #define TSIZ_SC_MC_PID_DATA1 2
790 #define TSIZ_SC_MC_PID_MDATA 3
791 #define TSIZ_SC_MC_PID_SETUP 3
792 #define TSIZ_PKTCNT_MASK (0x3ff << 19)
793 #define TSIZ_PKTCNT_SHIFT 19
794 #define TSIZ_NTD_MASK (0xff << 8)
795 #define TSIZ_NTD_SHIFT 8
796 #define TSIZ_SCHINFO_MASK (0xff << 0)
797 #define TSIZ_SCHINFO_SHIFT 0
798 #define TSIZ_XFERSIZE_MASK (0x7ffff << 0)
799 #define TSIZ_XFERSIZE_SHIFT 0
801 #define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch))
803 #define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch))
805 #define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch))
808 * struct dwc2_dma_desc - DMA descriptor structure,
809 * used for both host and gadget modes
811 * @status: DMA descriptor status quadlet
812 * @buf: DMA descriptor data buffer pointer
814 * DMA Descriptor structure contains two quadlets:
815 * Status quadlet and Data buffer pointer.
817 struct dwc2_dma_desc {
822 /* Host Mode DMA descriptor status quadlet */
824 #define HOST_DMA_A BIT(31)
825 #define HOST_DMA_STS_MASK (0x3 << 28)
826 #define HOST_DMA_STS_SHIFT 28
827 #define HOST_DMA_STS_PKTERR BIT(28)
828 #define HOST_DMA_EOL BIT(26)
829 #define HOST_DMA_IOC BIT(25)
830 #define HOST_DMA_SUP BIT(24)
831 #define HOST_DMA_ALT_QTD BIT(23)
832 #define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17)
833 #define HOST_DMA_QTD_OFFSET_SHIFT 17
834 #define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0)
835 #define HOST_DMA_ISOC_NBYTES_SHIFT 0
836 #define HOST_DMA_NBYTES_MASK (0x1ffff << 0)
837 #define HOST_DMA_NBYTES_SHIFT 0
838 #define HOST_DMA_NBYTES_LIMIT 131071
840 /* Device Mode DMA descriptor status quadlet */
842 #define DEV_DMA_BUFF_STS_MASK (0x3 << 30)
843 #define DEV_DMA_BUFF_STS_SHIFT 30
844 #define DEV_DMA_BUFF_STS_HREADY 0
845 #define DEV_DMA_BUFF_STS_DMABUSY 1
846 #define DEV_DMA_BUFF_STS_DMADONE 2
847 #define DEV_DMA_BUFF_STS_HBUSY 3
848 #define DEV_DMA_STS_MASK (0x3 << 28)
849 #define DEV_DMA_STS_SHIFT 28
850 #define DEV_DMA_STS_SUCC 0
851 #define DEV_DMA_STS_BUFF_FLUSH 1
852 #define DEV_DMA_STS_BUFF_ERR 3
853 #define DEV_DMA_L BIT(27)
854 #define DEV_DMA_SHORT BIT(26)
855 #define DEV_DMA_IOC BIT(25)
856 #define DEV_DMA_SR BIT(24)
857 #define DEV_DMA_MTRF BIT(23)
858 #define DEV_DMA_ISOC_PID_MASK (0x3 << 23)
859 #define DEV_DMA_ISOC_PID_SHIFT 23
860 #define DEV_DMA_ISOC_PID_DATA0 0
861 #define DEV_DMA_ISOC_PID_DATA2 1
862 #define DEV_DMA_ISOC_PID_DATA1 2
863 #define DEV_DMA_ISOC_PID_MDATA 3
864 #define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12)
865 #define DEV_DMA_ISOC_FRNUM_SHIFT 12
866 #define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0)
867 #define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff
868 #define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0)
869 #define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff
870 #define DEV_DMA_ISOC_NBYTES_SHIFT 0
871 #define DEV_DMA_NBYTES_MASK (0xffff << 0)
872 #define DEV_DMA_NBYTES_SHIFT 0
873 #define DEV_DMA_NBYTES_LIMIT 0xffff
875 #define MAX_DMA_DESC_NUM_GENERIC 64
876 #define MAX_DMA_DESC_NUM_HS_ISOC 256
878 #endif /* __DWC2_HW_H__ */
projects / releases.git / blob