drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 /**
  53  * dwc3_get_dr_mode - Validates and sets dr_mode
  54  * @dwc: pointer to our context structure
  55  */
  56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  57 {
  58         enum usb_dr_mode mode;
  59         struct device *dev = dwc->dev;
  60         unsigned int hw_mode;
  61
  62         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  63                 dwc->dr_mode = USB_DR_MODE_OTG;
  64
  65         mode = dwc->dr_mode;
  66         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  67
  68         switch (hw_mode) {
  69         case DWC3_GHWPARAMS0_MODE_GADGET:
  70                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  71                         dev_err(dev,
  72                                 "Controller does not support host mode.\n");
  73                         return -EINVAL;
  74                 }
  75                 mode = USB_DR_MODE_PERIPHERAL;
  76                 break;
  77         case DWC3_GHWPARAMS0_MODE_HOST:
  78                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  79                         dev_err(dev,
  80                                 "Controller does not support device mode.\n");
  81                         return -EINVAL;
  82                 }
  83                 mode = USB_DR_MODE_HOST;
  84                 break;
  85         default:
  86                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  87                         mode = USB_DR_MODE_HOST;
  88                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc);
 104 static int dwc3_event_buffers_setup(struct dwc3 *dwc);
 105
 106 static void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 107 {
 108         u32 reg;
 109
 110         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 111         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 112         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 113         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 114 }
 115
 116 static void __dwc3_set_mode(struct work_struct *work)
 117 {
 118         struct dwc3 *dwc = work_to_dwc(work);
 119         unsigned long flags;
 120         int ret;
 121
 122         if (!dwc->desired_dr_role)
 123                 return;
 124
 125         if (dwc->desired_dr_role == dwc->current_dr_role)
 126                 return;
 127
 128         if (dwc->dr_mode != USB_DR_MODE_OTG)
 129                 return;
 130
 131         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG)
 132                 return;
 133
 134         switch (dwc->current_dr_role) {
 135         case DWC3_GCTL_PRTCAP_HOST:
 136                 dwc3_host_exit(dwc);
 137                 break;
 138         case DWC3_GCTL_PRTCAP_DEVICE:
 139                 dwc3_gadget_exit(dwc);
 140                 dwc3_event_buffers_cleanup(dwc);
 141                 break;
 142         default:
 143                 break;
 144         }
 145
 146         spin_lock_irqsave(&dwc->lock, flags);
 147
 148         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 149
 150         dwc->current_dr_role = dwc->desired_dr_role;
 151
 152         spin_unlock_irqrestore(&dwc->lock, flags);
 153
 154         switch (dwc->desired_dr_role) {
 155         case DWC3_GCTL_PRTCAP_HOST:
 156                 ret = dwc3_host_init(dwc);
 157                 if (ret) {
 158                         dev_err(dwc->dev, "failed to initialize host\n");
 159                 } else {
 160                         if (dwc->usb2_phy)
 161                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 162                         if (dwc->usb2_generic_phy)
 163                                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 164
 165                 }
 166                 break;
 167         case DWC3_GCTL_PRTCAP_DEVICE:
 168                 dwc3_event_buffers_setup(dwc);
 169
 170                 if (dwc->usb2_phy)
 171                         otg_set_vbus(dwc->usb2_phy->otg, false);
 172                 if (dwc->usb2_generic_phy)
 173                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 174
 175                 ret = dwc3_gadget_init(dwc);
 176                 if (ret)
 177                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 178                 break;
 179         default:
 180                 break;
 181         }
 182 }
 183
 184 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 185 {
 186         unsigned long flags;
 187
 188         spin_lock_irqsave(&dwc->lock, flags);
 189         dwc->desired_dr_role = mode;
 190         spin_unlock_irqrestore(&dwc->lock, flags);
 191
 192         queue_work(system_freezable_wq, &dwc->drd_work);
 193 }
 194
 195 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 196 {
 197         struct dwc3             *dwc = dep->dwc;
 198         u32                     reg;
 199
 200         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 201                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 202                         DWC3_GDBGFIFOSPACE_TYPE(type));
 203
 204         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 205
 206         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 207 }
 208
 209 /**
 210  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 211  * @dwc: pointer to our context structure
 212  */
 213 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 214 {
 215         u32             reg;
 216         int             retries = 1000;
 217         int             ret;
 218
 219         usb_phy_init(dwc->usb2_phy);
 220         usb_phy_init(dwc->usb3_phy);
 221         ret = phy_init(dwc->usb2_generic_phy);
 222         if (ret < 0)
 223                 return ret;
 224
 225         ret = phy_init(dwc->usb3_generic_phy);
 226         if (ret < 0) {
 227                 phy_exit(dwc->usb2_generic_phy);
 228                 return ret;
 229         }
 230
 231         /*
 232          * We're resetting only the device side because, if we're in host mode,
 233          * XHCI driver will reset the host block. If dwc3 was configured for
 234          * host-only mode, then we can return early.
 235          */
 236         if (dwc->dr_mode == USB_DR_MODE_HOST)
 237                 return 0;
 238
 239         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 240         reg |= DWC3_DCTL_CSFTRST;
 241         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 242
 243         do {
 244                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 245                 if (!(reg & DWC3_DCTL_CSFTRST))
 246                         goto done;
 247
 248                 udelay(1);
 249         } while (--retries);
 250
 251         phy_exit(dwc->usb3_generic_phy);
 252         phy_exit(dwc->usb2_generic_phy);
 253
 254         return -ETIMEDOUT;
 255
 256 done:
 257         /*
 258          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 259          * we must wait at least 50ms before accessing the PHY domain
 260          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 261          */
 262         if (dwc3_is_usb31(dwc))
 263                 msleep(50);
 264
 265         return 0;
 266 }
 267
 268 /*
 269  * dwc3_frame_length_adjustment - Adjusts frame length if required
 270  * @dwc3: Pointer to our controller context structure
 271  */
 272 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 273 {
 274         u32 reg;
 275         u32 dft;
 276
 277         if (dwc->revision < DWC3_REVISION_250A)
 278                 return;
 279
 280         if (dwc->fladj == 0)
 281                 return;
 282
 283         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 284         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 285         if (dft != dwc->fladj) {
 286                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 287                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 288                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 289         }
 290 }
 291
 292 /**
 293  * dwc3_free_one_event_buffer - Frees one event buffer
 294  * @dwc: Pointer to our controller context structure
 295  * @evt: Pointer to event buffer to be freed
 296  */
 297 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 298                 struct dwc3_event_buffer *evt)
 299 {
 300         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 301 }
 302
 303 /**
 304  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 305  * @dwc: Pointer to our controller context structure
 306  * @length: size of the event buffer
 307  *
 308  * Returns a pointer to the allocated event buffer structure on success
 309  * otherwise ERR_PTR(errno).
 310  */
 311 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 312                 unsigned length)
 313 {
 314         struct dwc3_event_buffer        *evt;
 315
 316         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 317         if (!evt)
 318                 return ERR_PTR(-ENOMEM);
 319
 320         evt->dwc        = dwc;
 321         evt->length     = length;
 322         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 323         if (!evt->cache)
 324                 return ERR_PTR(-ENOMEM);
 325
 326         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 327                         &evt->dma, GFP_KERNEL);
 328         if (!evt->buf)
 329                 return ERR_PTR(-ENOMEM);
 330
 331         return evt;
 332 }
 333
 334 /**
 335  * dwc3_free_event_buffers - frees all allocated event buffers
 336  * @dwc: Pointer to our controller context structure
 337  */
 338 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 339 {
 340         struct dwc3_event_buffer        *evt;
 341
 342         evt = dwc->ev_buf;
 343         if (evt)
 344                 dwc3_free_one_event_buffer(dwc, evt);
 345 }
 346
 347 /**
 348  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 349  * @dwc: pointer to our controller context structure
 350  * @length: size of event buffer
 351  *
 352  * Returns 0 on success otherwise negative errno. In the error case, dwc
 353  * may contain some buffers allocated but not all which were requested.
 354  */
 355 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 356 {
 357         struct dwc3_event_buffer *evt;
 358
 359         evt = dwc3_alloc_one_event_buffer(dwc, length);
 360         if (IS_ERR(evt)) {
 361                 dev_err(dwc->dev, "can't allocate event buffer\n");
 362                 return PTR_ERR(evt);
 363         }
 364         dwc->ev_buf = evt;
 365
 366         return 0;
 367 }
 368
 369 /**
 370  * dwc3_event_buffers_setup - setup our allocated event buffers
 371  * @dwc: pointer to our controller context structure
 372  *
 373  * Returns 0 on success otherwise negative errno.
 374  */
 375 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 376 {
 377         struct dwc3_event_buffer        *evt;
 378
 379         evt = dwc->ev_buf;
 380         evt->lpos = 0;
 381         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 382                         lower_32_bits(evt->dma));
 383         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 384                         upper_32_bits(evt->dma));
 385         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 386                         DWC3_GEVNTSIZ_SIZE(evt->length));
 387         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 388
 389         return 0;
 390 }
 391
 392 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 393 {
 394         struct dwc3_event_buffer        *evt;
 395
 396         evt = dwc->ev_buf;
 397
 398         evt->lpos = 0;
 399
 400         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 401         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 402         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 403                         | DWC3_GEVNTSIZ_SIZE(0));
 404         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 405 }
 406
 407 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 408 {
 409         if (!dwc->has_hibernation)
 410                 return 0;
 411
 412         if (!dwc->nr_scratch)
 413                 return 0;
 414
 415         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 416                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 417         if (!dwc->scratchbuf)
 418                 return -ENOMEM;
 419
 420         return 0;
 421 }
 422
 423 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 424 {
 425         dma_addr_t scratch_addr;
 426         u32 param;
 427         int ret;
 428
 429         if (!dwc->has_hibernation)
 430                 return 0;
 431
 432         if (!dwc->nr_scratch)
 433                 return 0;
 434
 435          /* should never fall here */
 436         if (!WARN_ON(dwc->scratchbuf))
 437                 return 0;
 438
 439         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 440                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 441                         DMA_BIDIRECTIONAL);
 442         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 443                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 444                 ret = -EFAULT;
 445                 goto err0;
 446         }
 447
 448         dwc->scratch_addr = scratch_addr;
 449
 450         param = lower_32_bits(scratch_addr);
 451
 452         ret = dwc3_send_gadget_generic_command(dwc,
 453                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 454         if (ret < 0)
 455                 goto err1;
 456
 457         param = upper_32_bits(scratch_addr);
 458
 459         ret = dwc3_send_gadget_generic_command(dwc,
 460                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 461         if (ret < 0)
 462                 goto err1;
 463
 464         return 0;
 465
 466 err1:
 467         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 468                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 469
 470 err0:
 471         return ret;
 472 }
 473
 474 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 475 {
 476         if (!dwc->has_hibernation)
 477                 return;
 478
 479         if (!dwc->nr_scratch)
 480                 return;
 481
 482          /* should never fall here */
 483         if (!WARN_ON(dwc->scratchbuf))
 484                 return;
 485
 486         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 487                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 488         kfree(dwc->scratchbuf);
 489 }
 490
 491 static void dwc3_core_num_eps(struct dwc3 *dwc)
 492 {
 493         struct dwc3_hwparams    *parms = &dwc->hwparams;
 494
 495         dwc->num_eps = DWC3_NUM_EPS(parms);
 496 }
 497
 498 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 499 {
 500         struct dwc3_hwparams    *parms = &dwc->hwparams;
 501
 502         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 503         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 504         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 505         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 506         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 507         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 508         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 509         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 510         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 511 }
 512
 513 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 514 {
 515         int intf;
 516         int ret = 0;
 517
 518         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 519
 520         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 521             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 522              dwc->hsphy_interface &&
 523              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 524                 ret = dwc3_ulpi_init(dwc);
 525
 526         return ret;
 527 }
 528
 529 /**
 530  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 531  * @dwc: Pointer to our controller context structure
 532  *
 533  * Returns 0 on success. The USB PHY interfaces are configured but not
 534  * initialized. The PHY interfaces and the PHYs get initialized together with
 535  * the core in dwc3_core_init.
 536  */
 537 static int dwc3_phy_setup(struct dwc3 *dwc)
 538 {
 539         u32 reg;
 540
 541         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 542
 543         /*
 544          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 545          * PHYs. Also, this bit is not supposed to be used in normal operation.
 546          */
 547         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 548
 549         /*
 550          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 551          * to '0' during coreConsultant configuration. So default value
 552          * will be '0' when the core is reset. Application needs to set it
 553          * to '1' after the core initialization is completed.
 554          */
 555         if (dwc->revision > DWC3_REVISION_194A)
 556                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 557
 558         if (dwc->u2ss_inp3_quirk)
 559                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 560
 561         if (dwc->dis_rxdet_inp3_quirk)
 562                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 563
 564         if (dwc->req_p1p2p3_quirk)
 565                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 566
 567         if (dwc->del_p1p2p3_quirk)
 568                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 569
 570         if (dwc->del_phy_power_chg_quirk)
 571                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 572
 573         if (dwc->lfps_filter_quirk)
 574                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 575
 576         if (dwc->rx_detect_poll_quirk)
 577                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 578
 579         if (dwc->tx_de_emphasis_quirk)
 580                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 581
 582         if (dwc->dis_u3_susphy_quirk)
 583                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 584
 585         if (dwc->dis_del_phy_power_chg_quirk)
 586                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 587
 588         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 589
 590         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 591
 592         /* Select the HS PHY interface */
 593         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 594         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 595                 if (dwc->hsphy_interface &&
 596                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 597                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 598                         break;
 599                 } else if (dwc->hsphy_interface &&
 600                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 601                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 602                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 603                 } else {
 604                         /* Relying on default value. */
 605                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 606                                 break;
 607                 }
 608                 /* FALLTHROUGH */
 609         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 610                 /* FALLTHROUGH */
 611         default:
 612                 break;
 613         }
 614
 615         switch (dwc->hsphy_mode) {
 616         case USBPHY_INTERFACE_MODE_UTMI:
 617                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 618                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 619                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 620                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 621                 break;
 622         case USBPHY_INTERFACE_MODE_UTMIW:
 623                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 624                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 625                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 626                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 627                 break;
 628         default:
 629                 break;
 630         }
 631
 632         /*
 633          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 634          * '0' during coreConsultant configuration. So default value will
 635          * be '0' when the core is reset. Application needs to set it to
 636          * '1' after the core initialization is completed.
 637          */
 638         if (dwc->revision > DWC3_REVISION_194A)
 639                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 640
 641         if (dwc->dis_u2_susphy_quirk)
 642                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 643
 644         if (dwc->dis_enblslpm_quirk)
 645                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 646
 647         if (dwc->dis_u2_freeclk_exists_quirk)
 648                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 649
 650         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 651
 652         return 0;
 653 }
 654
 655 static void dwc3_core_exit(struct dwc3 *dwc)
 656 {
 657         dwc3_event_buffers_cleanup(dwc);
 658
 659         usb_phy_shutdown(dwc->usb2_phy);
 660         usb_phy_shutdown(dwc->usb3_phy);
 661         phy_exit(dwc->usb2_generic_phy);
 662         phy_exit(dwc->usb3_generic_phy);
 663
 664         usb_phy_set_suspend(dwc->usb2_phy, 1);
 665         usb_phy_set_suspend(dwc->usb3_phy, 1);
 666         phy_power_off(dwc->usb2_generic_phy);
 667         phy_power_off(dwc->usb3_generic_phy);
 668 }
 669
 670 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 671 {
 672         u32 reg;
 673
 674         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 675
 676         /* This should read as U3 followed by revision number */
 677         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 678                 /* Detected DWC_usb3 IP */
 679                 dwc->revision = reg;
 680         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 681                 /* Detected DWC_usb31 IP */
 682                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 683                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 684         } else {
 685                 return false;
 686         }
 687
 688         return true;
 689 }
 690
 691 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 692 {
 693         u32 hwparams4 = dwc->hwparams.hwparams4;
 694         u32 reg;
 695
 696         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 697         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 698
 699         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 700         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 701                 /**
 702                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 703                  * issue which would cause xHCI compliance tests to fail.
 704                  *
 705                  * Because of that we cannot enable clock gating on such
 706                  * configurations.
 707                  *
 708                  * Refers to:
 709                  *
 710                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 711                  * SOF/ITP Mode Used
 712                  */
 713                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 714                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 715                                 (dwc->revision >= DWC3_REVISION_210A &&
 716                                 dwc->revision <= DWC3_REVISION_250A))
 717                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 718                 else
 719                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 720                 break;
 721         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 722                 /* enable hibernation here */
 723                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 724
 725                 /*
 726                  * REVISIT Enabling this bit so that host-mode hibernation
 727                  * will work. Device-mode hibernation is not yet implemented.
 728                  */
 729                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 730                 break;
 731         default:
 732                 /* nothing */
 733                 break;
 734         }
 735
 736         /* check if current dwc3 is on simulation board */
 737         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 738                 dev_info(dwc->dev, "Running with FPGA optmizations\n");
 739                 dwc->is_fpga = true;
 740         }
 741
 742         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 743                         "disable_scramble cannot be used on non-FPGA builds\n");
 744
 745         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 746                 reg |= DWC3_GCTL_DISSCRAMBLE;
 747         else
 748                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 749
 750         if (dwc->u2exit_lfps_quirk)
 751                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 752
 753         /*
 754          * WORKAROUND: DWC3 revisions <1.90a have a bug
 755          * where the device can fail to connect at SuperSpeed
 756          * and falls back to high-speed mode which causes
 757          * the device to enter a Connect/Disconnect loop
 758          */
 759         if (dwc->revision < DWC3_REVISION_190A)
 760                 reg |= DWC3_GCTL_U2RSTECN;
 761
 762         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 763 }
 764
 765 static int dwc3_core_get_phy(struct dwc3 *dwc);
 766 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 767
 768 /**
 769  * dwc3_core_init - Low-level initialization of DWC3 Core
 770  * @dwc: Pointer to our controller context structure
 771  *
 772  * Returns 0 on success otherwise negative errno.
 773  */
 774 static int dwc3_core_init(struct dwc3 *dwc)
 775 {
 776         u32                     reg;
 777         int                     ret;
 778
 779         if (!dwc3_core_is_valid(dwc)) {
 780                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 781                 ret = -ENODEV;
 782                 goto err0;
 783         }
 784
 785         /*
 786          * Write Linux Version Code to our GUID register so it's easy to figure
 787          * out which kernel version a bug was found.
 788          */
 789         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 790
 791         /* Handle USB2.0-only core configuration */
 792         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 793                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 794                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 795                         dwc->maximum_speed = USB_SPEED_HIGH;
 796         }
 797
 798         ret = dwc3_phy_setup(dwc);
 799         if (ret)
 800                 goto err0;
 801
 802         if (!dwc->ulpi_ready) {
 803                 ret = dwc3_core_ulpi_init(dwc);
 804                 if (ret)
 805                         goto err0;
 806                 dwc->ulpi_ready = true;
 807         }
 808
 809         if (!dwc->phys_ready) {
 810                 ret = dwc3_core_get_phy(dwc);
 811                 if (ret)
 812                         goto err0a;
 813                 dwc->phys_ready = true;
 814         }
 815
 816         ret = dwc3_core_soft_reset(dwc);
 817         if (ret)
 818                 goto err0a;
 819
 820         dwc3_core_setup_global_control(dwc);
 821         dwc3_core_num_eps(dwc);
 822
 823         ret = dwc3_setup_scratch_buffers(dwc);
 824         if (ret)
 825                 goto err1;
 826
 827         /* Adjust Frame Length */
 828         dwc3_frame_length_adjustment(dwc);
 829
 830         usb_phy_set_suspend(dwc->usb2_phy, 0);
 831         usb_phy_set_suspend(dwc->usb3_phy, 0);
 832         ret = phy_power_on(dwc->usb2_generic_phy);
 833         if (ret < 0)
 834                 goto err2;
 835
 836         ret = phy_power_on(dwc->usb3_generic_phy);
 837         if (ret < 0)
 838                 goto err3;
 839
 840         ret = dwc3_event_buffers_setup(dwc);
 841         if (ret) {
 842                 dev_err(dwc->dev, "failed to setup event buffers\n");
 843                 goto err4;
 844         }
 845
 846         /*
 847          * ENDXFER polling is available on version 3.10a and later of
 848          * the DWC_usb3 controller. It is NOT available in the
 849          * DWC_usb31 controller.
 850          */
 851         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 852                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 853                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 854                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 855         }
 856
 857         if (dwc->revision >= DWC3_REVISION_250A) {
 858                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 859
 860                 /*
 861                  * Enable hardware control of sending remote wakeup
 862                  * in HS when the device is in the L1 state.
 863                  */
 864                 if (dwc->revision >= DWC3_REVISION_290A)
 865                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 866
 867                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 868                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 869
 870                 if (dwc->parkmode_disable_ss_quirk)
 871                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
 872
 873                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 874         }
 875
 876         return 0;
 877
 878 err4:
 879         phy_power_off(dwc->usb3_generic_phy);
 880
 881 err3:
 882         phy_power_off(dwc->usb2_generic_phy);
 883
 884 err2:
 885         usb_phy_set_suspend(dwc->usb2_phy, 1);
 886         usb_phy_set_suspend(dwc->usb3_phy, 1);
 887
 888 err1:
 889         usb_phy_shutdown(dwc->usb2_phy);
 890         usb_phy_shutdown(dwc->usb3_phy);
 891         phy_exit(dwc->usb2_generic_phy);
 892         phy_exit(dwc->usb3_generic_phy);
 893
 894 err0a:
 895         dwc3_ulpi_exit(dwc);
 896
 897 err0:
 898         return ret;
 899 }
 900
 901 static int dwc3_core_get_phy(struct dwc3 *dwc)
 902 {
 903         struct device           *dev = dwc->dev;
 904         struct device_node      *node = dev->of_node;
 905         int ret;
 906
 907         if (node) {
 908                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 909                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 910         } else {
 911                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 912                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 913         }
 914
 915         if (IS_ERR(dwc->usb2_phy)) {
 916                 ret = PTR_ERR(dwc->usb2_phy);
 917                 if (ret == -ENXIO || ret == -ENODEV) {
 918                         dwc->usb2_phy = NULL;
 919                 } else if (ret == -EPROBE_DEFER) {
 920                         return ret;
 921                 } else {
 922                         dev_err(dev, "no usb2 phy configured\n");
 923                         return ret;
 924                 }
 925         }
 926
 927         if (IS_ERR(dwc->usb3_phy)) {
 928                 ret = PTR_ERR(dwc->usb3_phy);
 929                 if (ret == -ENXIO || ret == -ENODEV) {
 930                         dwc->usb3_phy = NULL;
 931                 } else if (ret == -EPROBE_DEFER) {
 932                         return ret;
 933                 } else {
 934                         dev_err(dev, "no usb3 phy configured\n");
 935                         return ret;
 936                 }
 937         }
 938
 939         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 940         if (IS_ERR(dwc->usb2_generic_phy)) {
 941                 ret = PTR_ERR(dwc->usb2_generic_phy);
 942                 if (ret == -ENOSYS || ret == -ENODEV) {
 943                         dwc->usb2_generic_phy = NULL;
 944                 } else if (ret == -EPROBE_DEFER) {
 945                         return ret;
 946                 } else {
 947                         dev_err(dev, "no usb2 phy configured\n");
 948                         return ret;
 949                 }
 950         }
 951
 952         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 953         if (IS_ERR(dwc->usb3_generic_phy)) {
 954                 ret = PTR_ERR(dwc->usb3_generic_phy);
 955                 if (ret == -ENOSYS || ret == -ENODEV) {
 956                         dwc->usb3_generic_phy = NULL;
 957                 } else if (ret == -EPROBE_DEFER) {
 958                         return ret;
 959                 } else {
 960                         dev_err(dev, "no usb3 phy configured\n");
 961                         return ret;
 962                 }
 963         }
 964
 965         return 0;
 966 }
 967
 968 static int dwc3_core_init_mode(struct dwc3 *dwc)
 969 {
 970         struct device *dev = dwc->dev;
 971         int ret;
 972
 973         switch (dwc->dr_mode) {
 974         case USB_DR_MODE_PERIPHERAL:
 975                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 976
 977                 if (dwc->usb2_phy)
 978                         otg_set_vbus(dwc->usb2_phy->otg, false);
 979                 if (dwc->usb2_generic_phy)
 980                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 981
 982                 ret = dwc3_gadget_init(dwc);
 983                 if (ret) {
 984                         if (ret != -EPROBE_DEFER)
 985                                 dev_err(dev, "failed to initialize gadget\n");
 986                         return ret;
 987                 }
 988                 break;
 989         case USB_DR_MODE_HOST:
 990                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
 991
 992                 if (dwc->usb2_phy)
 993                         otg_set_vbus(dwc->usb2_phy->otg, true);
 994                 if (dwc->usb2_generic_phy)
 995                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 996
 997                 ret = dwc3_host_init(dwc);
 998                 if (ret) {
 999                         if (ret != -EPROBE_DEFER)
1000                                 dev_err(dev, "failed to initialize host\n");
1001                         return ret;
1002                 }
1003                 break;
1004         case USB_DR_MODE_OTG:
1005                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1006                 ret = dwc3_drd_init(dwc);
1007                 if (ret) {
1008                         if (ret != -EPROBE_DEFER)
1009                                 dev_err(dev, "failed to initialize dual-role\n");
1010                         return ret;
1011                 }
1012                 break;
1013         default:
1014                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1015                 return -EINVAL;
1016         }
1017
1018         return 0;
1019 }
1020
1021 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1022 {
1023         switch (dwc->dr_mode) {
1024         case USB_DR_MODE_PERIPHERAL:
1025                 dwc3_gadget_exit(dwc);
1026                 break;
1027         case USB_DR_MODE_HOST:
1028                 dwc3_host_exit(dwc);
1029                 break;
1030         case USB_DR_MODE_OTG:
1031                 dwc3_drd_exit(dwc);
1032                 break;
1033         default:
1034                 /* do nothing */
1035                 break;
1036         }
1037
1038         /* de-assert DRVVBUS for HOST and OTG mode */
1039         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1040 }
1041
1042 static void dwc3_get_properties(struct dwc3 *dwc)
1043 {
1044         struct device           *dev = dwc->dev;
1045         u8                      lpm_nyet_threshold;
1046         u8                      tx_de_emphasis;
1047         u8                      hird_threshold;
1048
1049         /* default to highest possible threshold */
1050         lpm_nyet_threshold = 0xf;
1051
1052         /* default to -3.5dB de-emphasis */
1053         tx_de_emphasis = 1;
1054
1055         /*
1056          * default to assert utmi_sleep_n and use maximum allowed HIRD
1057          * threshold value of 0b1100
1058          */
1059         hird_threshold = 12;
1060
1061         dwc->maximum_speed = usb_get_maximum_speed(dev);
1062         dwc->dr_mode = usb_get_dr_mode(dev);
1063         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1064
1065         dwc->sysdev_is_parent = device_property_read_bool(dev,
1066                                 "linux,sysdev_is_parent");
1067         if (dwc->sysdev_is_parent)
1068                 dwc->sysdev = dwc->dev->parent;
1069         else
1070                 dwc->sysdev = dwc->dev;
1071
1072         dwc->has_lpm_erratum = device_property_read_bool(dev,
1073                                 "snps,has-lpm-erratum");
1074         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1075                                 &lpm_nyet_threshold);
1076         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1077                                 "snps,is-utmi-l1-suspend");
1078         device_property_read_u8(dev, "snps,hird-threshold",
1079                                 &hird_threshold);
1080         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1081                                 "snps,usb3_lpm_capable");
1082
1083         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1084                                 "snps,disable_scramble_quirk");
1085         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1086                                 "snps,u2exit_lfps_quirk");
1087         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1088                                 "snps,u2ss_inp3_quirk");
1089         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1090                                 "snps,req_p1p2p3_quirk");
1091         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1092                                 "snps,del_p1p2p3_quirk");
1093         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1094                                 "snps,del_phy_power_chg_quirk");
1095         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1096                                 "snps,lfps_filter_quirk");
1097         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1098                                 "snps,rx_detect_poll_quirk");
1099         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1100                                 "snps,dis_u3_susphy_quirk");
1101         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1102                                 "snps,dis_u2_susphy_quirk");
1103         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1104                                 "snps,dis_enblslpm_quirk");
1105         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1106                                 "snps,dis_rxdet_inp3_quirk");
1107         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1108                                 "snps,dis-u2-freeclk-exists-quirk");
1109         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1110                                 "snps,dis-del-phy-power-chg-quirk");
1111         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1112                                 "snps,dis-tx-ipgap-linecheck-quirk");
1113         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1114                                 "snps,parkmode-disable-ss-quirk");
1115
1116         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1117                                 "snps,tx_de_emphasis_quirk");
1118         device_property_read_u8(dev, "snps,tx_de_emphasis",
1119                                 &tx_de_emphasis);
1120         device_property_read_string(dev, "snps,hsphy_interface",
1121                                     &dwc->hsphy_interface);
1122         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1123                                  &dwc->fladj);
1124
1125         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1126                                 "snps,dis_metastability_quirk");
1127
1128         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1129         dwc->tx_de_emphasis = tx_de_emphasis;
1130
1131         dwc->hird_threshold = hird_threshold
1132                 | (dwc->is_utmi_l1_suspend << 4);
1133
1134         dwc->imod_interval = 0;
1135 }
1136
1137 /* check whether the core supports IMOD */
1138 bool dwc3_has_imod(struct dwc3 *dwc)
1139 {
1140         return ((dwc3_is_usb3(dwc) &&
1141                  dwc->revision >= DWC3_REVISION_300A) ||
1142                 (dwc3_is_usb31(dwc) &&
1143                  dwc->revision >= DWC3_USB31_REVISION_120A));
1144 }
1145
1146 static void dwc3_check_params(struct dwc3 *dwc)
1147 {
1148         struct device *dev = dwc->dev;
1149
1150         /* Check for proper value of imod_interval */
1151         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1152                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1153                 dwc->imod_interval = 0;
1154         }
1155
1156         /*
1157          * Workaround for STAR 9000961433 which affects only version
1158          * 3.00a of the DWC_usb3 core. This prevents the controller
1159          * interrupt from being masked while handling events. IMOD
1160          * allows us to work around this issue. Enable it for the
1161          * affected version.
1162          */
1163         if (!dwc->imod_interval &&
1164             (dwc->revision == DWC3_REVISION_300A))
1165                 dwc->imod_interval = 1;
1166
1167         /* Check the maximum_speed parameter */
1168         switch (dwc->maximum_speed) {
1169         case USB_SPEED_LOW:
1170         case USB_SPEED_FULL:
1171         case USB_SPEED_HIGH:
1172         case USB_SPEED_SUPER:
1173         case USB_SPEED_SUPER_PLUS:
1174                 break;
1175         default:
1176                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1177                         dwc->maximum_speed);
1178                 /* fall through */
1179         case USB_SPEED_UNKNOWN:
1180                 /* default to superspeed */
1181                 dwc->maximum_speed = USB_SPEED_SUPER;
1182
1183                 /*
1184                  * default to superspeed plus if we are capable.
1185                  */
1186                 if (dwc3_is_usb31(dwc) &&
1187                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1188                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1189                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1190
1191                 break;
1192         }
1193 }
1194
1195 static int dwc3_probe(struct platform_device *pdev)
1196 {
1197         struct device           *dev = &pdev->dev;
1198         struct resource         *res;
1199         struct dwc3             *dwc;
1200
1201         int                     ret;
1202
1203         void __iomem            *regs;
1204
1205         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1206         if (!dwc)
1207                 return -ENOMEM;
1208
1209         dwc->dev = dev;
1210
1211         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1212         if (!res) {
1213                 dev_err(dev, "missing memory resource\n");
1214                 return -ENODEV;
1215         }
1216
1217         dwc->xhci_resources[0].start = res->start;
1218         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1219                                         DWC3_XHCI_REGS_END;
1220         dwc->xhci_resources[0].flags = res->flags;
1221         dwc->xhci_resources[0].name = res->name;
1222
1223         res->start += DWC3_GLOBALS_REGS_START;
1224
1225         /*
1226          * Request memory region but exclude xHCI regs,
1227          * since it will be requested by the xhci-plat driver.
1228          */
1229         regs = devm_ioremap_resource(dev, res);
1230         if (IS_ERR(regs)) {
1231                 ret = PTR_ERR(regs);
1232                 goto err0;
1233         }
1234
1235         dwc->regs       = regs;
1236         dwc->regs_size  = resource_size(res);
1237
1238         dwc3_get_properties(dwc);
1239
1240         platform_set_drvdata(pdev, dwc);
1241         dwc3_cache_hwparams(dwc);
1242
1243         spin_lock_init(&dwc->lock);
1244
1245         pm_runtime_set_active(dev);
1246         pm_runtime_use_autosuspend(dev);
1247         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1248         pm_runtime_enable(dev);
1249         ret = pm_runtime_get_sync(dev);
1250         if (ret < 0)
1251                 goto err1;
1252
1253         pm_runtime_forbid(dev);
1254
1255         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1256         if (ret) {
1257                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1258                 ret = -ENOMEM;
1259                 goto err2;
1260         }
1261
1262         ret = dwc3_get_dr_mode(dwc);
1263         if (ret)
1264                 goto err3;
1265
1266         ret = dwc3_alloc_scratch_buffers(dwc);
1267         if (ret)
1268                 goto err3;
1269
1270         ret = dwc3_core_init(dwc);
1271         if (ret) {
1272                 if (ret != -EPROBE_DEFER)
1273                         dev_err(dev, "failed to initialize core: %d\n", ret);
1274                 goto err4;
1275         }
1276
1277         dwc3_check_params(dwc);
1278
1279         ret = dwc3_core_init_mode(dwc);
1280         if (ret)
1281                 goto err5;
1282
1283         dwc3_debugfs_init(dwc);
1284         pm_runtime_put(dev);
1285
1286         return 0;
1287
1288 err5:
1289         dwc3_event_buffers_cleanup(dwc);
1290
1291         usb_phy_shutdown(dwc->usb2_phy);
1292         usb_phy_shutdown(dwc->usb3_phy);
1293         phy_exit(dwc->usb2_generic_phy);
1294         phy_exit(dwc->usb3_generic_phy);
1295
1296         usb_phy_set_suspend(dwc->usb2_phy, 1);
1297         usb_phy_set_suspend(dwc->usb3_phy, 1);
1298         phy_power_off(dwc->usb2_generic_phy);
1299         phy_power_off(dwc->usb3_generic_phy);
1300
1301         dwc3_ulpi_exit(dwc);
1302
1303 err4:
1304         dwc3_free_scratch_buffers(dwc);
1305
1306 err3:
1307         dwc3_free_event_buffers(dwc);
1308
1309 err2:
1310         pm_runtime_allow(&pdev->dev);
1311
1312 err1:
1313         pm_runtime_put_sync(&pdev->dev);
1314         pm_runtime_disable(&pdev->dev);
1315
1316 err0:
1317         /*
1318          * restore res->start back to its original value so that, in case the
1319          * probe is deferred, we don't end up getting error in request the
1320          * memory region the next time probe is called.
1321          */
1322         res->start -= DWC3_GLOBALS_REGS_START;
1323
1324         return ret;
1325 }
1326
1327 static int dwc3_remove(struct platform_device *pdev)
1328 {
1329         struct dwc3     *dwc = platform_get_drvdata(pdev);
1330         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1331
1332         pm_runtime_get_sync(&pdev->dev);
1333         /*
1334          * restore res->start back to its original value so that, in case the
1335          * probe is deferred, we don't end up getting error in request the
1336          * memory region the next time probe is called.
1337          */
1338         res->start -= DWC3_GLOBALS_REGS_START;
1339
1340         dwc3_core_exit_mode(dwc);
1341         dwc3_debugfs_exit(dwc);
1342
1343         dwc3_core_exit(dwc);
1344         dwc3_ulpi_exit(dwc);
1345
1346         pm_runtime_disable(&pdev->dev);
1347         pm_runtime_put_noidle(&pdev->dev);
1348         pm_runtime_set_suspended(&pdev->dev);
1349
1350         dwc3_free_event_buffers(dwc);
1351         dwc3_free_scratch_buffers(dwc);
1352
1353         return 0;
1354 }
1355
1356 #ifdef CONFIG_PM
1357 static int dwc3_suspend_common(struct dwc3 *dwc)
1358 {
1359         unsigned long   flags;
1360
1361         switch (dwc->dr_mode) {
1362         case USB_DR_MODE_PERIPHERAL:
1363         case USB_DR_MODE_OTG:
1364                 spin_lock_irqsave(&dwc->lock, flags);
1365                 dwc3_gadget_suspend(dwc);
1366                 spin_unlock_irqrestore(&dwc->lock, flags);
1367                 break;
1368         case USB_DR_MODE_HOST:
1369         default:
1370                 /* do nothing */
1371                 break;
1372         }
1373
1374         dwc3_core_exit(dwc);
1375
1376         return 0;
1377 }
1378
1379 static int dwc3_resume_common(struct dwc3 *dwc)
1380 {
1381         unsigned long   flags;
1382         int             ret;
1383
1384         ret = dwc3_core_init(dwc);
1385         if (ret)
1386                 return ret;
1387
1388         switch (dwc->dr_mode) {
1389         case USB_DR_MODE_PERIPHERAL:
1390         case USB_DR_MODE_OTG:
1391                 spin_lock_irqsave(&dwc->lock, flags);
1392                 dwc3_gadget_resume(dwc);
1393                 spin_unlock_irqrestore(&dwc->lock, flags);
1394                 /* FALLTHROUGH */
1395         case USB_DR_MODE_HOST:
1396         default:
1397                 /* do nothing */
1398                 break;
1399         }
1400
1401         return 0;
1402 }
1403
1404 static int dwc3_runtime_checks(struct dwc3 *dwc)
1405 {
1406         switch (dwc->dr_mode) {
1407         case USB_DR_MODE_PERIPHERAL:
1408         case USB_DR_MODE_OTG:
1409                 if (dwc->connected)
1410                         return -EBUSY;
1411                 break;
1412         case USB_DR_MODE_HOST:
1413         default:
1414                 /* do nothing */
1415                 break;
1416         }
1417
1418         return 0;
1419 }
1420
1421 static int dwc3_runtime_suspend(struct device *dev)
1422 {
1423         struct dwc3     *dwc = dev_get_drvdata(dev);
1424         int             ret;
1425
1426         if (dwc3_runtime_checks(dwc))
1427                 return -EBUSY;
1428
1429         ret = dwc3_suspend_common(dwc);
1430         if (ret)
1431                 return ret;
1432
1433         device_init_wakeup(dev, true);
1434
1435         return 0;
1436 }
1437
1438 static int dwc3_runtime_resume(struct device *dev)
1439 {
1440         struct dwc3     *dwc = dev_get_drvdata(dev);
1441         int             ret;
1442
1443         device_init_wakeup(dev, false);
1444
1445         ret = dwc3_resume_common(dwc);
1446         if (ret)
1447                 return ret;
1448
1449         switch (dwc->dr_mode) {
1450         case USB_DR_MODE_PERIPHERAL:
1451         case USB_DR_MODE_OTG:
1452                 dwc3_gadget_process_pending_events(dwc);
1453                 break;
1454         case USB_DR_MODE_HOST:
1455         default:
1456                 /* do nothing */
1457                 break;
1458         }
1459
1460         pm_runtime_mark_last_busy(dev);
1461         pm_runtime_put(dev);
1462
1463         return 0;
1464 }
1465
1466 static int dwc3_runtime_idle(struct device *dev)
1467 {
1468         struct dwc3     *dwc = dev_get_drvdata(dev);
1469
1470         switch (dwc->dr_mode) {
1471         case USB_DR_MODE_PERIPHERAL:
1472         case USB_DR_MODE_OTG:
1473                 if (dwc3_runtime_checks(dwc))
1474                         return -EBUSY;
1475                 break;
1476         case USB_DR_MODE_HOST:
1477         default:
1478                 /* do nothing */
1479                 break;
1480         }
1481
1482         pm_runtime_mark_last_busy(dev);
1483         pm_runtime_autosuspend(dev);
1484
1485         return 0;
1486 }
1487 #endif /* CONFIG_PM */
1488
1489 #ifdef CONFIG_PM_SLEEP
1490 static int dwc3_suspend(struct device *dev)
1491 {
1492         struct dwc3     *dwc = dev_get_drvdata(dev);
1493         int             ret;
1494
1495         ret = dwc3_suspend_common(dwc);
1496         if (ret)
1497                 return ret;
1498
1499         pinctrl_pm_select_sleep_state(dev);
1500
1501         return 0;
1502 }
1503
1504 static int dwc3_resume(struct device *dev)
1505 {
1506         struct dwc3     *dwc = dev_get_drvdata(dev);
1507         int             ret;
1508
1509         pinctrl_pm_select_default_state(dev);
1510
1511         ret = dwc3_resume_common(dwc);
1512         if (ret)
1513                 return ret;
1514
1515         pm_runtime_disable(dev);
1516         pm_runtime_set_active(dev);
1517         pm_runtime_enable(dev);
1518
1519         return 0;
1520 }
1521 #endif /* CONFIG_PM_SLEEP */
1522
1523 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1524         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1525         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1526                         dwc3_runtime_idle)
1527 };
1528
1529 #ifdef CONFIG_OF
1530 static const struct of_device_id of_dwc3_match[] = {
1531         {
1532                 .compatible = "snps,dwc3"
1533         },
1534         {
1535                 .compatible = "synopsys,dwc3"
1536         },
1537         { },
1538 };
1539 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1540 #endif
1541
1542 #ifdef CONFIG_ACPI
1543
1544 #define ACPI_ID_INTEL_BSW       "808622B7"
1545
1546 static const struct acpi_device_id dwc3_acpi_match[] = {
1547         { ACPI_ID_INTEL_BSW, 0 },
1548         { },
1549 };
1550 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1551 #endif
1552
1553 static struct platform_driver dwc3_driver = {
1554         .probe          = dwc3_probe,
1555         .remove         = dwc3_remove,
1556         .driver         = {
1557                 .name   = "dwc3",
1558                 .of_match_table = of_match_ptr(of_dwc3_match),
1559                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1560                 .pm     = &dwc3_dev_pm_ops,
1561         },
1562 };
1563
1564 module_platform_driver(dwc3_driver);
1565
1566 MODULE_ALIAS("platform:dwc3");
1567 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1568 MODULE_LICENSE("GPL v2");
1569 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");