drivers/usb/dwc3/core.c

   1 /**
   2  * core.c - DesignWare USB3 DRD Controller Core file
   3  *
   4  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   5  *
   6  * Authors: Felipe Balbi <balbi@ti.com>,
   7  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   8  *
   9  * This program is free software: you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2  of
  11  * the License as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <linux/version.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/interrupt.h>
  30 #include <linux/ioport.h>
  31 #include <linux/io.h>
  32 #include <linux/list.h>
  33 #include <linux/delay.h>
  34 #include <linux/dma-mapping.h>
  35 #include <linux/of.h>
  36 #include <linux/acpi.h>
  37 #include <linux/pinctrl/consumer.h>
  38
  39 #include <linux/usb/ch9.h>
  40 #include <linux/usb/gadget.h>
  41 #include <linux/usb/of.h>
  42 #include <linux/usb/otg.h>
  43
  44 #include "core.h"
  45 #include "gadget.h"
  46 #include "io.h"
  47
  48 #include "debug.h"
  49
  50 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  51
  52 /**
  53  * dwc3_get_dr_mode - Validates and sets dr_mode
  54  * @dwc: pointer to our context structure
  55  */
  56 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  57 {
  58         enum usb_dr_mode mode;
  59         struct device *dev = dwc->dev;
  60         unsigned int hw_mode;
  61
  62         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  63                 dwc->dr_mode = USB_DR_MODE_OTG;
  64
  65         mode = dwc->dr_mode;
  66         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  67
  68         switch (hw_mode) {
  69         case DWC3_GHWPARAMS0_MODE_GADGET:
  70                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  71                         dev_err(dev,
  72                                 "Controller does not support host mode.\n");
  73                         return -EINVAL;
  74                 }
  75                 mode = USB_DR_MODE_PERIPHERAL;
  76                 break;
  77         case DWC3_GHWPARAMS0_MODE_HOST:
  78                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  79                         dev_err(dev,
  80                                 "Controller does not support device mode.\n");
  81                         return -EINVAL;
  82                 }
  83                 mode = USB_DR_MODE_HOST;
  84                 break;
  85         default:
  86                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  87                         mode = USB_DR_MODE_HOST;
  88                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111 }
 112
 113 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 114 {
 115         struct dwc3             *dwc = dep->dwc;
 116         u32                     reg;
 117
 118         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 119                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 120                         DWC3_GDBGFIFOSPACE_TYPE(type));
 121
 122         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 123
 124         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 125 }
 126
 127 /**
 128  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 129  * @dwc: pointer to our context structure
 130  */
 131 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 132 {
 133         u32             reg;
 134         int             retries = 1000;
 135         int             ret;
 136
 137         usb_phy_init(dwc->usb2_phy);
 138         usb_phy_init(dwc->usb3_phy);
 139         ret = phy_init(dwc->usb2_generic_phy);
 140         if (ret < 0)
 141                 return ret;
 142
 143         ret = phy_init(dwc->usb3_generic_phy);
 144         if (ret < 0) {
 145                 phy_exit(dwc->usb2_generic_phy);
 146                 return ret;
 147         }
 148
 149         /*
 150          * We're resetting only the device side because, if we're in host mode,
 151          * XHCI driver will reset the host block. If dwc3 was configured for
 152          * host-only mode, then we can return early.
 153          */
 154         if (dwc->dr_mode == USB_DR_MODE_HOST)
 155                 return 0;
 156
 157         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 158         reg |= DWC3_DCTL_CSFTRST;
 159         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 160
 161         do {
 162                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 163                 if (!(reg & DWC3_DCTL_CSFTRST))
 164                         goto done;
 165
 166                 udelay(1);
 167         } while (--retries);
 168
 169         phy_exit(dwc->usb3_generic_phy);
 170         phy_exit(dwc->usb2_generic_phy);
 171
 172         return -ETIMEDOUT;
 173
 174 done:
 175         /*
 176          * For DWC_usb31 controller, once DWC3_DCTL_CSFTRST bit is cleared,
 177          * we must wait at least 50ms before accessing the PHY domain
 178          * (synchronization delay). DWC_usb31 programming guide section 1.3.2.
 179          */
 180         if (dwc3_is_usb31(dwc))
 181                 msleep(50);
 182
 183         return 0;
 184 }
 185
 186 /**
 187  * dwc3_soft_reset - Issue soft reset
 188  * @dwc: Pointer to our controller context structure
 189  */
 190 static int dwc3_soft_reset(struct dwc3 *dwc)
 191 {
 192         unsigned long timeout;
 193         u32 reg;
 194
 195         timeout = jiffies + msecs_to_jiffies(500);
 196         dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
 197         do {
 198                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 199                 if (!(reg & DWC3_DCTL_CSFTRST))
 200                         break;
 201
 202                 if (time_after(jiffies, timeout)) {
 203                         dev_err(dwc->dev, "Reset Timed Out\n");
 204                         return -ETIMEDOUT;
 205                 }
 206
 207                 cpu_relax();
 208         } while (true);
 209
 210         return 0;
 211 }
 212
 213 /*
 214  * dwc3_frame_length_adjustment - Adjusts frame length if required
 215  * @dwc3: Pointer to our controller context structure
 216  */
 217 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 218 {
 219         u32 reg;
 220         u32 dft;
 221
 222         if (dwc->revision < DWC3_REVISION_250A)
 223                 return;
 224
 225         if (dwc->fladj == 0)
 226                 return;
 227
 228         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 229         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 230         if (dft != dwc->fladj) {
 231                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 232                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 233                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 234         }
 235 }
 236
 237 /**
 238  * dwc3_free_one_event_buffer - Frees one event buffer
 239  * @dwc: Pointer to our controller context structure
 240  * @evt: Pointer to event buffer to be freed
 241  */
 242 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 243                 struct dwc3_event_buffer *evt)
 244 {
 245         dma_free_coherent(dwc->dev, evt->length, evt->buf, evt->dma);
 246 }
 247
 248 /**
 249  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 250  * @dwc: Pointer to our controller context structure
 251  * @length: size of the event buffer
 252  *
 253  * Returns a pointer to the allocated event buffer structure on success
 254  * otherwise ERR_PTR(errno).
 255  */
 256 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 257                 unsigned length)
 258 {
 259         struct dwc3_event_buffer        *evt;
 260
 261         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 262         if (!evt)
 263                 return ERR_PTR(-ENOMEM);
 264
 265         evt->dwc        = dwc;
 266         evt->length     = length;
 267         evt->buf        = dma_alloc_coherent(dwc->dev, length,
 268                         &evt->dma, GFP_KERNEL);
 269         if (!evt->buf)
 270                 return ERR_PTR(-ENOMEM);
 271
 272         return evt;
 273 }
 274
 275 /**
 276  * dwc3_free_event_buffers - frees all allocated event buffers
 277  * @dwc: Pointer to our controller context structure
 278  */
 279 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 280 {
 281         struct dwc3_event_buffer        *evt;
 282
 283         evt = dwc->ev_buf;
 284         if (evt)
 285                 dwc3_free_one_event_buffer(dwc, evt);
 286 }
 287
 288 /**
 289  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 290  * @dwc: pointer to our controller context structure
 291  * @length: size of event buffer
 292  *
 293  * Returns 0 on success otherwise negative errno. In the error case, dwc
 294  * may contain some buffers allocated but not all which were requested.
 295  */
 296 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 297 {
 298         struct dwc3_event_buffer *evt;
 299
 300         evt = dwc3_alloc_one_event_buffer(dwc, length);
 301         if (IS_ERR(evt)) {
 302                 dev_err(dwc->dev, "can't allocate event buffer\n");
 303                 return PTR_ERR(evt);
 304         }
 305         dwc->ev_buf = evt;
 306
 307         return 0;
 308 }
 309
 310 /**
 311  * dwc3_event_buffers_setup - setup our allocated event buffers
 312  * @dwc: pointer to our controller context structure
 313  *
 314  * Returns 0 on success otherwise negative errno.
 315  */
 316 static int dwc3_event_buffers_setup(struct dwc3 *dwc)
 317 {
 318         struct dwc3_event_buffer        *evt;
 319
 320         evt = dwc->ev_buf;
 321         dwc3_trace(trace_dwc3_core,
 322                         "Event buf %p dma %08llx length %d\n",
 323                         evt->buf, (unsigned long long) evt->dma,
 324                         evt->length);
 325
 326         evt->lpos = 0;
 327
 328         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 329                         lower_32_bits(evt->dma));
 330         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 331                         upper_32_bits(evt->dma));
 332         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 333                         DWC3_GEVNTSIZ_SIZE(evt->length));
 334         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 335
 336         return 0;
 337 }
 338
 339 static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 340 {
 341         struct dwc3_event_buffer        *evt;
 342
 343         evt = dwc->ev_buf;
 344
 345         evt->lpos = 0;
 346
 347         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 348         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 349         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 350                         | DWC3_GEVNTSIZ_SIZE(0));
 351         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 352 }
 353
 354 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 355 {
 356         if (!dwc->has_hibernation)
 357                 return 0;
 358
 359         if (!dwc->nr_scratch)
 360                 return 0;
 361
 362         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 363                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 364         if (!dwc->scratchbuf)
 365                 return -ENOMEM;
 366
 367         return 0;
 368 }
 369
 370 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 371 {
 372         dma_addr_t scratch_addr;
 373         u32 param;
 374         int ret;
 375
 376         if (!dwc->has_hibernation)
 377                 return 0;
 378
 379         if (!dwc->nr_scratch)
 380                 return 0;
 381
 382          /* should never fall here */
 383         if (!WARN_ON(dwc->scratchbuf))
 384                 return 0;
 385
 386         scratch_addr = dma_map_single(dwc->dev, dwc->scratchbuf,
 387                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 388                         DMA_BIDIRECTIONAL);
 389         if (dma_mapping_error(dwc->dev, scratch_addr)) {
 390                 dev_err(dwc->dev, "failed to map scratch buffer\n");
 391                 ret = -EFAULT;
 392                 goto err0;
 393         }
 394
 395         dwc->scratch_addr = scratch_addr;
 396
 397         param = lower_32_bits(scratch_addr);
 398
 399         ret = dwc3_send_gadget_generic_command(dwc,
 400                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 401         if (ret < 0)
 402                 goto err1;
 403
 404         param = upper_32_bits(scratch_addr);
 405
 406         ret = dwc3_send_gadget_generic_command(dwc,
 407                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 408         if (ret < 0)
 409                 goto err1;
 410
 411         return 0;
 412
 413 err1:
 414         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 415                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 416
 417 err0:
 418         return ret;
 419 }
 420
 421 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 422 {
 423         if (!dwc->has_hibernation)
 424                 return;
 425
 426         if (!dwc->nr_scratch)
 427                 return;
 428
 429          /* should never fall here */
 430         if (!WARN_ON(dwc->scratchbuf))
 431                 return;
 432
 433         dma_unmap_single(dwc->dev, dwc->scratch_addr, dwc->nr_scratch *
 434                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 435         kfree(dwc->scratchbuf);
 436 }
 437
 438 static void dwc3_core_num_eps(struct dwc3 *dwc)
 439 {
 440         struct dwc3_hwparams    *parms = &dwc->hwparams;
 441
 442         dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
 443         dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
 444
 445         dwc3_trace(trace_dwc3_core, "found %d IN and %d OUT endpoints",
 446                         dwc->num_in_eps, dwc->num_out_eps);
 447 }
 448
 449 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 450 {
 451         struct dwc3_hwparams    *parms = &dwc->hwparams;
 452
 453         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 454         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 455         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 456         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 457         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 458         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 459         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 460         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 461         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 462 }
 463
 464 /**
 465  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 466  * @dwc: Pointer to our controller context structure
 467  *
 468  * Returns 0 on success. The USB PHY interfaces are configured but not
 469  * initialized. The PHY interfaces and the PHYs get initialized together with
 470  * the core in dwc3_core_init.
 471  */
 472 static int dwc3_phy_setup(struct dwc3 *dwc)
 473 {
 474         u32 reg;
 475         int ret;
 476
 477         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 478
 479         /*
 480          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 481          * PHYs. Also, this bit is not supposed to be used in normal operation.
 482          */
 483         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 484
 485         /*
 486          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 487          * to '0' during coreConsultant configuration. So default value
 488          * will be '0' when the core is reset. Application needs to set it
 489          * to '1' after the core initialization is completed.
 490          */
 491         if (dwc->revision > DWC3_REVISION_194A)
 492                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 493
 494         if (dwc->u2ss_inp3_quirk)
 495                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 496
 497         if (dwc->dis_rxdet_inp3_quirk)
 498                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 499
 500         if (dwc->req_p1p2p3_quirk)
 501                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 502
 503         if (dwc->del_p1p2p3_quirk)
 504                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 505
 506         if (dwc->del_phy_power_chg_quirk)
 507                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 508
 509         if (dwc->lfps_filter_quirk)
 510                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 511
 512         if (dwc->rx_detect_poll_quirk)
 513                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 514
 515         if (dwc->tx_de_emphasis_quirk)
 516                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 517
 518         if (dwc->dis_u3_susphy_quirk)
 519                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 520
 521         if (dwc->dis_del_phy_power_chg_quirk)
 522                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 523
 524         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 525
 526         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 527
 528         /* Select the HS PHY interface */
 529         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 530         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 531                 if (dwc->hsphy_interface &&
 532                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 533                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 534                         break;
 535                 } else if (dwc->hsphy_interface &&
 536                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 537                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 538                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 539                 } else {
 540                         /* Relying on default value. */
 541                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 542                                 break;
 543                 }
 544                 /* FALLTHROUGH */
 545         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 546                 /* Making sure the interface and PHY are operational */
 547                 ret = dwc3_soft_reset(dwc);
 548                 if (ret)
 549                         return ret;
 550
 551                 udelay(1);
 552
 553                 ret = dwc3_ulpi_init(dwc);
 554                 if (ret)
 555                         return ret;
 556                 /* FALLTHROUGH */
 557         default:
 558                 break;
 559         }
 560
 561         switch (dwc->hsphy_mode) {
 562         case USBPHY_INTERFACE_MODE_UTMI:
 563                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 564                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 565                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 566                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 567                 break;
 568         case USBPHY_INTERFACE_MODE_UTMIW:
 569                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 570                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 571                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 572                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 573                 break;
 574         default:
 575                 break;
 576         }
 577
 578         /*
 579          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 580          * '0' during coreConsultant configuration. So default value will
 581          * be '0' when the core is reset. Application needs to set it to
 582          * '1' after the core initialization is completed.
 583          */
 584         if (dwc->revision > DWC3_REVISION_194A)
 585                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 586
 587         if (dwc->dis_u2_susphy_quirk)
 588                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 589
 590         if (dwc->dis_enblslpm_quirk)
 591                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 592
 593         if (dwc->dis_u2_freeclk_exists_quirk)
 594                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 595
 596         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 597
 598         return 0;
 599 }
 600
 601 static void dwc3_core_exit(struct dwc3 *dwc)
 602 {
 603         dwc3_event_buffers_cleanup(dwc);
 604
 605         usb_phy_shutdown(dwc->usb2_phy);
 606         usb_phy_shutdown(dwc->usb3_phy);
 607         phy_exit(dwc->usb2_generic_phy);
 608         phy_exit(dwc->usb3_generic_phy);
 609
 610         usb_phy_set_suspend(dwc->usb2_phy, 1);
 611         usb_phy_set_suspend(dwc->usb3_phy, 1);
 612         phy_power_off(dwc->usb2_generic_phy);
 613         phy_power_off(dwc->usb3_generic_phy);
 614 }
 615
 616 /**
 617  * dwc3_core_init - Low-level initialization of DWC3 Core
 618  * @dwc: Pointer to our controller context structure
 619  *
 620  * Returns 0 on success otherwise negative errno.
 621  */
 622 static int dwc3_core_init(struct dwc3 *dwc)
 623 {
 624         u32                     hwparams4 = dwc->hwparams.hwparams4;
 625         u32                     reg;
 626         int                     ret;
 627
 628         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 629         /* This should read as U3 followed by revision number */
 630         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 631                 /* Detected DWC_usb3 IP */
 632                 dwc->revision = reg;
 633         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 634                 /* Detected DWC_usb31 IP */
 635                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 636                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 637         } else {
 638                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
 639                 ret = -ENODEV;
 640                 goto err0;
 641         }
 642
 643         /*
 644          * Write Linux Version Code to our GUID register so it's easy to figure
 645          * out which kernel version a bug was found.
 646          */
 647         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 648
 649         /* Handle USB2.0-only core configuration */
 650         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 651                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 652                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 653                         dwc->maximum_speed = USB_SPEED_HIGH;
 654         }
 655
 656         /* issue device SoftReset too */
 657         ret = dwc3_soft_reset(dwc);
 658         if (ret)
 659                 goto err0;
 660
 661         ret = dwc3_core_soft_reset(dwc);
 662         if (ret)
 663                 goto err0;
 664
 665         ret = dwc3_phy_setup(dwc);
 666         if (ret)
 667                 goto err0;
 668
 669         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 670         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 671
 672         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 673         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 674                 /**
 675                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 676                  * issue which would cause xHCI compliance tests to fail.
 677                  *
 678                  * Because of that we cannot enable clock gating on such
 679                  * configurations.
 680                  *
 681                  * Refers to:
 682                  *
 683                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 684                  * SOF/ITP Mode Used
 685                  */
 686                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 687                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 688                                 (dwc->revision >= DWC3_REVISION_210A &&
 689                                 dwc->revision <= DWC3_REVISION_250A))
 690                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 691                 else
 692                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 693                 break;
 694         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 695                 /* enable hibernation here */
 696                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 697
 698                 /*
 699                  * REVISIT Enabling this bit so that host-mode hibernation
 700                  * will work. Device-mode hibernation is not yet implemented.
 701                  */
 702                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 703                 break;
 704         default:
 705                 dwc3_trace(trace_dwc3_core, "No power optimization available\n");
 706         }
 707
 708         /* check if current dwc3 is on simulation board */
 709         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 710                 dwc3_trace(trace_dwc3_core,
 711                                 "running on FPGA platform\n");
 712                 dwc->is_fpga = true;
 713         }
 714
 715         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 716                         "disable_scramble cannot be used on non-FPGA builds\n");
 717
 718         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 719                 reg |= DWC3_GCTL_DISSCRAMBLE;
 720         else
 721                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 722
 723         if (dwc->u2exit_lfps_quirk)
 724                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 725
 726         /*
 727          * WORKAROUND: DWC3 revisions <1.90a have a bug
 728          * where the device can fail to connect at SuperSpeed
 729          * and falls back to high-speed mode which causes
 730          * the device to enter a Connect/Disconnect loop
 731          */
 732         if (dwc->revision < DWC3_REVISION_190A)
 733                 reg |= DWC3_GCTL_U2RSTECN;
 734
 735         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 736
 737         dwc3_core_num_eps(dwc);
 738
 739         ret = dwc3_setup_scratch_buffers(dwc);
 740         if (ret)
 741                 goto err1;
 742
 743         /* Adjust Frame Length */
 744         dwc3_frame_length_adjustment(dwc);
 745
 746         usb_phy_set_suspend(dwc->usb2_phy, 0);
 747         usb_phy_set_suspend(dwc->usb3_phy, 0);
 748         ret = phy_power_on(dwc->usb2_generic_phy);
 749         if (ret < 0)
 750                 goto err2;
 751
 752         ret = phy_power_on(dwc->usb3_generic_phy);
 753         if (ret < 0)
 754                 goto err3;
 755
 756         ret = dwc3_event_buffers_setup(dwc);
 757         if (ret) {
 758                 dev_err(dwc->dev, "failed to setup event buffers\n");
 759                 goto err4;
 760         }
 761
 762         switch (dwc->dr_mode) {
 763         case USB_DR_MODE_PERIPHERAL:
 764                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 765                 break;
 766         case USB_DR_MODE_HOST:
 767                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
 768                 break;
 769         case USB_DR_MODE_OTG:
 770                 dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
 771                 break;
 772         default:
 773                 dev_warn(dwc->dev, "Unsupported mode %d\n", dwc->dr_mode);
 774                 break;
 775         }
 776
 777         /*
 778          * ENDXFER polling is available on version 3.10a and later of
 779          * the DWC_usb3 controller. It is NOT available in the
 780          * DWC_usb31 controller.
 781          */
 782         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 783                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 784                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 785                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 786         }
 787
 788         return 0;
 789
 790 err4:
 791         phy_power_off(dwc->usb3_generic_phy);
 792
 793 err3:
 794         phy_power_off(dwc->usb2_generic_phy);
 795
 796 err2:
 797         usb_phy_set_suspend(dwc->usb2_phy, 1);
 798         usb_phy_set_suspend(dwc->usb3_phy, 1);
 799
 800 err1:
 801         usb_phy_shutdown(dwc->usb2_phy);
 802         usb_phy_shutdown(dwc->usb3_phy);
 803         phy_exit(dwc->usb2_generic_phy);
 804         phy_exit(dwc->usb3_generic_phy);
 805
 806 err0:
 807         return ret;
 808 }
 809
 810 static int dwc3_core_get_phy(struct dwc3 *dwc)
 811 {
 812         struct device           *dev = dwc->dev;
 813         struct device_node      *node = dev->of_node;
 814         int ret;
 815
 816         if (node) {
 817                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
 818                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
 819         } else {
 820                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
 821                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
 822         }
 823
 824         if (IS_ERR(dwc->usb2_phy)) {
 825                 ret = PTR_ERR(dwc->usb2_phy);
 826                 if (ret == -ENXIO || ret == -ENODEV) {
 827                         dwc->usb2_phy = NULL;
 828                 } else if (ret == -EPROBE_DEFER) {
 829                         return ret;
 830                 } else {
 831                         dev_err(dev, "no usb2 phy configured\n");
 832                         return ret;
 833                 }
 834         }
 835
 836         if (IS_ERR(dwc->usb3_phy)) {
 837                 ret = PTR_ERR(dwc->usb3_phy);
 838                 if (ret == -ENXIO || ret == -ENODEV) {
 839                         dwc->usb3_phy = NULL;
 840                 } else if (ret == -EPROBE_DEFER) {
 841                         return ret;
 842                 } else {
 843                         dev_err(dev, "no usb3 phy configured\n");
 844                         return ret;
 845                 }
 846         }
 847
 848         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
 849         if (IS_ERR(dwc->usb2_generic_phy)) {
 850                 ret = PTR_ERR(dwc->usb2_generic_phy);
 851                 if (ret == -ENOSYS || ret == -ENODEV) {
 852                         dwc->usb2_generic_phy = NULL;
 853                 } else if (ret == -EPROBE_DEFER) {
 854                         return ret;
 855                 } else {
 856                         dev_err(dev, "no usb2 phy configured\n");
 857                         return ret;
 858                 }
 859         }
 860
 861         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
 862         if (IS_ERR(dwc->usb3_generic_phy)) {
 863                 ret = PTR_ERR(dwc->usb3_generic_phy);
 864                 if (ret == -ENOSYS || ret == -ENODEV) {
 865                         dwc->usb3_generic_phy = NULL;
 866                 } else if (ret == -EPROBE_DEFER) {
 867                         return ret;
 868                 } else {
 869                         dev_err(dev, "no usb3 phy configured\n");
 870                         return ret;
 871                 }
 872         }
 873
 874         return 0;
 875 }
 876
 877 static int dwc3_core_init_mode(struct dwc3 *dwc)
 878 {
 879         struct device *dev = dwc->dev;
 880         int ret;
 881
 882         switch (dwc->dr_mode) {
 883         case USB_DR_MODE_PERIPHERAL:
 884                 ret = dwc3_gadget_init(dwc);
 885                 if (ret) {
 886                         if (ret != -EPROBE_DEFER)
 887                                 dev_err(dev, "failed to initialize gadget\n");
 888                         return ret;
 889                 }
 890                 break;
 891         case USB_DR_MODE_HOST:
 892                 ret = dwc3_host_init(dwc);
 893                 if (ret) {
 894                         if (ret != -EPROBE_DEFER)
 895                                 dev_err(dev, "failed to initialize host\n");
 896                         return ret;
 897                 }
 898                 break;
 899         case USB_DR_MODE_OTG:
 900                 ret = dwc3_host_init(dwc);
 901                 if (ret) {
 902                         if (ret != -EPROBE_DEFER)
 903                                 dev_err(dev, "failed to initialize host\n");
 904                         return ret;
 905                 }
 906
 907                 ret = dwc3_gadget_init(dwc);
 908                 if (ret) {
 909                         if (ret != -EPROBE_DEFER)
 910                                 dev_err(dev, "failed to initialize gadget\n");
 911                         return ret;
 912                 }
 913                 break;
 914         default:
 915                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
 916                 return -EINVAL;
 917         }
 918
 919         return 0;
 920 }
 921
 922 static void dwc3_core_exit_mode(struct dwc3 *dwc)
 923 {
 924         switch (dwc->dr_mode) {
 925         case USB_DR_MODE_PERIPHERAL:
 926                 dwc3_gadget_exit(dwc);
 927                 break;
 928         case USB_DR_MODE_HOST:
 929                 dwc3_host_exit(dwc);
 930                 break;
 931         case USB_DR_MODE_OTG:
 932                 dwc3_host_exit(dwc);
 933                 dwc3_gadget_exit(dwc);
 934                 break;
 935         default:
 936                 /* do nothing */
 937                 break;
 938         }
 939
 940         /* de-assert DRVVBUS for HOST and OTG mode */
 941         dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
 942 }
 943
 944 #define DWC3_ALIGN_MASK         (16 - 1)
 945
 946 static int dwc3_probe(struct platform_device *pdev)
 947 {
 948         struct device           *dev = &pdev->dev;
 949         struct resource         *res;
 950         struct dwc3             *dwc;
 951         u8                      lpm_nyet_threshold;
 952         u8                      tx_de_emphasis;
 953         u8                      hird_threshold;
 954
 955         int                     ret;
 956
 957         void __iomem            *regs;
 958         void                    *mem;
 959
 960         mem = devm_kzalloc(dev, sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
 961         if (!mem)
 962                 return -ENOMEM;
 963
 964         dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
 965         dwc->mem = mem;
 966         dwc->dev = dev;
 967
 968         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 969         if (!res) {
 970                 dev_err(dev, "missing memory resource\n");
 971                 return -ENODEV;
 972         }
 973
 974         dwc->xhci_resources[0].start = res->start;
 975         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
 976                                         DWC3_XHCI_REGS_END;
 977         dwc->xhci_resources[0].flags = res->flags;
 978         dwc->xhci_resources[0].name = res->name;
 979
 980         res->start += DWC3_GLOBALS_REGS_START;
 981
 982         /*
 983          * Request memory region but exclude xHCI regs,
 984          * since it will be requested by the xhci-plat driver.
 985          */
 986         regs = devm_ioremap_resource(dev, res);
 987         if (IS_ERR(regs)) {
 988                 ret = PTR_ERR(regs);
 989                 goto err0;
 990         }
 991
 992         dwc->regs       = regs;
 993         dwc->regs_size  = resource_size(res);
 994
 995         /* default to highest possible threshold */
 996         lpm_nyet_threshold = 0xf;
 997
 998         /* default to -3.5dB de-emphasis */
 999         tx_de_emphasis = 1;
1000
1001         /*
1002          * default to assert utmi_sleep_n and use maximum allowed HIRD
1003          * threshold value of 0b1100
1004          */
1005         hird_threshold = 12;
1006
1007         dwc->maximum_speed = usb_get_maximum_speed(dev);
1008         dwc->dr_mode = usb_get_dr_mode(dev);
1009         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1010
1011         dwc->has_lpm_erratum = device_property_read_bool(dev,
1012                                 "snps,has-lpm-erratum");
1013         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1014                                 &lpm_nyet_threshold);
1015         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1016                                 "snps,is-utmi-l1-suspend");
1017         device_property_read_u8(dev, "snps,hird-threshold",
1018                                 &hird_threshold);
1019         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1020                                 "snps,usb3_lpm_capable");
1021
1022         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1023                                 "snps,disable_scramble_quirk");
1024         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1025                                 "snps,u2exit_lfps_quirk");
1026         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1027                                 "snps,u2ss_inp3_quirk");
1028         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1029                                 "snps,req_p1p2p3_quirk");
1030         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1031                                 "snps,del_p1p2p3_quirk");
1032         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1033                                 "snps,del_phy_power_chg_quirk");
1034         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1035                                 "snps,lfps_filter_quirk");
1036         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1037                                 "snps,rx_detect_poll_quirk");
1038         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1039                                 "snps,dis_u3_susphy_quirk");
1040         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1041                                 "snps,dis_u2_susphy_quirk");
1042         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1043                                 "snps,dis_enblslpm_quirk");
1044         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1045                                 "snps,dis_rxdet_inp3_quirk");
1046         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1047                                 "snps,dis-u2-freeclk-exists-quirk");
1048         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1049                                 "snps,dis-del-phy-power-chg-quirk");
1050
1051         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1052                                 "snps,tx_de_emphasis_quirk");
1053         device_property_read_u8(dev, "snps,tx_de_emphasis",
1054                                 &tx_de_emphasis);
1055         device_property_read_string(dev, "snps,hsphy_interface",
1056                                     &dwc->hsphy_interface);
1057         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1058                                  &dwc->fladj);
1059
1060         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1061         dwc->tx_de_emphasis = tx_de_emphasis;
1062
1063         dwc->hird_threshold = hird_threshold
1064                 | (dwc->is_utmi_l1_suspend << 4);
1065
1066         platform_set_drvdata(pdev, dwc);
1067         dwc3_cache_hwparams(dwc);
1068
1069         ret = dwc3_core_get_phy(dwc);
1070         if (ret)
1071                 goto err0;
1072
1073         spin_lock_init(&dwc->lock);
1074
1075         if (!dev->dma_mask) {
1076                 dev->dma_mask = dev->parent->dma_mask;
1077                 dev->dma_parms = dev->parent->dma_parms;
1078                 dma_set_coherent_mask(dev, dev->parent->coherent_dma_mask);
1079         }
1080
1081         pm_runtime_set_active(dev);
1082         pm_runtime_use_autosuspend(dev);
1083         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1084         pm_runtime_enable(dev);
1085         ret = pm_runtime_get_sync(dev);
1086         if (ret < 0)
1087                 goto err1;
1088
1089         pm_runtime_forbid(dev);
1090
1091         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1092         if (ret) {
1093                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1094                 ret = -ENOMEM;
1095                 goto err2;
1096         }
1097
1098         ret = dwc3_get_dr_mode(dwc);
1099         if (ret)
1100                 goto err3;
1101
1102         ret = dwc3_alloc_scratch_buffers(dwc);
1103         if (ret)
1104                 goto err3;
1105
1106         ret = dwc3_core_init(dwc);
1107         if (ret) {
1108                 if (ret != -EPROBE_DEFER)
1109                         dev_err(dev, "failed to initialize core: %d\n", ret);
1110                 goto err4;
1111         }
1112
1113         /* Check the maximum_speed parameter */
1114         switch (dwc->maximum_speed) {
1115         case USB_SPEED_LOW:
1116         case USB_SPEED_FULL:
1117         case USB_SPEED_HIGH:
1118         case USB_SPEED_SUPER:
1119         case USB_SPEED_SUPER_PLUS:
1120                 break;
1121         default:
1122                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1123                         dwc->maximum_speed);
1124                 /* fall through */
1125         case USB_SPEED_UNKNOWN:
1126                 /* default to superspeed */
1127                 dwc->maximum_speed = USB_SPEED_SUPER;
1128
1129                 /*
1130                  * default to superspeed plus if we are capable.
1131                  */
1132                 if (dwc3_is_usb31(dwc) &&
1133                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1134                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1135                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1136
1137                 break;
1138         }
1139
1140         ret = dwc3_core_init_mode(dwc);
1141         if (ret)
1142                 goto err5;
1143
1144         dwc3_debugfs_init(dwc);
1145         pm_runtime_put(dev);
1146
1147         return 0;
1148
1149 err5:
1150         dwc3_event_buffers_cleanup(dwc);
1151
1152         usb_phy_shutdown(dwc->usb2_phy);
1153         usb_phy_shutdown(dwc->usb3_phy);
1154         phy_exit(dwc->usb2_generic_phy);
1155         phy_exit(dwc->usb3_generic_phy);
1156
1157         usb_phy_set_suspend(dwc->usb2_phy, 1);
1158         usb_phy_set_suspend(dwc->usb3_phy, 1);
1159         phy_power_off(dwc->usb2_generic_phy);
1160         phy_power_off(dwc->usb3_generic_phy);
1161
1162         dwc3_ulpi_exit(dwc);
1163
1164 err4:
1165         dwc3_free_scratch_buffers(dwc);
1166
1167 err3:
1168         dwc3_free_event_buffers(dwc);
1169         dwc3_ulpi_exit(dwc);
1170
1171 err2:
1172         pm_runtime_allow(&pdev->dev);
1173
1174 err1:
1175         pm_runtime_put_sync(&pdev->dev);
1176         pm_runtime_disable(&pdev->dev);
1177
1178 err0:
1179         /*
1180          * restore res->start back to its original value so that, in case the
1181          * probe is deferred, we don't end up getting error in request the
1182          * memory region the next time probe is called.
1183          */
1184         res->start -= DWC3_GLOBALS_REGS_START;
1185
1186         return ret;
1187 }
1188
1189 static int dwc3_remove(struct platform_device *pdev)
1190 {
1191         struct dwc3     *dwc = platform_get_drvdata(pdev);
1192         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1193
1194         pm_runtime_get_sync(&pdev->dev);
1195         /*
1196          * restore res->start back to its original value so that, in case the
1197          * probe is deferred, we don't end up getting error in request the
1198          * memory region the next time probe is called.
1199          */
1200         res->start -= DWC3_GLOBALS_REGS_START;
1201
1202         dwc3_core_exit_mode(dwc);
1203         dwc3_debugfs_exit(dwc);
1204
1205         dwc3_core_exit(dwc);
1206         dwc3_ulpi_exit(dwc);
1207
1208         pm_runtime_disable(&pdev->dev);
1209         pm_runtime_put_noidle(&pdev->dev);
1210         pm_runtime_set_suspended(&pdev->dev);
1211
1212         dwc3_free_event_buffers(dwc);
1213         dwc3_free_scratch_buffers(dwc);
1214
1215         return 0;
1216 }
1217
1218 #ifdef CONFIG_PM
1219 static int dwc3_suspend_common(struct dwc3 *dwc)
1220 {
1221         unsigned long   flags;
1222
1223         switch (dwc->dr_mode) {
1224         case USB_DR_MODE_PERIPHERAL:
1225         case USB_DR_MODE_OTG:
1226                 spin_lock_irqsave(&dwc->lock, flags);
1227                 dwc3_gadget_suspend(dwc);
1228                 spin_unlock_irqrestore(&dwc->lock, flags);
1229                 break;
1230         case USB_DR_MODE_HOST:
1231         default:
1232                 /* do nothing */
1233                 break;
1234         }
1235
1236         dwc3_core_exit(dwc);
1237
1238         return 0;
1239 }
1240
1241 static int dwc3_resume_common(struct dwc3 *dwc)
1242 {
1243         unsigned long   flags;
1244         int             ret;
1245
1246         ret = dwc3_core_init(dwc);
1247         if (ret)
1248                 return ret;
1249
1250         switch (dwc->dr_mode) {
1251         case USB_DR_MODE_PERIPHERAL:
1252         case USB_DR_MODE_OTG:
1253                 spin_lock_irqsave(&dwc->lock, flags);
1254                 dwc3_gadget_resume(dwc);
1255                 spin_unlock_irqrestore(&dwc->lock, flags);
1256                 /* FALLTHROUGH */
1257         case USB_DR_MODE_HOST:
1258         default:
1259                 /* do nothing */
1260                 break;
1261         }
1262
1263         return 0;
1264 }
1265
1266 static int dwc3_runtime_checks(struct dwc3 *dwc)
1267 {
1268         switch (dwc->dr_mode) {
1269         case USB_DR_MODE_PERIPHERAL:
1270         case USB_DR_MODE_OTG:
1271                 if (dwc->connected)
1272                         return -EBUSY;
1273                 break;
1274         case USB_DR_MODE_HOST:
1275         default:
1276                 /* do nothing */
1277                 break;
1278         }
1279
1280         return 0;
1281 }
1282
1283 static int dwc3_runtime_suspend(struct device *dev)
1284 {
1285         struct dwc3     *dwc = dev_get_drvdata(dev);
1286         int             ret;
1287
1288         if (dwc3_runtime_checks(dwc))
1289                 return -EBUSY;
1290
1291         ret = dwc3_suspend_common(dwc);
1292         if (ret)
1293                 return ret;
1294
1295         device_init_wakeup(dev, true);
1296
1297         return 0;
1298 }
1299
1300 static int dwc3_runtime_resume(struct device *dev)
1301 {
1302         struct dwc3     *dwc = dev_get_drvdata(dev);
1303         int             ret;
1304
1305         device_init_wakeup(dev, false);
1306
1307         ret = dwc3_resume_common(dwc);
1308         if (ret)
1309                 return ret;
1310
1311         switch (dwc->dr_mode) {
1312         case USB_DR_MODE_PERIPHERAL:
1313         case USB_DR_MODE_OTG:
1314                 dwc3_gadget_process_pending_events(dwc);
1315                 break;
1316         case USB_DR_MODE_HOST:
1317         default:
1318                 /* do nothing */
1319                 break;
1320         }
1321
1322         pm_runtime_mark_last_busy(dev);
1323         pm_runtime_put(dev);
1324
1325         return 0;
1326 }
1327
1328 static int dwc3_runtime_idle(struct device *dev)
1329 {
1330         struct dwc3     *dwc = dev_get_drvdata(dev);
1331
1332         switch (dwc->dr_mode) {
1333         case USB_DR_MODE_PERIPHERAL:
1334         case USB_DR_MODE_OTG:
1335                 if (dwc3_runtime_checks(dwc))
1336                         return -EBUSY;
1337                 break;
1338         case USB_DR_MODE_HOST:
1339         default:
1340                 /* do nothing */
1341                 break;
1342         }
1343
1344         pm_runtime_mark_last_busy(dev);
1345         pm_runtime_autosuspend(dev);
1346
1347         return 0;
1348 }
1349 #endif /* CONFIG_PM */
1350
1351 #ifdef CONFIG_PM_SLEEP
1352 static int dwc3_suspend(struct device *dev)
1353 {
1354         struct dwc3     *dwc = dev_get_drvdata(dev);
1355         int             ret;
1356
1357         ret = dwc3_suspend_common(dwc);
1358         if (ret)
1359                 return ret;
1360
1361         pinctrl_pm_select_sleep_state(dev);
1362
1363         return 0;
1364 }
1365
1366 static int dwc3_resume(struct device *dev)
1367 {
1368         struct dwc3     *dwc = dev_get_drvdata(dev);
1369         int             ret;
1370
1371         pinctrl_pm_select_default_state(dev);
1372
1373         ret = dwc3_resume_common(dwc);
1374         if (ret)
1375                 return ret;
1376
1377         pm_runtime_disable(dev);
1378         pm_runtime_set_active(dev);
1379         pm_runtime_enable(dev);
1380
1381         return 0;
1382 }
1383 #endif /* CONFIG_PM_SLEEP */
1384
1385 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1386         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1387         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1388                         dwc3_runtime_idle)
1389 };
1390
1391 #ifdef CONFIG_OF
1392 static const struct of_device_id of_dwc3_match[] = {
1393         {
1394                 .compatible = "snps,dwc3"
1395         },
1396         {
1397                 .compatible = "synopsys,dwc3"
1398         },
1399         { },
1400 };
1401 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1402 #endif
1403
1404 #ifdef CONFIG_ACPI
1405
1406 #define ACPI_ID_INTEL_BSW       "808622B7"
1407
1408 static const struct acpi_device_id dwc3_acpi_match[] = {
1409         { ACPI_ID_INTEL_BSW, 0 },
1410         { },
1411 };
1412 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1413 #endif
1414
1415 static struct platform_driver dwc3_driver = {
1416         .probe          = dwc3_probe,
1417         .remove         = dwc3_remove,
1418         .driver         = {
1419                 .name   = "dwc3",
1420                 .of_match_table = of_match_ptr(of_dwc3_match),
1421                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1422                 .pm     = &dwc3_dev_pm_ops,
1423         },
1424 };
1425
1426 module_platform_driver(dwc3_driver);
1427
1428 MODULE_ALIAS("platform:dwc3");
1429 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
1430 MODULE_LICENSE("GPL v2");
1431 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");