drivers/usb/dwc3/dwc3-qcom.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
   3  *
   4  * Inspired by dwc3-of-simple.c
   5  */
   6
   7 #include <linux/io.h>
   8 #include <linux/of.h>
   9 #include <linux/clk.h>
  10 #include <linux/irq.h>
  11 #include <linux/clk-provider.h>
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/extcon.h>
  15 #include <linux/of_platform.h>
  16 #include <linux/platform_device.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/usb/of.h>
  19 #include <linux/reset.h>
  20 #include <linux/iopoll.h>
  21
  22 #include "core.h"
  23
  24 /* USB QSCRATCH Hardware registers */
  25 #define QSCRATCH_HS_PHY_CTRL                    0x10
  26 #define UTMI_OTG_VBUS_VALID                     BIT(20)
  27 #define SW_SESSVLD_SEL                          BIT(28)
  28
  29 #define QSCRATCH_SS_PHY_CTRL                    0x30
  30 #define LANE0_PWR_PRESENT                       BIT(24)
  31
  32 #define QSCRATCH_GENERAL_CFG                    0x08
  33 #define PIPE_UTMI_CLK_SEL                       BIT(0)
  34 #define PIPE3_PHYSTATUS_SW                      BIT(3)
  35 #define PIPE_UTMI_CLK_DIS                       BIT(8)
  36
  37 #define PWR_EVNT_IRQ_STAT_REG                   0x58
  38 #define PWR_EVNT_LPM_IN_L2_MASK                 BIT(4)
  39 #define PWR_EVNT_LPM_OUT_L2_MASK                BIT(5)
  40
  41 struct dwc3_qcom {
  42         struct device           *dev;
  43         void __iomem            *qscratch_base;
  44         struct platform_device  *dwc3;
  45         struct clk              **clks;
  46         int                     num_clocks;
  47         struct reset_control    *resets;
  48
  49         int                     hs_phy_irq;
  50         int                     dp_hs_phy_irq;
  51         int                     dm_hs_phy_irq;
  52         int                     ss_phy_irq;
  53
  54         struct extcon_dev       *edev;
  55         struct extcon_dev       *host_edev;
  56         struct notifier_block   vbus_nb;
  57         struct notifier_block   host_nb;
  58
  59         enum usb_dr_mode        mode;
  60         bool                    is_suspended;
  61         bool                    pm_suspended;
  62 };
  63
  64 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
  65 {
  66         u32 reg;
  67
  68         reg = readl(base + offset);
  69         reg |= val;
  70         writel(reg, base + offset);
  71
  72         /* ensure that above write is through */
  73         readl(base + offset);
  74 }
  75
  76 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
  77 {
  78         u32 reg;
  79
  80         reg = readl(base + offset);
  81         reg &= ~val;
  82         writel(reg, base + offset);
  83
  84         /* ensure that above write is through */
  85         readl(base + offset);
  86 }
  87
  88 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
  89 {
  90         if (enable) {
  91                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
  92                                   LANE0_PWR_PRESENT);
  93                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
  94                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
  95         } else {
  96                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
  97                                   LANE0_PWR_PRESENT);
  98                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
  99                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
 100         }
 101 }
 102
 103 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
 104                                    unsigned long event, void *ptr)
 105 {
 106         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
 107
 108         /* enable vbus override for device mode */
 109         dwc3_qcom_vbus_override_enable(qcom, event);
 110         qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
 111
 112         return NOTIFY_DONE;
 113 }
 114
 115 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
 116                                    unsigned long event, void *ptr)
 117 {
 118         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
 119
 120         /* disable vbus override in host mode */
 121         dwc3_qcom_vbus_override_enable(qcom, !event);
 122         qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
 123
 124         return NOTIFY_DONE;
 125 }
 126
 127 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
 128 {
 129         struct device           *dev = qcom->dev;
 130         struct extcon_dev       *host_edev;
 131         int                     ret;
 132
 133         if (!of_property_read_bool(dev->of_node, "extcon"))
 134                 return 0;
 135
 136         qcom->edev = extcon_get_edev_by_phandle(dev, 0);
 137         if (IS_ERR(qcom->edev))
 138                 return PTR_ERR(qcom->edev);
 139
 140         qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
 141
 142         qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
 143         if (IS_ERR(qcom->host_edev))
 144                 qcom->host_edev = NULL;
 145
 146         ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
 147                                             &qcom->vbus_nb);
 148         if (ret < 0) {
 149                 dev_err(dev, "VBUS notifier register failed\n");
 150                 return ret;
 151         }
 152
 153         if (qcom->host_edev)
 154                 host_edev = qcom->host_edev;
 155         else
 156                 host_edev = qcom->edev;
 157
 158         qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
 159         ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
 160                                             &qcom->host_nb);
 161         if (ret < 0) {
 162                 dev_err(dev, "Host notifier register failed\n");
 163                 return ret;
 164         }
 165
 166         /* Update initial VBUS override based on extcon state */
 167         if (extcon_get_state(qcom->edev, EXTCON_USB) ||
 168             !extcon_get_state(host_edev, EXTCON_USB_HOST))
 169                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
 170         else
 171                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
 172
 173         return 0;
 174 }
 175
 176 /* Only usable in contexts where the role can not change. */
 177 static bool dwc3_qcom_is_host(struct dwc3_qcom *qcom)
 178 {
 179         struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
 180
 181         return dwc->xhci;
 182 }
 183
 184 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
 185 {
 186         if (qcom->hs_phy_irq) {
 187                 disable_irq_wake(qcom->hs_phy_irq);
 188                 disable_irq_nosync(qcom->hs_phy_irq);
 189         }
 190
 191         if (qcom->dp_hs_phy_irq) {
 192                 disable_irq_wake(qcom->dp_hs_phy_irq);
 193                 disable_irq_nosync(qcom->dp_hs_phy_irq);
 194         }
 195
 196         if (qcom->dm_hs_phy_irq) {
 197                 disable_irq_wake(qcom->dm_hs_phy_irq);
 198                 disable_irq_nosync(qcom->dm_hs_phy_irq);
 199         }
 200
 201         if (qcom->ss_phy_irq) {
 202                 disable_irq_wake(qcom->ss_phy_irq);
 203                 disable_irq_nosync(qcom->ss_phy_irq);
 204         }
 205 }
 206
 207 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
 208 {
 209         if (qcom->hs_phy_irq) {
 210                 enable_irq(qcom->hs_phy_irq);
 211                 enable_irq_wake(qcom->hs_phy_irq);
 212         }
 213
 214         if (qcom->dp_hs_phy_irq) {
 215                 enable_irq(qcom->dp_hs_phy_irq);
 216                 enable_irq_wake(qcom->dp_hs_phy_irq);
 217         }
 218
 219         if (qcom->dm_hs_phy_irq) {
 220                 enable_irq(qcom->dm_hs_phy_irq);
 221                 enable_irq_wake(qcom->dm_hs_phy_irq);
 222         }
 223
 224         if (qcom->ss_phy_irq) {
 225                 enable_irq(qcom->ss_phy_irq);
 226                 enable_irq_wake(qcom->ss_phy_irq);
 227         }
 228 }
 229
 230 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
 231 {
 232         u32 val;
 233         int i;
 234
 235         if (qcom->is_suspended)
 236                 return 0;
 237
 238         val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
 239         if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
 240                 dev_err(qcom->dev, "HS-PHY not in L2\n");
 241
 242         for (i = qcom->num_clocks - 1; i >= 0; i--)
 243                 clk_disable_unprepare(qcom->clks[i]);
 244
 245         if (device_may_wakeup(qcom->dev))
 246                 dwc3_qcom_enable_interrupts(qcom);
 247
 248         qcom->is_suspended = true;
 249
 250         return 0;
 251 }
 252
 253 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
 254 {
 255         int ret;
 256         int i;
 257
 258         if (!qcom->is_suspended)
 259                 return 0;
 260
 261         if (device_may_wakeup(qcom->dev))
 262                 dwc3_qcom_disable_interrupts(qcom);
 263
 264         for (i = 0; i < qcom->num_clocks; i++) {
 265                 ret = clk_prepare_enable(qcom->clks[i]);
 266                 if (ret < 0) {
 267                         while (--i >= 0)
 268                                 clk_disable_unprepare(qcom->clks[i]);
 269                         return ret;
 270                 }
 271         }
 272
 273         /* Clear existing events from PHY related to L2 in/out */
 274         dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
 275                           PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
 276
 277         qcom->is_suspended = false;
 278
 279         return 0;
 280 }
 281
 282 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
 283 {
 284         struct dwc3_qcom *qcom = data;
 285         struct dwc3     *dwc = platform_get_drvdata(qcom->dwc3);
 286
 287         /* If pm_suspended then let pm_resume take care of resuming h/w */
 288         if (qcom->pm_suspended)
 289                 return IRQ_HANDLED;
 290
 291         /*
 292          * This is safe as role switching is done from a freezable workqueue
 293          * and the wakeup interrupts are disabled as part of resume.
 294          */
 295         if (dwc3_qcom_is_host(qcom))
 296                 pm_runtime_resume(&dwc->xhci->dev);
 297
 298         return IRQ_HANDLED;
 299 }
 300
 301 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
 302 {
 303         /* Configure dwc3 to use UTMI clock as PIPE clock not present */
 304         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 305                           PIPE_UTMI_CLK_DIS);
 306
 307         usleep_range(100, 1000);
 308
 309         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 310                           PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
 311
 312         usleep_range(100, 1000);
 313
 314         dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
 315                           PIPE_UTMI_CLK_DIS);
 316 }
 317
 318 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
 319 {
 320         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 321         int irq, ret;
 322
 323         irq = platform_get_irq_byname(pdev, "hs_phy_irq");
 324         if (irq > 0) {
 325                 /* Keep wakeup interrupts disabled until suspend */
 326                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 327                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 328                                         qcom_dwc3_resume_irq,
 329                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 330                                         "qcom_dwc3 HS", qcom);
 331                 if (ret) {
 332                         dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
 333                         return ret;
 334                 }
 335                 qcom->hs_phy_irq = irq;
 336         }
 337
 338         irq = platform_get_irq_byname(pdev, "dp_hs_phy_irq");
 339         if (irq > 0) {
 340                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 341                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 342                                         qcom_dwc3_resume_irq,
 343                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 344                                         "qcom_dwc3 DP_HS", qcom);
 345                 if (ret) {
 346                         dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
 347                         return ret;
 348                 }
 349                 qcom->dp_hs_phy_irq = irq;
 350         }
 351
 352         irq = platform_get_irq_byname(pdev, "dm_hs_phy_irq");
 353         if (irq > 0) {
 354                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 355                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 356                                         qcom_dwc3_resume_irq,
 357                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 358                                         "qcom_dwc3 DM_HS", qcom);
 359                 if (ret) {
 360                         dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
 361                         return ret;
 362                 }
 363                 qcom->dm_hs_phy_irq = irq;
 364         }
 365
 366         irq = platform_get_irq_byname(pdev, "ss_phy_irq");
 367         if (irq > 0) {
 368                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
 369                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
 370                                         qcom_dwc3_resume_irq,
 371                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
 372                                         "qcom_dwc3 SS", qcom);
 373                 if (ret) {
 374                         dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
 375                         return ret;
 376                 }
 377                 qcom->ss_phy_irq = irq;
 378         }
 379
 380         return 0;
 381 }
 382
 383 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
 384 {
 385         struct device           *dev = qcom->dev;
 386         struct device_node      *np = dev->of_node;
 387         int                     i;
 388
 389         qcom->num_clocks = count;
 390
 391         if (!count)
 392                 return 0;
 393
 394         qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
 395                                   sizeof(struct clk *), GFP_KERNEL);
 396         if (!qcom->clks)
 397                 return -ENOMEM;
 398
 399         for (i = 0; i < qcom->num_clocks; i++) {
 400                 struct clk      *clk;
 401                 int             ret;
 402
 403                 clk = of_clk_get(np, i);
 404                 if (IS_ERR(clk)) {
 405                         while (--i >= 0)
 406                                 clk_put(qcom->clks[i]);
 407                         return PTR_ERR(clk);
 408                 }
 409
 410                 ret = clk_prepare_enable(clk);
 411                 if (ret < 0) {
 412                         while (--i >= 0) {
 413                                 clk_disable_unprepare(qcom->clks[i]);
 414                                 clk_put(qcom->clks[i]);
 415                         }
 416                         clk_put(clk);
 417
 418                         return ret;
 419                 }
 420
 421                 qcom->clks[i] = clk;
 422         }
 423
 424         return 0;
 425 }
 426
 427 static int dwc3_qcom_probe(struct platform_device *pdev)
 428 {
 429         struct device_node      *np = pdev->dev.of_node, *dwc3_np;
 430         struct device           *dev = &pdev->dev;
 431         struct dwc3_qcom        *qcom;
 432         struct resource         *res;
 433         int                     ret, i;
 434         bool                    ignore_pipe_clk;
 435
 436         qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
 437         if (!qcom)
 438                 return -ENOMEM;
 439
 440         platform_set_drvdata(pdev, qcom);
 441         qcom->dev = &pdev->dev;
 442
 443         qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
 444         if (IS_ERR(qcom->resets)) {
 445                 ret = PTR_ERR(qcom->resets);
 446                 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
 447                 return ret;
 448         }
 449
 450         ret = reset_control_assert(qcom->resets);
 451         if (ret) {
 452                 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
 453                 return ret;
 454         }
 455
 456         usleep_range(10, 1000);
 457
 458         ret = reset_control_deassert(qcom->resets);
 459         if (ret) {
 460                 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
 461                 goto reset_assert;
 462         }
 463
 464         ret = dwc3_qcom_clk_init(qcom, of_count_phandle_with_args(np,
 465                                                 "clocks", "#clock-cells"));
 466         if (ret) {
 467                 dev_err(dev, "failed to get clocks\n");
 468                 goto reset_assert;
 469         }
 470
 471         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 472         qcom->qscratch_base = devm_ioremap_resource(dev, res);
 473         if (IS_ERR(qcom->qscratch_base)) {
 474                 dev_err(dev, "failed to map qscratch, err=%d\n", ret);
 475                 ret = PTR_ERR(qcom->qscratch_base);
 476                 goto clk_disable;
 477         }
 478
 479         ret = dwc3_qcom_setup_irq(pdev);
 480         if (ret)
 481                 goto clk_disable;
 482
 483         dwc3_np = of_get_child_by_name(np, "dwc3");
 484         if (!dwc3_np) {
 485                 dev_err(dev, "failed to find dwc3 core child\n");
 486                 ret = -ENODEV;
 487                 goto clk_disable;
 488         }
 489
 490         /*
 491          * Disable pipe_clk requirement if specified. Used when dwc3
 492          * operates without SSPHY and only HS/FS/LS modes are supported.
 493          */
 494         ignore_pipe_clk = device_property_read_bool(dev,
 495                                 "qcom,select-utmi-as-pipe-clk");
 496         if (ignore_pipe_clk)
 497                 dwc3_qcom_select_utmi_clk(qcom);
 498
 499         ret = of_platform_populate(np, NULL, NULL, dev);
 500         if (ret) {
 501                 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
 502                 goto clk_disable;
 503         }
 504
 505         qcom->dwc3 = of_find_device_by_node(dwc3_np);
 506         if (!qcom->dwc3) {
 507                 dev_err(&pdev->dev, "failed to get dwc3 platform device\n");
 508                 ret = -ENODEV;
 509                 goto depopulate;
 510         }
 511
 512         qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
 513
 514         /* enable vbus override for device mode */
 515         if (qcom->mode != USB_DR_MODE_HOST)
 516                 dwc3_qcom_vbus_override_enable(qcom, true);
 517
 518         /* register extcon to override sw_vbus on Vbus change later */
 519         ret = dwc3_qcom_register_extcon(qcom);
 520         if (ret)
 521                 goto depopulate;
 522
 523         device_init_wakeup(&pdev->dev, 1);
 524         qcom->is_suspended = false;
 525         pm_runtime_set_active(dev);
 526         pm_runtime_enable(dev);
 527         pm_runtime_forbid(dev);
 528
 529         return 0;
 530
 531 depopulate:
 532         of_platform_depopulate(&pdev->dev);
 533 clk_disable:
 534         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 535                 clk_disable_unprepare(qcom->clks[i]);
 536                 clk_put(qcom->clks[i]);
 537         }
 538 reset_assert:
 539         reset_control_assert(qcom->resets);
 540
 541         return ret;
 542 }
 543
 544 static int dwc3_qcom_remove(struct platform_device *pdev)
 545 {
 546         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
 547         struct device *dev = &pdev->dev;
 548         int i;
 549
 550         of_platform_depopulate(dev);
 551
 552         for (i = qcom->num_clocks - 1; i >= 0; i--) {
 553                 clk_disable_unprepare(qcom->clks[i]);
 554                 clk_put(qcom->clks[i]);
 555         }
 556         qcom->num_clocks = 0;
 557
 558         reset_control_assert(qcom->resets);
 559
 560         pm_runtime_allow(dev);
 561         pm_runtime_disable(dev);
 562
 563         return 0;
 564 }
 565
 566 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
 567 {
 568         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 569         int ret = 0;
 570
 571         ret = dwc3_qcom_suspend(qcom);
 572         if (!ret)
 573                 qcom->pm_suspended = true;
 574
 575         return ret;
 576 }
 577
 578 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
 579 {
 580         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 581         int ret;
 582
 583         ret = dwc3_qcom_resume(qcom);
 584         if (!ret)
 585                 qcom->pm_suspended = false;
 586
 587         return ret;
 588 }
 589
 590 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
 591 {
 592         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 593
 594         return dwc3_qcom_suspend(qcom);
 595 }
 596
 597 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
 598 {
 599         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
 600
 601         return dwc3_qcom_resume(qcom);
 602 }
 603
 604 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
 605         SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
 606         SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
 607                            NULL)
 608 };
 609
 610 static const struct of_device_id dwc3_qcom_of_match[] = {
 611         { .compatible = "qcom,dwc3" },
 612         { .compatible = "qcom,msm8996-dwc3" },
 613         { .compatible = "qcom,sdm845-dwc3" },
 614         { }
 615 };
 616 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
 617
 618 static struct platform_driver dwc3_qcom_driver = {
 619         .probe          = dwc3_qcom_probe,
 620         .remove         = dwc3_qcom_remove,
 621         .driver         = {
 622                 .name   = "dwc3-qcom",
 623                 .pm     = &dwc3_qcom_dev_pm_ops,
 624                 .of_match_table = dwc3_qcom_of_match,
 625         },
 626 };
 627
 628 module_platform_driver(dwc3_qcom_driver);
 629
 630 MODULE_LICENSE("GPL v2");
 631 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");