drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <balbi@ti.com>,
   8  *          Sebastian Andrzej Siewior <bigeasy@linutronix.de>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84         return 0;
  85 }
  86
  87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                 struct dwc3_request *req)
  89 {
  90         struct dwc3             *dwc = dep->dwc;
  91
  92         req->request.actual     = 0;
  93         req->request.status     = -EINPROGRESS;
  94         req->epnum              = dep->number;
  95
  96         list_add_tail(&req->list, &dep->pending_list);
  97
  98         /*
  99          * Gadget driver might not be quick enough to queue a request
 100          * before we get a Transfer Not Ready event on this endpoint.
 101          *
 102          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103          * flag is set, it's telling us that as soon as Gadget queues the
 104          * required request, we should kick the transfer here because the
 105          * IRQ we were waiting for is long gone.
 106          */
 107         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                 unsigned        direction;
 109
 110                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                 if (dwc->ep0state != EP0_DATA_PHASE) {
 113                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                         return 0;
 115                 }
 116
 117                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                 DWC3_EP0_DIR_IN);
 121
 122                 return 0;
 123         }
 124
 125         /*
 126          * In case gadget driver asked us to delay the STATUS phase,
 127          * handle it here.
 128          */
 129         if (dwc->delayed_status) {
 130                 unsigned        direction;
 131
 132                 direction = !dwc->ep0_expect_in;
 133                 dwc->delayed_status = false;
 134                 usb_gadget_set_state(&dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                 if (dwc->ep0state == EP0_STATUS_PHASE)
 137                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                 return 0;
 140         }
 141
 142         /*
 143          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144          *
 145          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146          * come before issueing Start Transfer command, but if we do, we will
 147          * miss situations where the host starts another SETUP phase instead of
 148          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149          * Layer Compliance Suite.
 150          *
 151          * The problem surfaces due to the fact that in case of back-to-back
 152          * SETUP packets there will be no XferNotReady(DATA) generated and we
 153          * will be stuck waiting for XferNotReady(DATA) forever.
 154          *
 155          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156          * it tells us to start Data Phase right away. It also mentions that if
 157          * we receive a SETUP phase instead of the DATA phase, core will issue
 158          * XferComplete for the DATA phase, before actually initiating it in
 159          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160          * can only be used to print some debugging logs, as the core expects
 161          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162          * just so it completes right away, without transferring anything and,
 163          * only then, we can go back to the SETUP phase.
 164          *
 165          * Because of this scenario, SNPS decided to change the programming
 166          * model of control transfers and support on-demand transfers only for
 167          * the STATUS phase. To fix the issue we have now, we will always wait
 168          * for gadget driver to queue the DATA phase's struct usb_request, then
 169          * start it right away.
 170          *
 171          * If we're actually in a 2-stage transfer, we will wait for
 172          * XferNotReady(STATUS).
 173          */
 174         if (dwc->three_stage_setup) {
 175                 unsigned        direction;
 176
 177                 direction = dwc->ep0_expect_in;
 178                 dwc->ep0state = EP0_DATA_PHASE;
 179
 180                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                 dep->flags &= ~DWC3_EP0_DIR_IN;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                 gfp_t gfp_flags)
 190 {
 191         struct dwc3_request             *req = to_dwc3_request(request);
 192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193         struct dwc3                     *dwc = dep->dwc;
 194
 195         unsigned long                   flags;
 196
 197         int                             ret;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         if (!dep->endpoint.desc) {
 201                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                 dep->name);
 203                 ret = -ESHUTDOWN;
 204                 goto out;
 205         }
 206
 207         /* we share one TRB for ep0/1 */
 208         if (!list_empty(&dep->pending_list)) {
 209                 ret = -EBUSY;
 210                 goto out;
 211         }
 212
 213         ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215 out:
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         return ret;
 219 }
 220
 221 static void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222 {
 223         struct dwc3_ep          *dep;
 224
 225         /* reinitialize physical ep1 */
 226         dep = dwc->eps[1];
 227         dep->flags = DWC3_EP_ENABLED;
 228
 229         /* stall is always issued on EP0 */
 230         dep = dwc->eps[0];
 231         __dwc3_gadget_ep_set_halt(dep, 1, false);
 232         dep->flags = DWC3_EP_ENABLED;
 233         dwc->delayed_status = false;
 234
 235         if (!list_empty(&dep->pending_list)) {
 236                 struct dwc3_request     *req;
 237
 238                 req = next_request(&dep->pending_list);
 239                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240         }
 241
 242         dwc->ep0state = EP0_SETUP_PHASE;
 243         dwc3_ep0_out_start(dwc);
 244 }
 245
 246 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 247 {
 248         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 249         struct dwc3                     *dwc = dep->dwc;
 250
 251         dwc3_ep0_stall_and_restart(dwc);
 252
 253         return 0;
 254 }
 255
 256 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 257 {
 258         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 259         struct dwc3                     *dwc = dep->dwc;
 260         unsigned long                   flags;
 261         int                             ret;
 262
 263         spin_lock_irqsave(&dwc->lock, flags);
 264         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 265         spin_unlock_irqrestore(&dwc->lock, flags);
 266
 267         return ret;
 268 }
 269
 270 void dwc3_ep0_out_start(struct dwc3 *dwc)
 271 {
 272         struct dwc3_ep                  *dep;
 273         int                             ret;
 274
 275         complete(&dwc->ep0_in_setup);
 276
 277         dep = dwc->eps[0];
 278         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 279                         DWC3_TRBCTL_CONTROL_SETUP, false);
 280         ret = dwc3_ep0_start_trans(dep);
 281         WARN_ON(ret < 0);
 282 }
 283
 284 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 285 {
 286         struct dwc3_ep          *dep;
 287         u32                     windex = le16_to_cpu(wIndex_le);
 288         u32                     epnum;
 289
 290         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 291         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 292                 epnum |= 1;
 293
 294         dep = dwc->eps[epnum];
 295         if (dep == NULL)
 296                 return NULL;
 297
 298         if (dep->flags & DWC3_EP_ENABLED)
 299                 return dep;
 300
 301         return NULL;
 302 }
 303
 304 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 305 {
 306 }
 307 /*
 308  * ch 9.4.5
 309  */
 310 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 311                 struct usb_ctrlrequest *ctrl)
 312 {
 313         struct dwc3_ep          *dep;
 314         u32                     recip;
 315         u32                     value;
 316         u32                     reg;
 317         u16                     usb_status = 0;
 318         __le16                  *response_pkt;
 319
 320         /* We don't support PTM_STATUS */
 321         value = le16_to_cpu(ctrl->wValue);
 322         if (value != 0)
 323                 return -EINVAL;
 324
 325         recip = ctrl->bRequestType & USB_RECIP_MASK;
 326         switch (recip) {
 327         case USB_RECIP_DEVICE:
 328                 /*
 329                  * LTM will be set once we know how to set this in HW.
 330                  */
 331                 usb_status |= dwc->gadget.is_selfpowered;
 332
 333                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 334                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 335                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 336                         if (reg & DWC3_DCTL_INITU1ENA)
 337                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 338                         if (reg & DWC3_DCTL_INITU2ENA)
 339                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 340                 }
 341
 342                 break;
 343
 344         case USB_RECIP_INTERFACE:
 345                 /*
 346                  * Function Remote Wake Capable D0
 347                  * Function Remote Wakeup       D1
 348                  */
 349                 break;
 350
 351         case USB_RECIP_ENDPOINT:
 352                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 353                 if (!dep)
 354                         return -EINVAL;
 355
 356                 if (dep->flags & DWC3_EP_STALL)
 357                         usb_status = 1 << USB_ENDPOINT_HALT;
 358                 break;
 359         default:
 360                 return -EINVAL;
 361         }
 362
 363         response_pkt = (__le16 *) dwc->setup_buf;
 364         *response_pkt = cpu_to_le16(usb_status);
 365
 366         dep = dwc->eps[0];
 367         dwc->ep0_usb_req.dep = dep;
 368         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 369         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 370         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 371
 372         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 373 }
 374
 375 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 376                 int set)
 377 {
 378         u32 reg;
 379
 380         if (state != USB_STATE_CONFIGURED)
 381                 return -EINVAL;
 382         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 383                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 384                 return -EINVAL;
 385
 386         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 387         if (set)
 388                 reg |= DWC3_DCTL_INITU1ENA;
 389         else
 390                 reg &= ~DWC3_DCTL_INITU1ENA;
 391         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 392
 393         return 0;
 394 }
 395
 396 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 397                 int set)
 398 {
 399         u32 reg;
 400
 401
 402         if (state != USB_STATE_CONFIGURED)
 403                 return -EINVAL;
 404         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 405                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 406                 return -EINVAL;
 407
 408         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 409         if (set)
 410                 reg |= DWC3_DCTL_INITU2ENA;
 411         else
 412                 reg &= ~DWC3_DCTL_INITU2ENA;
 413         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 414
 415         return 0;
 416 }
 417
 418 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 419                 u32 wIndex, int set)
 420 {
 421         if ((wIndex & 0xff) != 0)
 422                 return -EINVAL;
 423         if (!set)
 424                 return -EINVAL;
 425
 426         switch (wIndex >> 8) {
 427         case TEST_J:
 428         case TEST_K:
 429         case TEST_SE0_NAK:
 430         case TEST_PACKET:
 431         case TEST_FORCE_EN:
 432                 dwc->test_mode_nr = wIndex >> 8;
 433                 dwc->test_mode = true;
 434                 break;
 435         default:
 436                 return -EINVAL;
 437         }
 438
 439         return 0;
 440 }
 441
 442 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 443                 struct usb_ctrlrequest *ctrl, int set)
 444 {
 445         enum usb_device_state   state;
 446         u32                     wValue;
 447         u32                     wIndex;
 448         int                     ret = 0;
 449
 450         wValue = le16_to_cpu(ctrl->wValue);
 451         wIndex = le16_to_cpu(ctrl->wIndex);
 452         state = dwc->gadget.state;
 453
 454         switch (wValue) {
 455         case USB_DEVICE_REMOTE_WAKEUP:
 456                 break;
 457         /*
 458          * 9.4.1 says only only for SS, in AddressState only for
 459          * default control pipe
 460          */
 461         case USB_DEVICE_U1_ENABLE:
 462                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 463                 break;
 464         case USB_DEVICE_U2_ENABLE:
 465                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 466                 break;
 467         case USB_DEVICE_LTM_ENABLE:
 468                 ret = -EINVAL;
 469                 break;
 470         case USB_DEVICE_TEST_MODE:
 471                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 472                 break;
 473         default:
 474                 ret = -EINVAL;
 475         }
 476
 477         return ret;
 478 }
 479
 480 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 481                 struct usb_ctrlrequest *ctrl, int set)
 482 {
 483         u32                     wValue;
 484         int                     ret = 0;
 485
 486         wValue = le16_to_cpu(ctrl->wValue);
 487
 488         switch (wValue) {
 489         case USB_INTRF_FUNC_SUSPEND:
 490                 /*
 491                  * REVISIT: Ideally we would enable some low power mode here,
 492                  * however it's unclear what we should be doing here.
 493                  *
 494                  * For now, we're not doing anything, just making sure we return
 495                  * 0 so USB Command Verifier tests pass without any errors.
 496                  */
 497                 break;
 498         default:
 499                 ret = -EINVAL;
 500         }
 501
 502         return ret;
 503 }
 504
 505 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 506                 struct usb_ctrlrequest *ctrl, int set)
 507 {
 508         struct dwc3_ep          *dep;
 509         u32                     wValue;
 510         int                     ret;
 511
 512         wValue = le16_to_cpu(ctrl->wValue);
 513
 514         switch (wValue) {
 515         case USB_ENDPOINT_HALT:
 516                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 517                 if (!dep)
 518                         return -EINVAL;
 519
 520                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 521                         break;
 522
 523                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 524                 if (ret)
 525                         return -EINVAL;
 526                 break;
 527         default:
 528                 return -EINVAL;
 529         }
 530
 531         return 0;
 532 }
 533
 534 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 535                 struct usb_ctrlrequest *ctrl, int set)
 536 {
 537         u32                     recip;
 538         int                     ret;
 539
 540         recip = ctrl->bRequestType & USB_RECIP_MASK;
 541
 542         switch (recip) {
 543         case USB_RECIP_DEVICE:
 544                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 545                 break;
 546         case USB_RECIP_INTERFACE:
 547                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 548                 break;
 549         case USB_RECIP_ENDPOINT:
 550                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 551                 break;
 552         default:
 553                 ret = -EINVAL;
 554         }
 555
 556         return ret;
 557 }
 558
 559 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 560 {
 561         enum usb_device_state state = dwc->gadget.state;
 562         u32 addr;
 563         u32 reg;
 564
 565         addr = le16_to_cpu(ctrl->wValue);
 566         if (addr > 127) {
 567                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 568                 return -EINVAL;
 569         }
 570
 571         if (state == USB_STATE_CONFIGURED) {
 572                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 573                 return -EINVAL;
 574         }
 575
 576         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 577         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 578         reg |= DWC3_DCFG_DEVADDR(addr);
 579         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 580
 581         if (addr)
 582                 usb_gadget_set_state(&dwc->gadget, USB_STATE_ADDRESS);
 583         else
 584                 usb_gadget_set_state(&dwc->gadget, USB_STATE_DEFAULT);
 585
 586         return 0;
 587 }
 588
 589 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 590 {
 591         int ret;
 592
 593         spin_unlock(&dwc->lock);
 594         ret = dwc->gadget_driver->setup(&dwc->gadget, ctrl);
 595         spin_lock(&dwc->lock);
 596         return ret;
 597 }
 598
 599 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 600 {
 601         enum usb_device_state state = dwc->gadget.state;
 602         u32 cfg;
 603         int ret;
 604         u32 reg;
 605
 606         cfg = le16_to_cpu(ctrl->wValue);
 607
 608         switch (state) {
 609         case USB_STATE_DEFAULT:
 610                 return -EINVAL;
 611
 612         case USB_STATE_ADDRESS:
 613                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 614                 /* if the cfg matches and the cfg is non zero */
 615                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 616
 617                         /*
 618                          * only change state if set_config has already
 619                          * been processed. If gadget driver returns
 620                          * USB_GADGET_DELAYED_STATUS, we will wait
 621                          * to change the state on the next usb_ep_queue()
 622                          */
 623                         if (ret == 0)
 624                                 usb_gadget_set_state(&dwc->gadget,
 625                                                 USB_STATE_CONFIGURED);
 626
 627                         /*
 628                          * Enable transition to U1/U2 state when
 629                          * nothing is pending from application.
 630                          */
 631                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 632                         reg |= (DWC3_DCTL_ACCEPTU1ENA | DWC3_DCTL_ACCEPTU2ENA);
 633                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 634                 }
 635                 break;
 636
 637         case USB_STATE_CONFIGURED:
 638                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 639                 if (!cfg && !ret)
 640                         usb_gadget_set_state(&dwc->gadget,
 641                                         USB_STATE_ADDRESS);
 642                 break;
 643         default:
 644                 ret = -EINVAL;
 645         }
 646         return ret;
 647 }
 648
 649 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 650 {
 651         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 652         struct dwc3     *dwc = dep->dwc;
 653
 654         u32             param = 0;
 655         u32             reg;
 656
 657         struct timing {
 658                 u8      u1sel;
 659                 u8      u1pel;
 660                 __le16  u2sel;
 661                 __le16  u2pel;
 662         } __packed timing;
 663
 664         int             ret;
 665
 666         memcpy(&timing, req->buf, sizeof(timing));
 667
 668         dwc->u1sel = timing.u1sel;
 669         dwc->u1pel = timing.u1pel;
 670         dwc->u2sel = le16_to_cpu(timing.u2sel);
 671         dwc->u2pel = le16_to_cpu(timing.u2pel);
 672
 673         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 674         if (reg & DWC3_DCTL_INITU2ENA)
 675                 param = dwc->u2pel;
 676         if (reg & DWC3_DCTL_INITU1ENA)
 677                 param = dwc->u1pel;
 678
 679         /*
 680          * According to Synopsys Databook, if parameter is
 681          * greater than 125, a value of zero should be
 682          * programmed in the register.
 683          */
 684         if (param > 125)
 685                 param = 0;
 686
 687         /* now that we have the time, issue DGCMD Set Sel */
 688         ret = dwc3_send_gadget_generic_command(dwc,
 689                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 690         WARN_ON(ret < 0);
 691 }
 692
 693 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 694 {
 695         struct dwc3_ep  *dep;
 696         enum usb_device_state state = dwc->gadget.state;
 697         u16             wLength;
 698
 699         if (state == USB_STATE_DEFAULT)
 700                 return -EINVAL;
 701
 702         wLength = le16_to_cpu(ctrl->wLength);
 703
 704         if (wLength != 6) {
 705                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 706                                 wLength);
 707                 return -EINVAL;
 708         }
 709
 710         /*
 711          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 712          * queue a usb_request for 6 bytes.
 713          *
 714          * Remember, though, this controller can't handle non-wMaxPacketSize
 715          * aligned transfers on the OUT direction, so we queue a request for
 716          * wMaxPacketSize instead.
 717          */
 718         dep = dwc->eps[0];
 719         dwc->ep0_usb_req.dep = dep;
 720         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 721         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 722         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 723
 724         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 725 }
 726
 727 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 728 {
 729         u16             wLength;
 730         u16             wValue;
 731         u16             wIndex;
 732
 733         wValue = le16_to_cpu(ctrl->wValue);
 734         wLength = le16_to_cpu(ctrl->wLength);
 735         wIndex = le16_to_cpu(ctrl->wIndex);
 736
 737         if (wIndex || wLength)
 738                 return -EINVAL;
 739
 740         dwc->gadget.isoch_delay = wValue;
 741
 742         return 0;
 743 }
 744
 745 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 746 {
 747         int ret;
 748
 749         switch (ctrl->bRequest) {
 750         case USB_REQ_GET_STATUS:
 751                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 752                 break;
 753         case USB_REQ_CLEAR_FEATURE:
 754                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 755                 break;
 756         case USB_REQ_SET_FEATURE:
 757                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 758                 break;
 759         case USB_REQ_SET_ADDRESS:
 760                 ret = dwc3_ep0_set_address(dwc, ctrl);
 761                 break;
 762         case USB_REQ_SET_CONFIGURATION:
 763                 ret = dwc3_ep0_set_config(dwc, ctrl);
 764                 break;
 765         case USB_REQ_SET_SEL:
 766                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 767                 break;
 768         case USB_REQ_SET_ISOCH_DELAY:
 769                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 770                 break;
 771         default:
 772                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 773                 break;
 774         }
 775
 776         return ret;
 777 }
 778
 779 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 780                 const struct dwc3_event_depevt *event)
 781 {
 782         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 783         int ret = -EINVAL;
 784         u32 len;
 785
 786         if (!dwc->gadget_driver)
 787                 goto out;
 788
 789         trace_dwc3_ctrl_req(ctrl);
 790
 791         len = le16_to_cpu(ctrl->wLength);
 792         if (!len) {
 793                 dwc->three_stage_setup = false;
 794                 dwc->ep0_expect_in = false;
 795                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 796         } else {
 797                 dwc->three_stage_setup = true;
 798                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 799                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 800         }
 801
 802         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 803                 ret = dwc3_ep0_std_request(dwc, ctrl);
 804         else
 805                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 806
 807         if (ret == USB_GADGET_DELAYED_STATUS)
 808                 dwc->delayed_status = true;
 809
 810 out:
 811         if (ret < 0)
 812                 dwc3_ep0_stall_and_restart(dwc);
 813 }
 814
 815 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 816                 const struct dwc3_event_depevt *event)
 817 {
 818         struct dwc3_request     *r;
 819         struct usb_request      *ur;
 820         struct dwc3_trb         *trb;
 821         struct dwc3_ep          *ep0;
 822         u32                     transferred = 0;
 823         u32                     status;
 824         u32                     length;
 825         u8                      epnum;
 826
 827         epnum = event->endpoint_number;
 828         ep0 = dwc->eps[0];
 829
 830         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 831         trb = dwc->ep0_trb;
 832         trace_dwc3_complete_trb(ep0, trb);
 833
 834         r = next_request(&ep0->pending_list);
 835         if (!r)
 836                 return;
 837
 838         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 839         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 840                 dwc->setup_packet_pending = true;
 841                 if (r)
 842                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 843
 844                 return;
 845         }
 846
 847         ur = &r->request;
 848
 849         length = trb->size & DWC3_TRB_SIZE_MASK;
 850         transferred = ur->length - length;
 851         ur->actual += transferred;
 852
 853         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 854              ur->length && ur->zero) || dwc->ep0_bounced) {
 855                 trb++;
 856                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 857                 trace_dwc3_complete_trb(ep0, trb);
 858
 859                 if (r->direction)
 860                         dwc->eps[1]->trb_enqueue = 0;
 861                 else
 862                         dwc->eps[0]->trb_enqueue = 0;
 863
 864                 dwc->ep0_bounced = false;
 865         }
 866
 867         if ((epnum & 1) && ur->actual < ur->length)
 868                 dwc3_ep0_stall_and_restart(dwc);
 869         else
 870                 dwc3_gadget_giveback(ep0, r, 0);
 871 }
 872
 873 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 874                 const struct dwc3_event_depevt *event)
 875 {
 876         struct dwc3_request     *r;
 877         struct dwc3_ep          *dep;
 878         struct dwc3_trb         *trb;
 879         u32                     status;
 880
 881         dep = dwc->eps[0];
 882         trb = dwc->ep0_trb;
 883
 884         trace_dwc3_complete_trb(dep, trb);
 885
 886         if (!list_empty(&dep->pending_list)) {
 887                 r = next_request(&dep->pending_list);
 888
 889                 dwc3_gadget_giveback(dep, r, 0);
 890         }
 891
 892         if (dwc->test_mode) {
 893                 int ret;
 894
 895                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 896                 if (ret < 0) {
 897                         dev_err(dwc->dev, "invalid test #%d\n",
 898                                         dwc->test_mode_nr);
 899                         dwc3_ep0_stall_and_restart(dwc);
 900                         return;
 901                 }
 902         }
 903
 904         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 905         if (status == DWC3_TRBSTS_SETUP_PENDING)
 906                 dwc->setup_packet_pending = true;
 907
 908         dwc->ep0state = EP0_SETUP_PHASE;
 909         dwc3_ep0_out_start(dwc);
 910 }
 911
 912 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 913                         const struct dwc3_event_depevt *event)
 914 {
 915         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 916
 917         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 918         dep->resource_index = 0;
 919         dwc->setup_packet_pending = false;
 920
 921         switch (dwc->ep0state) {
 922         case EP0_SETUP_PHASE:
 923                 dwc3_ep0_inspect_setup(dwc, event);
 924                 break;
 925
 926         case EP0_DATA_PHASE:
 927                 dwc3_ep0_complete_data(dwc, event);
 928                 break;
 929
 930         case EP0_STATUS_PHASE:
 931                 dwc3_ep0_complete_status(dwc, event);
 932                 break;
 933         default:
 934                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 935         }
 936 }
 937
 938 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 939                 struct dwc3_ep *dep, struct dwc3_request *req)
 940 {
 941         unsigned int            trb_length = 0;
 942         int                     ret;
 943
 944         req->direction = !!dep->number;
 945
 946         if (req->request.length == 0) {
 947                 if (!req->direction)
 948                         trb_length = dep->endpoint.maxpacket;
 949
 950                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 951                                 DWC3_TRBCTL_CONTROL_DATA, false);
 952                 ret = dwc3_ep0_start_trans(dep);
 953         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 954                         && (dep->number == 0)) {
 955                 u32     maxpacket;
 956                 u32     rem;
 957
 958                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 959                                 &req->request, dep->number);
 960                 if (ret)
 961                         return;
 962
 963                 maxpacket = dep->endpoint.maxpacket;
 964                 rem = req->request.length % maxpacket;
 965                 dwc->ep0_bounced = true;
 966
 967                 /* prepare normal TRB */
 968                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 969                                          req->request.length,
 970                                          DWC3_TRBCTL_CONTROL_DATA,
 971                                          true);
 972
 973                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 974
 975                 /* Now prepare one extra TRB to align transfer size */
 976                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
 977                                          maxpacket - rem,
 978                                          DWC3_TRBCTL_CONTROL_DATA,
 979                                          false);
 980                 ret = dwc3_ep0_start_trans(dep);
 981         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
 982                    req->request.length && req->request.zero) {
 983
 984                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 985                                 &req->request, dep->number);
 986                 if (ret)
 987                         return;
 988
 989                 /* prepare normal TRB */
 990                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
 991                                          req->request.length,
 992                                          DWC3_TRBCTL_CONTROL_DATA,
 993                                          true);
 994
 995                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
 996
 997                 if (!req->direction)
 998                         trb_length = dep->endpoint.maxpacket;
 999
1000                 /* Now prepare one extra TRB to align transfer size */
1001                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1002                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1003                                          false);
1004                 ret = dwc3_ep0_start_trans(dep);
1005         } else {
1006                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1007                                 &req->request, dep->number);
1008                 if (ret)
1009                         return;
1010
1011                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1012                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1013                                 false);
1014
1015                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1016
1017                 ret = dwc3_ep0_start_trans(dep);
1018         }
1019
1020         WARN_ON(ret < 0);
1021 }
1022
1023 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1024 {
1025         struct dwc3             *dwc = dep->dwc;
1026         u32                     type;
1027
1028         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1029                 : DWC3_TRBCTL_CONTROL_STATUS2;
1030
1031         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1032         return dwc3_ep0_start_trans(dep);
1033 }
1034
1035 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1036 {
1037         WARN_ON(dwc3_ep0_start_control_status(dep));
1038 }
1039
1040 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1041                 const struct dwc3_event_depevt *event)
1042 {
1043         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1044
1045         __dwc3_ep0_do_control_status(dwc, dep);
1046 }
1047
1048 static void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1049 {
1050         struct dwc3_gadget_ep_cmd_params params;
1051         u32                     cmd;
1052         int                     ret;
1053
1054         if (!dep->resource_index)
1055                 return;
1056
1057         cmd = DWC3_DEPCMD_ENDTRANSFER;
1058         cmd |= DWC3_DEPCMD_CMDIOC;
1059         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1060         memset(&params, 0, sizeof(params));
1061         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1062         WARN_ON_ONCE(ret);
1063         dep->resource_index = 0;
1064 }
1065
1066 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1067                 const struct dwc3_event_depevt *event)
1068 {
1069         switch (event->status) {
1070         case DEPEVT_STATUS_CONTROL_DATA:
1071                 /*
1072                  * We already have a DATA transfer in the controller's cache,
1073                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1074                  * it's for the wrong direction.
1075                  *
1076                  * In that case, we must issue END_TRANSFER command to the Data
1077                  * Phase we already have started and issue SetStall on the
1078                  * control endpoint.
1079                  */
1080                 if (dwc->ep0_expect_in != event->endpoint_number) {
1081                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1082
1083                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1084                         dwc3_ep0_end_control_data(dwc, dep);
1085                         dwc3_ep0_stall_and_restart(dwc);
1086                         return;
1087                 }
1088
1089                 break;
1090
1091         case DEPEVT_STATUS_CONTROL_STATUS:
1092                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1093                         return;
1094
1095                 dwc->ep0state = EP0_STATUS_PHASE;
1096
1097                 if (dwc->delayed_status) {
1098                         struct dwc3_ep *dep = dwc->eps[0];
1099
1100                         WARN_ON_ONCE(event->endpoint_number != 1);
1101                         /*
1102                          * We should handle the delay STATUS phase here if the
1103                          * request for handling delay STATUS has been queued
1104                          * into the list.
1105                          */
1106                         if (!list_empty(&dep->pending_list)) {
1107                                 dwc->delayed_status = false;
1108                                 usb_gadget_set_state(&dwc->gadget,
1109                                                      USB_STATE_CONFIGURED);
1110                                 dwc3_ep0_do_control_status(dwc, event);
1111                         }
1112
1113                         return;
1114                 }
1115
1116                 dwc3_ep0_do_control_status(dwc, event);
1117         }
1118 }
1119
1120 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1121                 const struct dwc3_event_depevt *event)
1122 {
1123         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1124         u8              cmd;
1125
1126         switch (event->endpoint_event) {
1127         case DWC3_DEPEVT_XFERCOMPLETE:
1128                 dwc3_ep0_xfer_complete(dwc, event);
1129                 break;
1130
1131         case DWC3_DEPEVT_XFERNOTREADY:
1132                 dwc3_ep0_xfernotready(dwc, event);
1133                 break;
1134
1135         case DWC3_DEPEVT_XFERINPROGRESS:
1136         case DWC3_DEPEVT_RXTXFIFOEVT:
1137         case DWC3_DEPEVT_STREAMEVT:
1138                 break;
1139         case DWC3_DEPEVT_EPCMDCMPLT:
1140                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1141
1142                 if (cmd == DWC3_DEPCMD_ENDTRANSFER)
1143                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1144                 break;
1145         }
1146 }