2 * gadget.c - DesignWare USB3 DRD Controller Gadget Framework Link
4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 * Authors: Felipe Balbi <balbi@ti.com>,
7 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 * This program is free software: you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 of
11 * the License as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spinlock.h>
23 #include <linux/platform_device.h>
24 #include <linux/pm_runtime.h>
25 #include <linux/interrupt.h>
27 #include <linux/list.h>
28 #include <linux/dma-mapping.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
39 * dwc3_gadget_set_test_mode - enables usb2 test modes
40 * @dwc: pointer to our context structure
41 * @mode: the mode to set (J, K SE0 NAK, Force Enable)
43 * Caller should take care of locking. This function will return 0 on
44 * success or -EINVAL if wrong Test Selector is passed.
46 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode)
50 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
51 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
65 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
71 * dwc3_gadget_get_link_state - gets current state of usb link
72 * @dwc: pointer to our context structure
74 * Caller should take care of locking. This function will
75 * return the link state on success (>= 0) or -ETIMEDOUT.
77 int dwc3_gadget_get_link_state(struct dwc3 *dwc)
81 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
83 return DWC3_DSTS_USBLNKST(reg);
87 * dwc3_gadget_set_link_state - sets usb link to a particular state
88 * @dwc: pointer to our context structure
89 * @state: the state to put link into
91 * Caller should take care of locking. This function will
92 * return 0 on success or -ETIMEDOUT.
94 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state)
100 * Wait until device controller is ready. Only applies to 1.94a and
103 if (dwc->revision >= DWC3_REVISION_194A) {
105 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
106 if (reg & DWC3_DSTS_DCNRD)
116 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
117 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
119 /* set requested state */
120 reg |= DWC3_DCTL_ULSTCHNGREQ(state);
121 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
124 * The following code is racy when called from dwc3_gadget_wakeup,
125 * and is not needed, at least on newer versions
127 if (dwc->revision >= DWC3_REVISION_194A)
130 /* wait for a change in DSTS */
133 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
135 if (DWC3_DSTS_USBLNKST(reg) == state)
145 * dwc3_ep_inc_trb - increment a trb index.
146 * @index: Pointer to the TRB index to increment.
148 * The index should never point to the link TRB. After incrementing,
149 * if it is point to the link TRB, wrap around to the beginning. The
150 * link TRB is always at the last TRB entry.
152 static void dwc3_ep_inc_trb(u8 *index)
155 if (*index == (DWC3_TRB_NUM - 1))
160 * dwc3_ep_inc_enq - increment endpoint's enqueue pointer
161 * @dep: The endpoint whose enqueue pointer we're incrementing
163 static void dwc3_ep_inc_enq(struct dwc3_ep *dep)
165 dwc3_ep_inc_trb(&dep->trb_enqueue);
169 * dwc3_ep_inc_deq - increment endpoint's dequeue pointer
170 * @dep: The endpoint whose enqueue pointer we're incrementing
172 static void dwc3_ep_inc_deq(struct dwc3_ep *dep)
174 dwc3_ep_inc_trb(&dep->trb_dequeue);
177 void dwc3_gadget_del_and_unmap_request(struct dwc3_ep *dep,
178 struct dwc3_request *req, int status)
180 struct dwc3 *dwc = dep->dwc;
182 req->started = false;
183 list_del(&req->list);
185 req->unaligned = false;
188 if (req->request.status == -EINPROGRESS)
189 req->request.status = status;
192 usb_gadget_unmap_request_by_dev(dwc->sysdev,
193 &req->request, req->direction);
196 trace_dwc3_gadget_giveback(req);
199 pm_runtime_put(dwc->dev);
203 * dwc3_gadget_giveback - call struct usb_request's ->complete callback
204 * @dep: The endpoint to whom the request belongs to
205 * @req: The request we're giving back
206 * @status: completion code for the request
208 * Must be called with controller's lock held and interrupts disabled. This
209 * function will unmap @req and call its ->complete() callback to notify upper
210 * layers that it has completed.
212 void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
215 struct dwc3 *dwc = dep->dwc;
217 dwc3_gadget_del_and_unmap_request(dep, req, status);
219 spin_unlock(&dwc->lock);
220 usb_gadget_giveback_request(&dep->endpoint, &req->request);
221 spin_lock(&dwc->lock);
225 * dwc3_send_gadget_generic_command - issue a generic command for the controller
226 * @dwc: pointer to the controller context
227 * @cmd: the command to be issued
228 * @param: command parameter
230 * Caller should take care of locking. Issue @cmd with a given @param to @dwc
231 * and wait for its completion.
233 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned cmd, u32 param)
240 dwc3_writel(dwc->regs, DWC3_DGCMDPAR, param);
241 dwc3_writel(dwc->regs, DWC3_DGCMD, cmd | DWC3_DGCMD_CMDACT);
244 reg = dwc3_readl(dwc->regs, DWC3_DGCMD);
245 if (!(reg & DWC3_DGCMD_CMDACT)) {
246 status = DWC3_DGCMD_STATUS(reg);
258 trace_dwc3_gadget_generic_cmd(cmd, param, status);
263 static int __dwc3_gadget_wakeup(struct dwc3 *dwc);
266 * dwc3_send_gadget_ep_cmd - issue an endpoint command
267 * @dep: the endpoint to which the command is going to be issued
268 * @cmd: the command to be issued
269 * @params: parameters to the command
271 * Caller should handle locking. This function will issue @cmd with given
272 * @params to @dep and wait for its completion.
274 int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
275 struct dwc3_gadget_ep_cmd_params *params)
277 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
278 struct dwc3 *dwc = dep->dwc;
280 u32 saved_config = 0;
287 * When operating in USB 2.0 speeds (HS/FS), if GUSB2PHYCFG.ENBLSLPM or
288 * GUSB2PHYCFG.SUSPHY is set, it must be cleared before issuing an
291 * Save and clear both GUSB2PHYCFG.ENBLSLPM and GUSB2PHYCFG.SUSPHY
292 * settings. Restore them after the command is completed.
294 * DWC_usb3 3.30a and DWC_usb31 1.90a programming guide section 3.2.2
296 if (dwc->gadget.speed <= USB_SPEED_HIGH) {
297 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
298 if (unlikely(reg & DWC3_GUSB2PHYCFG_SUSPHY)) {
299 saved_config |= DWC3_GUSB2PHYCFG_SUSPHY;
300 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
303 if (reg & DWC3_GUSB2PHYCFG_ENBLSLPM) {
304 saved_config |= DWC3_GUSB2PHYCFG_ENBLSLPM;
305 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
309 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
312 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_STARTTRANSFER) {
315 link_state = dwc3_gadget_get_link_state(dwc);
316 if (link_state == DWC3_LINK_STATE_U1 ||
317 link_state == DWC3_LINK_STATE_U2 ||
318 link_state == DWC3_LINK_STATE_U3) {
319 ret = __dwc3_gadget_wakeup(dwc);
320 dev_WARN_ONCE(dwc->dev, ret, "wakeup failed --> %d\n",
325 dwc3_writel(dep->regs, DWC3_DEPCMDPAR0, params->param0);
326 dwc3_writel(dep->regs, DWC3_DEPCMDPAR1, params->param1);
327 dwc3_writel(dep->regs, DWC3_DEPCMDPAR2, params->param2);
330 * Synopsys Databook 2.60a states in section 6.3.2.5.6 of that if we're
331 * not relying on XferNotReady, we can make use of a special "No
332 * Response Update Transfer" command where we should clear both CmdAct
335 * With this, we don't need to wait for command completion and can
336 * straight away issue further commands to the endpoint.
338 * NOTICE: We're making an assumption that control endpoints will never
339 * make use of Update Transfer command. This is a safe assumption
340 * because we can never have more than one request at a time with
341 * Control Endpoints. If anybody changes that assumption, this chunk
342 * needs to be updated accordingly.
344 if (DWC3_DEPCMD_CMD(cmd) == DWC3_DEPCMD_UPDATETRANSFER &&
345 !usb_endpoint_xfer_isoc(desc))
346 cmd &= ~(DWC3_DEPCMD_CMDIOC | DWC3_DEPCMD_CMDACT);
348 cmd |= DWC3_DEPCMD_CMDACT;
350 dwc3_writel(dep->regs, DWC3_DEPCMD, cmd);
352 reg = dwc3_readl(dep->regs, DWC3_DEPCMD);
353 if (!(reg & DWC3_DEPCMD_CMDACT)) {
354 cmd_status = DWC3_DEPCMD_STATUS(reg);
356 switch (cmd_status) {
360 case DEPEVT_TRANSFER_NO_RESOURCE:
363 case DEPEVT_TRANSFER_BUS_EXPIRY:
365 * SW issues START TRANSFER command to
366 * isochronous ep with future frame interval. If
367 * future interval time has already passed when
368 * core receives the command, it will respond
369 * with an error status of 'Bus Expiry'.
371 * Instead of always returning -EINVAL, let's
372 * give a hint to the gadget driver that this is
373 * the case by returning -EAGAIN.
378 dev_WARN(dwc->dev, "UNKNOWN cmd status\n");
387 cmd_status = -ETIMEDOUT;
390 trace_dwc3_gadget_ep_cmd(dep, cmd, params, cmd_status);
393 switch (DWC3_DEPCMD_CMD(cmd)) {
394 case DWC3_DEPCMD_STARTTRANSFER:
395 dep->flags |= DWC3_EP_TRANSFER_STARTED;
397 case DWC3_DEPCMD_ENDTRANSFER:
398 dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
407 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
409 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
415 static int dwc3_send_clear_stall_ep_cmd(struct dwc3_ep *dep)
417 struct dwc3 *dwc = dep->dwc;
418 struct dwc3_gadget_ep_cmd_params params;
419 u32 cmd = DWC3_DEPCMD_CLEARSTALL;
422 * As of core revision 2.60a the recommended programming model
423 * is to set the ClearPendIN bit when issuing a Clear Stall EP
424 * command for IN endpoints. This is to prevent an issue where
425 * some (non-compliant) hosts may not send ACK TPs for pending
426 * IN transfers due to a mishandled error condition. Synopsys
429 if (dep->direction && (dwc->revision >= DWC3_REVISION_260A) &&
430 (dwc->gadget.speed >= USB_SPEED_SUPER))
431 cmd |= DWC3_DEPCMD_CLEARPENDIN;
433 memset(¶ms, 0, sizeof(params));
435 return dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
438 static dma_addr_t dwc3_trb_dma_offset(struct dwc3_ep *dep,
439 struct dwc3_trb *trb)
441 u32 offset = (char *) trb - (char *) dep->trb_pool;
443 return dep->trb_pool_dma + offset;
446 static int dwc3_alloc_trb_pool(struct dwc3_ep *dep)
448 struct dwc3 *dwc = dep->dwc;
453 dep->trb_pool = dma_alloc_coherent(dwc->sysdev,
454 sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
455 &dep->trb_pool_dma, GFP_KERNEL);
456 if (!dep->trb_pool) {
457 dev_err(dep->dwc->dev, "failed to allocate trb pool for %s\n",
465 static void dwc3_free_trb_pool(struct dwc3_ep *dep)
467 struct dwc3 *dwc = dep->dwc;
469 dma_free_coherent(dwc->sysdev, sizeof(struct dwc3_trb) * DWC3_TRB_NUM,
470 dep->trb_pool, dep->trb_pool_dma);
472 dep->trb_pool = NULL;
473 dep->trb_pool_dma = 0;
476 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep);
479 * dwc3_gadget_start_config - configure ep resources
480 * @dwc: pointer to our controller context structure
481 * @dep: endpoint that is being enabled
483 * Issue a %DWC3_DEPCMD_DEPSTARTCFG command to @dep. After the command's
484 * completion, it will set Transfer Resource for all available endpoints.
486 * The assignment of transfer resources cannot perfectly follow the data book
487 * due to the fact that the controller driver does not have all knowledge of the
488 * configuration in advance. It is given this information piecemeal by the
489 * composite gadget framework after every SET_CONFIGURATION and
490 * SET_INTERFACE. Trying to follow the databook programming model in this
491 * scenario can cause errors. For two reasons:
493 * 1) The databook says to do %DWC3_DEPCMD_DEPSTARTCFG for every
494 * %USB_REQ_SET_CONFIGURATION and %USB_REQ_SET_INTERFACE (8.1.5). This is
495 * incorrect in the scenario of multiple interfaces.
497 * 2) The databook does not mention doing more %DWC3_DEPCMD_DEPXFERCFG for new
498 * endpoint on alt setting (8.1.6).
500 * The following simplified method is used instead:
502 * All hardware endpoints can be assigned a transfer resource and this setting
503 * will stay persistent until either a core reset or hibernation. So whenever we
504 * do a %DWC3_DEPCMD_DEPSTARTCFG(0) we can go ahead and do
505 * %DWC3_DEPCMD_DEPXFERCFG for every hardware endpoint as well. We are
506 * guaranteed that there are as many transfer resources as endpoints.
508 * This function is called for each endpoint when it is being enabled but is
509 * triggered only when called for EP0-out, which always happens first, and which
510 * should only happen in one of the above conditions.
512 static int dwc3_gadget_start_config(struct dwc3 *dwc, struct dwc3_ep *dep)
514 struct dwc3_gadget_ep_cmd_params params;
522 memset(¶ms, 0x00, sizeof(params));
523 cmd = DWC3_DEPCMD_DEPSTARTCFG;
525 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
529 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
530 struct dwc3_ep *dep = dwc->eps[i];
535 ret = dwc3_gadget_set_xfer_resource(dwc, dep);
543 static int dwc3_gadget_set_ep_config(struct dwc3 *dwc, struct dwc3_ep *dep,
544 bool modify, bool restore)
546 const struct usb_ss_ep_comp_descriptor *comp_desc;
547 const struct usb_endpoint_descriptor *desc;
548 struct dwc3_gadget_ep_cmd_params params;
550 if (dev_WARN_ONCE(dwc->dev, modify && restore,
551 "Can't modify and restore\n"))
554 comp_desc = dep->endpoint.comp_desc;
555 desc = dep->endpoint.desc;
557 memset(¶ms, 0x00, sizeof(params));
559 params.param0 = DWC3_DEPCFG_EP_TYPE(usb_endpoint_type(desc))
560 | DWC3_DEPCFG_MAX_PACKET_SIZE(usb_endpoint_maxp(desc));
562 /* Burst size is only needed in SuperSpeed mode */
563 if (dwc->gadget.speed >= USB_SPEED_SUPER) {
564 u32 burst = dep->endpoint.maxburst;
565 params.param0 |= DWC3_DEPCFG_BURST_SIZE(burst - 1);
569 params.param0 |= DWC3_DEPCFG_ACTION_MODIFY;
570 } else if (restore) {
571 params.param0 |= DWC3_DEPCFG_ACTION_RESTORE;
572 params.param2 |= dep->saved_state;
574 params.param0 |= DWC3_DEPCFG_ACTION_INIT;
577 if (usb_endpoint_xfer_control(desc))
578 params.param1 = DWC3_DEPCFG_XFER_COMPLETE_EN;
580 if (dep->number <= 1 || usb_endpoint_xfer_isoc(desc))
581 params.param1 |= DWC3_DEPCFG_XFER_NOT_READY_EN;
583 if (usb_ss_max_streams(comp_desc) && usb_endpoint_xfer_bulk(desc)) {
584 params.param1 |= DWC3_DEPCFG_STREAM_CAPABLE
585 | DWC3_DEPCFG_STREAM_EVENT_EN;
586 dep->stream_capable = true;
589 if (!usb_endpoint_xfer_control(desc))
590 params.param1 |= DWC3_DEPCFG_XFER_IN_PROGRESS_EN;
593 * We are doing 1:1 mapping for endpoints, meaning
594 * Physical Endpoints 2 maps to Logical Endpoint 2 and
595 * so on. We consider the direction bit as part of the physical
596 * endpoint number. So USB endpoint 0x81 is 0x03.
598 params.param1 |= DWC3_DEPCFG_EP_NUMBER(dep->number);
601 * We must use the lower 16 TX FIFOs even though
605 params.param0 |= DWC3_DEPCFG_FIFO_NUMBER(dep->number >> 1);
607 if (desc->bInterval) {
611 * Valid range for DEPCFG.bInterval_m1 is from 0 to 13, and it
612 * must be set to 0 when the controller operates in full-speed.
614 bInterval_m1 = min_t(u8, desc->bInterval - 1, 13);
615 if (dwc->gadget.speed == USB_SPEED_FULL)
618 if (usb_endpoint_type(desc) == USB_ENDPOINT_XFER_INT &&
619 dwc->gadget.speed == USB_SPEED_FULL)
620 dep->interval = desc->bInterval;
622 dep->interval = 1 << (desc->bInterval - 1);
624 params.param1 |= DWC3_DEPCFG_BINTERVAL_M1(bInterval_m1);
627 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETEPCONFIG, ¶ms);
630 static int dwc3_gadget_set_xfer_resource(struct dwc3 *dwc, struct dwc3_ep *dep)
632 struct dwc3_gadget_ep_cmd_params params;
634 memset(¶ms, 0x00, sizeof(params));
636 params.param0 = DWC3_DEPXFERCFG_NUM_XFER_RES(1);
638 return dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETTRANSFRESOURCE,
643 * __dwc3_gadget_ep_enable - initializes a hw endpoint
644 * @dep: endpoint to be initialized
645 * @modify: if true, modify existing endpoint configuration
646 * @restore: if true, restore endpoint configuration from scratch buffer
648 * Caller should take care of locking. Execute all necessary commands to
649 * initialize a HW endpoint so it can be used by a gadget driver.
651 static int __dwc3_gadget_ep_enable(struct dwc3_ep *dep,
652 bool modify, bool restore)
654 const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
655 struct dwc3 *dwc = dep->dwc;
660 if (!(dep->flags & DWC3_EP_ENABLED)) {
661 ret = dwc3_gadget_start_config(dwc, dep);
666 ret = dwc3_gadget_set_ep_config(dwc, dep, modify, restore);
670 if (!(dep->flags & DWC3_EP_ENABLED)) {
671 struct dwc3_trb *trb_st_hw;
672 struct dwc3_trb *trb_link;
674 dep->type = usb_endpoint_type(desc);
675 dep->flags |= DWC3_EP_ENABLED;
676 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
678 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
679 reg |= DWC3_DALEPENA_EP(dep->number);
680 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
682 init_waitqueue_head(&dep->wait_end_transfer);
684 if (usb_endpoint_xfer_control(desc))
687 /* Initialize the TRB ring */
688 dep->trb_dequeue = 0;
689 dep->trb_enqueue = 0;
690 memset(dep->trb_pool, 0,
691 sizeof(struct dwc3_trb) * DWC3_TRB_NUM);
693 /* Link TRB. The HWO bit is never reset */
694 trb_st_hw = &dep->trb_pool[0];
696 trb_link = &dep->trb_pool[DWC3_TRB_NUM - 1];
697 trb_link->bpl = lower_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
698 trb_link->bph = upper_32_bits(dwc3_trb_dma_offset(dep, trb_st_hw));
699 trb_link->ctrl |= DWC3_TRBCTL_LINK_TRB;
700 trb_link->ctrl |= DWC3_TRB_CTRL_HWO;
704 * Issue StartTransfer here with no-op TRB so we can always rely on No
705 * Response Update Transfer command.
707 if (usb_endpoint_xfer_bulk(desc)) {
708 struct dwc3_gadget_ep_cmd_params params;
709 struct dwc3_trb *trb;
713 memset(¶ms, 0, sizeof(params));
714 trb = &dep->trb_pool[0];
715 trb_dma = dwc3_trb_dma_offset(dep, trb);
717 params.param0 = upper_32_bits(trb_dma);
718 params.param1 = lower_32_bits(trb_dma);
720 cmd = DWC3_DEPCMD_STARTTRANSFER;
722 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
726 dep->flags |= DWC3_EP_BUSY;
728 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
729 WARN_ON_ONCE(!dep->resource_index);
734 trace_dwc3_gadget_ep_enable(dep);
739 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force);
740 static void dwc3_remove_requests(struct dwc3 *dwc, struct dwc3_ep *dep)
742 struct dwc3_request *req;
744 dwc3_stop_active_transfer(dwc, dep->number, true);
746 /* - giveback all requests to gadget driver */
747 while (!list_empty(&dep->started_list)) {
748 req = next_request(&dep->started_list);
750 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
753 while (!list_empty(&dep->pending_list)) {
754 req = next_request(&dep->pending_list);
756 dwc3_gadget_giveback(dep, req, -ESHUTDOWN);
761 * __dwc3_gadget_ep_disable - disables a hw endpoint
762 * @dep: the endpoint to disable
764 * This function undoes what __dwc3_gadget_ep_enable did and also removes
765 * requests which are currently being processed by the hardware and those which
766 * are not yet scheduled.
768 * Caller should take care of locking.
770 static int __dwc3_gadget_ep_disable(struct dwc3_ep *dep)
772 struct dwc3 *dwc = dep->dwc;
775 trace_dwc3_gadget_ep_disable(dep);
777 dwc3_remove_requests(dwc, dep);
779 /* make sure HW endpoint isn't stalled */
780 if (dep->flags & DWC3_EP_STALL)
781 __dwc3_gadget_ep_set_halt(dep, 0, false);
783 reg = dwc3_readl(dwc->regs, DWC3_DALEPENA);
784 reg &= ~DWC3_DALEPENA_EP(dep->number);
785 dwc3_writel(dwc->regs, DWC3_DALEPENA, reg);
787 dep->stream_capable = false;
789 dep->flags &= DWC3_EP_END_TRANSFER_PENDING;
791 /* Clear out the ep descriptors for non-ep0 */
792 if (dep->number > 1) {
793 dep->endpoint.comp_desc = NULL;
794 dep->endpoint.desc = NULL;
800 /* -------------------------------------------------------------------------- */
802 static int dwc3_gadget_ep0_enable(struct usb_ep *ep,
803 const struct usb_endpoint_descriptor *desc)
808 static int dwc3_gadget_ep0_disable(struct usb_ep *ep)
813 /* -------------------------------------------------------------------------- */
815 static int dwc3_gadget_ep_enable(struct usb_ep *ep,
816 const struct usb_endpoint_descriptor *desc)
823 if (!ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT) {
824 pr_debug("dwc3: invalid parameters\n");
828 if (!desc->wMaxPacketSize) {
829 pr_debug("dwc3: missing wMaxPacketSize\n");
833 dep = to_dwc3_ep(ep);
836 if (dev_WARN_ONCE(dwc->dev, dep->flags & DWC3_EP_ENABLED,
837 "%s is already enabled\n",
841 spin_lock_irqsave(&dwc->lock, flags);
842 ret = __dwc3_gadget_ep_enable(dep, false, false);
843 spin_unlock_irqrestore(&dwc->lock, flags);
848 static int dwc3_gadget_ep_disable(struct usb_ep *ep)
856 pr_debug("dwc3: invalid parameters\n");
860 dep = to_dwc3_ep(ep);
863 if (dev_WARN_ONCE(dwc->dev, !(dep->flags & DWC3_EP_ENABLED),
864 "%s is already disabled\n",
868 spin_lock_irqsave(&dwc->lock, flags);
869 ret = __dwc3_gadget_ep_disable(dep);
870 spin_unlock_irqrestore(&dwc->lock, flags);
875 static struct usb_request *dwc3_gadget_ep_alloc_request(struct usb_ep *ep,
878 struct dwc3_request *req;
879 struct dwc3_ep *dep = to_dwc3_ep(ep);
881 req = kzalloc(sizeof(*req), gfp_flags);
885 req->epnum = dep->number;
888 dep->allocated_requests++;
890 trace_dwc3_alloc_request(req);
892 return &req->request;
895 static void dwc3_gadget_ep_free_request(struct usb_ep *ep,
896 struct usb_request *request)
898 struct dwc3_request *req = to_dwc3_request(request);
899 struct dwc3_ep *dep = to_dwc3_ep(ep);
901 dep->allocated_requests--;
902 trace_dwc3_free_request(req);
906 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep);
908 static void __dwc3_prepare_one_trb(struct dwc3_ep *dep, struct dwc3_trb *trb,
909 dma_addr_t dma, unsigned length, unsigned chain, unsigned node,
910 unsigned stream_id, unsigned short_not_ok, unsigned no_interrupt)
912 struct dwc3 *dwc = dep->dwc;
913 struct usb_gadget *gadget = &dwc->gadget;
914 enum usb_device_speed speed = gadget->speed;
916 trb->size = DWC3_TRB_SIZE_LENGTH(length);
917 trb->bpl = lower_32_bits(dma);
918 trb->bph = upper_32_bits(dma);
920 switch (usb_endpoint_type(dep->endpoint.desc)) {
921 case USB_ENDPOINT_XFER_CONTROL:
922 trb->ctrl = DWC3_TRBCTL_CONTROL_SETUP;
925 case USB_ENDPOINT_XFER_ISOC:
927 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS_FIRST;
930 * USB Specification 2.0 Section 5.9.2 states that: "If
931 * there is only a single transaction in the microframe,
932 * only a DATA0 data packet PID is used. If there are
933 * two transactions per microframe, DATA1 is used for
934 * the first transaction data packet and DATA0 is used
935 * for the second transaction data packet. If there are
936 * three transactions per microframe, DATA2 is used for
937 * the first transaction data packet, DATA1 is used for
938 * the second, and DATA0 is used for the third."
940 * IOW, we should satisfy the following cases:
942 * 1) length <= maxpacket
945 * 2) maxpacket < length <= (2 * maxpacket)
948 * 3) (2 * maxpacket) < length <= (3 * maxpacket)
949 * - DATA2, DATA1, DATA0
951 if (speed == USB_SPEED_HIGH) {
952 struct usb_ep *ep = &dep->endpoint;
953 unsigned int mult = ep->mult - 1;
954 unsigned int maxp = usb_endpoint_maxp(ep->desc);
956 if (length <= (2 * maxp))
962 trb->size |= DWC3_TRB_SIZE_PCM1(mult);
965 trb->ctrl = DWC3_TRBCTL_ISOCHRONOUS;
968 /* always enable Interrupt on Missed ISOC */
969 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
972 case USB_ENDPOINT_XFER_BULK:
973 case USB_ENDPOINT_XFER_INT:
974 trb->ctrl = DWC3_TRBCTL_NORMAL;
978 * This is only possible with faulty memory because we
979 * checked it already :)
981 dev_WARN(dwc->dev, "Unknown endpoint type %d\n",
982 usb_endpoint_type(dep->endpoint.desc));
986 * Enable Continue on Short Packet
987 * when endpoint is not a stream capable
989 if (usb_endpoint_dir_out(dep->endpoint.desc)) {
990 if (!dep->stream_capable)
991 trb->ctrl |= DWC3_TRB_CTRL_CSP;
994 trb->ctrl |= DWC3_TRB_CTRL_ISP_IMI;
997 if ((!no_interrupt && !chain) ||
998 (dwc3_calc_trbs_left(dep) == 1))
999 trb->ctrl |= DWC3_TRB_CTRL_IOC;
1002 trb->ctrl |= DWC3_TRB_CTRL_CHN;
1004 if (usb_endpoint_xfer_bulk(dep->endpoint.desc) && dep->stream_capable)
1005 trb->ctrl |= DWC3_TRB_CTRL_SID_SOFN(stream_id);
1008 * As per data book 4.2.3.2TRB Control Bit Rules section
1010 * The controller autonomously checks the HWO field of a TRB to determine if the
1011 * entire TRB is valid. Therefore, software must ensure that the rest of the TRB
1012 * is valid before setting the HWO field to '1'. In most systems, this means that
1013 * software must update the fourth DWORD of a TRB last.
1015 * However there is a possibility of CPU re-ordering here which can cause
1016 * controller to observe the HWO bit set prematurely.
1017 * Add a write memory barrier to prevent CPU re-ordering.
1020 trb->ctrl |= DWC3_TRB_CTRL_HWO;
1022 dwc3_ep_inc_enq(dep);
1024 trace_dwc3_prepare_trb(dep, trb);
1028 * dwc3_prepare_one_trb - setup one TRB from one request
1029 * @dep: endpoint for which this request is prepared
1030 * @req: dwc3_request pointer
1031 * @chain: should this TRB be chained to the next?
1032 * @node: only for isochronous endpoints. First TRB needs different type.
1034 static void dwc3_prepare_one_trb(struct dwc3_ep *dep,
1035 struct dwc3_request *req, unsigned chain, unsigned node)
1037 struct dwc3_trb *trb;
1038 unsigned length = req->request.length;
1039 unsigned stream_id = req->request.stream_id;
1040 unsigned short_not_ok = req->request.short_not_ok;
1041 unsigned no_interrupt = req->request.no_interrupt;
1042 dma_addr_t dma = req->request.dma;
1044 trb = &dep->trb_pool[dep->trb_enqueue];
1047 dwc3_gadget_move_started_request(req);
1049 req->trb_dma = dwc3_trb_dma_offset(dep, trb);
1050 dep->queued_requests++;
1053 __dwc3_prepare_one_trb(dep, trb, dma, length, chain, node,
1054 stream_id, short_not_ok, no_interrupt);
1058 * dwc3_ep_prev_trb - returns the previous TRB in the ring
1059 * @dep: The endpoint with the TRB ring
1060 * @index: The index of the current TRB in the ring
1062 * Returns the TRB prior to the one pointed to by the index. If the
1063 * index is 0, we will wrap backwards, skip the link TRB, and return
1064 * the one just before that.
1066 static struct dwc3_trb *dwc3_ep_prev_trb(struct dwc3_ep *dep, u8 index)
1071 tmp = DWC3_TRB_NUM - 1;
1073 return &dep->trb_pool[tmp - 1];
1076 static u32 dwc3_calc_trbs_left(struct dwc3_ep *dep)
1081 * If the enqueue & dequeue are equal then the TRB ring is either full
1082 * or empty. It's considered full when there are DWC3_TRB_NUM-1 of TRBs
1083 * pending to be processed by the driver.
1085 if (dep->trb_enqueue == dep->trb_dequeue) {
1087 * If there is any request remained in the started_list at
1088 * this point, that means there is no TRB available.
1090 if (!list_empty(&dep->started_list))
1093 return DWC3_TRB_NUM - 1;
1096 trbs_left = dep->trb_dequeue - dep->trb_enqueue;
1097 trbs_left &= (DWC3_TRB_NUM - 1);
1099 if (dep->trb_dequeue < dep->trb_enqueue)
1105 static void dwc3_prepare_one_trb_sg(struct dwc3_ep *dep,
1106 struct dwc3_request *req)
1108 struct scatterlist *sg = req->sg;
1109 struct scatterlist *s;
1112 for_each_sg(sg, s, req->num_pending_sgs, i) {
1113 unsigned int length = req->request.length;
1114 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1115 unsigned int rem = length % maxp;
1116 unsigned chain = true;
1121 if (rem && usb_endpoint_dir_out(dep->endpoint.desc) && !chain) {
1122 struct dwc3 *dwc = dep->dwc;
1123 struct dwc3_trb *trb;
1125 req->unaligned = true;
1127 /* prepare normal TRB */
1128 dwc3_prepare_one_trb(dep, req, true, i);
1130 /* Now prepare one extra TRB to align transfer size */
1131 trb = &dep->trb_pool[dep->trb_enqueue];
1132 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr,
1133 maxp - rem, false, 1,
1134 req->request.stream_id,
1135 req->request.short_not_ok,
1136 req->request.no_interrupt);
1138 dwc3_prepare_one_trb(dep, req, chain, i);
1141 if (!dwc3_calc_trbs_left(dep))
1146 static void dwc3_prepare_one_trb_linear(struct dwc3_ep *dep,
1147 struct dwc3_request *req)
1149 unsigned int length = req->request.length;
1150 unsigned int maxp = usb_endpoint_maxp(dep->endpoint.desc);
1151 unsigned int rem = length % maxp;
1153 if ((!length || rem) && usb_endpoint_dir_out(dep->endpoint.desc)) {
1154 struct dwc3 *dwc = dep->dwc;
1155 struct dwc3_trb *trb;
1157 req->unaligned = true;
1159 /* prepare normal TRB */
1160 dwc3_prepare_one_trb(dep, req, true, 0);
1162 /* Now prepare one extra TRB to align transfer size */
1163 trb = &dep->trb_pool[dep->trb_enqueue];
1164 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, maxp - rem,
1165 false, 1, req->request.stream_id,
1166 req->request.short_not_ok,
1167 req->request.no_interrupt);
1168 } else if (req->request.zero && req->request.length &&
1169 (IS_ALIGNED(req->request.length,dep->endpoint.maxpacket))) {
1170 struct dwc3 *dwc = dep->dwc;
1171 struct dwc3_trb *trb;
1175 /* prepare normal TRB */
1176 dwc3_prepare_one_trb(dep, req, true, 0);
1178 /* Now prepare one extra TRB to handle ZLP */
1179 trb = &dep->trb_pool[dep->trb_enqueue];
1180 __dwc3_prepare_one_trb(dep, trb, dwc->bounce_addr, 0,
1181 false, 1, req->request.stream_id,
1182 req->request.short_not_ok,
1183 req->request.no_interrupt);
1185 dwc3_prepare_one_trb(dep, req, false, 0);
1190 * dwc3_prepare_trbs - setup TRBs from requests
1191 * @dep: endpoint for which requests are being prepared
1193 * The function goes through the requests list and sets up TRBs for the
1194 * transfers. The function returns once there are no more TRBs available or
1195 * it runs out of requests.
1197 static void dwc3_prepare_trbs(struct dwc3_ep *dep)
1199 struct dwc3_request *req, *n;
1201 BUILD_BUG_ON_NOT_POWER_OF_2(DWC3_TRB_NUM);
1203 if (!dwc3_calc_trbs_left(dep))
1207 * We can get in a situation where there's a request in the started list
1208 * but there weren't enough TRBs to fully kick it in the first time
1209 * around, so it has been waiting for more TRBs to be freed up.
1211 * In that case, we should check if we have a request with pending_sgs
1212 * in the started list and prepare TRBs for that request first,
1213 * otherwise we will prepare TRBs completely out of order and that will
1216 list_for_each_entry(req, &dep->started_list, list) {
1217 if (req->num_pending_sgs > 0)
1218 dwc3_prepare_one_trb_sg(dep, req);
1220 if (!dwc3_calc_trbs_left(dep))
1224 list_for_each_entry_safe(req, n, &dep->pending_list, list) {
1225 struct dwc3 *dwc = dep->dwc;
1228 ret = usb_gadget_map_request_by_dev(dwc->sysdev, &req->request,
1233 req->sg = req->request.sg;
1234 req->num_pending_sgs = req->request.num_mapped_sgs;
1236 if (req->num_pending_sgs > 0)
1237 dwc3_prepare_one_trb_sg(dep, req);
1239 dwc3_prepare_one_trb_linear(dep, req);
1241 if (!dwc3_calc_trbs_left(dep))
1246 static int __dwc3_gadget_kick_transfer(struct dwc3_ep *dep, u16 cmd_param)
1248 struct dwc3_gadget_ep_cmd_params params;
1249 struct dwc3_request *req;
1254 starting = !(dep->flags & DWC3_EP_BUSY);
1256 dwc3_prepare_trbs(dep);
1257 req = next_request(&dep->started_list);
1259 dep->flags |= DWC3_EP_PENDING_REQUEST;
1263 memset(¶ms, 0, sizeof(params));
1266 params.param0 = upper_32_bits(req->trb_dma);
1267 params.param1 = lower_32_bits(req->trb_dma);
1268 cmd = DWC3_DEPCMD_STARTTRANSFER |
1269 DWC3_DEPCMD_PARAM(cmd_param);
1271 cmd = DWC3_DEPCMD_UPDATETRANSFER |
1272 DWC3_DEPCMD_PARAM(dep->resource_index);
1275 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
1278 * FIXME we need to iterate over the list of requests
1279 * here and stop, unmap, free and del each of the linked
1280 * requests instead of what we do now.
1283 memset(req->trb, 0, sizeof(struct dwc3_trb));
1284 dep->queued_requests--;
1285 dwc3_gadget_del_and_unmap_request(dep, req, ret);
1289 dep->flags |= DWC3_EP_BUSY;
1292 dep->resource_index = dwc3_gadget_ep_get_transfer_index(dep);
1293 WARN_ON_ONCE(!dep->resource_index);
1299 static int __dwc3_gadget_get_frame(struct dwc3 *dwc)
1303 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1304 return DWC3_DSTS_SOFFN(reg);
1307 static void __dwc3_gadget_start_isoc(struct dwc3 *dwc,
1308 struct dwc3_ep *dep, u32 cur_uf)
1312 if (list_empty(&dep->pending_list)) {
1313 dev_info(dwc->dev, "%s: ran out of requests\n",
1315 dep->flags |= DWC3_EP_PENDING_REQUEST;
1320 * Schedule the first trb for one interval in the future or at
1321 * least 4 microframes.
1323 uf = cur_uf + max_t(u32, 4, dep->interval);
1325 __dwc3_gadget_kick_transfer(dep, uf);
1328 static void dwc3_gadget_start_isoc(struct dwc3 *dwc,
1329 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
1333 mask = ~(dep->interval - 1);
1334 cur_uf = event->parameters & mask;
1336 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1339 static int __dwc3_gadget_ep_queue(struct dwc3_ep *dep, struct dwc3_request *req)
1341 struct dwc3 *dwc = dep->dwc;
1344 if (!dep->endpoint.desc) {
1345 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
1350 if (WARN(req->dep != dep, "request %pK belongs to '%s'\n",
1351 &req->request, req->dep->name))
1354 pm_runtime_get(dwc->dev);
1356 req->request.actual = 0;
1357 req->request.status = -EINPROGRESS;
1358 req->direction = dep->direction;
1359 req->epnum = dep->number;
1361 trace_dwc3_ep_queue(req);
1363 list_add_tail(&req->list, &dep->pending_list);
1366 * NOTICE: Isochronous endpoints should NEVER be prestarted. We must
1367 * wait for a XferNotReady event so we will know what's the current
1368 * (micro-)frame number.
1370 * Without this trick, we are very, very likely gonna get Bus Expiry
1371 * errors which will force us issue EndTransfer command.
1373 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1374 if ((dep->flags & DWC3_EP_PENDING_REQUEST)) {
1375 if (dep->flags & DWC3_EP_TRANSFER_STARTED) {
1376 dwc3_stop_active_transfer(dwc, dep->number, true);
1377 dep->flags = DWC3_EP_ENABLED;
1381 cur_uf = __dwc3_gadget_get_frame(dwc);
1382 __dwc3_gadget_start_isoc(dwc, dep, cur_uf);
1383 dep->flags &= ~DWC3_EP_PENDING_REQUEST;
1388 if ((dep->flags & DWC3_EP_BUSY) &&
1389 !(dep->flags & DWC3_EP_MISSED_ISOC)) {
1390 WARN_ON_ONCE(!dep->resource_index);
1391 ret = __dwc3_gadget_kick_transfer(dep,
1392 dep->resource_index);
1398 if (!dwc3_calc_trbs_left(dep))
1401 ret = __dwc3_gadget_kick_transfer(dep, 0);
1409 static int dwc3_gadget_ep_queue(struct usb_ep *ep, struct usb_request *request,
1412 struct dwc3_request *req = to_dwc3_request(request);
1413 struct dwc3_ep *dep = to_dwc3_ep(ep);
1414 struct dwc3 *dwc = dep->dwc;
1416 unsigned long flags;
1420 spin_lock_irqsave(&dwc->lock, flags);
1421 ret = __dwc3_gadget_ep_queue(dep, req);
1422 spin_unlock_irqrestore(&dwc->lock, flags);
1427 static int dwc3_gadget_ep_dequeue(struct usb_ep *ep,
1428 struct usb_request *request)
1430 struct dwc3_request *req = to_dwc3_request(request);
1431 struct dwc3_request *r = NULL;
1433 struct dwc3_ep *dep = to_dwc3_ep(ep);
1434 struct dwc3 *dwc = dep->dwc;
1436 unsigned long flags;
1439 trace_dwc3_ep_dequeue(req);
1441 spin_lock_irqsave(&dwc->lock, flags);
1443 list_for_each_entry(r, &dep->pending_list, list) {
1449 list_for_each_entry(r, &dep->started_list, list) {
1454 /* wait until it is processed */
1455 dwc3_stop_active_transfer(dwc, dep->number, true);
1458 * If request was already started, this means we had to
1459 * stop the transfer. With that we also need to ignore
1460 * all TRBs used by the request, however TRBs can only
1461 * be modified after completion of END_TRANSFER
1462 * command. So what we do here is that we wait for
1463 * END_TRANSFER completion and only after that, we jump
1464 * over TRBs by clearing HWO and incrementing dequeue
1467 * Note that we have 2 possible types of transfers here:
1469 * i) Linear buffer request
1470 * ii) SG-list based request
1472 * SG-list based requests will have r->num_pending_sgs
1473 * set to a valid number (> 0). Linear requests,
1474 * normally use a single TRB.
1476 * For each of these two cases, if r->unaligned flag is
1477 * set, one extra TRB has been used to align transfer
1478 * size to wMaxPacketSize.
1480 * All of these cases need to be taken into
1481 * consideration so we don't mess up our TRB ring
1484 wait_event_lock_irq(dep->wait_end_transfer,
1485 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
1491 if (r->num_pending_sgs) {
1492 struct dwc3_trb *trb;
1495 for (i = 0; i < r->num_pending_sgs; i++) {
1497 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1498 dwc3_ep_inc_deq(dep);
1501 if (r->unaligned || r->zero) {
1502 trb = r->trb + r->num_pending_sgs + 1;
1503 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1504 dwc3_ep_inc_deq(dep);
1507 struct dwc3_trb *trb = r->trb;
1509 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1510 dwc3_ep_inc_deq(dep);
1512 if (r->unaligned || r->zero) {
1514 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
1515 dwc3_ep_inc_deq(dep);
1520 dev_err(dwc->dev, "request %pK was not queued to %s\n",
1527 /* giveback the request */
1528 dep->queued_requests--;
1529 dwc3_gadget_giveback(dep, req, -ECONNRESET);
1532 spin_unlock_irqrestore(&dwc->lock, flags);
1537 int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value, int protocol)
1539 struct dwc3_gadget_ep_cmd_params params;
1540 struct dwc3 *dwc = dep->dwc;
1543 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
1544 dev_err(dwc->dev, "%s is of Isochronous type\n", dep->name);
1548 memset(¶ms, 0x00, sizeof(params));
1551 struct dwc3_trb *trb;
1553 unsigned transfer_in_flight;
1556 if (dep->number > 1)
1557 trb = dwc3_ep_prev_trb(dep, dep->trb_enqueue);
1559 trb = &dwc->ep0_trb[dep->trb_enqueue];
1561 transfer_in_flight = trb->ctrl & DWC3_TRB_CTRL_HWO;
1562 started = !list_empty(&dep->started_list);
1564 if (!protocol && ((dep->direction && transfer_in_flight) ||
1565 (!dep->direction && started))) {
1569 ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_SETSTALL,
1572 dev_err(dwc->dev, "failed to set STALL on %s\n",
1575 dep->flags |= DWC3_EP_STALL;
1578 ret = dwc3_send_clear_stall_ep_cmd(dep);
1580 dev_err(dwc->dev, "failed to clear STALL on %s\n",
1583 dep->flags &= ~(DWC3_EP_STALL | DWC3_EP_WEDGE);
1589 static int dwc3_gadget_ep_set_halt(struct usb_ep *ep, int value)
1591 struct dwc3_ep *dep = to_dwc3_ep(ep);
1592 struct dwc3 *dwc = dep->dwc;
1594 unsigned long flags;
1598 spin_lock_irqsave(&dwc->lock, flags);
1599 ret = __dwc3_gadget_ep_set_halt(dep, value, false);
1600 spin_unlock_irqrestore(&dwc->lock, flags);
1605 static int dwc3_gadget_ep_set_wedge(struct usb_ep *ep)
1607 struct dwc3_ep *dep = to_dwc3_ep(ep);
1608 struct dwc3 *dwc = dep->dwc;
1609 unsigned long flags;
1612 spin_lock_irqsave(&dwc->lock, flags);
1613 dep->flags |= DWC3_EP_WEDGE;
1615 if (dep->number == 0 || dep->number == 1)
1616 ret = __dwc3_gadget_ep0_set_halt(ep, 1);
1618 ret = __dwc3_gadget_ep_set_halt(dep, 1, false);
1619 spin_unlock_irqrestore(&dwc->lock, flags);
1624 /* -------------------------------------------------------------------------- */
1626 static struct usb_endpoint_descriptor dwc3_gadget_ep0_desc = {
1627 .bLength = USB_DT_ENDPOINT_SIZE,
1628 .bDescriptorType = USB_DT_ENDPOINT,
1629 .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
1632 static const struct usb_ep_ops dwc3_gadget_ep0_ops = {
1633 .enable = dwc3_gadget_ep0_enable,
1634 .disable = dwc3_gadget_ep0_disable,
1635 .alloc_request = dwc3_gadget_ep_alloc_request,
1636 .free_request = dwc3_gadget_ep_free_request,
1637 .queue = dwc3_gadget_ep0_queue,
1638 .dequeue = dwc3_gadget_ep_dequeue,
1639 .set_halt = dwc3_gadget_ep0_set_halt,
1640 .set_wedge = dwc3_gadget_ep_set_wedge,
1643 static const struct usb_ep_ops dwc3_gadget_ep_ops = {
1644 .enable = dwc3_gadget_ep_enable,
1645 .disable = dwc3_gadget_ep_disable,
1646 .alloc_request = dwc3_gadget_ep_alloc_request,
1647 .free_request = dwc3_gadget_ep_free_request,
1648 .queue = dwc3_gadget_ep_queue,
1649 .dequeue = dwc3_gadget_ep_dequeue,
1650 .set_halt = dwc3_gadget_ep_set_halt,
1651 .set_wedge = dwc3_gadget_ep_set_wedge,
1654 /* -------------------------------------------------------------------------- */
1656 static int dwc3_gadget_get_frame(struct usb_gadget *g)
1658 struct dwc3 *dwc = gadget_to_dwc(g);
1660 return __dwc3_gadget_get_frame(dwc);
1663 static int __dwc3_gadget_wakeup(struct dwc3 *dwc)
1673 * According to the Databook Remote wakeup request should
1674 * be issued only when the device is in early suspend state.
1676 * We can check that via USB Link State bits in DSTS register.
1678 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1680 link_state = DWC3_DSTS_USBLNKST(reg);
1682 switch (link_state) {
1683 case DWC3_LINK_STATE_RESET:
1684 case DWC3_LINK_STATE_RX_DET: /* in HS, means Early Suspend */
1685 case DWC3_LINK_STATE_U3: /* in HS, means SUSPEND */
1686 case DWC3_LINK_STATE_U2: /* in HS, means Sleep (L1) */
1687 case DWC3_LINK_STATE_U1:
1688 case DWC3_LINK_STATE_RESUME:
1694 ret = dwc3_gadget_set_link_state(dwc, DWC3_LINK_STATE_RECOV);
1696 dev_err(dwc->dev, "failed to put link in Recovery\n");
1700 /* Recent versions do this automatically */
1701 if (dwc->revision < DWC3_REVISION_194A) {
1702 /* write zeroes to Link Change Request */
1703 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1704 reg &= ~DWC3_DCTL_ULSTCHNGREQ_MASK;
1705 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1708 /* poll until Link State changes to ON */
1712 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1714 /* in HS, means ON */
1715 if (DWC3_DSTS_USBLNKST(reg) == DWC3_LINK_STATE_U0)
1719 if (DWC3_DSTS_USBLNKST(reg) != DWC3_LINK_STATE_U0) {
1720 dev_err(dwc->dev, "failed to send remote wakeup\n");
1727 static int dwc3_gadget_wakeup(struct usb_gadget *g)
1729 struct dwc3 *dwc = gadget_to_dwc(g);
1730 unsigned long flags;
1733 spin_lock_irqsave(&dwc->lock, flags);
1734 ret = __dwc3_gadget_wakeup(dwc);
1735 spin_unlock_irqrestore(&dwc->lock, flags);
1740 static int dwc3_gadget_set_selfpowered(struct usb_gadget *g,
1743 struct dwc3 *dwc = gadget_to_dwc(g);
1744 unsigned long flags;
1746 spin_lock_irqsave(&dwc->lock, flags);
1747 g->is_selfpowered = !!is_selfpowered;
1748 spin_unlock_irqrestore(&dwc->lock, flags);
1753 static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend)
1758 if (pm_runtime_suspended(dwc->dev))
1761 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
1763 if (dwc->revision <= DWC3_REVISION_187A) {
1764 reg &= ~DWC3_DCTL_TRGTULST_MASK;
1765 reg |= DWC3_DCTL_TRGTULST_RX_DET;
1768 if (dwc->revision >= DWC3_REVISION_194A)
1769 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1770 reg |= DWC3_DCTL_RUN_STOP;
1772 if (dwc->has_hibernation)
1773 reg |= DWC3_DCTL_KEEP_CONNECT;
1775 dwc->pullups_connected = true;
1777 reg &= ~DWC3_DCTL_RUN_STOP;
1779 if (dwc->has_hibernation && !suspend)
1780 reg &= ~DWC3_DCTL_KEEP_CONNECT;
1782 dwc->pullups_connected = false;
1785 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
1788 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
1789 reg &= DWC3_DSTS_DEVCTRLHLT;
1790 } while (--timeout && !(!is_on ^ !reg));
1798 static int dwc3_gadget_pullup(struct usb_gadget *g, int is_on)
1800 struct dwc3 *dwc = gadget_to_dwc(g);
1801 unsigned long flags;
1807 * Per databook, when we want to stop the gadget, if a control transfer
1808 * is still in process, complete it and get the core into setup phase.
1810 if (!is_on && dwc->ep0state != EP0_SETUP_PHASE) {
1811 reinit_completion(&dwc->ep0_in_setup);
1813 ret = wait_for_completion_timeout(&dwc->ep0_in_setup,
1814 msecs_to_jiffies(DWC3_PULL_UP_TIMEOUT));
1816 dev_warn(dwc->dev, "timed out waiting for SETUP phase\n");
1819 spin_lock_irqsave(&dwc->lock, flags);
1820 ret = dwc3_gadget_run_stop(dwc, is_on, false);
1821 spin_unlock_irqrestore(&dwc->lock, flags);
1826 static void dwc3_gadget_enable_irq(struct dwc3 *dwc)
1830 /* Enable all but Start and End of Frame IRQs */
1831 reg = (DWC3_DEVTEN_VNDRDEVTSTRCVEDEN |
1832 DWC3_DEVTEN_EVNTOVERFLOWEN |
1833 DWC3_DEVTEN_CMDCMPLTEN |
1834 DWC3_DEVTEN_ERRTICERREN |
1835 DWC3_DEVTEN_WKUPEVTEN |
1836 DWC3_DEVTEN_CONNECTDONEEN |
1837 DWC3_DEVTEN_USBRSTEN |
1838 DWC3_DEVTEN_DISCONNEVTEN);
1840 if (dwc->revision < DWC3_REVISION_250A)
1841 reg |= DWC3_DEVTEN_ULSTCNGEN;
1843 /* On 2.30a and above this bit enables U3/L2-L1 Suspend Events */
1844 if (dwc->revision >= DWC3_REVISION_230A)
1845 reg |= DWC3_DEVTEN_EOPFEN;
1847 dwc3_writel(dwc->regs, DWC3_DEVTEN, reg);
1850 static void dwc3_gadget_disable_irq(struct dwc3 *dwc)
1852 /* mask all interrupts */
1853 dwc3_writel(dwc->regs, DWC3_DEVTEN, 0x00);
1856 static irqreturn_t dwc3_interrupt(int irq, void *_dwc);
1857 static irqreturn_t dwc3_thread_interrupt(int irq, void *_dwc);
1860 * dwc3_gadget_setup_nump - calculate and initialize NUMP field of %DWC3_DCFG
1861 * @dwc: pointer to our context structure
1863 * The following looks like complex but it's actually very simple. In order to
1864 * calculate the number of packets we can burst at once on OUT transfers, we're
1865 * gonna use RxFIFO size.
1867 * To calculate RxFIFO size we need two numbers:
1868 * MDWIDTH = size, in bits, of the internal memory bus
1869 * RAM2_DEPTH = depth, in MDWIDTH, of internal RAM2 (where RxFIFO sits)
1871 * Given these two numbers, the formula is simple:
1873 * RxFIFO Size = (RAM2_DEPTH * MDWIDTH / 8) - 24 - 16;
1875 * 24 bytes is for 3x SETUP packets
1876 * 16 bytes is a clock domain crossing tolerance
1878 * Given RxFIFO Size, NUMP = RxFIFOSize / 1024;
1880 static void dwc3_gadget_setup_nump(struct dwc3 *dwc)
1887 ram2_depth = DWC3_GHWPARAMS7_RAM2_DEPTH(dwc->hwparams.hwparams7);
1888 mdwidth = DWC3_GHWPARAMS0_MDWIDTH(dwc->hwparams.hwparams0);
1890 nump = ((ram2_depth * mdwidth / 8) - 24 - 16) / 1024;
1891 nump = min_t(u32, nump, 16);
1894 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
1895 reg &= ~DWC3_DCFG_NUMP_MASK;
1896 reg |= nump << DWC3_DCFG_NUMP_SHIFT;
1897 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
1900 static int __dwc3_gadget_start(struct dwc3 *dwc)
1902 struct dwc3_ep *dep;
1907 * Use IMOD if enabled via dwc->imod_interval. Otherwise, if
1908 * the core supports IMOD, disable it.
1910 if (dwc->imod_interval) {
1911 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
1912 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
1913 } else if (dwc3_has_imod(dwc)) {
1914 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), 0);
1918 * We are telling dwc3 that we want to use DCFG.NUMP as ACK TP's NUMP
1919 * field instead of letting dwc3 itself calculate that automatically.
1921 * This way, we maximize the chances that we'll be able to get several
1922 * bursts of data without going through any sort of endpoint throttling.
1924 reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1925 reg &= ~DWC3_GRXTHRCFG_PKTCNTSEL;
1926 dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1928 dwc3_gadget_setup_nump(dwc);
1930 /* Start with SuperSpeed Default */
1931 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
1934 ret = __dwc3_gadget_ep_enable(dep, false, false);
1936 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1941 ret = __dwc3_gadget_ep_enable(dep, false, false);
1943 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
1947 /* begin to receive SETUP packets */
1948 dwc->ep0state = EP0_SETUP_PHASE;
1949 dwc->link_state = DWC3_LINK_STATE_SS_DIS;
1950 dwc->delayed_status = false;
1951 dwc3_ep0_out_start(dwc);
1953 dwc3_gadget_enable_irq(dwc);
1958 __dwc3_gadget_ep_disable(dwc->eps[0]);
1964 static int dwc3_gadget_start(struct usb_gadget *g,
1965 struct usb_gadget_driver *driver)
1967 struct dwc3 *dwc = gadget_to_dwc(g);
1968 unsigned long flags;
1972 irq = dwc->irq_gadget;
1973 ret = request_threaded_irq(irq, dwc3_interrupt, dwc3_thread_interrupt,
1974 IRQF_SHARED, "dwc3", dwc->ev_buf);
1976 dev_err(dwc->dev, "failed to request irq #%d --> %d\n",
1981 spin_lock_irqsave(&dwc->lock, flags);
1982 if (dwc->gadget_driver) {
1983 dev_err(dwc->dev, "%s is already bound to %s\n",
1985 dwc->gadget_driver->driver.name);
1990 dwc->gadget_driver = driver;
1992 if (pm_runtime_active(dwc->dev))
1993 __dwc3_gadget_start(dwc);
1995 spin_unlock_irqrestore(&dwc->lock, flags);
2000 spin_unlock_irqrestore(&dwc->lock, flags);
2007 static void __dwc3_gadget_stop(struct dwc3 *dwc)
2009 dwc3_gadget_disable_irq(dwc);
2010 __dwc3_gadget_ep_disable(dwc->eps[0]);
2011 __dwc3_gadget_ep_disable(dwc->eps[1]);
2014 static int dwc3_gadget_stop(struct usb_gadget *g)
2016 struct dwc3 *dwc = gadget_to_dwc(g);
2017 unsigned long flags;
2020 spin_lock_irqsave(&dwc->lock, flags);
2022 if (pm_runtime_suspended(dwc->dev))
2025 __dwc3_gadget_stop(dwc);
2027 for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2028 struct dwc3_ep *dep = dwc->eps[epnum];
2033 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2036 wait_event_lock_irq(dep->wait_end_transfer,
2037 !(dep->flags & DWC3_EP_END_TRANSFER_PENDING),
2042 dwc->gadget_driver = NULL;
2043 spin_unlock_irqrestore(&dwc->lock, flags);
2045 free_irq(dwc->irq_gadget, dwc->ev_buf);
2050 static void dwc3_gadget_set_speed(struct usb_gadget *g,
2051 enum usb_device_speed speed)
2053 struct dwc3 *dwc = gadget_to_dwc(g);
2054 unsigned long flags;
2057 spin_lock_irqsave(&dwc->lock, flags);
2058 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2059 reg &= ~(DWC3_DCFG_SPEED_MASK);
2062 * WORKAROUND: DWC3 revision < 2.20a have an issue
2063 * which would cause metastability state on Run/Stop
2064 * bit if we try to force the IP to USB2-only mode.
2066 * Because of that, we cannot configure the IP to any
2067 * speed other than the SuperSpeed
2071 * STAR#9000525659: Clock Domain Crossing on DCTL in
2074 if (dwc->revision < DWC3_REVISION_220A &&
2075 !dwc->dis_metastability_quirk) {
2076 reg |= DWC3_DCFG_SUPERSPEED;
2080 reg |= DWC3_DCFG_LOWSPEED;
2082 case USB_SPEED_FULL:
2083 reg |= DWC3_DCFG_FULLSPEED;
2085 case USB_SPEED_HIGH:
2086 reg |= DWC3_DCFG_HIGHSPEED;
2088 case USB_SPEED_SUPER:
2089 reg |= DWC3_DCFG_SUPERSPEED;
2091 case USB_SPEED_SUPER_PLUS:
2092 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2095 dev_err(dwc->dev, "invalid speed (%d)\n", speed);
2097 if (dwc->revision & DWC3_REVISION_IS_DWC31)
2098 reg |= DWC3_DCFG_SUPERSPEED_PLUS;
2100 reg |= DWC3_DCFG_SUPERSPEED;
2103 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2105 spin_unlock_irqrestore(&dwc->lock, flags);
2108 static const struct usb_gadget_ops dwc3_gadget_ops = {
2109 .get_frame = dwc3_gadget_get_frame,
2110 .wakeup = dwc3_gadget_wakeup,
2111 .set_selfpowered = dwc3_gadget_set_selfpowered,
2112 .pullup = dwc3_gadget_pullup,
2113 .udc_start = dwc3_gadget_start,
2114 .udc_stop = dwc3_gadget_stop,
2115 .udc_set_speed = dwc3_gadget_set_speed,
2118 /* -------------------------------------------------------------------------- */
2120 static int dwc3_gadget_init_endpoints(struct dwc3 *dwc, u8 total)
2122 struct dwc3_ep *dep;
2125 INIT_LIST_HEAD(&dwc->gadget.ep_list);
2127 for (epnum = 0; epnum < total; epnum++) {
2128 bool direction = epnum & 1;
2129 u8 num = epnum >> 1;
2131 dep = kzalloc(sizeof(*dep), GFP_KERNEL);
2136 dep->number = epnum;
2137 dep->direction = direction;
2138 dep->regs = dwc->regs + DWC3_DEP_BASE(epnum);
2139 dwc->eps[epnum] = dep;
2141 snprintf(dep->name, sizeof(dep->name), "ep%u%s", num,
2142 direction ? "in" : "out");
2144 dep->endpoint.name = dep->name;
2146 if (!(dep->number > 1)) {
2147 dep->endpoint.desc = &dwc3_gadget_ep0_desc;
2148 dep->endpoint.comp_desc = NULL;
2151 spin_lock_init(&dep->lock);
2154 usb_ep_set_maxpacket_limit(&dep->endpoint, 512);
2155 dep->endpoint.maxburst = 1;
2156 dep->endpoint.ops = &dwc3_gadget_ep0_ops;
2158 dwc->gadget.ep0 = &dep->endpoint;
2159 } else if (direction) {
2165 mdwidth = DWC3_MDWIDTH(dwc->hwparams.hwparams0);
2166 /* MDWIDTH is represented in bits, we need it in bytes */
2169 size = dwc3_readl(dwc->regs, DWC3_GTXFIFOSIZ(num));
2170 size = DWC3_GTXFIFOSIZ_TXFDEF(size);
2172 /* FIFO Depth is in MDWDITH bytes. Multiply */
2175 kbytes = size / 1024;
2180 * FIFO sizes account an extra MDWIDTH * (kbytes + 1) bytes for
2181 * internal overhead. We don't really know how these are used,
2182 * but documentation say it exists.
2184 size -= mdwidth * (kbytes + 1);
2187 usb_ep_set_maxpacket_limit(&dep->endpoint, size);
2189 dep->endpoint.max_streams = 15;
2190 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2191 list_add_tail(&dep->endpoint.ep_list,
2192 &dwc->gadget.ep_list);
2194 ret = dwc3_alloc_trb_pool(dep);
2200 usb_ep_set_maxpacket_limit(&dep->endpoint, 1024);
2201 dep->endpoint.max_streams = 15;
2202 dep->endpoint.ops = &dwc3_gadget_ep_ops;
2203 list_add_tail(&dep->endpoint.ep_list,
2204 &dwc->gadget.ep_list);
2206 ret = dwc3_alloc_trb_pool(dep);
2212 dep->endpoint.caps.type_control = true;
2214 dep->endpoint.caps.type_iso = true;
2215 dep->endpoint.caps.type_bulk = true;
2216 dep->endpoint.caps.type_int = true;
2219 dep->endpoint.caps.dir_in = direction;
2220 dep->endpoint.caps.dir_out = !direction;
2222 INIT_LIST_HEAD(&dep->pending_list);
2223 INIT_LIST_HEAD(&dep->started_list);
2229 static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
2231 struct dwc3_ep *dep;
2234 for (epnum = 0; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2235 dep = dwc->eps[epnum];
2239 * Physical endpoints 0 and 1 are special; they form the
2240 * bi-directional USB endpoint 0.
2242 * For those two physical endpoints, we don't allocate a TRB
2243 * pool nor do we add them the endpoints list. Due to that, we
2244 * shouldn't do these two operations otherwise we would end up
2245 * with all sorts of bugs when removing dwc3.ko.
2247 if (epnum != 0 && epnum != 1) {
2248 dwc3_free_trb_pool(dep);
2249 list_del(&dep->endpoint.ep_list);
2256 /* -------------------------------------------------------------------------- */
2258 static int __dwc3_cleanup_done_trbs(struct dwc3 *dwc, struct dwc3_ep *dep,
2259 struct dwc3_request *req, struct dwc3_trb *trb,
2260 const struct dwc3_event_depevt *event, int status,
2264 unsigned int s_pkt = 0;
2265 unsigned int trb_status;
2267 dwc3_ep_inc_deq(dep);
2269 if (req->trb == trb)
2270 dep->queued_requests--;
2272 trace_dwc3_complete_trb(dep, trb);
2275 * If we're in the middle of series of chained TRBs and we
2276 * receive a short transfer along the way, DWC3 will skip
2277 * through all TRBs including the last TRB in the chain (the
2278 * where CHN bit is zero. DWC3 will also avoid clearing HWO
2279 * bit and SW has to do it manually.
2281 * We're going to do that here to avoid problems of HW trying
2282 * to use bogus TRBs for transfers.
2284 if (chain && (trb->ctrl & DWC3_TRB_CTRL_HWO))
2285 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2288 * If we're dealing with unaligned size OUT transfer, we will be left
2289 * with one TRB pending in the ring. We need to manually clear HWO bit
2292 if ((req->zero || req->unaligned) && !(trb->ctrl & DWC3_TRB_CTRL_CHN)) {
2293 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
2297 count = trb->size & DWC3_TRB_SIZE_MASK;
2298 req->remaining += count;
2300 if ((trb->ctrl & DWC3_TRB_CTRL_HWO) && status != -ESHUTDOWN)
2303 if (dep->direction) {
2305 trb_status = DWC3_TRB_SIZE_TRBSTS(trb->size);
2306 if (trb_status == DWC3_TRBSTS_MISSED_ISOC) {
2308 * If missed isoc occurred and there is
2309 * no request queued then issue END
2310 * TRANSFER, so that core generates
2311 * next xfernotready and we will issue
2312 * a fresh START TRANSFER.
2313 * If there are still queued request
2314 * then wait, do not issue either END
2315 * or UPDATE TRANSFER, just attach next
2316 * request in pending_list during
2317 * giveback.If any future queued request
2318 * is successfully transferred then we
2319 * will issue UPDATE TRANSFER for all
2320 * request in the pending_list.
2322 dep->flags |= DWC3_EP_MISSED_ISOC;
2324 dev_err(dwc->dev, "incomplete IN transfer %s\n",
2326 status = -ECONNRESET;
2329 dep->flags &= ~DWC3_EP_MISSED_ISOC;
2332 if (count && (event->status & DEPEVT_STATUS_SHORT))
2336 if (s_pkt && !chain)
2339 if ((event->status & DEPEVT_STATUS_IOC) &&
2340 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2346 static int dwc3_cleanup_done_reqs(struct dwc3 *dwc, struct dwc3_ep *dep,
2347 const struct dwc3_event_depevt *event, int status)
2349 struct dwc3_request *req, *n;
2350 struct dwc3_trb *trb;
2354 list_for_each_entry_safe(req, n, &dep->started_list, list) {
2358 length = req->request.length;
2359 chain = req->num_pending_sgs > 0;
2361 struct scatterlist *sg = req->sg;
2362 struct scatterlist *s;
2363 unsigned int pending = req->num_pending_sgs;
2366 for_each_sg(sg, s, pending, i) {
2367 trb = &dep->trb_pool[dep->trb_dequeue];
2369 if (trb->ctrl & DWC3_TRB_CTRL_HWO)
2372 req->sg = sg_next(s);
2373 req->num_pending_sgs--;
2375 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2376 event, status, chain);
2381 trb = &dep->trb_pool[dep->trb_dequeue];
2382 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2383 event, status, chain);
2386 if (req->unaligned || req->zero) {
2387 trb = &dep->trb_pool[dep->trb_dequeue];
2388 ret = __dwc3_cleanup_done_trbs(dwc, dep, req, trb,
2389 event, status, false);
2390 req->unaligned = false;
2394 req->request.actual = length - req->remaining;
2396 if ((req->request.actual < length) && req->num_pending_sgs)
2397 return __dwc3_gadget_kick_transfer(dep, 0);
2399 dwc3_gadget_giveback(dep, req, status);
2402 if ((event->status & DEPEVT_STATUS_IOC) &&
2403 (trb->ctrl & DWC3_TRB_CTRL_IOC))
2410 * Our endpoint might get disabled by another thread during
2411 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2412 * early on so DWC3_EP_BUSY flag gets cleared
2414 if (!dep->endpoint.desc)
2417 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) &&
2418 list_empty(&dep->started_list)) {
2419 if (list_empty(&dep->pending_list)) {
2421 * If there is no entry in request list then do
2422 * not issue END TRANSFER now. Just set PENDING
2423 * flag, so that END TRANSFER is issued when an
2424 * entry is added into request list.
2426 dep->flags = DWC3_EP_PENDING_REQUEST;
2428 dwc3_stop_active_transfer(dwc, dep->number, true);
2429 dep->flags = DWC3_EP_ENABLED;
2434 if (usb_endpoint_xfer_isoc(dep->endpoint.desc) && ioc)
2440 static void dwc3_endpoint_transfer_complete(struct dwc3 *dwc,
2441 struct dwc3_ep *dep, const struct dwc3_event_depevt *event)
2443 unsigned status = 0;
2445 u32 is_xfer_complete;
2447 is_xfer_complete = (event->endpoint_event == DWC3_DEPEVT_XFERCOMPLETE);
2449 if (event->status & DEPEVT_STATUS_BUSERR)
2450 status = -ECONNRESET;
2452 clean_busy = dwc3_cleanup_done_reqs(dwc, dep, event, status);
2453 if (clean_busy && (!dep->endpoint.desc || is_xfer_complete ||
2454 usb_endpoint_xfer_isoc(dep->endpoint.desc)))
2455 dep->flags &= ~DWC3_EP_BUSY;
2458 * WORKAROUND: This is the 2nd half of U1/U2 -> U0 workaround.
2459 * See dwc3_gadget_linksts_change_interrupt() for 1st half.
2461 if (dwc->revision < DWC3_REVISION_183A) {
2465 for (i = 0; i < DWC3_ENDPOINTS_NUM; i++) {
2468 if (!(dep->flags & DWC3_EP_ENABLED))
2471 if (!list_empty(&dep->started_list))
2475 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2477 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2483 * Our endpoint might get disabled by another thread during
2484 * dwc3_gadget_giveback(). If that happens, we're just gonna return 1
2485 * early on so DWC3_EP_BUSY flag gets cleared
2487 if (!dep->endpoint.desc)
2490 if (!usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2493 ret = __dwc3_gadget_kick_transfer(dep, 0);
2494 if (!ret || ret == -EBUSY)
2499 static void dwc3_endpoint_interrupt(struct dwc3 *dwc,
2500 const struct dwc3_event_depevt *event)
2502 struct dwc3_ep *dep;
2503 u8 epnum = event->endpoint_number;
2506 dep = dwc->eps[epnum];
2508 if (!(dep->flags & DWC3_EP_ENABLED)) {
2509 if (!(dep->flags & DWC3_EP_END_TRANSFER_PENDING))
2512 /* Handle only EPCMDCMPLT when EP disabled */
2513 if (event->endpoint_event != DWC3_DEPEVT_EPCMDCMPLT)
2517 if (epnum == 0 || epnum == 1) {
2518 dwc3_ep0_interrupt(dwc, event);
2522 switch (event->endpoint_event) {
2523 case DWC3_DEPEVT_XFERCOMPLETE:
2524 dep->resource_index = 0;
2526 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2527 dev_err(dwc->dev, "XferComplete for Isochronous endpoint\n");
2531 dwc3_endpoint_transfer_complete(dwc, dep, event);
2533 case DWC3_DEPEVT_XFERINPROGRESS:
2534 dwc3_endpoint_transfer_complete(dwc, dep, event);
2536 case DWC3_DEPEVT_XFERNOTREADY:
2537 if (usb_endpoint_xfer_isoc(dep->endpoint.desc)) {
2538 dwc3_gadget_start_isoc(dwc, dep, event);
2542 ret = __dwc3_gadget_kick_transfer(dep, 0);
2543 if (!ret || ret == -EBUSY)
2548 case DWC3_DEPEVT_STREAMEVT:
2549 if (!usb_endpoint_xfer_bulk(dep->endpoint.desc)) {
2550 dev_err(dwc->dev, "Stream event for non-Bulk %s\n",
2555 case DWC3_DEPEVT_EPCMDCMPLT:
2556 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
2558 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
2559 dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
2560 wake_up(&dep->wait_end_transfer);
2563 case DWC3_DEPEVT_RXTXFIFOEVT:
2568 static void dwc3_disconnect_gadget(struct dwc3 *dwc)
2570 if (dwc->gadget_driver && dwc->gadget_driver->disconnect) {
2571 spin_unlock(&dwc->lock);
2572 dwc->gadget_driver->disconnect(&dwc->gadget);
2573 spin_lock(&dwc->lock);
2577 static void dwc3_suspend_gadget(struct dwc3 *dwc)
2579 if (dwc->gadget_driver && dwc->gadget_driver->suspend) {
2580 spin_unlock(&dwc->lock);
2581 dwc->gadget_driver->suspend(&dwc->gadget);
2582 spin_lock(&dwc->lock);
2586 static void dwc3_resume_gadget(struct dwc3 *dwc)
2588 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2589 spin_unlock(&dwc->lock);
2590 dwc->gadget_driver->resume(&dwc->gadget);
2591 spin_lock(&dwc->lock);
2595 static void dwc3_reset_gadget(struct dwc3 *dwc)
2597 if (!dwc->gadget_driver)
2600 if (dwc->gadget.speed != USB_SPEED_UNKNOWN) {
2601 spin_unlock(&dwc->lock);
2602 usb_gadget_udc_reset(&dwc->gadget, dwc->gadget_driver);
2603 spin_lock(&dwc->lock);
2607 static void dwc3_stop_active_transfer(struct dwc3 *dwc, u32 epnum, bool force)
2609 struct dwc3_ep *dep;
2610 struct dwc3_gadget_ep_cmd_params params;
2614 dep = dwc->eps[epnum];
2616 if ((dep->flags & DWC3_EP_END_TRANSFER_PENDING) ||
2617 !dep->resource_index)
2621 * NOTICE: We are violating what the Databook says about the
2622 * EndTransfer command. Ideally we would _always_ wait for the
2623 * EndTransfer Command Completion IRQ, but that's causing too
2624 * much trouble synchronizing between us and gadget driver.
2626 * We have discussed this with the IP Provider and it was
2627 * suggested to giveback all requests here, but give HW some
2628 * extra time to synchronize with the interconnect. We're using
2629 * an arbitrary 100us delay for that.
2631 * Note also that a similar handling was tested by Synopsys
2632 * (thanks a lot Paul) and nothing bad has come out of it.
2633 * In short, what we're doing is:
2635 * - Issue EndTransfer WITH CMDIOC bit set
2638 * As of IP version 3.10a of the DWC_usb3 IP, the controller
2639 * supports a mode to work around the above limitation. The
2640 * software can poll the CMDACT bit in the DEPCMD register
2641 * after issuing a EndTransfer command. This mode is enabled
2642 * by writing GUCTL2[14]. This polling is already done in the
2643 * dwc3_send_gadget_ep_cmd() function so if the mode is
2644 * enabled, the EndTransfer command will have completed upon
2645 * returning from this function and we don't need to delay for
2648 * This mode is NOT available on the DWC_usb31 IP.
2651 cmd = DWC3_DEPCMD_ENDTRANSFER;
2652 cmd |= force ? DWC3_DEPCMD_HIPRI_FORCERM : 0;
2653 cmd |= DWC3_DEPCMD_CMDIOC;
2654 cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
2655 memset(¶ms, 0, sizeof(params));
2656 ret = dwc3_send_gadget_ep_cmd(dep, cmd, ¶ms);
2658 dep->resource_index = 0;
2659 dep->flags &= ~DWC3_EP_BUSY;
2661 if (dwc3_is_usb31(dwc) || dwc->revision < DWC3_REVISION_310A) {
2662 dep->flags |= DWC3_EP_END_TRANSFER_PENDING;
2667 static void dwc3_clear_stall_all_ep(struct dwc3 *dwc)
2671 for (epnum = 1; epnum < DWC3_ENDPOINTS_NUM; epnum++) {
2672 struct dwc3_ep *dep;
2675 dep = dwc->eps[epnum];
2679 if (!(dep->flags & DWC3_EP_STALL))
2682 dep->flags &= ~DWC3_EP_STALL;
2684 ret = dwc3_send_clear_stall_ep_cmd(dep);
2689 static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
2693 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2694 reg &= ~DWC3_DCTL_INITU1ENA;
2695 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2697 reg &= ~DWC3_DCTL_INITU2ENA;
2698 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2700 dwc3_disconnect_gadget(dwc);
2702 dwc->gadget.speed = USB_SPEED_UNKNOWN;
2703 dwc->setup_packet_pending = false;
2704 usb_gadget_set_state(&dwc->gadget, USB_STATE_NOTATTACHED);
2706 dwc->connected = false;
2709 static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
2713 dwc->connected = true;
2716 * Ideally, dwc3_reset_gadget() would trigger the function
2717 * drivers to stop any active transfers through ep disable.
2718 * However, for functions which defer ep disable, such as mass
2719 * storage, we will need to rely on the call to stop active
2720 * transfers here, and avoid allowing of request queuing.
2722 dwc->connected = false;
2725 * WORKAROUND: DWC3 revisions <1.88a have an issue which
2726 * would cause a missing Disconnect Event if there's a
2727 * pending Setup Packet in the FIFO.
2729 * There's no suggested workaround on the official Bug
2730 * report, which states that "unless the driver/application
2731 * is doing any special handling of a disconnect event,
2732 * there is no functional issue".
2734 * Unfortunately, it turns out that we _do_ some special
2735 * handling of a disconnect event, namely complete all
2736 * pending transfers, notify gadget driver of the
2737 * disconnection, and so on.
2739 * Our suggested workaround is to follow the Disconnect
2740 * Event steps here, instead, based on a setup_packet_pending
2741 * flag. Such flag gets set whenever we have a SETUP_PENDING
2742 * status for EP0 TRBs and gets cleared on XferComplete for the
2747 * STAR#9000466709: RTL: Device : Disconnect event not
2748 * generated if setup packet pending in FIFO
2750 if (dwc->revision < DWC3_REVISION_188A) {
2751 if (dwc->setup_packet_pending)
2752 dwc3_gadget_disconnect_interrupt(dwc);
2755 dwc3_reset_gadget(dwc);
2757 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2758 reg &= ~DWC3_DCTL_TSTCTRL_MASK;
2759 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2760 dwc->test_mode = false;
2761 dwc3_clear_stall_all_ep(dwc);
2763 /* Reset device address to zero */
2764 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2765 reg &= ~(DWC3_DCFG_DEVADDR_MASK);
2766 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2769 static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc)
2771 struct dwc3_ep *dep;
2776 reg = dwc3_readl(dwc->regs, DWC3_DSTS);
2777 speed = reg & DWC3_DSTS_CONNECTSPD;
2781 * RAMClkSel is reset to 0 after USB reset, so it must be reprogrammed
2782 * each time on Connect Done.
2784 * Currently we always use the reset value. If any platform
2785 * wants to set this to a different value, we need to add a
2786 * setting and update GCTL.RAMCLKSEL here.
2790 case DWC3_DSTS_SUPERSPEED_PLUS:
2791 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2792 dwc->gadget.ep0->maxpacket = 512;
2793 dwc->gadget.speed = USB_SPEED_SUPER_PLUS;
2795 case DWC3_DSTS_SUPERSPEED:
2797 * WORKAROUND: DWC3 revisions <1.90a have an issue which
2798 * would cause a missing USB3 Reset event.
2800 * In such situations, we should force a USB3 Reset
2801 * event by calling our dwc3_gadget_reset_interrupt()
2806 * STAR#9000483510: RTL: SS : USB3 reset event may
2807 * not be generated always when the link enters poll
2809 if (dwc->revision < DWC3_REVISION_190A)
2810 dwc3_gadget_reset_interrupt(dwc);
2812 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(512);
2813 dwc->gadget.ep0->maxpacket = 512;
2814 dwc->gadget.speed = USB_SPEED_SUPER;
2816 case DWC3_DSTS_HIGHSPEED:
2817 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2818 dwc->gadget.ep0->maxpacket = 64;
2819 dwc->gadget.speed = USB_SPEED_HIGH;
2821 case DWC3_DSTS_FULLSPEED:
2822 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(64);
2823 dwc->gadget.ep0->maxpacket = 64;
2824 dwc->gadget.speed = USB_SPEED_FULL;
2826 case DWC3_DSTS_LOWSPEED:
2827 dwc3_gadget_ep0_desc.wMaxPacketSize = cpu_to_le16(8);
2828 dwc->gadget.ep0->maxpacket = 8;
2829 dwc->gadget.speed = USB_SPEED_LOW;
2833 dwc->eps[1]->endpoint.maxpacket = dwc->gadget.ep0->maxpacket;
2835 /* Enable USB2 LPM Capability */
2837 if ((dwc->revision > DWC3_REVISION_194A) &&
2838 (speed != DWC3_DSTS_SUPERSPEED) &&
2839 (speed != DWC3_DSTS_SUPERSPEED_PLUS)) {
2840 reg = dwc3_readl(dwc->regs, DWC3_DCFG);
2841 reg |= DWC3_DCFG_LPM_CAP;
2842 dwc3_writel(dwc->regs, DWC3_DCFG, reg);
2844 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2845 reg &= ~(DWC3_DCTL_HIRD_THRES_MASK | DWC3_DCTL_L1_HIBER_EN);
2847 reg |= DWC3_DCTL_HIRD_THRES(dwc->hird_threshold);
2850 * When dwc3 revisions >= 2.40a, LPM Erratum is enabled and
2851 * DCFG.LPMCap is set, core responses with an ACK and the
2852 * BESL value in the LPM token is less than or equal to LPM
2855 WARN_ONCE(dwc->revision < DWC3_REVISION_240A
2856 && dwc->has_lpm_erratum,
2857 "LPM Erratum not available on dwc3 revisions < 2.40a\n");
2859 if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A)
2860 reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
2862 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2864 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2865 reg &= ~DWC3_DCTL_HIRD_THRES_MASK;
2866 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2870 ret = __dwc3_gadget_ep_enable(dep, true, false);
2872 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2877 ret = __dwc3_gadget_ep_enable(dep, true, false);
2879 dev_err(dwc->dev, "failed to enable %s\n", dep->name);
2884 * Configure PHY via GUSB3PIPECTLn if required.
2886 * Update GTXFIFOSIZn
2888 * In both cases reset values should be sufficient.
2892 static void dwc3_gadget_wakeup_interrupt(struct dwc3 *dwc)
2895 * TODO take core out of low power mode when that's
2899 if (dwc->gadget_driver && dwc->gadget_driver->resume) {
2900 spin_unlock(&dwc->lock);
2901 dwc->gadget_driver->resume(&dwc->gadget);
2902 spin_lock(&dwc->lock);
2906 static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
2907 unsigned int evtinfo)
2909 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
2910 unsigned int pwropt;
2913 * WORKAROUND: DWC3 < 2.50a have an issue when configured without
2914 * Hibernation mode enabled which would show up when device detects
2915 * host-initiated U3 exit.
2917 * In that case, device will generate a Link State Change Interrupt
2918 * from U3 to RESUME which is only necessary if Hibernation is
2921 * There are no functional changes due to such spurious event and we
2922 * just need to ignore it.
2926 * STAR#9000570034 RTL: SS Resume event generated in non-Hibernation
2929 pwropt = DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1);
2930 if ((dwc->revision < DWC3_REVISION_250A) &&
2931 (pwropt != DWC3_GHWPARAMS1_EN_PWROPT_HIB)) {
2932 if ((dwc->link_state == DWC3_LINK_STATE_U3) &&
2933 (next == DWC3_LINK_STATE_RESUME)) {
2939 * WORKAROUND: DWC3 Revisions <1.83a have an issue which, depending
2940 * on the link partner, the USB session might do multiple entry/exit
2941 * of low power states before a transfer takes place.
2943 * Due to this problem, we might experience lower throughput. The
2944 * suggested workaround is to disable DCTL[12:9] bits if we're
2945 * transitioning from U1/U2 to U0 and enable those bits again
2946 * after a transfer completes and there are no pending transfers
2947 * on any of the enabled endpoints.
2949 * This is the first half of that workaround.
2953 * STAR#9000446952: RTL: Device SS : if U1/U2 ->U0 takes >128us
2954 * core send LGO_Ux entering U0
2956 if (dwc->revision < DWC3_REVISION_183A) {
2957 if (next == DWC3_LINK_STATE_U0) {
2961 switch (dwc->link_state) {
2962 case DWC3_LINK_STATE_U1:
2963 case DWC3_LINK_STATE_U2:
2964 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
2965 u1u2 = reg & (DWC3_DCTL_INITU2ENA
2966 | DWC3_DCTL_ACCEPTU2ENA
2967 | DWC3_DCTL_INITU1ENA
2968 | DWC3_DCTL_ACCEPTU1ENA);
2971 dwc->u1u2 = reg & u1u2;
2975 dwc3_writel(dwc->regs, DWC3_DCTL, reg);
2985 case DWC3_LINK_STATE_U1:
2986 if (dwc->speed == USB_SPEED_SUPER)
2987 dwc3_suspend_gadget(dwc);
2989 case DWC3_LINK_STATE_U2:
2990 case DWC3_LINK_STATE_U3:
2991 dwc3_suspend_gadget(dwc);
2993 case DWC3_LINK_STATE_RESUME:
2994 dwc3_resume_gadget(dwc);
3001 dwc->link_state = next;
3004 static void dwc3_gadget_suspend_interrupt(struct dwc3 *dwc,
3005 unsigned int evtinfo)
3007 enum dwc3_link_state next = evtinfo & DWC3_LINK_STATE_MASK;
3009 if (dwc->link_state != next && next == DWC3_LINK_STATE_U3)
3010 dwc3_suspend_gadget(dwc);
3012 dwc->link_state = next;
3015 static void dwc3_gadget_hibernation_interrupt(struct dwc3 *dwc,
3016 unsigned int evtinfo)
3018 unsigned int is_ss = evtinfo & BIT(4);
3021 * WORKAROUND: DWC3 revison 2.20a with hibernation support
3022 * have a known issue which can cause USB CV TD.9.23 to fail
3025 * Because of this issue, core could generate bogus hibernation
3026 * events which SW needs to ignore.
3030 * STAR#9000546576: Device Mode Hibernation: Issue in USB 2.0
3031 * Device Fallback from SuperSpeed
3033 if (is_ss ^ (dwc->speed == USB_SPEED_SUPER))
3036 /* enter hibernation here */
3039 static void dwc3_gadget_interrupt(struct dwc3 *dwc,
3040 const struct dwc3_event_devt *event)
3042 switch (event->type) {
3043 case DWC3_DEVICE_EVENT_DISCONNECT:
3044 dwc3_gadget_disconnect_interrupt(dwc);
3046 case DWC3_DEVICE_EVENT_RESET:
3047 dwc3_gadget_reset_interrupt(dwc);
3049 case DWC3_DEVICE_EVENT_CONNECT_DONE:
3050 dwc3_gadget_conndone_interrupt(dwc);
3052 case DWC3_DEVICE_EVENT_WAKEUP:
3053 dwc3_gadget_wakeup_interrupt(dwc);
3055 case DWC3_DEVICE_EVENT_HIBER_REQ:
3056 if (dev_WARN_ONCE(dwc->dev, !dwc->has_hibernation,
3057 "unexpected hibernation event\n"))
3060 dwc3_gadget_hibernation_interrupt(dwc, event->event_info);
3062 case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
3063 dwc3_gadget_linksts_change_interrupt(dwc, event->event_info);
3065 case DWC3_DEVICE_EVENT_EOPF:
3066 /* It changed to be suspend event for version 2.30a and above */
3067 if (dwc->revision >= DWC3_REVISION_230A) {
3069 * Ignore suspend event until the gadget enters into
3070 * USB_STATE_CONFIGURED state.
3072 if (dwc->gadget.state >= USB_STATE_CONFIGURED)
3073 dwc3_gadget_suspend_interrupt(dwc,
3077 case DWC3_DEVICE_EVENT_SOF:
3078 case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
3079 case DWC3_DEVICE_EVENT_CMD_CMPL:
3080 case DWC3_DEVICE_EVENT_OVERFLOW:
3083 dev_WARN(dwc->dev, "UNKNOWN IRQ %d\n", event->type);
3087 static void dwc3_process_event_entry(struct dwc3 *dwc,
3088 const union dwc3_event *event)
3090 trace_dwc3_event(event->raw, dwc);
3092 if (!event->type.is_devspec)
3093 dwc3_endpoint_interrupt(dwc, &event->depevt);
3094 else if (event->type.type == DWC3_EVENT_TYPE_DEV)
3095 dwc3_gadget_interrupt(dwc, &event->devt);
3097 dev_err(dwc->dev, "UNKNOWN IRQ type %d\n", event->raw);
3100 static irqreturn_t dwc3_process_event_buf(struct dwc3_event_buffer *evt)
3102 struct dwc3 *dwc = evt->dwc;
3103 irqreturn_t ret = IRQ_NONE;
3109 if (!(evt->flags & DWC3_EVENT_PENDING))
3113 union dwc3_event event;
3115 event.raw = *(u32 *) (evt->cache + evt->lpos);
3117 dwc3_process_event_entry(dwc, &event);
3120 * FIXME we wrap around correctly to the next entry as
3121 * almost all entries are 4 bytes in size. There is one
3122 * entry which has 12 bytes which is a regular entry
3123 * followed by 8 bytes data. ATM I don't know how
3124 * things are organized if we get next to the a
3125 * boundary so I worry about that once we try to handle
3128 evt->lpos = (evt->lpos + 4) % evt->length;
3135 /* Unmask interrupt */
3136 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3137 reg &= ~DWC3_GEVNTSIZ_INTMASK;
3138 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3140 if (dwc->imod_interval) {
3141 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), DWC3_GEVNTCOUNT_EHB);
3142 dwc3_writel(dwc->regs, DWC3_DEV_IMOD(0), dwc->imod_interval);
3145 /* Keep the clearing of DWC3_EVENT_PENDING at the end */
3146 evt->flags &= ~DWC3_EVENT_PENDING;
3151 static irqreturn_t dwc3_thread_interrupt(int irq, void *_evt)
3153 struct dwc3_event_buffer *evt = _evt;
3154 struct dwc3 *dwc = evt->dwc;
3155 unsigned long flags;
3156 irqreturn_t ret = IRQ_NONE;
3159 spin_lock_irqsave(&dwc->lock, flags);
3160 ret = dwc3_process_event_buf(evt);
3161 spin_unlock_irqrestore(&dwc->lock, flags);
3167 static irqreturn_t dwc3_check_event_buf(struct dwc3_event_buffer *evt)
3169 struct dwc3 *dwc = evt->dwc;
3174 if (pm_runtime_suspended(dwc->dev)) {
3175 pm_runtime_get(dwc->dev);
3176 disable_irq_nosync(dwc->irq_gadget);
3177 dwc->pending_events = true;
3182 * With PCIe legacy interrupt, test shows that top-half irq handler can
3183 * be called again after HW interrupt deassertion. Check if bottom-half
3184 * irq event handler completes before caching new event to prevent
3187 if (evt->flags & DWC3_EVENT_PENDING)
3190 count = dwc3_readl(dwc->regs, DWC3_GEVNTCOUNT(0));
3191 count &= DWC3_GEVNTCOUNT_MASK;
3196 evt->flags |= DWC3_EVENT_PENDING;
3198 /* Mask interrupt */
3199 reg = dwc3_readl(dwc->regs, DWC3_GEVNTSIZ(0));
3200 reg |= DWC3_GEVNTSIZ_INTMASK;
3201 dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), reg);
3203 amount = min(count, evt->length - evt->lpos);
3204 memcpy(evt->cache + evt->lpos, evt->buf + evt->lpos, amount);
3207 memcpy(evt->cache, evt->buf, count - amount);
3209 dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), count);
3211 return IRQ_WAKE_THREAD;
3214 static irqreturn_t dwc3_interrupt(int irq, void *_evt)
3216 struct dwc3_event_buffer *evt = _evt;
3218 return dwc3_check_event_buf(evt);
3221 static int dwc3_gadget_get_irq(struct dwc3 *dwc)
3223 struct platform_device *dwc3_pdev = to_platform_device(dwc->dev);
3226 irq = platform_get_irq_byname(dwc3_pdev, "peripheral");
3230 if (irq == -EPROBE_DEFER)
3233 irq = platform_get_irq_byname(dwc3_pdev, "dwc_usb3");
3237 if (irq == -EPROBE_DEFER)
3240 irq = platform_get_irq(dwc3_pdev, 0);
3244 if (irq != -EPROBE_DEFER)
3245 dev_err(dwc->dev, "missing peripheral IRQ\n");
3255 * dwc3_gadget_init - initializes gadget related registers
3256 * @dwc: pointer to our controller context structure
3258 * Returns 0 on success otherwise negative errno.
3260 int dwc3_gadget_init(struct dwc3 *dwc)
3265 irq = dwc3_gadget_get_irq(dwc);
3271 dwc->irq_gadget = irq;
3273 dwc->ep0_trb = dma_alloc_coherent(dwc->sysdev,
3274 sizeof(*dwc->ep0_trb) * 2,
3275 &dwc->ep0_trb_addr, GFP_KERNEL);
3276 if (!dwc->ep0_trb) {
3277 dev_err(dwc->dev, "failed to allocate ep0 trb\n");
3282 dwc->setup_buf = kzalloc(DWC3_EP0_SETUP_SIZE, GFP_KERNEL);
3283 if (!dwc->setup_buf) {
3288 dwc->bounce = dma_alloc_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE,
3289 &dwc->bounce_addr, GFP_KERNEL);
3295 init_completion(&dwc->ep0_in_setup);
3297 dwc->gadget.ops = &dwc3_gadget_ops;
3298 dwc->gadget.speed = USB_SPEED_UNKNOWN;
3299 dwc->gadget.sg_supported = true;
3300 dwc->gadget.name = "dwc3-gadget";
3303 * FIXME We might be setting max_speed to <SUPER, however versions
3304 * <2.20a of dwc3 have an issue with metastability (documented
3305 * elsewhere in this driver) which tells us we can't set max speed to
3306 * anything lower than SUPER.
3308 * Because gadget.max_speed is only used by composite.c and function
3309 * drivers (i.e. it won't go into dwc3's registers) we are allowing this
3310 * to happen so we avoid sending SuperSpeed Capability descriptor
3311 * together with our BOS descriptor as that could confuse host into
3312 * thinking we can handle super speed.
3314 * Note that, in fact, we won't even support GetBOS requests when speed
3315 * is less than super speed because we don't have means, yet, to tell
3316 * composite.c that we are USB 2.0 + LPM ECN.
3318 if (dwc->revision < DWC3_REVISION_220A &&
3319 !dwc->dis_metastability_quirk)
3320 dev_info(dwc->dev, "changing max_speed on rev %08x\n",
3323 dwc->gadget.max_speed = dwc->maximum_speed;
3326 * REVISIT: Here we should clear all pending IRQs to be
3327 * sure we're starting from a well known location.
3330 ret = dwc3_gadget_init_endpoints(dwc, dwc->num_eps);
3334 ret = usb_add_gadget_udc(dwc->dev, &dwc->gadget);
3336 dev_err(dwc->dev, "failed to register udc\n");
3340 dwc3_gadget_set_speed(&dwc->gadget, dwc->maximum_speed);
3345 dwc3_gadget_free_endpoints(dwc);
3348 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3352 kfree(dwc->setup_buf);
3355 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3356 dwc->ep0_trb, dwc->ep0_trb_addr);
3362 /* -------------------------------------------------------------------------- */
3364 void dwc3_gadget_exit(struct dwc3 *dwc)
3366 usb_del_gadget_udc(&dwc->gadget);
3367 dwc3_gadget_free_endpoints(dwc);
3368 dma_free_coherent(dwc->sysdev, DWC3_BOUNCE_SIZE, dwc->bounce,
3370 kfree(dwc->setup_buf);
3371 dma_free_coherent(dwc->sysdev, sizeof(*dwc->ep0_trb) * 2,
3372 dwc->ep0_trb, dwc->ep0_trb_addr);
3375 int dwc3_gadget_suspend(struct dwc3 *dwc)
3377 if (!dwc->gadget_driver)
3380 dwc3_gadget_run_stop(dwc, false, false);
3381 dwc3_disconnect_gadget(dwc);
3382 __dwc3_gadget_stop(dwc);
3384 synchronize_irq(dwc->irq_gadget);
3389 int dwc3_gadget_resume(struct dwc3 *dwc)
3393 if (!dwc->gadget_driver)
3396 ret = __dwc3_gadget_start(dwc);
3400 ret = dwc3_gadget_run_stop(dwc, true, false);
3407 __dwc3_gadget_stop(dwc);
3413 void dwc3_gadget_process_pending_events(struct dwc3 *dwc)
3415 if (dwc->pending_events) {
3416 dwc3_interrupt(dwc->irq_gadget, dwc->ev_buf);
3417 dwc->pending_events = false;
3418 enable_irq(dwc->irq_gadget);