drivers/usb/gadget/udc/mv_u3d_core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2011 Marvell International Ltd. All rights reserved.
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/dma-mapping.h>
   8 #include <linux/dmapool.h>
   9 #include <linux/kernel.h>
  10 #include <linux/delay.h>
  11 #include <linux/ioport.h>
  12 #include <linux/sched.h>
  13 #include <linux/slab.h>
  14 #include <linux/errno.h>
  15 #include <linux/timer.h>
  16 #include <linux/list.h>
  17 #include <linux/notifier.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/device.h>
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/pm.h>
  24 #include <linux/io.h>
  25 #include <linux/irq.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/platform_data/mv_usb.h>
  28 #include <linux/clk.h>
  29
  30 #include "mv_u3d.h"
  31
  32 #define DRIVER_DESC             "Marvell PXA USB3.0 Device Controller driver"
  33
  34 static const char driver_name[] = "mv_u3d";
  35 static const char driver_desc[] = DRIVER_DESC;
  36
  37 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status);
  38 static void mv_u3d_stop_activity(struct mv_u3d *u3d,
  39                         struct usb_gadget_driver *driver);
  40
  41 /* for endpoint 0 operations */
  42 static const struct usb_endpoint_descriptor mv_u3d_ep0_desc = {
  43         .bLength =              USB_DT_ENDPOINT_SIZE,
  44         .bDescriptorType =      USB_DT_ENDPOINT,
  45         .bEndpointAddress =     0,
  46         .bmAttributes =         USB_ENDPOINT_XFER_CONTROL,
  47         .wMaxPacketSize =       MV_U3D_EP0_MAX_PKT_SIZE,
  48 };
  49
  50 static void mv_u3d_ep0_reset(struct mv_u3d *u3d)
  51 {
  52         struct mv_u3d_ep *ep;
  53         u32 epxcr;
  54         int i;
  55
  56         for (i = 0; i < 2; i++) {
  57                 ep = &u3d->eps[i];
  58                 ep->u3d = u3d;
  59
  60                 /* ep0 ep context, ep0 in and out share the same ep context */
  61                 ep->ep_context = &u3d->ep_context[1];
  62         }
  63
  64         /* reset ep state machine */
  65         /* reset ep0 out */
  66         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
  67         epxcr |= MV_U3D_EPXCR_EP_INIT;
  68         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  69         udelay(5);
  70         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  71         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr0);
  72
  73         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  74                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  75                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  76                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  77                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  78         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxoutcr1);
  79
  80         /* reset ep0 in */
  81         epxcr = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
  82         epxcr |= MV_U3D_EPXCR_EP_INIT;
  83         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  84         udelay(5);
  85         epxcr &= ~MV_U3D_EPXCR_EP_INIT;
  86         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr0);
  87
  88         epxcr = ((MV_U3D_EP0_MAX_PKT_SIZE
  89                 << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
  90                 | (1 << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
  91                 | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
  92                 | MV_U3D_EPXCR_EP_TYPE_CONTROL);
  93         iowrite32(epxcr, &u3d->vuc_regs->epcr[0].epxincr1);
  94 }
  95
  96 static void mv_u3d_ep0_stall(struct mv_u3d *u3d)
  97 {
  98         u32 tmp;
  99         dev_dbg(u3d->dev, "%s\n", __func__);
 100
 101         /* set TX and RX to stall */
 102         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 103         tmp |= MV_U3D_EPXCR_EP_HALT;
 104         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 105
 106         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 107         tmp |= MV_U3D_EPXCR_EP_HALT;
 108         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 109
 110         /* update ep0 state */
 111         u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 112         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 113 }
 114
 115 static int mv_u3d_process_ep_req(struct mv_u3d *u3d, int index,
 116         struct mv_u3d_req *curr_req)
 117 {
 118         struct mv_u3d_trb       *curr_trb;
 119         int actual, remaining_length = 0;
 120         int direction, ep_num;
 121         int retval = 0;
 122         u32 tmp, status, length;
 123
 124         direction = index % 2;
 125         ep_num = index / 2;
 126
 127         actual = curr_req->req.length;
 128
 129         while (!list_empty(&curr_req->trb_list)) {
 130                 curr_trb = list_entry(curr_req->trb_list.next,
 131                                         struct mv_u3d_trb, trb_list);
 132                 if (!curr_trb->trb_hw->ctrl.own) {
 133                         dev_err(u3d->dev, "%s, TRB own error!\n",
 134                                 u3d->eps[index].name);
 135                         return 1;
 136                 }
 137
 138                 curr_trb->trb_hw->ctrl.own = 0;
 139                 if (direction == MV_U3D_EP_DIR_OUT)
 140                         tmp = ioread32(&u3d->vuc_regs->rxst[ep_num].statuslo);
 141                 else
 142                         tmp = ioread32(&u3d->vuc_regs->txst[ep_num].statuslo);
 143
 144                 status = tmp >> MV_U3D_XFERSTATUS_COMPLETE_SHIFT;
 145                 length = tmp & MV_U3D_XFERSTATUS_TRB_LENGTH_MASK;
 146
 147                 if (status == MV_U3D_COMPLETE_SUCCESS ||
 148                         (status == MV_U3D_COMPLETE_SHORT_PACKET &&
 149                         direction == MV_U3D_EP_DIR_OUT)) {
 150                         remaining_length += length;
 151                         actual -= remaining_length;
 152                 } else {
 153                         dev_err(u3d->dev,
 154                                 "complete_tr error: ep=%d %s: error = 0x%x\n",
 155                                 index >> 1, direction ? "SEND" : "RECV",
 156                                 status);
 157                         retval = -EPROTO;
 158                 }
 159
 160                 list_del_init(&curr_trb->trb_list);
 161         }
 162         if (retval)
 163                 return retval;
 164
 165         curr_req->req.actual = actual;
 166         return 0;
 167 }
 168
 169 /*
 170  * mv_u3d_done() - retire a request; caller blocked irqs
 171  * @status : request status to be set, only works when
 172  * request is still in progress.
 173  */
 174 static
 175 void mv_u3d_done(struct mv_u3d_ep *ep, struct mv_u3d_req *req, int status)
 176         __releases(&ep->udc->lock)
 177         __acquires(&ep->udc->lock)
 178 {
 179         struct mv_u3d *u3d = (struct mv_u3d *)ep->u3d;
 180
 181         dev_dbg(u3d->dev, "mv_u3d_done: remove req->queue\n");
 182         /* Removed the req from ep queue */
 183         list_del_init(&req->queue);
 184
 185         /* req.status should be set as -EINPROGRESS in ep_queue() */
 186         if (req->req.status == -EINPROGRESS)
 187                 req->req.status = status;
 188         else
 189                 status = req->req.status;
 190
 191         /* Free trb for the request */
 192         if (!req->chain)
 193                 dma_pool_free(u3d->trb_pool,
 194                         req->trb_head->trb_hw, req->trb_head->trb_dma);
 195         else {
 196                 dma_unmap_single(ep->u3d->gadget.dev.parent,
 197                         (dma_addr_t)req->trb_head->trb_dma,
 198                         req->trb_count * sizeof(struct mv_u3d_trb_hw),
 199                         DMA_BIDIRECTIONAL);
 200                 kfree(req->trb_head->trb_hw);
 201         }
 202         kfree(req->trb_head);
 203
 204         usb_gadget_unmap_request(&u3d->gadget, &req->req, mv_u3d_ep_dir(ep));
 205
 206         if (status && (status != -ESHUTDOWN)) {
 207                 dev_dbg(u3d->dev, "complete %s req %p stat %d len %u/%u",
 208                         ep->ep.name, &req->req, status,
 209                         req->req.actual, req->req.length);
 210         }
 211
 212         spin_unlock(&ep->u3d->lock);
 213
 214         usb_gadget_giveback_request(&ep->ep, &req->req);
 215
 216         spin_lock(&ep->u3d->lock);
 217 }
 218
 219 static int mv_u3d_queue_trb(struct mv_u3d_ep *ep, struct mv_u3d_req *req)
 220 {
 221         u32 tmp, direction;
 222         struct mv_u3d *u3d;
 223         struct mv_u3d_ep_context *ep_context;
 224         int retval = 0;
 225
 226         u3d = ep->u3d;
 227         direction = mv_u3d_ep_dir(ep);
 228
 229         /* ep0 in and out share the same ep context slot 1*/
 230         if (ep->ep_num == 0)
 231                 ep_context = &(u3d->ep_context[1]);
 232         else
 233                 ep_context = &(u3d->ep_context[ep->ep_num * 2 + direction]);
 234
 235         /* check if the pipe is empty or not */
 236         if (!list_empty(&ep->queue)) {
 237                 dev_err(u3d->dev, "add trb to non-empty queue!\n");
 238                 retval = -ENOMEM;
 239                 WARN_ON(1);
 240         } else {
 241                 ep_context->rsvd0 = cpu_to_le32(1);
 242                 ep_context->rsvd1 = 0;
 243
 244                 /* Configure the trb address and set the DCS bit.
 245                  * Both DCS bit and own bit in trb should be set.
 246                  */
 247                 ep_context->trb_addr_lo =
 248                         cpu_to_le32(req->trb_head->trb_dma | DCS_ENABLE);
 249                 ep_context->trb_addr_hi = 0;
 250
 251                 /* Ensure that updates to the EP Context will
 252                  * occure before Ring Bell.
 253                  */
 254                 wmb();
 255
 256                 /* ring bell the ep */
 257                 if (ep->ep_num == 0)
 258                         tmp = 0x1;
 259                 else
 260                         tmp = ep->ep_num * 2
 261                                 + ((direction == MV_U3D_EP_DIR_OUT) ? 0 : 1);
 262
 263                 iowrite32(tmp, &u3d->op_regs->doorbell);
 264         }
 265         return retval;
 266 }
 267
 268 static struct mv_u3d_trb *mv_u3d_build_trb_one(struct mv_u3d_req *req,
 269                                 unsigned *length, dma_addr_t *dma)
 270 {
 271         u32 temp;
 272         unsigned int direction;
 273         struct mv_u3d_trb *trb;
 274         struct mv_u3d_trb_hw *trb_hw;
 275         struct mv_u3d *u3d;
 276
 277         /* how big will this transfer be? */
 278         *length = req->req.length - req->req.actual;
 279         BUG_ON(*length > (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 280
 281         u3d = req->ep->u3d;
 282
 283         trb = kzalloc(sizeof(*trb), GFP_ATOMIC);
 284         if (!trb)
 285                 return NULL;
 286
 287         /*
 288          * Be careful that no _GFP_HIGHMEM is set,
 289          * or we can not use dma_to_virt
 290          * cannot use GFP_KERNEL in spin lock
 291          */
 292         trb_hw = dma_pool_alloc(u3d->trb_pool, GFP_ATOMIC, dma);
 293         if (!trb_hw) {
 294                 kfree(trb);
 295                 dev_err(u3d->dev,
 296                         "%s, dma_pool_alloc fail\n", __func__);
 297                 return NULL;
 298         }
 299         trb->trb_dma = *dma;
 300         trb->trb_hw = trb_hw;
 301
 302         /* initialize buffer page pointers */
 303         temp = (u32)(req->req.dma + req->req.actual);
 304
 305         trb_hw->buf_addr_lo = cpu_to_le32(temp);
 306         trb_hw->buf_addr_hi = 0;
 307         trb_hw->trb_len = cpu_to_le32(*length);
 308         trb_hw->ctrl.own = 1;
 309
 310         if (req->ep->ep_num == 0)
 311                 trb_hw->ctrl.type = TYPE_DATA;
 312         else
 313                 trb_hw->ctrl.type = TYPE_NORMAL;
 314
 315         req->req.actual += *length;
 316
 317         direction = mv_u3d_ep_dir(req->ep);
 318         if (direction == MV_U3D_EP_DIR_IN)
 319                 trb_hw->ctrl.dir = 1;
 320         else
 321                 trb_hw->ctrl.dir = 0;
 322
 323         /* Enable interrupt for the last trb of a request */
 324         if (!req->req.no_interrupt)
 325                 trb_hw->ctrl.ioc = 1;
 326
 327         trb_hw->ctrl.chain = 0;
 328
 329         wmb();
 330         return trb;
 331 }
 332
 333 static int mv_u3d_build_trb_chain(struct mv_u3d_req *req, unsigned *length,
 334                 struct mv_u3d_trb *trb, int *is_last)
 335 {
 336         u32 temp;
 337         unsigned int direction;
 338         struct mv_u3d *u3d;
 339
 340         /* how big will this transfer be? */
 341         *length = min(req->req.length - req->req.actual,
 342                         (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER);
 343
 344         u3d = req->ep->u3d;
 345
 346         trb->trb_dma = 0;
 347
 348         /* initialize buffer page pointers */
 349         temp = (u32)(req->req.dma + req->req.actual);
 350
 351         trb->trb_hw->buf_addr_lo = cpu_to_le32(temp);
 352         trb->trb_hw->buf_addr_hi = 0;
 353         trb->trb_hw->trb_len = cpu_to_le32(*length);
 354         trb->trb_hw->ctrl.own = 1;
 355
 356         if (req->ep->ep_num == 0)
 357                 trb->trb_hw->ctrl.type = TYPE_DATA;
 358         else
 359                 trb->trb_hw->ctrl.type = TYPE_NORMAL;
 360
 361         req->req.actual += *length;
 362
 363         direction = mv_u3d_ep_dir(req->ep);
 364         if (direction == MV_U3D_EP_DIR_IN)
 365                 trb->trb_hw->ctrl.dir = 1;
 366         else
 367                 trb->trb_hw->ctrl.dir = 0;
 368
 369         /* zlp is needed if req->req.zero is set */
 370         if (req->req.zero) {
 371                 if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
 372                         *is_last = 1;
 373                 else
 374                         *is_last = 0;
 375         } else if (req->req.length == req->req.actual)
 376                 *is_last = 1;
 377         else
 378                 *is_last = 0;
 379
 380         /* Enable interrupt for the last trb of a request */
 381         if (*is_last && !req->req.no_interrupt)
 382                 trb->trb_hw->ctrl.ioc = 1;
 383
 384         if (*is_last)
 385                 trb->trb_hw->ctrl.chain = 0;
 386         else {
 387                 trb->trb_hw->ctrl.chain = 1;
 388                 dev_dbg(u3d->dev, "chain trb\n");
 389         }
 390
 391         wmb();
 392
 393         return 0;
 394 }
 395
 396 /* generate TRB linked list for a request
 397  * usb controller only supports continous trb chain,
 398  * that trb structure physical address should be continous.
 399  */
 400 static int mv_u3d_req_to_trb(struct mv_u3d_req *req)
 401 {
 402         unsigned count;
 403         int is_last;
 404         struct mv_u3d_trb *trb;
 405         struct mv_u3d_trb_hw *trb_hw;
 406         struct mv_u3d *u3d;
 407         dma_addr_t dma;
 408         unsigned length;
 409         unsigned trb_num;
 410
 411         u3d = req->ep->u3d;
 412
 413         INIT_LIST_HEAD(&req->trb_list);
 414
 415         length = req->req.length - req->req.actual;
 416         /* normally the request transfer length is less than 16KB.
 417          * we use buil_trb_one() to optimize it.
 418          */
 419         if (length <= (unsigned)MV_U3D_EP_MAX_LENGTH_TRANSFER) {
 420                 trb = mv_u3d_build_trb_one(req, &count, &dma);
 421                 list_add_tail(&trb->trb_list, &req->trb_list);
 422                 req->trb_head = trb;
 423                 req->trb_count = 1;
 424                 req->chain = 0;
 425         } else {
 426                 trb_num = length / MV_U3D_EP_MAX_LENGTH_TRANSFER;
 427                 if (length % MV_U3D_EP_MAX_LENGTH_TRANSFER)
 428                         trb_num++;
 429
 430                 trb = kcalloc(trb_num, sizeof(*trb), GFP_ATOMIC);
 431                 if (!trb)
 432                         return -ENOMEM;
 433
 434                 trb_hw = kcalloc(trb_num, sizeof(*trb_hw), GFP_ATOMIC);
 435                 if (!trb_hw) {
 436                         kfree(trb);
 437                         return -ENOMEM;
 438                 }
 439
 440                 do {
 441                         trb->trb_hw = trb_hw;
 442                         if (mv_u3d_build_trb_chain(req, &count,
 443                                                 trb, &is_last)) {
 444                                 dev_err(u3d->dev,
 445                                         "%s, mv_u3d_build_trb_chain fail\n",
 446                                         __func__);
 447                                 return -EIO;
 448                         }
 449
 450                         list_add_tail(&trb->trb_list, &req->trb_list);
 451                         req->trb_count++;
 452                         trb++;
 453                         trb_hw++;
 454                 } while (!is_last);
 455
 456                 req->trb_head = list_entry(req->trb_list.next,
 457                                         struct mv_u3d_trb, trb_list);
 458                 req->trb_head->trb_dma = dma_map_single(u3d->gadget.dev.parent,
 459                                         req->trb_head->trb_hw,
 460                                         trb_num * sizeof(*trb_hw),
 461                                         DMA_BIDIRECTIONAL);
 462                 if (dma_mapping_error(u3d->gadget.dev.parent,
 463                                         req->trb_head->trb_dma)) {
 464                         kfree(req->trb_head->trb_hw);
 465                         kfree(req->trb_head);
 466                         return -EFAULT;
 467                 }
 468
 469                 req->chain = 1;
 470         }
 471
 472         return 0;
 473 }
 474
 475 static int
 476 mv_u3d_start_queue(struct mv_u3d_ep *ep)
 477 {
 478         struct mv_u3d *u3d = ep->u3d;
 479         struct mv_u3d_req *req;
 480         int ret;
 481
 482         if (!list_empty(&ep->req_list) && !ep->processing)
 483                 req = list_entry(ep->req_list.next, struct mv_u3d_req, list);
 484         else
 485                 return 0;
 486
 487         ep->processing = 1;
 488
 489         /* set up dma mapping */
 490         ret = usb_gadget_map_request(&u3d->gadget, &req->req,
 491                                         mv_u3d_ep_dir(ep));
 492         if (ret)
 493                 goto break_processing;
 494
 495         req->req.status = -EINPROGRESS;
 496         req->req.actual = 0;
 497         req->trb_count = 0;
 498
 499         /* build trbs */
 500         ret = mv_u3d_req_to_trb(req);
 501         if (ret) {
 502                 dev_err(u3d->dev, "%s, mv_u3d_req_to_trb fail\n", __func__);
 503                 goto break_processing;
 504         }
 505
 506         /* and push them to device queue */
 507         ret = mv_u3d_queue_trb(ep, req);
 508         if (ret)
 509                 goto break_processing;
 510
 511         /* irq handler advances the queue */
 512         list_add_tail(&req->queue, &ep->queue);
 513
 514         return 0;
 515
 516 break_processing:
 517         ep->processing = 0;
 518         return ret;
 519 }
 520
 521 static int mv_u3d_ep_enable(struct usb_ep *_ep,
 522                 const struct usb_endpoint_descriptor *desc)
 523 {
 524         struct mv_u3d *u3d;
 525         struct mv_u3d_ep *ep;
 526         u16 max = 0;
 527         unsigned maxburst = 0;
 528         u32 epxcr, direction;
 529
 530         if (!_ep || !desc || desc->bDescriptorType != USB_DT_ENDPOINT)
 531                 return -EINVAL;
 532
 533         ep = container_of(_ep, struct mv_u3d_ep, ep);
 534         u3d = ep->u3d;
 535
 536         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN)
 537                 return -ESHUTDOWN;
 538
 539         direction = mv_u3d_ep_dir(ep);
 540         max = le16_to_cpu(desc->wMaxPacketSize);
 541
 542         if (!_ep->maxburst)
 543                 _ep->maxburst = 1;
 544         maxburst = _ep->maxburst;
 545
 546         /* Set the max burst size */
 547         switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
 548         case USB_ENDPOINT_XFER_BULK:
 549                 if (maxburst > 16) {
 550                         dev_dbg(u3d->dev,
 551                                 "max burst should not be greater "
 552                                 "than 16 on bulk ep\n");
 553                         maxburst = 1;
 554                         _ep->maxburst = maxburst;
 555                 }
 556                 dev_dbg(u3d->dev,
 557                         "maxburst: %d on bulk %s\n", maxburst, ep->name);
 558                 break;
 559         case USB_ENDPOINT_XFER_CONTROL:
 560                 /* control transfer only supports maxburst as one */
 561                 maxburst = 1;
 562                 _ep->maxburst = maxburst;
 563                 break;
 564         case USB_ENDPOINT_XFER_INT:
 565                 if (maxburst != 1) {
 566                         dev_dbg(u3d->dev,
 567                                 "max burst should be 1 on int ep "
 568                                 "if transfer size is not 1024\n");
 569                         maxburst = 1;
 570                         _ep->maxburst = maxburst;
 571                 }
 572                 break;
 573         case USB_ENDPOINT_XFER_ISOC:
 574                 if (maxburst != 1) {
 575                         dev_dbg(u3d->dev,
 576                                 "max burst should be 1 on isoc ep "
 577                                 "if transfer size is not 1024\n");
 578                         maxburst = 1;
 579                         _ep->maxburst = maxburst;
 580                 }
 581                 break;
 582         default:
 583                 goto en_done;
 584         }
 585
 586         ep->ep.maxpacket = max;
 587         ep->ep.desc = desc;
 588         ep->enabled = 1;
 589
 590         /* Enable the endpoint for Rx or Tx and set the endpoint type */
 591         if (direction == MV_U3D_EP_DIR_OUT) {
 592                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 593                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 594                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 595                 udelay(5);
 596                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 597                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 598
 599                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 600                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 601                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 602                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 603                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 604         } else {
 605                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 606                 epxcr |= MV_U3D_EPXCR_EP_INIT;
 607                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 608                 udelay(5);
 609                 epxcr &= ~MV_U3D_EPXCR_EP_INIT;
 610                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 611
 612                 epxcr = ((max << MV_U3D_EPXCR_MAX_PACKET_SIZE_SHIFT)
 613                       | ((maxburst - 1) << MV_U3D_EPXCR_MAX_BURST_SIZE_SHIFT)
 614                       | (1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 615                       | (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK));
 616                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 617         }
 618
 619         return 0;
 620 en_done:
 621         return -EINVAL;
 622 }
 623
 624 static int  mv_u3d_ep_disable(struct usb_ep *_ep)
 625 {
 626         struct mv_u3d *u3d;
 627         struct mv_u3d_ep *ep;
 628         u32 epxcr, direction;
 629         unsigned long flags;
 630
 631         if (!_ep)
 632                 return -EINVAL;
 633
 634         ep = container_of(_ep, struct mv_u3d_ep, ep);
 635         if (!ep->ep.desc)
 636                 return -EINVAL;
 637
 638         u3d = ep->u3d;
 639
 640         direction = mv_u3d_ep_dir(ep);
 641
 642         /* nuke all pending requests (does flush) */
 643         spin_lock_irqsave(&u3d->lock, flags);
 644         mv_u3d_nuke(ep, -ESHUTDOWN);
 645         spin_unlock_irqrestore(&u3d->lock, flags);
 646
 647         /* Disable the endpoint for Rx or Tx and reset the endpoint type */
 648         if (direction == MV_U3D_EP_DIR_OUT) {
 649                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 650                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 651                       | USB_ENDPOINT_XFERTYPE_MASK);
 652                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr1);
 653         } else {
 654                 epxcr = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 655                 epxcr &= ~((1 << MV_U3D_EPXCR_EP_ENABLE_SHIFT)
 656                       | USB_ENDPOINT_XFERTYPE_MASK);
 657                 iowrite32(epxcr, &u3d->vuc_regs->epcr[ep->ep_num].epxincr1);
 658         }
 659
 660         ep->enabled = 0;
 661
 662         ep->ep.desc = NULL;
 663         return 0;
 664 }
 665
 666 static struct usb_request *
 667 mv_u3d_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
 668 {
 669         struct mv_u3d_req *req = NULL;
 670
 671         req = kzalloc(sizeof *req, gfp_flags);
 672         if (!req)
 673                 return NULL;
 674
 675         INIT_LIST_HEAD(&req->queue);
 676
 677         return &req->req;
 678 }
 679
 680 static void mv_u3d_free_request(struct usb_ep *_ep, struct usb_request *_req)
 681 {
 682         struct mv_u3d_req *req = container_of(_req, struct mv_u3d_req, req);
 683
 684         kfree(req);
 685 }
 686
 687 static void mv_u3d_ep_fifo_flush(struct usb_ep *_ep)
 688 {
 689         struct mv_u3d *u3d;
 690         u32 direction;
 691         struct mv_u3d_ep *ep = container_of(_ep, struct mv_u3d_ep, ep);
 692         unsigned int loops;
 693         u32 tmp;
 694
 695         /* if endpoint is not enabled, cannot flush endpoint */
 696         if (!ep->enabled)
 697                 return;
 698
 699         u3d = ep->u3d;
 700         direction = mv_u3d_ep_dir(ep);
 701
 702         /* ep0 need clear bit after flushing fifo. */
 703         if (!ep->ep_num) {
 704                 if (direction == MV_U3D_EP_DIR_OUT) {
 705                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxoutcr0);
 706                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 707                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 708                         udelay(10);
 709                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 710                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxoutcr0);
 711                 } else {
 712                         tmp = ioread32(&u3d->vuc_regs->epcr[0].epxincr0);
 713                         tmp |= MV_U3D_EPXCR_EP_FLUSH;
 714                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 715                         udelay(10);
 716                         tmp &= ~MV_U3D_EPXCR_EP_FLUSH;
 717                         iowrite32(tmp, &u3d->vuc_regs->epcr[0].epxincr0);
 718                 }
 719                 return;
 720         }
 721
 722         if (direction == MV_U3D_EP_DIR_OUT) {
 723                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 724                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 725                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 726
 727                 /* Wait until flushing completed */
 728                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 729                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0) &
 730                         MV_U3D_EPXCR_EP_FLUSH) {
 731                         /*
 732                          * EP_FLUSH bit should be cleared to indicate this
 733                          * operation is complete
 734                          */
 735                         if (loops == 0) {
 736                                 dev_dbg(u3d->dev,
 737                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 738                                     direction ? "in" : "out");
 739                                 return;
 740                         }
 741                         loops--;
 742                         udelay(LOOPS_USEC);
 743                 }
 744         } else {        /* EP_DIR_IN */
 745                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 746                 tmp |= MV_U3D_EPXCR_EP_FLUSH;
 747                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 748
 749                 /* Wait until flushing completed */
 750                 loops = LOOPS(MV_U3D_FLUSH_TIMEOUT);
 751                 while (ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0) &
 752                         MV_U3D_EPXCR_EP_FLUSH) {
 753                         /*
 754                         * EP_FLUSH bit should be cleared to indicate this
 755                         * operation is complete
 756                         */
 757                         if (loops == 0) {
 758                                 dev_dbg(u3d->dev,
 759                                     "EP FLUSH TIMEOUT for ep%d%s\n", ep->ep_num,
 760                                     direction ? "in" : "out");
 761                                 return;
 762                         }
 763                         loops--;
 764                         udelay(LOOPS_USEC);
 765                 }
 766         }
 767 }
 768
 769 /* queues (submits) an I/O request to an endpoint */
 770 static int
 771 mv_u3d_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
 772 {
 773         struct mv_u3d_ep *ep;
 774         struct mv_u3d_req *req;
 775         struct mv_u3d *u3d;
 776         unsigned long flags;
 777         int is_first_req = 0;
 778
 779         if (unlikely(!_ep || !_req))
 780                 return -EINVAL;
 781
 782         ep = container_of(_ep, struct mv_u3d_ep, ep);
 783         u3d = ep->u3d;
 784
 785         req = container_of(_req, struct mv_u3d_req, req);
 786
 787         if (!ep->ep_num
 788                 && u3d->ep0_state == MV_U3D_STATUS_STAGE
 789                 && !_req->length) {
 790                 dev_dbg(u3d->dev, "ep0 status stage\n");
 791                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
 792                 return 0;
 793         }
 794
 795         dev_dbg(u3d->dev, "%s: %s, req: 0x%p\n",
 796                         __func__, _ep->name, req);
 797
 798         /* catch various bogus parameters */
 799         if (!req->req.complete || !req->req.buf
 800                         || !list_empty(&req->queue)) {
 801                 dev_err(u3d->dev,
 802                         "%s, bad params, _req: 0x%p,"
 803                         "req->req.complete: 0x%p, req->req.buf: 0x%p,"
 804                         "list_empty: 0x%x\n",
 805                         __func__, _req,
 806                         req->req.complete, req->req.buf,
 807                         list_empty(&req->queue));
 808                 return -EINVAL;
 809         }
 810         if (unlikely(!ep->ep.desc)) {
 811                 dev_err(u3d->dev, "%s, bad ep\n", __func__);
 812                 return -EINVAL;
 813         }
 814         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 815                 if (req->req.length > ep->ep.maxpacket)
 816                         return -EMSGSIZE;
 817         }
 818
 819         if (!u3d->driver || u3d->gadget.speed == USB_SPEED_UNKNOWN) {
 820                 dev_err(u3d->dev,
 821                         "bad params of driver/speed\n");
 822                 return -ESHUTDOWN;
 823         }
 824
 825         req->ep = ep;
 826
 827         /* Software list handles usb request. */
 828         spin_lock_irqsave(&ep->req_lock, flags);
 829         is_first_req = list_empty(&ep->req_list);
 830         list_add_tail(&req->list, &ep->req_list);
 831         spin_unlock_irqrestore(&ep->req_lock, flags);
 832         if (!is_first_req) {
 833                 dev_dbg(u3d->dev, "list is not empty\n");
 834                 return 0;
 835         }
 836
 837         dev_dbg(u3d->dev, "call mv_u3d_start_queue from usb_ep_queue\n");
 838         spin_lock_irqsave(&u3d->lock, flags);
 839         mv_u3d_start_queue(ep);
 840         spin_unlock_irqrestore(&u3d->lock, flags);
 841         return 0;
 842 }
 843
 844 /* dequeues (cancels, unlinks) an I/O request from an endpoint */
 845 static int mv_u3d_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
 846 {
 847         struct mv_u3d_ep *ep;
 848         struct mv_u3d_req *req;
 849         struct mv_u3d *u3d;
 850         struct mv_u3d_ep_context *ep_context;
 851         struct mv_u3d_req *next_req;
 852
 853         unsigned long flags;
 854         int ret = 0;
 855
 856         if (!_ep || !_req)
 857                 return -EINVAL;
 858
 859         ep = container_of(_ep, struct mv_u3d_ep, ep);
 860         u3d = ep->u3d;
 861
 862         spin_lock_irqsave(&ep->u3d->lock, flags);
 863
 864         /* make sure it's actually queued on this endpoint */
 865         list_for_each_entry(req, &ep->queue, queue) {
 866                 if (&req->req == _req)
 867                         break;
 868         }
 869         if (&req->req != _req) {
 870                 ret = -EINVAL;
 871                 goto out;
 872         }
 873
 874         /* The request is in progress, or completed but not dequeued */
 875         if (ep->queue.next == &req->queue) {
 876                 _req->status = -ECONNRESET;
 877                 mv_u3d_ep_fifo_flush(_ep);
 878
 879                 /* The request isn't the last request in this ep queue */
 880                 if (req->queue.next != &ep->queue) {
 881                         dev_dbg(u3d->dev,
 882                                 "it is the last request in this ep queue\n");
 883                         ep_context = ep->ep_context;
 884                         next_req = list_entry(req->queue.next,
 885                                         struct mv_u3d_req, queue);
 886
 887                         /* Point first TRB of next request to the EP context. */
 888                         iowrite32((unsigned long) next_req->trb_head,
 889                                         &ep_context->trb_addr_lo);
 890                 } else {
 891                         struct mv_u3d_ep_context *ep_context;
 892                         ep_context = ep->ep_context;
 893                         ep_context->trb_addr_lo = 0;
 894                         ep_context->trb_addr_hi = 0;
 895                 }
 896
 897         } else
 898                 WARN_ON(1);
 899
 900         mv_u3d_done(ep, req, -ECONNRESET);
 901
 902         /* remove the req from the ep req list */
 903         if (!list_empty(&ep->req_list)) {
 904                 struct mv_u3d_req *curr_req;
 905                 curr_req = list_entry(ep->req_list.next,
 906                                         struct mv_u3d_req, list);
 907                 if (curr_req == req) {
 908                         list_del_init(&req->list);
 909                         ep->processing = 0;
 910                 }
 911         }
 912
 913 out:
 914         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 915         return ret;
 916 }
 917
 918 static void
 919 mv_u3d_ep_set_stall(struct mv_u3d *u3d, u8 ep_num, u8 direction, int stall)
 920 {
 921         u32 tmp;
 922         struct mv_u3d_ep *ep = u3d->eps;
 923
 924         dev_dbg(u3d->dev, "%s\n", __func__);
 925         if (direction == MV_U3D_EP_DIR_OUT) {
 926                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 927                 if (stall)
 928                         tmp |= MV_U3D_EPXCR_EP_HALT;
 929                 else
 930                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 931                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxoutcr0);
 932         } else {
 933                 tmp = ioread32(&u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 934                 if (stall)
 935                         tmp |= MV_U3D_EPXCR_EP_HALT;
 936                 else
 937                         tmp &= ~MV_U3D_EPXCR_EP_HALT;
 938                 iowrite32(tmp, &u3d->vuc_regs->epcr[ep->ep_num].epxincr0);
 939         }
 940 }
 941
 942 static int mv_u3d_ep_set_halt_wedge(struct usb_ep *_ep, int halt, int wedge)
 943 {
 944         struct mv_u3d_ep *ep;
 945         unsigned long flags = 0;
 946         int status = 0;
 947         struct mv_u3d *u3d;
 948
 949         ep = container_of(_ep, struct mv_u3d_ep, ep);
 950         u3d = ep->u3d;
 951         if (!ep->ep.desc) {
 952                 status = -EINVAL;
 953                 goto out;
 954         }
 955
 956         if (ep->ep.desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
 957                 status = -EOPNOTSUPP;
 958                 goto out;
 959         }
 960
 961         /*
 962          * Attempt to halt IN ep will fail if any transfer requests
 963          * are still queue
 964          */
 965         if (halt && (mv_u3d_ep_dir(ep) == MV_U3D_EP_DIR_IN)
 966                         && !list_empty(&ep->queue)) {
 967                 status = -EAGAIN;
 968                 goto out;
 969         }
 970
 971         spin_lock_irqsave(&ep->u3d->lock, flags);
 972         mv_u3d_ep_set_stall(u3d, ep->ep_num, mv_u3d_ep_dir(ep), halt);
 973         if (halt && wedge)
 974                 ep->wedge = 1;
 975         else if (!halt)
 976                 ep->wedge = 0;
 977         spin_unlock_irqrestore(&ep->u3d->lock, flags);
 978
 979         if (ep->ep_num == 0)
 980                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
 981 out:
 982         return status;
 983 }
 984
 985 static int mv_u3d_ep_set_halt(struct usb_ep *_ep, int halt)
 986 {
 987         return mv_u3d_ep_set_halt_wedge(_ep, halt, 0);
 988 }
 989
 990 static int mv_u3d_ep_set_wedge(struct usb_ep *_ep)
 991 {
 992         return mv_u3d_ep_set_halt_wedge(_ep, 1, 1);
 993 }
 994
 995 static const struct usb_ep_ops mv_u3d_ep_ops = {
 996         .enable         = mv_u3d_ep_enable,
 997         .disable        = mv_u3d_ep_disable,
 998
 999         .alloc_request  = mv_u3d_alloc_request,
1000         .free_request   = mv_u3d_free_request,
1001
1002         .queue          = mv_u3d_ep_queue,
1003         .dequeue        = mv_u3d_ep_dequeue,
1004
1005         .set_wedge      = mv_u3d_ep_set_wedge,
1006         .set_halt       = mv_u3d_ep_set_halt,
1007         .fifo_flush     = mv_u3d_ep_fifo_flush,
1008 };
1009
1010 static void mv_u3d_controller_stop(struct mv_u3d *u3d)
1011 {
1012         u32 tmp;
1013
1014         if (!u3d->clock_gating && u3d->vbus_valid_detect)
1015                 iowrite32(MV_U3D_INTR_ENABLE_VBUS_VALID,
1016                                 &u3d->vuc_regs->intrenable);
1017         else
1018                 iowrite32(0, &u3d->vuc_regs->intrenable);
1019         iowrite32(~0x0, &u3d->vuc_regs->endcomplete);
1020         iowrite32(~0x0, &u3d->vuc_regs->trbunderrun);
1021         iowrite32(~0x0, &u3d->vuc_regs->trbcomplete);
1022         iowrite32(~0x0, &u3d->vuc_regs->linkchange);
1023         iowrite32(0x1, &u3d->vuc_regs->setuplock);
1024
1025         /* Reset the RUN bit in the command register to stop USB */
1026         tmp = ioread32(&u3d->op_regs->usbcmd);
1027         tmp &= ~MV_U3D_CMD_RUN_STOP;
1028         iowrite32(tmp, &u3d->op_regs->usbcmd);
1029         dev_dbg(u3d->dev, "after u3d_stop, USBCMD 0x%x\n",
1030                 ioread32(&u3d->op_regs->usbcmd));
1031 }
1032
1033 static void mv_u3d_controller_start(struct mv_u3d *u3d)
1034 {
1035         u32 usbintr;
1036         u32 temp;
1037
1038         /* enable link LTSSM state machine */
1039         temp = ioread32(&u3d->vuc_regs->ltssm);
1040         temp |= MV_U3D_LTSSM_PHY_INIT_DONE;
1041         iowrite32(temp, &u3d->vuc_regs->ltssm);
1042
1043         /* Enable interrupts */
1044         usbintr = MV_U3D_INTR_ENABLE_LINK_CHG | MV_U3D_INTR_ENABLE_TXDESC_ERR |
1045                 MV_U3D_INTR_ENABLE_RXDESC_ERR | MV_U3D_INTR_ENABLE_TX_COMPLETE |
1046                 MV_U3D_INTR_ENABLE_RX_COMPLETE | MV_U3D_INTR_ENABLE_SETUP |
1047                 (u3d->vbus_valid_detect ? MV_U3D_INTR_ENABLE_VBUS_VALID : 0);
1048         iowrite32(usbintr, &u3d->vuc_regs->intrenable);
1049
1050         /* Enable ctrl ep */
1051         iowrite32(0x1, &u3d->vuc_regs->ctrlepenable);
1052
1053         /* Set the Run bit in the command register */
1054         iowrite32(MV_U3D_CMD_RUN_STOP, &u3d->op_regs->usbcmd);
1055         dev_dbg(u3d->dev, "after u3d_start, USBCMD 0x%x\n",
1056                 ioread32(&u3d->op_regs->usbcmd));
1057 }
1058
1059 static int mv_u3d_controller_reset(struct mv_u3d *u3d)
1060 {
1061         unsigned int loops;
1062         u32 tmp;
1063
1064         /* Stop the controller */
1065         tmp = ioread32(&u3d->op_regs->usbcmd);
1066         tmp &= ~MV_U3D_CMD_RUN_STOP;
1067         iowrite32(tmp, &u3d->op_regs->usbcmd);
1068
1069         /* Reset the controller to get default values */
1070         iowrite32(MV_U3D_CMD_CTRL_RESET, &u3d->op_regs->usbcmd);
1071
1072         /* wait for reset to complete */
1073         loops = LOOPS(MV_U3D_RESET_TIMEOUT);
1074         while (ioread32(&u3d->op_regs->usbcmd) & MV_U3D_CMD_CTRL_RESET) {
1075                 if (loops == 0) {
1076                         dev_err(u3d->dev,
1077                                 "Wait for RESET completed TIMEOUT\n");
1078                         return -ETIMEDOUT;
1079                 }
1080                 loops--;
1081                 udelay(LOOPS_USEC);
1082         }
1083
1084         /* Configure the Endpoint Context Address */
1085         iowrite32(u3d->ep_context_dma, &u3d->op_regs->dcbaapl);
1086         iowrite32(0, &u3d->op_regs->dcbaaph);
1087
1088         return 0;
1089 }
1090
1091 static int mv_u3d_enable(struct mv_u3d *u3d)
1092 {
1093         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1094         int retval;
1095
1096         if (u3d->active)
1097                 return 0;
1098
1099         if (!u3d->clock_gating) {
1100                 u3d->active = 1;
1101                 return 0;
1102         }
1103
1104         dev_dbg(u3d->dev, "enable u3d\n");
1105         clk_enable(u3d->clk);
1106         if (pdata->phy_init) {
1107                 retval = pdata->phy_init(u3d->phy_regs);
1108                 if (retval) {
1109                         dev_err(u3d->dev,
1110                                 "init phy error %d\n", retval);
1111                         clk_disable(u3d->clk);
1112                         return retval;
1113                 }
1114         }
1115         u3d->active = 1;
1116
1117         return 0;
1118 }
1119
1120 static void mv_u3d_disable(struct mv_u3d *u3d)
1121 {
1122         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1123         if (u3d->clock_gating && u3d->active) {
1124                 dev_dbg(u3d->dev, "disable u3d\n");
1125                 if (pdata->phy_deinit)
1126                         pdata->phy_deinit(u3d->phy_regs);
1127                 clk_disable(u3d->clk);
1128                 u3d->active = 0;
1129         }
1130 }
1131
1132 static int mv_u3d_vbus_session(struct usb_gadget *gadget, int is_active)
1133 {
1134         struct mv_u3d *u3d;
1135         unsigned long flags;
1136         int retval = 0;
1137
1138         u3d = container_of(gadget, struct mv_u3d, gadget);
1139
1140         spin_lock_irqsave(&u3d->lock, flags);
1141
1142         u3d->vbus_active = (is_active != 0);
1143         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1144                 __func__, u3d->softconnect, u3d->vbus_active);
1145         /*
1146          * 1. external VBUS detect: we can disable/enable clock on demand.
1147          * 2. UDC VBUS detect: we have to enable clock all the time.
1148          * 3. No VBUS detect: we have to enable clock all the time.
1149          */
1150         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1151                 retval = mv_u3d_enable(u3d);
1152                 if (retval == 0) {
1153                         /*
1154                          * after clock is disabled, we lost all the register
1155                          *  context. We have to re-init registers
1156                          */
1157                         mv_u3d_controller_reset(u3d);
1158                         mv_u3d_ep0_reset(u3d);
1159                         mv_u3d_controller_start(u3d);
1160                 }
1161         } else if (u3d->driver && u3d->softconnect) {
1162                 if (!u3d->active)
1163                         goto out;
1164
1165                 /* stop all the transfer in queue*/
1166                 mv_u3d_stop_activity(u3d, u3d->driver);
1167                 mv_u3d_controller_stop(u3d);
1168                 mv_u3d_disable(u3d);
1169         }
1170
1171 out:
1172         spin_unlock_irqrestore(&u3d->lock, flags);
1173         return retval;
1174 }
1175
1176 /* constrain controller's VBUS power usage
1177  * This call is used by gadget drivers during SET_CONFIGURATION calls,
1178  * reporting how much power the device may consume.  For example, this
1179  * could affect how quickly batteries are recharged.
1180  *
1181  * Returns zero on success, else negative errno.
1182  */
1183 static int mv_u3d_vbus_draw(struct usb_gadget *gadget, unsigned mA)
1184 {
1185         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1186
1187         u3d->power = mA;
1188
1189         return 0;
1190 }
1191
1192 static int mv_u3d_pullup(struct usb_gadget *gadget, int is_on)
1193 {
1194         struct mv_u3d *u3d = container_of(gadget, struct mv_u3d, gadget);
1195         unsigned long flags;
1196         int retval = 0;
1197
1198         spin_lock_irqsave(&u3d->lock, flags);
1199
1200         dev_dbg(u3d->dev, "%s: softconnect %d, vbus_active %d\n",
1201                 __func__, u3d->softconnect, u3d->vbus_active);
1202         u3d->softconnect = (is_on != 0);
1203         if (u3d->driver && u3d->softconnect && u3d->vbus_active) {
1204                 retval = mv_u3d_enable(u3d);
1205                 if (retval == 0) {
1206                         /*
1207                          * after clock is disabled, we lost all the register
1208                          *  context. We have to re-init registers
1209                          */
1210                         mv_u3d_controller_reset(u3d);
1211                         mv_u3d_ep0_reset(u3d);
1212                         mv_u3d_controller_start(u3d);
1213                 }
1214         } else if (u3d->driver && u3d->vbus_active) {
1215                 /* stop all the transfer in queue*/
1216                 mv_u3d_stop_activity(u3d, u3d->driver);
1217                 mv_u3d_controller_stop(u3d);
1218                 mv_u3d_disable(u3d);
1219         }
1220
1221         spin_unlock_irqrestore(&u3d->lock, flags);
1222
1223         return retval;
1224 }
1225
1226 static int mv_u3d_start(struct usb_gadget *g,
1227                 struct usb_gadget_driver *driver)
1228 {
1229         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1230         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1231         unsigned long flags;
1232
1233         if (u3d->driver)
1234                 return -EBUSY;
1235
1236         spin_lock_irqsave(&u3d->lock, flags);
1237
1238         if (!u3d->clock_gating) {
1239                 clk_enable(u3d->clk);
1240                 if (pdata->phy_init)
1241                         pdata->phy_init(u3d->phy_regs);
1242         }
1243
1244         /* hook up the driver ... */
1245         driver->driver.bus = NULL;
1246         u3d->driver = driver;
1247
1248         u3d->ep0_dir = USB_DIR_OUT;
1249
1250         spin_unlock_irqrestore(&u3d->lock, flags);
1251
1252         u3d->vbus_valid_detect = 1;
1253
1254         return 0;
1255 }
1256
1257 static int mv_u3d_stop(struct usb_gadget *g)
1258 {
1259         struct mv_u3d *u3d = container_of(g, struct mv_u3d, gadget);
1260         struct mv_usb_platform_data *pdata = dev_get_platdata(u3d->dev);
1261         unsigned long flags;
1262
1263         u3d->vbus_valid_detect = 0;
1264         spin_lock_irqsave(&u3d->lock, flags);
1265
1266         /* enable clock to access controller register */
1267         clk_enable(u3d->clk);
1268         if (pdata->phy_init)
1269                 pdata->phy_init(u3d->phy_regs);
1270
1271         mv_u3d_controller_stop(u3d);
1272         /* stop all usb activities */
1273         u3d->gadget.speed = USB_SPEED_UNKNOWN;
1274         mv_u3d_stop_activity(u3d, NULL);
1275         mv_u3d_disable(u3d);
1276
1277         if (pdata->phy_deinit)
1278                 pdata->phy_deinit(u3d->phy_regs);
1279         clk_disable(u3d->clk);
1280
1281         spin_unlock_irqrestore(&u3d->lock, flags);
1282
1283         u3d->driver = NULL;
1284
1285         return 0;
1286 }
1287
1288 /* device controller usb_gadget_ops structure */
1289 static const struct usb_gadget_ops mv_u3d_ops = {
1290         /* notify controller that VBUS is powered or not */
1291         .vbus_session   = mv_u3d_vbus_session,
1292
1293         /* constrain controller's VBUS power usage */
1294         .vbus_draw      = mv_u3d_vbus_draw,
1295
1296         .pullup         = mv_u3d_pullup,
1297         .udc_start      = mv_u3d_start,
1298         .udc_stop       = mv_u3d_stop,
1299 };
1300
1301 static int mv_u3d_eps_init(struct mv_u3d *u3d)
1302 {
1303         struct mv_u3d_ep        *ep;
1304         char name[14];
1305         int i;
1306
1307         /* initialize ep0, ep0 in/out use eps[1] */
1308         ep = &u3d->eps[1];
1309         ep->u3d = u3d;
1310         strncpy(ep->name, "ep0", sizeof(ep->name));
1311         ep->ep.name = ep->name;
1312         ep->ep.ops = &mv_u3d_ep_ops;
1313         ep->wedge = 0;
1314         usb_ep_set_maxpacket_limit(&ep->ep, MV_U3D_EP0_MAX_PKT_SIZE);
1315         ep->ep.caps.type_control = true;
1316         ep->ep.caps.dir_in = true;
1317         ep->ep.caps.dir_out = true;
1318         ep->ep_num = 0;
1319         ep->ep.desc = &mv_u3d_ep0_desc;
1320         INIT_LIST_HEAD(&ep->queue);
1321         INIT_LIST_HEAD(&ep->req_list);
1322         ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
1323
1324         /* add ep0 ep_context */
1325         ep->ep_context = &u3d->ep_context[1];
1326
1327         /* initialize other endpoints */
1328         for (i = 2; i < u3d->max_eps * 2; i++) {
1329                 ep = &u3d->eps[i];
1330                 if (i & 1) {
1331                         snprintf(name, sizeof(name), "ep%din", i >> 1);
1332                         ep->direction = MV_U3D_EP_DIR_IN;
1333                         ep->ep.caps.dir_in = true;
1334                 } else {
1335                         snprintf(name, sizeof(name), "ep%dout", i >> 1);
1336                         ep->direction = MV_U3D_EP_DIR_OUT;
1337                         ep->ep.caps.dir_out = true;
1338                 }
1339                 ep->u3d = u3d;
1340                 strncpy(ep->name, name, sizeof(ep->name));
1341                 ep->ep.name = ep->name;
1342
1343                 ep->ep.caps.type_iso = true;
1344                 ep->ep.caps.type_bulk = true;
1345                 ep->ep.caps.type_int = true;
1346
1347                 ep->ep.ops = &mv_u3d_ep_ops;
1348                 usb_ep_set_maxpacket_limit(&ep->ep, (unsigned short) ~0);
1349                 ep->ep_num = i / 2;
1350
1351                 INIT_LIST_HEAD(&ep->queue);
1352                 list_add_tail(&ep->ep.ep_list, &u3d->gadget.ep_list);
1353
1354                 INIT_LIST_HEAD(&ep->req_list);
1355                 spin_lock_init(&ep->req_lock);
1356                 ep->ep_context = &u3d->ep_context[i];
1357         }
1358
1359         return 0;
1360 }
1361
1362 /* delete all endpoint requests, called with spinlock held */
1363 static void mv_u3d_nuke(struct mv_u3d_ep *ep, int status)
1364 {
1365         /* endpoint fifo flush */
1366         mv_u3d_ep_fifo_flush(&ep->ep);
1367
1368         while (!list_empty(&ep->queue)) {
1369                 struct mv_u3d_req *req = NULL;
1370                 req = list_entry(ep->queue.next, struct mv_u3d_req, queue);
1371                 mv_u3d_done(ep, req, status);
1372         }
1373 }
1374
1375 /* stop all USB activities */
1376 static
1377 void mv_u3d_stop_activity(struct mv_u3d *u3d, struct usb_gadget_driver *driver)
1378 {
1379         struct mv_u3d_ep        *ep;
1380
1381         mv_u3d_nuke(&u3d->eps[1], -ESHUTDOWN);
1382
1383         list_for_each_entry(ep, &u3d->gadget.ep_list, ep.ep_list) {
1384                 mv_u3d_nuke(ep, -ESHUTDOWN);
1385         }
1386
1387         /* report disconnect; the driver is already quiesced */
1388         if (driver) {
1389                 spin_unlock(&u3d->lock);
1390                 driver->disconnect(&u3d->gadget);
1391                 spin_lock(&u3d->lock);
1392         }
1393 }
1394
1395 static void mv_u3d_irq_process_error(struct mv_u3d *u3d)
1396 {
1397         /* Increment the error count */
1398         u3d->errors++;
1399         dev_err(u3d->dev, "%s\n", __func__);
1400 }
1401
1402 static void mv_u3d_irq_process_link_change(struct mv_u3d *u3d)
1403 {
1404         u32 linkchange;
1405
1406         linkchange = ioread32(&u3d->vuc_regs->linkchange);
1407         iowrite32(linkchange, &u3d->vuc_regs->linkchange);
1408
1409         dev_dbg(u3d->dev, "linkchange: 0x%x\n", linkchange);
1410
1411         if (linkchange & MV_U3D_LINK_CHANGE_LINK_UP) {
1412                 dev_dbg(u3d->dev, "link up: ltssm state: 0x%x\n",
1413                         ioread32(&u3d->vuc_regs->ltssmstate));
1414
1415                 u3d->usb_state = USB_STATE_DEFAULT;
1416                 u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1417                 u3d->ep0_state = MV_U3D_WAIT_FOR_SETUP;
1418
1419                 /* set speed */
1420                 u3d->gadget.speed = USB_SPEED_SUPER;
1421         }
1422
1423         if (linkchange & MV_U3D_LINK_CHANGE_SUSPEND) {
1424                 dev_dbg(u3d->dev, "link suspend\n");
1425                 u3d->resume_state = u3d->usb_state;
1426                 u3d->usb_state = USB_STATE_SUSPENDED;
1427         }
1428
1429         if (linkchange & MV_U3D_LINK_CHANGE_RESUME) {
1430                 dev_dbg(u3d->dev, "link resume\n");
1431                 u3d->usb_state = u3d->resume_state;
1432                 u3d->resume_state = 0;
1433         }
1434
1435         if (linkchange & MV_U3D_LINK_CHANGE_WRESET) {
1436                 dev_dbg(u3d->dev, "warm reset\n");
1437                 u3d->usb_state = USB_STATE_POWERED;
1438         }
1439
1440         if (linkchange & MV_U3D_LINK_CHANGE_HRESET) {
1441                 dev_dbg(u3d->dev, "hot reset\n");
1442                 u3d->usb_state = USB_STATE_DEFAULT;
1443         }
1444
1445         if (linkchange & MV_U3D_LINK_CHANGE_INACT)
1446                 dev_dbg(u3d->dev, "inactive\n");
1447
1448         if (linkchange & MV_U3D_LINK_CHANGE_DISABLE_AFTER_U0)
1449                 dev_dbg(u3d->dev, "ss.disabled\n");
1450
1451         if (linkchange & MV_U3D_LINK_CHANGE_VBUS_INVALID) {
1452                 dev_dbg(u3d->dev, "vbus invalid\n");
1453                 u3d->usb_state = USB_STATE_ATTACHED;
1454                 u3d->vbus_valid_detect = 1;
1455                 /* if external vbus detect is not supported,
1456                  * we handle it here.
1457                  */
1458                 if (!u3d->vbus) {
1459                         spin_unlock(&u3d->lock);
1460                         mv_u3d_vbus_session(&u3d->gadget, 0);
1461                         spin_lock(&u3d->lock);
1462                 }
1463         }
1464 }
1465
1466 static void mv_u3d_ch9setaddress(struct mv_u3d *u3d,
1467                                 struct usb_ctrlrequest *setup)
1468 {
1469         u32 tmp;
1470
1471         if (u3d->usb_state != USB_STATE_DEFAULT) {
1472                 dev_err(u3d->dev,
1473                         "%s, cannot setaddr in this state (%d)\n",
1474                         __func__, u3d->usb_state);
1475                 goto err;
1476         }
1477
1478         u3d->dev_addr = (u8)setup->wValue;
1479
1480         dev_dbg(u3d->dev, "%s: 0x%x\n", __func__, u3d->dev_addr);
1481
1482         if (u3d->dev_addr > 127) {
1483                 dev_err(u3d->dev,
1484                         "%s, u3d address is wrong (out of range)\n", __func__);
1485                 u3d->dev_addr = 0;
1486                 goto err;
1487         }
1488
1489         /* update usb state */
1490         u3d->usb_state = USB_STATE_ADDRESS;
1491
1492         /* set the new address */
1493         tmp = ioread32(&u3d->vuc_regs->devaddrtiebrkr);
1494         tmp &= ~0x7F;
1495         tmp |= (u32)u3d->dev_addr;
1496         iowrite32(tmp, &u3d->vuc_regs->devaddrtiebrkr);
1497
1498         return;
1499 err:
1500         mv_u3d_ep0_stall(u3d);
1501 }
1502
1503 static int mv_u3d_is_set_configuration(struct usb_ctrlrequest *setup)
1504 {
1505         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
1506                 if (setup->bRequest == USB_REQ_SET_CONFIGURATION)
1507                         return 1;
1508
1509         return 0;
1510 }
1511
1512 static void mv_u3d_handle_setup_packet(struct mv_u3d *u3d, u8 ep_num,
1513         struct usb_ctrlrequest *setup)
1514         __releases(&u3c->lock)
1515         __acquires(&u3c->lock)
1516 {
1517         bool delegate = false;
1518
1519         mv_u3d_nuke(&u3d->eps[ep_num * 2 + MV_U3D_EP_DIR_IN], -ESHUTDOWN);
1520
1521         dev_dbg(u3d->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
1522                         setup->bRequestType, setup->bRequest,
1523                         setup->wValue, setup->wIndex, setup->wLength);
1524
1525         /* We process some stardard setup requests here */
1526         if ((setup->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
1527                 switch (setup->bRequest) {
1528                 case USB_REQ_GET_STATUS:
1529                         delegate = true;
1530                         break;
1531
1532                 case USB_REQ_SET_ADDRESS:
1533                         mv_u3d_ch9setaddress(u3d, setup);
1534                         break;
1535
1536                 case USB_REQ_CLEAR_FEATURE:
1537                         delegate = true;
1538                         break;
1539
1540                 case USB_REQ_SET_FEATURE:
1541                         delegate = true;
1542                         break;
1543
1544                 default:
1545                         delegate = true;
1546                 }
1547         } else
1548                 delegate = true;
1549
1550         /* delegate USB standard requests to the gadget driver */
1551         if (delegate == true) {
1552                 /* USB requests handled by gadget */
1553                 if (setup->wLength) {
1554                         /* DATA phase from gadget, STATUS phase from u3d */
1555                         u3d->ep0_dir = (setup->bRequestType & USB_DIR_IN)
1556                                         ? MV_U3D_EP_DIR_IN : MV_U3D_EP_DIR_OUT;
1557                         spin_unlock(&u3d->lock);
1558                         if (u3d->driver->setup(&u3d->gadget,
1559                                 &u3d->local_setup_buff) < 0) {
1560                                 dev_err(u3d->dev, "setup error!\n");
1561                                 mv_u3d_ep0_stall(u3d);
1562                         }
1563                         spin_lock(&u3d->lock);
1564                 } else {
1565                         /* no DATA phase, STATUS phase from gadget */
1566                         u3d->ep0_dir = MV_U3D_EP_DIR_IN;
1567                         u3d->ep0_state = MV_U3D_STATUS_STAGE;
1568                         spin_unlock(&u3d->lock);
1569                         if (u3d->driver->setup(&u3d->gadget,
1570                                 &u3d->local_setup_buff) < 0)
1571                                 mv_u3d_ep0_stall(u3d);
1572                         spin_lock(&u3d->lock);
1573                 }
1574
1575                 if (mv_u3d_is_set_configuration(setup)) {
1576                         dev_dbg(u3d->dev, "u3d configured\n");
1577                         u3d->usb_state = USB_STATE_CONFIGURED;
1578                 }
1579         }
1580 }
1581
1582 static void mv_u3d_get_setup_data(struct mv_u3d *u3d, u8 ep_num, u8 *buffer_ptr)
1583 {
1584         struct mv_u3d_ep_context *epcontext;
1585
1586         epcontext = &u3d->ep_context[ep_num * 2 + MV_U3D_EP_DIR_IN];
1587
1588         /* Copy the setup packet to local buffer */
1589         memcpy(buffer_ptr, (u8 *) &epcontext->setup_buffer, 8);
1590 }
1591
1592 static void mv_u3d_irq_process_setup(struct mv_u3d *u3d)
1593 {
1594         u32 tmp, i;
1595         /* Process all Setup packet received interrupts */
1596         tmp = ioread32(&u3d->vuc_regs->setuplock);
1597         if (tmp) {
1598                 for (i = 0; i < u3d->max_eps; i++) {
1599                         if (tmp & (1 << i)) {
1600                                 mv_u3d_get_setup_data(u3d, i,
1601                                         (u8 *)(&u3d->local_setup_buff));
1602                                 mv_u3d_handle_setup_packet(u3d, i,
1603                                         &u3d->local_setup_buff);
1604                         }
1605                 }
1606         }
1607
1608         iowrite32(tmp, &u3d->vuc_regs->setuplock);
1609 }
1610
1611 static void mv_u3d_irq_process_tr_complete(struct mv_u3d *u3d)
1612 {
1613         u32 tmp, bit_pos;
1614         int i, ep_num = 0, direction = 0;
1615         struct mv_u3d_ep        *curr_ep;
1616         struct mv_u3d_req *curr_req, *temp_req;
1617         int status;
1618
1619         tmp = ioread32(&u3d->vuc_regs->endcomplete);
1620
1621         dev_dbg(u3d->dev, "tr_complete: ep: 0x%x\n", tmp);
1622         if (!tmp)
1623                 return;
1624         iowrite32(tmp, &u3d->vuc_regs->endcomplete);
1625
1626         for (i = 0; i < u3d->max_eps * 2; i++) {
1627                 ep_num = i >> 1;
1628                 direction = i % 2;
1629
1630                 bit_pos = 1 << (ep_num + 16 * direction);
1631
1632                 if (!(bit_pos & tmp))
1633                         continue;
1634
1635                 if (i == 0)
1636                         curr_ep = &u3d->eps[1];
1637                 else
1638                         curr_ep = &u3d->eps[i];
1639
1640                 /* remove req out of ep request list after completion */
1641                 dev_dbg(u3d->dev, "tr comp: check req_list\n");
1642                 spin_lock(&curr_ep->req_lock);
1643                 if (!list_empty(&curr_ep->req_list)) {
1644                         struct mv_u3d_req *req;
1645                         req = list_entry(curr_ep->req_list.next,
1646                                                 struct mv_u3d_req, list);
1647                         list_del_init(&req->list);
1648                         curr_ep->processing = 0;
1649                 }
1650                 spin_unlock(&curr_ep->req_lock);
1651
1652                 /* process the req queue until an uncomplete request */
1653                 list_for_each_entry_safe(curr_req, temp_req,
1654                         &curr_ep->queue, queue) {
1655                         status = mv_u3d_process_ep_req(u3d, i, curr_req);
1656                         if (status)
1657                                 break;
1658                         /* write back status to req */
1659                         curr_req->req.status = status;
1660
1661                         /* ep0 request completion */
1662                         if (ep_num == 0) {
1663                                 mv_u3d_done(curr_ep, curr_req, 0);
1664                                 break;
1665                         } else {
1666                                 mv_u3d_done(curr_ep, curr_req, status);
1667                         }
1668                 }
1669
1670                 dev_dbg(u3d->dev, "call mv_u3d_start_queue from ep complete\n");
1671                 mv_u3d_start_queue(curr_ep);
1672         }
1673 }
1674
1675 static irqreturn_t mv_u3d_irq(int irq, void *dev)
1676 {
1677         struct mv_u3d *u3d = (struct mv_u3d *)dev;
1678         u32 status, intr;
1679         u32 bridgesetting;
1680         u32 trbunderrun;
1681
1682         spin_lock(&u3d->lock);
1683
1684         status = ioread32(&u3d->vuc_regs->intrcause);
1685         intr = ioread32(&u3d->vuc_regs->intrenable);
1686         status &= intr;
1687
1688         if (status == 0) {
1689                 spin_unlock(&u3d->lock);
1690                 dev_err(u3d->dev, "irq error!\n");
1691                 return IRQ_NONE;
1692         }
1693
1694         if (status & MV_U3D_USBINT_VBUS_VALID) {
1695                 bridgesetting = ioread32(&u3d->vuc_regs->bridgesetting);
1696                 if (bridgesetting & MV_U3D_BRIDGE_SETTING_VBUS_VALID) {
1697                         /* write vbus valid bit of bridge setting to clear */
1698                         bridgesetting = MV_U3D_BRIDGE_SETTING_VBUS_VALID;
1699                         iowrite32(bridgesetting, &u3d->vuc_regs->bridgesetting);
1700                         dev_dbg(u3d->dev, "vbus valid\n");
1701
1702                         u3d->usb_state = USB_STATE_POWERED;
1703                         u3d->vbus_valid_detect = 0;
1704                         /* if external vbus detect is not supported,
1705                          * we handle it here.
1706                          */
1707                         if (!u3d->vbus) {
1708                                 spin_unlock(&u3d->lock);
1709                                 mv_u3d_vbus_session(&u3d->gadget, 1);
1710                                 spin_lock(&u3d->lock);
1711                         }
1712                 } else
1713                         dev_err(u3d->dev, "vbus bit is not set\n");
1714         }
1715
1716         /* RX data is already in the 16KB FIFO.*/
1717         if (status & MV_U3D_USBINT_UNDER_RUN) {
1718                 trbunderrun = ioread32(&u3d->vuc_regs->trbunderrun);
1719                 dev_err(u3d->dev, "under run, ep%d\n", trbunderrun);
1720                 iowrite32(trbunderrun, &u3d->vuc_regs->trbunderrun);
1721                 mv_u3d_irq_process_error(u3d);
1722         }
1723
1724         if (status & (MV_U3D_USBINT_RXDESC_ERR | MV_U3D_USBINT_TXDESC_ERR)) {
1725                 /* write one to clear */
1726                 iowrite32(status & (MV_U3D_USBINT_RXDESC_ERR
1727                         | MV_U3D_USBINT_TXDESC_ERR),
1728                         &u3d->vuc_regs->intrcause);
1729                 dev_err(u3d->dev, "desc err 0x%x\n", status);
1730                 mv_u3d_irq_process_error(u3d);
1731         }
1732
1733         if (status & MV_U3D_USBINT_LINK_CHG)
1734                 mv_u3d_irq_process_link_change(u3d);
1735
1736         if (status & MV_U3D_USBINT_TX_COMPLETE)
1737                 mv_u3d_irq_process_tr_complete(u3d);
1738
1739         if (status & MV_U3D_USBINT_RX_COMPLETE)
1740                 mv_u3d_irq_process_tr_complete(u3d);
1741
1742         if (status & MV_U3D_USBINT_SETUP)
1743                 mv_u3d_irq_process_setup(u3d);
1744
1745         spin_unlock(&u3d->lock);
1746         return IRQ_HANDLED;
1747 }
1748
1749 static int mv_u3d_remove(struct platform_device *dev)
1750 {
1751         struct mv_u3d *u3d = platform_get_drvdata(dev);
1752
1753         BUG_ON(u3d == NULL);
1754
1755         usb_del_gadget_udc(&u3d->gadget);
1756
1757         /* free memory allocated in probe */
1758         dma_pool_destroy(u3d->trb_pool);
1759
1760         if (u3d->ep_context)
1761                 dma_free_coherent(&dev->dev, u3d->ep_context_size,
1762                         u3d->ep_context, u3d->ep_context_dma);
1763
1764         kfree(u3d->eps);
1765
1766         if (u3d->irq)
1767                 free_irq(u3d->irq, u3d);
1768
1769         if (u3d->cap_regs)
1770                 iounmap(u3d->cap_regs);
1771         u3d->cap_regs = NULL;
1772
1773         kfree(u3d->status_req);
1774
1775         clk_put(u3d->clk);
1776
1777         kfree(u3d);
1778
1779         return 0;
1780 }
1781
1782 static int mv_u3d_probe(struct platform_device *dev)
1783 {
1784         struct mv_u3d *u3d = NULL;
1785         struct mv_usb_platform_data *pdata = dev_get_platdata(&dev->dev);
1786         int retval = 0;
1787         struct resource *r;
1788         size_t size;
1789
1790         if (!dev_get_platdata(&dev->dev)) {
1791                 dev_err(&dev->dev, "missing platform_data\n");
1792                 retval = -ENODEV;
1793                 goto err_pdata;
1794         }
1795
1796         u3d = kzalloc(sizeof(*u3d), GFP_KERNEL);
1797         if (!u3d) {
1798                 retval = -ENOMEM;
1799                 goto err_alloc_private;
1800         }
1801
1802         spin_lock_init(&u3d->lock);
1803
1804         platform_set_drvdata(dev, u3d);
1805
1806         u3d->dev = &dev->dev;
1807         u3d->vbus = pdata->vbus;
1808
1809         u3d->clk = clk_get(&dev->dev, NULL);
1810         if (IS_ERR(u3d->clk)) {
1811                 retval = PTR_ERR(u3d->clk);
1812                 goto err_get_clk;
1813         }
1814
1815         r = platform_get_resource_byname(dev, IORESOURCE_MEM, "capregs");
1816         if (!r) {
1817                 dev_err(&dev->dev, "no I/O memory resource defined\n");
1818                 retval = -ENODEV;
1819                 goto err_get_cap_regs;
1820         }
1821
1822         u3d->cap_regs = (struct mv_u3d_cap_regs __iomem *)
1823                 ioremap(r->start, resource_size(r));
1824         if (!u3d->cap_regs) {
1825                 dev_err(&dev->dev, "failed to map I/O memory\n");
1826                 retval = -EBUSY;
1827                 goto err_map_cap_regs;
1828         } else {
1829                 dev_dbg(&dev->dev, "cap_regs address: 0x%lx/0x%lx\n",
1830                         (unsigned long) r->start,
1831                         (unsigned long) u3d->cap_regs);
1832         }
1833
1834         /* we will access controller register, so enable the u3d controller */
1835         retval = clk_enable(u3d->clk);
1836         if (retval) {
1837                 dev_err(&dev->dev, "clk_enable error %d\n", retval);
1838                 goto err_u3d_enable;
1839         }
1840
1841         if (pdata->phy_init) {
1842                 retval = pdata->phy_init(u3d->phy_regs);
1843                 if (retval) {
1844                         dev_err(&dev->dev, "init phy error %d\n", retval);
1845                         clk_disable(u3d->clk);
1846                         goto err_phy_init;
1847                 }
1848         }
1849
1850         u3d->op_regs = (struct mv_u3d_op_regs __iomem *)(u3d->cap_regs
1851                 + MV_U3D_USB3_OP_REGS_OFFSET);
1852
1853         u3d->vuc_regs = (struct mv_u3d_vuc_regs __iomem *)(u3d->cap_regs
1854                 + ioread32(&u3d->cap_regs->vuoff));
1855
1856         u3d->max_eps = 16;
1857
1858         /*
1859          * some platform will use usb to download image, it may not disconnect
1860          * usb gadget before loading kernel. So first stop u3d here.
1861          */
1862         mv_u3d_controller_stop(u3d);
1863         iowrite32(0xFFFFFFFF, &u3d->vuc_regs->intrcause);
1864
1865         if (pdata->phy_deinit)
1866                 pdata->phy_deinit(u3d->phy_regs);
1867         clk_disable(u3d->clk);
1868
1869         size = u3d->max_eps * sizeof(struct mv_u3d_ep_context) * 2;
1870         size = (size + MV_U3D_EP_CONTEXT_ALIGNMENT - 1)
1871                 & ~(MV_U3D_EP_CONTEXT_ALIGNMENT - 1);
1872         u3d->ep_context = dma_alloc_coherent(&dev->dev, size,
1873                                         &u3d->ep_context_dma, GFP_KERNEL);
1874         if (!u3d->ep_context) {
1875                 dev_err(&dev->dev, "allocate ep context memory failed\n");
1876                 retval = -ENOMEM;
1877                 goto err_alloc_ep_context;
1878         }
1879         u3d->ep_context_size = size;
1880
1881         /* create TRB dma_pool resource */
1882         u3d->trb_pool = dma_pool_create("u3d_trb",
1883                         &dev->dev,
1884                         sizeof(struct mv_u3d_trb_hw),
1885                         MV_U3D_TRB_ALIGNMENT,
1886                         MV_U3D_DMA_BOUNDARY);
1887
1888         if (!u3d->trb_pool) {
1889                 retval = -ENOMEM;
1890                 goto err_alloc_trb_pool;
1891         }
1892
1893         size = u3d->max_eps * sizeof(struct mv_u3d_ep) * 2;
1894         u3d->eps = kzalloc(size, GFP_KERNEL);
1895         if (!u3d->eps) {
1896                 retval = -ENOMEM;
1897                 goto err_alloc_eps;
1898         }
1899
1900         /* initialize ep0 status request structure */
1901         u3d->status_req = kzalloc(sizeof(struct mv_u3d_req) + 8, GFP_KERNEL);
1902         if (!u3d->status_req) {
1903                 retval = -ENOMEM;
1904                 goto err_alloc_status_req;
1905         }
1906         INIT_LIST_HEAD(&u3d->status_req->queue);
1907
1908         /* allocate a small amount of memory to get valid address */
1909         u3d->status_req->req.buf = (char *)u3d->status_req
1910                                         + sizeof(struct mv_u3d_req);
1911         u3d->status_req->req.dma = virt_to_phys(u3d->status_req->req.buf);
1912
1913         u3d->resume_state = USB_STATE_NOTATTACHED;
1914         u3d->usb_state = USB_STATE_ATTACHED;
1915         u3d->ep0_dir = MV_U3D_EP_DIR_OUT;
1916         u3d->remote_wakeup = 0;
1917
1918         r = platform_get_resource(dev, IORESOURCE_IRQ, 0);
1919         if (!r) {
1920                 dev_err(&dev->dev, "no IRQ resource defined\n");
1921                 retval = -ENODEV;
1922                 goto err_get_irq;
1923         }
1924         u3d->irq = r->start;
1925
1926         /* initialize gadget structure */
1927         u3d->gadget.ops = &mv_u3d_ops;  /* usb_gadget_ops */
1928         u3d->gadget.ep0 = &u3d->eps[1].ep;      /* gadget ep0 */
1929         INIT_LIST_HEAD(&u3d->gadget.ep_list);   /* ep_list */
1930         u3d->gadget.speed = USB_SPEED_UNKNOWN;  /* speed */
1931
1932         /* the "gadget" abstracts/virtualizes the controller */
1933         u3d->gadget.name = driver_name;         /* gadget name */
1934
1935         mv_u3d_eps_init(u3d);
1936
1937         if (request_irq(u3d->irq, mv_u3d_irq,
1938                 IRQF_SHARED, driver_name, u3d)) {
1939                 u3d->irq = 0;
1940                 dev_err(&dev->dev, "Request irq %d for u3d failed\n",
1941                         u3d->irq);
1942                 retval = -ENODEV;
1943                 goto err_request_irq;
1944         }
1945
1946         /* external vbus detection */
1947         if (u3d->vbus) {
1948                 u3d->clock_gating = 1;
1949                 dev_err(&dev->dev, "external vbus detection\n");
1950         }
1951
1952         if (!u3d->clock_gating)
1953                 u3d->vbus_active = 1;
1954
1955         /* enable usb3 controller vbus detection */
1956         u3d->vbus_valid_detect = 1;
1957
1958         retval = usb_add_gadget_udc(&dev->dev, &u3d->gadget);
1959         if (retval)
1960                 goto err_unregister;
1961
1962         dev_dbg(&dev->dev, "successful probe usb3 device %s clock gating.\n",
1963                 u3d->clock_gating ? "with" : "without");
1964
1965         return 0;
1966
1967 err_unregister:
1968         free_irq(u3d->irq, u3d);
1969 err_get_irq:
1970 err_request_irq:
1971         kfree(u3d->status_req);
1972 err_alloc_status_req:
1973         kfree(u3d->eps);
1974 err_alloc_eps:
1975         dma_pool_destroy(u3d->trb_pool);
1976 err_alloc_trb_pool:
1977         dma_free_coherent(&dev->dev, u3d->ep_context_size,
1978                 u3d->ep_context, u3d->ep_context_dma);
1979 err_alloc_ep_context:
1980 err_phy_init:
1981 err_u3d_enable:
1982         iounmap(u3d->cap_regs);
1983 err_map_cap_regs:
1984 err_get_cap_regs:
1985         clk_put(u3d->clk);
1986 err_get_clk:
1987         kfree(u3d);
1988 err_alloc_private:
1989 err_pdata:
1990         return retval;
1991 }
1992
1993 #ifdef CONFIG_PM_SLEEP
1994 static int mv_u3d_suspend(struct device *dev)
1995 {
1996         struct mv_u3d *u3d = dev_get_drvdata(dev);
1997
1998         /*
1999          * only cable is unplugged, usb can suspend.
2000          * So do not care about clock_gating == 1, it is handled by
2001          * vbus session.
2002          */
2003         if (!u3d->clock_gating) {
2004                 mv_u3d_controller_stop(u3d);
2005
2006                 spin_lock_irq(&u3d->lock);
2007                 /* stop all usb activities */
2008                 mv_u3d_stop_activity(u3d, u3d->driver);
2009                 spin_unlock_irq(&u3d->lock);
2010
2011                 mv_u3d_disable(u3d);
2012         }
2013
2014         return 0;
2015 }
2016
2017 static int mv_u3d_resume(struct device *dev)
2018 {
2019         struct mv_u3d *u3d = dev_get_drvdata(dev);
2020         int retval;
2021
2022         if (!u3d->clock_gating) {
2023                 retval = mv_u3d_enable(u3d);
2024                 if (retval)
2025                         return retval;
2026
2027                 if (u3d->driver && u3d->softconnect) {
2028                         mv_u3d_controller_reset(u3d);
2029                         mv_u3d_ep0_reset(u3d);
2030                         mv_u3d_controller_start(u3d);
2031                 }
2032         }
2033
2034         return 0;
2035 }
2036 #endif
2037
2038 static SIMPLE_DEV_PM_OPS(mv_u3d_pm_ops, mv_u3d_suspend, mv_u3d_resume);
2039
2040 static void mv_u3d_shutdown(struct platform_device *dev)
2041 {
2042         struct mv_u3d *u3d = platform_get_drvdata(dev);
2043         u32 tmp;
2044
2045         tmp = ioread32(&u3d->op_regs->usbcmd);
2046         tmp &= ~MV_U3D_CMD_RUN_STOP;
2047         iowrite32(tmp, &u3d->op_regs->usbcmd);
2048 }
2049
2050 static struct platform_driver mv_u3d_driver = {
2051         .probe          = mv_u3d_probe,
2052         .remove         = mv_u3d_remove,
2053         .shutdown       = mv_u3d_shutdown,
2054         .driver         = {
2055                 .name   = "mv-u3d",
2056                 .pm     = &mv_u3d_pm_ops,
2057         },
2058 };
2059
2060 module_platform_driver(mv_u3d_driver);
2061 MODULE_ALIAS("platform:mv-u3d");
2062 MODULE_DESCRIPTION(DRIVER_DESC);
2063 MODULE_AUTHOR("Yu Xu <yuxu@marvell.com>");
2064 MODULE_LICENSE("GPL");