2 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/delay.h>
13 #include <linux/errno.h>
14 #include <linux/list.h>
15 #include <linux/interrupt.h>
16 #include <linux/usb/ch9.h>
17 #include <linux/usb/gadget.h>
18 #include <linux/gpio.h>
19 #include <linux/irq.h>
21 /* GPIO port for VBUS detecting */
22 static int vbus_gpio_port = -1; /* GPIO port number (-1:Not used) */
24 #define PCH_VBUS_PERIOD 3000 /* VBUS polling period (msec) */
25 #define PCH_VBUS_INTERVAL 10 /* VBUS polling interval (msec) */
27 /* Address offset of Registers */
28 #define UDC_EP_REG_SHIFT 0x20 /* Offset to next EP */
30 #define UDC_EPCTL_ADDR 0x00 /* Endpoint control */
31 #define UDC_EPSTS_ADDR 0x04 /* Endpoint status */
32 #define UDC_BUFIN_FRAMENUM_ADDR 0x08 /* buffer size in / frame number out */
33 #define UDC_BUFOUT_MAXPKT_ADDR 0x0C /* buffer size out / maxpkt in */
34 #define UDC_SUBPTR_ADDR 0x10 /* setup buffer pointer */
35 #define UDC_DESPTR_ADDR 0x14 /* Data descriptor pointer */
36 #define UDC_CONFIRM_ADDR 0x18 /* Write/Read confirmation */
38 #define UDC_DEVCFG_ADDR 0x400 /* Device configuration */
39 #define UDC_DEVCTL_ADDR 0x404 /* Device control */
40 #define UDC_DEVSTS_ADDR 0x408 /* Device status */
41 #define UDC_DEVIRQSTS_ADDR 0x40C /* Device irq status */
42 #define UDC_DEVIRQMSK_ADDR 0x410 /* Device irq mask */
43 #define UDC_EPIRQSTS_ADDR 0x414 /* Endpoint irq status */
44 #define UDC_EPIRQMSK_ADDR 0x418 /* Endpoint irq mask */
45 #define UDC_DEVLPM_ADDR 0x41C /* LPM control / status */
46 #define UDC_CSR_BUSY_ADDR 0x4f0 /* UDC_CSR_BUSY Status register */
47 #define UDC_SRST_ADDR 0x4fc /* SOFT RESET register */
48 #define UDC_CSR_ADDR 0x500 /* USB_DEVICE endpoint register */
50 /* Endpoint control register */
52 #define UDC_EPCTL_MRXFLUSH (1 << 12)
53 #define UDC_EPCTL_RRDY (1 << 9)
54 #define UDC_EPCTL_CNAK (1 << 8)
55 #define UDC_EPCTL_SNAK (1 << 7)
56 #define UDC_EPCTL_NAK (1 << 6)
57 #define UDC_EPCTL_P (1 << 3)
58 #define UDC_EPCTL_F (1 << 1)
59 #define UDC_EPCTL_S (1 << 0)
60 #define UDC_EPCTL_ET_SHIFT 4
62 #define UDC_EPCTL_ET_MASK 0x00000030
63 /* Value for ET field */
64 #define UDC_EPCTL_ET_CONTROL 0
65 #define UDC_EPCTL_ET_ISO 1
66 #define UDC_EPCTL_ET_BULK 2
67 #define UDC_EPCTL_ET_INTERRUPT 3
69 /* Endpoint status register */
71 #define UDC_EPSTS_XFERDONE (1 << 27)
72 #define UDC_EPSTS_RSS (1 << 26)
73 #define UDC_EPSTS_RCS (1 << 25)
74 #define UDC_EPSTS_TXEMPTY (1 << 24)
75 #define UDC_EPSTS_TDC (1 << 10)
76 #define UDC_EPSTS_HE (1 << 9)
77 #define UDC_EPSTS_MRXFIFO_EMP (1 << 8)
78 #define UDC_EPSTS_BNA (1 << 7)
79 #define UDC_EPSTS_IN (1 << 6)
80 #define UDC_EPSTS_OUT_SHIFT 4
82 #define UDC_EPSTS_OUT_MASK 0x00000030
83 #define UDC_EPSTS_ALL_CLR_MASK 0x1F0006F0
84 /* Value for OUT field */
85 #define UDC_EPSTS_OUT_SETUP 2
86 #define UDC_EPSTS_OUT_DATA 1
88 /* Device configuration register */
90 #define UDC_DEVCFG_CSR_PRG (1 << 17)
91 #define UDC_DEVCFG_SP (1 << 3)
93 #define UDC_DEVCFG_SPD_HS 0x0
94 #define UDC_DEVCFG_SPD_FS 0x1
95 #define UDC_DEVCFG_SPD_LS 0x2
97 /* Device control register */
99 #define UDC_DEVCTL_THLEN_SHIFT 24
100 #define UDC_DEVCTL_BRLEN_SHIFT 16
101 #define UDC_DEVCTL_CSR_DONE (1 << 13)
102 #define UDC_DEVCTL_SD (1 << 10)
103 #define UDC_DEVCTL_MODE (1 << 9)
104 #define UDC_DEVCTL_BREN (1 << 8)
105 #define UDC_DEVCTL_THE (1 << 7)
106 #define UDC_DEVCTL_DU (1 << 4)
107 #define UDC_DEVCTL_TDE (1 << 3)
108 #define UDC_DEVCTL_RDE (1 << 2)
109 #define UDC_DEVCTL_RES (1 << 0)
111 /* Device status register */
113 #define UDC_DEVSTS_TS_SHIFT 18
114 #define UDC_DEVSTS_ENUM_SPEED_SHIFT 13
115 #define UDC_DEVSTS_ALT_SHIFT 8
116 #define UDC_DEVSTS_INTF_SHIFT 4
117 #define UDC_DEVSTS_CFG_SHIFT 0
119 #define UDC_DEVSTS_TS_MASK 0xfffc0000
120 #define UDC_DEVSTS_ENUM_SPEED_MASK 0x00006000
121 #define UDC_DEVSTS_ALT_MASK 0x00000f00
122 #define UDC_DEVSTS_INTF_MASK 0x000000f0
123 #define UDC_DEVSTS_CFG_MASK 0x0000000f
124 /* value for maximum speed for SPEED field */
125 #define UDC_DEVSTS_ENUM_SPEED_FULL 1
126 #define UDC_DEVSTS_ENUM_SPEED_HIGH 0
127 #define UDC_DEVSTS_ENUM_SPEED_LOW 2
128 #define UDC_DEVSTS_ENUM_SPEED_FULLX 3
130 /* Device irq register */
132 #define UDC_DEVINT_RWKP (1 << 7)
133 #define UDC_DEVINT_ENUM (1 << 6)
134 #define UDC_DEVINT_SOF (1 << 5)
135 #define UDC_DEVINT_US (1 << 4)
136 #define UDC_DEVINT_UR (1 << 3)
137 #define UDC_DEVINT_ES (1 << 2)
138 #define UDC_DEVINT_SI (1 << 1)
139 #define UDC_DEVINT_SC (1 << 0)
141 #define UDC_DEVINT_MSK 0x7f
143 /* Endpoint irq register */
145 #define UDC_EPINT_IN_SHIFT 0
146 #define UDC_EPINT_OUT_SHIFT 16
147 #define UDC_EPINT_IN_EP0 (1 << 0)
148 #define UDC_EPINT_OUT_EP0 (1 << 16)
150 #define UDC_EPINT_MSK_DISABLE_ALL 0xffffffff
152 /* UDC_CSR_BUSY Status register */
154 #define UDC_CSR_BUSY (1 << 0)
156 /* SOFT RESET register */
158 #define UDC_PSRST (1 << 1)
159 #define UDC_SRST (1 << 0)
161 /* USB_DEVICE endpoint register */
163 #define UDC_CSR_NE_NUM_SHIFT 0
164 #define UDC_CSR_NE_DIR_SHIFT 4
165 #define UDC_CSR_NE_TYPE_SHIFT 5
166 #define UDC_CSR_NE_CFG_SHIFT 7
167 #define UDC_CSR_NE_INTF_SHIFT 11
168 #define UDC_CSR_NE_ALT_SHIFT 15
169 #define UDC_CSR_NE_MAX_PKT_SHIFT 19
171 #define UDC_CSR_NE_NUM_MASK 0x0000000f
172 #define UDC_CSR_NE_DIR_MASK 0x00000010
173 #define UDC_CSR_NE_TYPE_MASK 0x00000060
174 #define UDC_CSR_NE_CFG_MASK 0x00000780
175 #define UDC_CSR_NE_INTF_MASK 0x00007800
176 #define UDC_CSR_NE_ALT_MASK 0x00078000
177 #define UDC_CSR_NE_MAX_PKT_MASK 0x3ff80000
179 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
180 #define PCH_UDC_EPINT(in, num)\
181 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
183 /* Index of endpoint */
184 #define UDC_EP0IN_IDX 0
185 #define UDC_EP0OUT_IDX 1
186 #define UDC_EPIN_IDX(ep) (ep * 2)
187 #define UDC_EPOUT_IDX(ep) (ep * 2 + 1)
188 #define PCH_UDC_EP0 0
189 #define PCH_UDC_EP1 1
190 #define PCH_UDC_EP2 2
191 #define PCH_UDC_EP3 3
193 /* Number of endpoint */
194 #define PCH_UDC_EP_NUM 32 /* Total number of EPs (16 IN,16 OUT) */
195 #define PCH_UDC_USED_EP_NUM 4 /* EP number of EP's really used */
197 #define PCH_UDC_BRLEN 0x0F /* Burst length */
198 #define PCH_UDC_THLEN 0x1F /* Threshold length */
199 /* Value of EP Buffer Size */
200 #define UDC_EP0IN_BUFF_SIZE 16
201 #define UDC_EPIN_BUFF_SIZE 256
202 #define UDC_EP0OUT_BUFF_SIZE 16
203 #define UDC_EPOUT_BUFF_SIZE 256
204 /* Value of EP maximum packet size */
205 #define UDC_EP0IN_MAX_PKT_SIZE 64
206 #define UDC_EP0OUT_MAX_PKT_SIZE 64
207 #define UDC_BULK_MAX_PKT_SIZE 512
210 #define DMA_DIR_RX 1 /* DMA for data receive */
211 #define DMA_DIR_TX 2 /* DMA for data transmit */
212 #define DMA_ADDR_INVALID (~(dma_addr_t)0)
213 #define UDC_DMA_MAXPACKET 65536 /* maximum packet size for DMA */
216 * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
218 * @status: Status quadlet
219 * @reserved: Reserved
220 * @dataptr: Buffer descriptor
221 * @next: Next descriptor
223 struct pch_udc_data_dma_desc {
231 * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
234 * @reserved: Reserved
235 * @data12: First setup word
236 * @data34: Second setup word
238 struct pch_udc_stp_dma_desc {
241 struct usb_ctrlrequest request;
242 } __attribute((packed));
244 /* DMA status definitions */
246 #define PCH_UDC_BUFF_STS 0xC0000000
247 #define PCH_UDC_BS_HST_RDY 0x00000000
248 #define PCH_UDC_BS_DMA_BSY 0x40000000
249 #define PCH_UDC_BS_DMA_DONE 0x80000000
250 #define PCH_UDC_BS_HST_BSY 0xC0000000
252 #define PCH_UDC_RXTX_STS 0x30000000
253 #define PCH_UDC_RTS_SUCC 0x00000000
254 #define PCH_UDC_RTS_DESERR 0x10000000
255 #define PCH_UDC_RTS_BUFERR 0x30000000
256 /* Last Descriptor Indication */
257 #define PCH_UDC_DMA_LAST 0x08000000
258 /* Number of Rx/Tx Bytes Mask */
259 #define PCH_UDC_RXTX_BYTES 0x0000ffff
262 * struct pch_udc_cfg_data - Structure to hold current configuration
263 * and interface information
264 * @cur_cfg: current configuration in use
265 * @cur_intf: current interface in use
266 * @cur_alt: current alt interface in use
268 struct pch_udc_cfg_data {
275 * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
276 * @ep: embedded ep request
277 * @td_stp_phys: for setup request
278 * @td_data_phys: for data request
279 * @td_stp: for setup request
280 * @td_data: for data request
281 * @dev: reference to device struct
282 * @offset_addr: offset address of ep register
284 * @queue: queue for requests
285 * @num: endpoint number
286 * @in: endpoint is IN
287 * @halted: endpoint halted?
288 * @epsts: Endpoint status
292 dma_addr_t td_stp_phys;
293 dma_addr_t td_data_phys;
294 struct pch_udc_stp_dma_desc *td_stp;
295 struct pch_udc_data_dma_desc *td_data;
296 struct pch_udc_dev *dev;
297 unsigned long offset_addr;
298 struct list_head queue;
306 * struct pch_vbus_gpio_data - Structure holding GPIO informaton
308 * @port: gpio port number
309 * @intr: gpio interrupt number
310 * @irq_work_fall Structure for WorkQueue
311 * @irq_work_rise Structure for WorkQueue
313 struct pch_vbus_gpio_data {
316 struct work_struct irq_work_fall;
317 struct work_struct irq_work_rise;
321 * struct pch_udc_dev - Structure holding complete information
322 * of the PCH USB device
323 * @gadget: gadget driver data
324 * @driver: reference to gadget driver bound
325 * @pdev: reference to the PCI device
326 * @ep: array of endpoints
327 * @lock: protects all state
328 * @stall: stall requested
329 * @prot_stall: protcol stall requested
330 * @registered: driver registered with system
331 * @suspended: driver in suspended state
332 * @connected: gadget driver associated
333 * @vbus_session: required vbus_session state
334 * @set_cfg_not_acked: pending acknowledgement 4 setup
335 * @waiting_zlp_ack: pending acknowledgement 4 ZLP
336 * @data_requests: DMA pool for data requests
337 * @stp_requests: DMA pool for setup requests
338 * @dma_addr: DMA pool for received
339 * @setup_data: Received setup data
340 * @base_addr: for mapped device memory
341 * @cfg_data: current cfg, intf, and alt in use
342 * @vbus_gpio: GPIO informaton for detecting VBUS
345 struct usb_gadget gadget;
346 struct usb_gadget_driver *driver;
347 struct pci_dev *pdev;
348 struct pch_udc_ep ep[PCH_UDC_EP_NUM];
349 spinlock_t lock; /* protects all state */
358 struct pci_pool *data_requests;
359 struct pci_pool *stp_requests;
361 struct usb_ctrlrequest setup_data;
362 void __iomem *base_addr;
363 struct pch_udc_cfg_data cfg_data;
364 struct pch_vbus_gpio_data vbus_gpio;
366 #define to_pch_udc(g) (container_of((g), struct pch_udc_dev, gadget))
368 #define PCH_UDC_PCI_BAR_QUARK_X1000 0
369 #define PCH_UDC_PCI_BAR 1
371 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC 0x0939
372 #define PCI_DEVICE_ID_INTEL_EG20T_UDC 0x8808
374 #define PCI_VENDOR_ID_ROHM 0x10DB
375 #define PCI_DEVICE_ID_ML7213_IOH_UDC 0x801D
376 #define PCI_DEVICE_ID_ML7831_IOH_UDC 0x8808
378 static const char ep0_string[] = "ep0in";
379 static DEFINE_SPINLOCK(udc_stall_spinlock); /* stall spin lock */
380 static bool speed_fs;
381 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
382 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
385 * struct pch_udc_request - Structure holding a PCH USB device request packet
386 * @req: embedded ep request
387 * @td_data_phys: phys. address
388 * @td_data: first dma desc. of chain
389 * @td_data_last: last dma desc. of chain
390 * @queue: associated queue
391 * @dma_going: DMA in progress for request
392 * @dma_mapped: DMA memory mapped for request
393 * @dma_done: DMA completed for request
394 * @chain_len: chain length
395 * @buf: Buffer memory for align adjustment
396 * @dma: DMA memory for align adjustment
398 struct pch_udc_request {
399 struct usb_request req;
400 dma_addr_t td_data_phys;
401 struct pch_udc_data_dma_desc *td_data;
402 struct pch_udc_data_dma_desc *td_data_last;
403 struct list_head queue;
404 unsigned dma_going:1,
412 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
414 return ioread32(dev->base_addr + reg);
417 static inline void pch_udc_writel(struct pch_udc_dev *dev,
418 unsigned long val, unsigned long reg)
420 iowrite32(val, dev->base_addr + reg);
423 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
425 unsigned long bitmask)
427 pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
430 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
432 unsigned long bitmask)
434 pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
437 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
439 return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
442 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
443 unsigned long val, unsigned long reg)
445 iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
448 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
450 unsigned long bitmask)
452 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
455 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
457 unsigned long bitmask)
459 pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
463 * pch_udc_csr_busy() - Wait till idle.
464 * @dev: Reference to pch_udc_dev structure
466 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
468 unsigned int count = 200;
471 while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
475 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
479 * pch_udc_write_csr() - Write the command and status registers.
480 * @dev: Reference to pch_udc_dev structure
481 * @val: value to be written to CSR register
482 * @addr: address of CSR register
484 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
487 unsigned long reg = PCH_UDC_CSR(ep);
489 pch_udc_csr_busy(dev); /* Wait till idle */
490 pch_udc_writel(dev, val, reg);
491 pch_udc_csr_busy(dev); /* Wait till idle */
495 * pch_udc_read_csr() - Read the command and status registers.
496 * @dev: Reference to pch_udc_dev structure
497 * @addr: address of CSR register
499 * Return codes: content of CSR register
501 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
503 unsigned long reg = PCH_UDC_CSR(ep);
505 pch_udc_csr_busy(dev); /* Wait till idle */
506 pch_udc_readl(dev, reg); /* Dummy read */
507 pch_udc_csr_busy(dev); /* Wait till idle */
508 return pch_udc_readl(dev, reg);
512 * pch_udc_rmt_wakeup() - Initiate for remote wakeup
513 * @dev: Reference to pch_udc_dev structure
515 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
517 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
519 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
523 * pch_udc_get_frame() - Get the current frame from device status register
524 * @dev: Reference to pch_udc_dev structure
525 * Retern current frame
527 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
529 u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
530 return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
534 * pch_udc_clear_selfpowered() - Clear the self power control
535 * @dev: Reference to pch_udc_regs structure
537 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
539 pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
543 * pch_udc_set_selfpowered() - Set the self power control
544 * @dev: Reference to pch_udc_regs structure
546 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
548 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
552 * pch_udc_set_disconnect() - Set the disconnect status.
553 * @dev: Reference to pch_udc_regs structure
555 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
557 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
561 * pch_udc_clear_disconnect() - Clear the disconnect status.
562 * @dev: Reference to pch_udc_regs structure
564 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
566 /* Clear the disconnect */
567 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
568 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
570 /* Resume USB signalling */
571 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
575 * pch_udc_reconnect() - This API initializes usb device controller,
576 * and clear the disconnect status.
577 * @dev: Reference to pch_udc_regs structure
579 static void pch_udc_init(struct pch_udc_dev *dev);
580 static void pch_udc_reconnect(struct pch_udc_dev *dev)
584 /* enable device interrupts */
585 /* pch_udc_enable_interrupts() */
586 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
587 UDC_DEVINT_UR | UDC_DEVINT_ENUM);
589 /* Clear the disconnect */
590 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
591 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
593 /* Resume USB signalling */
594 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
598 * pch_udc_vbus_session() - set or clearr the disconnect status.
599 * @dev: Reference to pch_udc_regs structure
600 * @is_active: Parameter specifying the action
601 * 0: indicating VBUS power is ending
602 * !0: indicating VBUS power is starting
604 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
607 unsigned long iflags;
609 spin_lock_irqsave(&dev->lock, iflags);
611 pch_udc_reconnect(dev);
612 dev->vbus_session = 1;
614 if (dev->driver && dev->driver->disconnect) {
615 spin_unlock_irqrestore(&dev->lock, iflags);
616 dev->driver->disconnect(&dev->gadget);
617 spin_lock_irqsave(&dev->lock, iflags);
619 pch_udc_set_disconnect(dev);
620 dev->vbus_session = 0;
622 spin_unlock_irqrestore(&dev->lock, iflags);
626 * pch_udc_ep_set_stall() - Set the stall of endpoint
627 * @ep: Reference to structure of type pch_udc_ep_regs
629 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
632 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
633 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
635 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
640 * pch_udc_ep_clear_stall() - Clear the stall of endpoint
641 * @ep: Reference to structure of type pch_udc_ep_regs
643 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
645 /* Clear the stall */
646 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
647 /* Clear NAK by writing CNAK */
648 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
652 * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
653 * @ep: Reference to structure of type pch_udc_ep_regs
654 * @type: Type of endpoint
656 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
659 pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
660 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
664 * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
665 * @ep: Reference to structure of type pch_udc_ep_regs
666 * @buf_size: The buffer word size
668 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
669 u32 buf_size, u32 ep_in)
673 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
674 data = (data & 0xffff0000) | (buf_size & 0xffff);
675 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
677 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
678 data = (buf_size << 16) | (data & 0xffff);
679 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
684 * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
685 * @ep: Reference to structure of type pch_udc_ep_regs
686 * @pkt_size: The packet byte size
688 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
690 u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
691 data = (data & 0xffff0000) | (pkt_size & 0xffff);
692 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
696 * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
697 * @ep: Reference to structure of type pch_udc_ep_regs
698 * @addr: Address of the register
700 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
702 pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
706 * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
707 * @ep: Reference to structure of type pch_udc_ep_regs
708 * @addr: Address of the register
710 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
712 pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
716 * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
717 * @ep: Reference to structure of type pch_udc_ep_regs
719 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
721 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
725 * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
726 * @ep: Reference to structure of type pch_udc_ep_regs
728 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
730 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
734 * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
735 * @ep: Reference to structure of type pch_udc_ep_regs
737 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
739 pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
743 * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
744 * register depending on the direction specified
745 * @dev: Reference to structure of type pch_udc_regs
746 * @dir: whether Tx or Rx
747 * DMA_DIR_RX: Receive
748 * DMA_DIR_TX: Transmit
750 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
752 if (dir == DMA_DIR_RX)
753 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
754 else if (dir == DMA_DIR_TX)
755 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
759 * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
760 * register depending on the direction specified
761 * @dev: Reference to structure of type pch_udc_regs
762 * @dir: Whether Tx or Rx
763 * DMA_DIR_RX: Receive
764 * DMA_DIR_TX: Transmit
766 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
768 if (dir == DMA_DIR_RX)
769 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
770 else if (dir == DMA_DIR_TX)
771 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
775 * pch_udc_set_csr_done() - Set the device control register
776 * CSR done field (bit 13)
777 * @dev: reference to structure of type pch_udc_regs
779 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
781 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
785 * pch_udc_disable_interrupts() - Disables the specified interrupts
786 * @dev: Reference to structure of type pch_udc_regs
787 * @mask: Mask to disable interrupts
789 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
792 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
796 * pch_udc_enable_interrupts() - Enable the specified interrupts
797 * @dev: Reference to structure of type pch_udc_regs
798 * @mask: Mask to enable interrupts
800 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
803 pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
807 * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
808 * @dev: Reference to structure of type pch_udc_regs
809 * @mask: Mask to disable interrupts
811 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
814 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
818 * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
819 * @dev: Reference to structure of type pch_udc_regs
820 * @mask: Mask to enable interrupts
822 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
825 pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
829 * pch_udc_read_device_interrupts() - Read the device interrupts
830 * @dev: Reference to structure of type pch_udc_regs
831 * Retern The device interrupts
833 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
835 return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
839 * pch_udc_write_device_interrupts() - Write device interrupts
840 * @dev: Reference to structure of type pch_udc_regs
841 * @val: The value to be written to interrupt register
843 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
846 pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
850 * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
851 * @dev: Reference to structure of type pch_udc_regs
852 * Retern The endpoint interrupt
854 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
856 return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
860 * pch_udc_write_ep_interrupts() - Clear endpoint interupts
861 * @dev: Reference to structure of type pch_udc_regs
862 * @val: The value to be written to interrupt register
864 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
867 pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
871 * pch_udc_read_device_status() - Read the device status
872 * @dev: Reference to structure of type pch_udc_regs
873 * Retern The device status
875 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
877 return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
881 * pch_udc_read_ep_control() - Read the endpoint control
882 * @ep: Reference to structure of type pch_udc_ep_regs
883 * Retern The endpoint control register value
885 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
887 return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
891 * pch_udc_clear_ep_control() - Clear the endpoint control register
892 * @ep: Reference to structure of type pch_udc_ep_regs
893 * Retern The endpoint control register value
895 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
897 return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
901 * pch_udc_read_ep_status() - Read the endpoint status
902 * @ep: Reference to structure of type pch_udc_ep_regs
903 * Retern The endpoint status
905 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
907 return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
911 * pch_udc_clear_ep_status() - Clear the endpoint status
912 * @ep: Reference to structure of type pch_udc_ep_regs
913 * @stat: Endpoint status
915 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
918 return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
922 * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
923 * of the endpoint control register
924 * @ep: Reference to structure of type pch_udc_ep_regs
926 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
928 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
932 * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
933 * of the endpoint control register
934 * @ep: reference to structure of type pch_udc_ep_regs
936 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
938 unsigned int loopcnt = 0;
939 struct pch_udc_dev *dev = ep->dev;
941 if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
945 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
949 dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
953 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
954 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
958 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
959 __func__, ep->num, (ep->in ? "in" : "out"));
963 * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
964 * @ep: reference to structure of type pch_udc_ep_regs
965 * @dir: direction of endpoint
969 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
971 if (dir) { /* IN ep */
972 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
978 * pch_udc_ep_enable() - This api enables endpoint
979 * @regs: Reference to structure pch_udc_ep_regs
980 * @desc: endpoint descriptor
982 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
983 struct pch_udc_cfg_data *cfg,
984 const struct usb_endpoint_descriptor *desc)
989 pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
991 buff_size = UDC_EPIN_BUFF_SIZE;
993 buff_size = UDC_EPOUT_BUFF_SIZE;
994 pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
995 pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
996 pch_udc_ep_set_nak(ep);
997 pch_udc_ep_fifo_flush(ep, ep->in);
998 /* Configure the endpoint */
999 val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1000 ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
1001 UDC_CSR_NE_TYPE_SHIFT) |
1002 (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
1003 (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1004 (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
1005 usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
1008 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1010 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1014 * pch_udc_ep_disable() - This api disables endpoint
1015 * @regs: Reference to structure pch_udc_ep_regs
1017 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1020 /* flush the fifo */
1021 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1023 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1024 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1027 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1029 /* reset desc pointer */
1030 pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1034 * pch_udc_wait_ep_stall() - Wait EP stall.
1035 * @dev: Reference to pch_udc_dev structure
1037 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1039 unsigned int count = 10000;
1041 /* Wait till idle */
1042 while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1045 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1049 * pch_udc_init() - This API initializes usb device controller
1050 * @dev: Rreference to pch_udc_regs structure
1052 static void pch_udc_init(struct pch_udc_dev *dev)
1055 pr_err("%s: Invalid address\n", __func__);
1058 /* Soft Reset and Reset PHY */
1059 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1060 pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1062 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1063 pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1065 /* mask and clear all device interrupts */
1066 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1067 pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1069 /* mask and clear all ep interrupts */
1070 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1071 pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1073 /* enable dynamic CSR programmingi, self powered and device speed */
1075 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1076 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1077 else /* defaul high speed */
1078 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1079 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1080 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1081 (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1082 (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1083 UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1088 * pch_udc_exit() - This API exit usb device controller
1089 * @dev: Reference to pch_udc_regs structure
1091 static void pch_udc_exit(struct pch_udc_dev *dev)
1093 /* mask all device interrupts */
1094 pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1095 /* mask all ep interrupts */
1096 pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1097 /* put device in disconnected state */
1098 pch_udc_set_disconnect(dev);
1102 * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1103 * @gadget: Reference to the gadget driver
1107 * -EINVAL: If the gadget passed is NULL
1109 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1111 struct pch_udc_dev *dev;
1115 dev = container_of(gadget, struct pch_udc_dev, gadget);
1116 return pch_udc_get_frame(dev);
1120 * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1121 * @gadget: Reference to the gadget driver
1125 * -EINVAL: If the gadget passed is NULL
1127 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1129 struct pch_udc_dev *dev;
1130 unsigned long flags;
1134 dev = container_of(gadget, struct pch_udc_dev, gadget);
1135 spin_lock_irqsave(&dev->lock, flags);
1136 pch_udc_rmt_wakeup(dev);
1137 spin_unlock_irqrestore(&dev->lock, flags);
1142 * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1143 * is self powered or not
1144 * @gadget: Reference to the gadget driver
1145 * @value: Specifies self powered or not
1149 * -EINVAL: If the gadget passed is NULL
1151 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1153 struct pch_udc_dev *dev;
1157 gadget->is_selfpowered = (value != 0);
1158 dev = container_of(gadget, struct pch_udc_dev, gadget);
1160 pch_udc_set_selfpowered(dev);
1162 pch_udc_clear_selfpowered(dev);
1167 * pch_udc_pcd_pullup() - This API is invoked to make the device
1168 * visible/invisible to the host
1169 * @gadget: Reference to the gadget driver
1170 * @is_on: Specifies whether the pull up is made active or inactive
1174 * -EINVAL: If the gadget passed is NULL
1176 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1178 struct pch_udc_dev *dev;
1179 unsigned long iflags;
1184 dev = container_of(gadget, struct pch_udc_dev, gadget);
1186 spin_lock_irqsave(&dev->lock, iflags);
1188 pch_udc_reconnect(dev);
1190 if (dev->driver && dev->driver->disconnect) {
1191 spin_unlock_irqrestore(&dev->lock, iflags);
1192 dev->driver->disconnect(&dev->gadget);
1193 spin_lock_irqsave(&dev->lock, iflags);
1195 pch_udc_set_disconnect(dev);
1197 spin_unlock_irqrestore(&dev->lock, iflags);
1203 * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1204 * transceiver (or GPIO) that
1205 * detects a VBUS power session starting/ending
1206 * @gadget: Reference to the gadget driver
1207 * @is_active: specifies whether the session is starting or ending
1211 * -EINVAL: If the gadget passed is NULL
1213 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1215 struct pch_udc_dev *dev;
1219 dev = container_of(gadget, struct pch_udc_dev, gadget);
1220 pch_udc_vbus_session(dev, is_active);
1225 * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1226 * SET_CONFIGURATION calls to
1227 * specify how much power the device can consume
1228 * @gadget: Reference to the gadget driver
1229 * @mA: specifies the current limit in 2mA unit
1232 * -EINVAL: If the gadget passed is NULL
1235 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1240 static int pch_udc_start(struct usb_gadget *g,
1241 struct usb_gadget_driver *driver);
1242 static int pch_udc_stop(struct usb_gadget *g);
1244 static const struct usb_gadget_ops pch_udc_ops = {
1245 .get_frame = pch_udc_pcd_get_frame,
1246 .wakeup = pch_udc_pcd_wakeup,
1247 .set_selfpowered = pch_udc_pcd_selfpowered,
1248 .pullup = pch_udc_pcd_pullup,
1249 .vbus_session = pch_udc_pcd_vbus_session,
1250 .vbus_draw = pch_udc_pcd_vbus_draw,
1251 .udc_start = pch_udc_start,
1252 .udc_stop = pch_udc_stop,
1256 * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1257 * @dev: Reference to the driver structure
1262 * -1: It is not enable to detect VBUS using GPIO
1264 static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1268 if (dev->vbus_gpio.port)
1269 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1277 * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1278 * If VBUS is Low, disconnect is processed
1279 * @irq_work: Structure for WorkQueue
1282 static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1284 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1285 struct pch_vbus_gpio_data, irq_work_fall);
1286 struct pch_udc_dev *dev =
1287 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1288 int vbus_saved = -1;
1292 if (!dev->vbus_gpio.port)
1295 for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1297 vbus = pch_vbus_gpio_get_value(dev);
1299 if ((vbus_saved == vbus) && (vbus == 0)) {
1300 dev_dbg(&dev->pdev->dev, "VBUS fell");
1302 && dev->driver->disconnect) {
1303 dev->driver->disconnect(
1306 if (dev->vbus_gpio.intr)
1309 pch_udc_reconnect(dev);
1313 mdelay(PCH_VBUS_INTERVAL);
1318 * pch_vbus_gpio_work_rise() - This API checks VBUS is High.
1319 * If VBUS is High, connect is processed
1320 * @irq_work: Structure for WorkQueue
1323 static void pch_vbus_gpio_work_rise(struct work_struct *irq_work)
1325 struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1326 struct pch_vbus_gpio_data, irq_work_rise);
1327 struct pch_udc_dev *dev =
1328 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1331 if (!dev->vbus_gpio.port)
1334 mdelay(PCH_VBUS_INTERVAL);
1335 vbus = pch_vbus_gpio_get_value(dev);
1338 dev_dbg(&dev->pdev->dev, "VBUS rose");
1339 pch_udc_reconnect(dev);
1345 * pch_vbus_gpio_irq() - IRQ handler for GPIO intrerrupt for changing VBUS
1346 * @irq: Interrupt request number
1347 * @dev: Reference to the device structure
1351 * -EINVAL: GPIO port is invalid or can't be initialized.
1353 static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
1355 struct pch_udc_dev *dev = (struct pch_udc_dev *)data;
1357 if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr)
1360 if (pch_vbus_gpio_get_value(dev))
1361 schedule_work(&dev->vbus_gpio.irq_work_rise);
1363 schedule_work(&dev->vbus_gpio.irq_work_fall);
1369 * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1370 * @dev: Reference to the driver structure
1371 * @vbus_gpio Number of GPIO port to detect gpio
1375 * -EINVAL: GPIO port is invalid or can't be initialized.
1377 static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1382 dev->vbus_gpio.port = 0;
1383 dev->vbus_gpio.intr = 0;
1385 if (vbus_gpio_port <= -1)
1388 err = gpio_is_valid(vbus_gpio_port);
1390 pr_err("%s: gpio port %d is invalid\n",
1391 __func__, vbus_gpio_port);
1395 err = gpio_request(vbus_gpio_port, "pch_vbus");
1397 pr_err("%s: can't request gpio port %d, err: %d\n",
1398 __func__, vbus_gpio_port, err);
1402 dev->vbus_gpio.port = vbus_gpio_port;
1403 gpio_direction_input(vbus_gpio_port);
1404 INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1406 irq_num = gpio_to_irq(vbus_gpio_port);
1408 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH);
1409 err = request_irq(irq_num, pch_vbus_gpio_irq, 0,
1410 "vbus_detect", dev);
1412 dev->vbus_gpio.intr = irq_num;
1413 INIT_WORK(&dev->vbus_gpio.irq_work_rise,
1414 pch_vbus_gpio_work_rise);
1416 pr_err("%s: can't request irq %d, err: %d\n",
1417 __func__, irq_num, err);
1425 * pch_vbus_gpio_free() - This API frees resources of GPIO port
1426 * @dev: Reference to the driver structure
1428 static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1430 if (dev->vbus_gpio.intr)
1431 free_irq(dev->vbus_gpio.intr, dev);
1433 if (dev->vbus_gpio.port)
1434 gpio_free(dev->vbus_gpio.port);
1438 * complete_req() - This API is invoked from the driver when processing
1439 * of a request is complete
1440 * @ep: Reference to the endpoint structure
1441 * @req: Reference to the request structure
1442 * @status: Indicates the success/failure of completion
1444 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1446 __releases(&dev->lock)
1447 __acquires(&dev->lock)
1449 struct pch_udc_dev *dev;
1450 unsigned halted = ep->halted;
1452 list_del_init(&req->queue);
1454 /* set new status if pending */
1455 if (req->req.status == -EINPROGRESS)
1456 req->req.status = status;
1458 status = req->req.status;
1461 if (req->dma_mapped) {
1462 if (req->dma == DMA_ADDR_INVALID) {
1464 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1468 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1471 req->req.dma = DMA_ADDR_INVALID;
1474 dma_unmap_single(&dev->pdev->dev, req->dma,
1478 dma_unmap_single(&dev->pdev->dev, req->dma,
1481 memcpy(req->req.buf, req->buf, req->req.length);
1484 req->dma = DMA_ADDR_INVALID;
1486 req->dma_mapped = 0;
1489 spin_unlock(&dev->lock);
1491 pch_udc_ep_clear_rrdy(ep);
1492 usb_gadget_giveback_request(&ep->ep, &req->req);
1493 spin_lock(&dev->lock);
1494 ep->halted = halted;
1498 * empty_req_queue() - This API empties the request queue of an endpoint
1499 * @ep: Reference to the endpoint structure
1501 static void empty_req_queue(struct pch_udc_ep *ep)
1503 struct pch_udc_request *req;
1506 while (!list_empty(&ep->queue)) {
1507 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1508 complete_req(ep, req, -ESHUTDOWN); /* Remove from list */
1513 * pch_udc_free_dma_chain() - This function frees the DMA chain created
1515 * @dev Reference to the driver structure
1516 * @req Reference to the request to be freed
1521 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1522 struct pch_udc_request *req)
1524 struct pch_udc_data_dma_desc *td = req->td_data;
1525 unsigned i = req->chain_len;
1528 dma_addr_t addr = (dma_addr_t)td->next;
1530 for (; i > 1; --i) {
1531 /* do not free first desc., will be done by free for request */
1532 td = phys_to_virt(addr);
1533 addr2 = (dma_addr_t)td->next;
1534 pci_pool_free(dev->data_requests, td, addr);
1541 * pch_udc_create_dma_chain() - This function creates or reinitializes
1543 * @ep: Reference to the endpoint structure
1544 * @req: Reference to the request
1545 * @buf_len: The buffer length
1546 * @gfp_flags: Flags to be used while mapping the data buffer
1550 * -ENOMEM: pci_pool_alloc invocation fails
1552 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1553 struct pch_udc_request *req,
1554 unsigned long buf_len,
1557 struct pch_udc_data_dma_desc *td = req->td_data, *last;
1558 unsigned long bytes = req->req.length, i = 0;
1559 dma_addr_t dma_addr;
1562 if (req->chain_len > 1)
1563 pch_udc_free_dma_chain(ep->dev, req);
1565 if (req->dma == DMA_ADDR_INVALID)
1566 td->dataptr = req->req.dma;
1568 td->dataptr = req->dma;
1570 td->status = PCH_UDC_BS_HST_BSY;
1571 for (; ; bytes -= buf_len, ++len) {
1572 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1573 if (bytes <= buf_len)
1576 td = pci_pool_alloc(ep->dev->data_requests, gfp_flags,
1581 td->dataptr = req->td_data->dataptr + i;
1582 last->next = dma_addr;
1585 req->td_data_last = td;
1586 td->status |= PCH_UDC_DMA_LAST;
1587 td->next = req->td_data_phys;
1588 req->chain_len = len;
1593 req->chain_len = len;
1594 pch_udc_free_dma_chain(ep->dev, req);
1601 * prepare_dma() - This function creates and initializes the DMA chain
1603 * @ep: Reference to the endpoint structure
1604 * @req: Reference to the request
1605 * @gfp: Flag to be used while mapping the data buffer
1609 * Other 0: linux error number on failure
1611 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1616 /* Allocate and create a DMA chain */
1617 retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1619 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1623 req->td_data->status = (req->td_data->status &
1624 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1629 * process_zlp() - This function process zero length packets
1630 * from the gadget driver
1631 * @ep: Reference to the endpoint structure
1632 * @req: Reference to the request
1634 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1636 struct pch_udc_dev *dev = ep->dev;
1638 /* IN zlp's are handled by hardware */
1639 complete_req(ep, req, 0);
1641 /* if set_config or set_intf is waiting for ack by zlp
1644 if (dev->set_cfg_not_acked) {
1645 pch_udc_set_csr_done(dev);
1646 dev->set_cfg_not_acked = 0;
1648 /* setup command is ACK'ed now by zlp */
1649 if (!dev->stall && dev->waiting_zlp_ack) {
1650 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1651 dev->waiting_zlp_ack = 0;
1656 * pch_udc_start_rxrequest() - This function starts the receive requirement.
1657 * @ep: Reference to the endpoint structure
1658 * @req: Reference to the request structure
1660 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1661 struct pch_udc_request *req)
1663 struct pch_udc_data_dma_desc *td_data;
1665 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1666 td_data = req->td_data;
1667 /* Set the status bits for all descriptors */
1669 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1671 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
1673 td_data = phys_to_virt(td_data->next);
1675 /* Write the descriptor pointer */
1676 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1678 pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1679 pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1680 pch_udc_ep_clear_nak(ep);
1681 pch_udc_ep_set_rrdy(ep);
1685 * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1686 * from gadget driver
1687 * @usbep: Reference to the USB endpoint structure
1688 * @desc: Reference to the USB endpoint descriptor structure
1695 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1696 const struct usb_endpoint_descriptor *desc)
1698 struct pch_udc_ep *ep;
1699 struct pch_udc_dev *dev;
1700 unsigned long iflags;
1702 if (!usbep || (usbep->name == ep0_string) || !desc ||
1703 (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1706 ep = container_of(usbep, struct pch_udc_ep, ep);
1708 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1710 spin_lock_irqsave(&dev->lock, iflags);
1713 pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1714 ep->ep.maxpacket = usb_endpoint_maxp(desc);
1715 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1716 spin_unlock_irqrestore(&dev->lock, iflags);
1721 * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1722 * from gadget driver
1723 * @usbep Reference to the USB endpoint structure
1729 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1731 struct pch_udc_ep *ep;
1732 unsigned long iflags;
1737 ep = container_of(usbep, struct pch_udc_ep, ep);
1738 if ((usbep->name == ep0_string) || !ep->ep.desc)
1741 spin_lock_irqsave(&ep->dev->lock, iflags);
1742 empty_req_queue(ep);
1744 pch_udc_ep_disable(ep);
1745 pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1747 INIT_LIST_HEAD(&ep->queue);
1748 spin_unlock_irqrestore(&ep->dev->lock, iflags);
1753 * pch_udc_alloc_request() - This function allocates request structure.
1754 * It is called by gadget driver
1755 * @usbep: Reference to the USB endpoint structure
1756 * @gfp: Flag to be used while allocating memory
1760 * Allocated address: Success
1762 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1765 struct pch_udc_request *req;
1766 struct pch_udc_ep *ep;
1767 struct pch_udc_data_dma_desc *dma_desc;
1771 ep = container_of(usbep, struct pch_udc_ep, ep);
1772 req = kzalloc(sizeof *req, gfp);
1775 req->req.dma = DMA_ADDR_INVALID;
1776 req->dma = DMA_ADDR_INVALID;
1777 INIT_LIST_HEAD(&req->queue);
1778 if (!ep->dev->dma_addr)
1780 /* ep0 in requests are allocated from data pool here */
1781 dma_desc = pci_pool_alloc(ep->dev->data_requests, gfp,
1782 &req->td_data_phys);
1783 if (NULL == dma_desc) {
1787 /* prevent from using desc. - set HOST BUSY */
1788 dma_desc->status |= PCH_UDC_BS_HST_BSY;
1789 dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID);
1790 req->td_data = dma_desc;
1791 req->td_data_last = dma_desc;
1797 * pch_udc_free_request() - This function frees request structure.
1798 * It is called by gadget driver
1799 * @usbep: Reference to the USB endpoint structure
1800 * @usbreq: Reference to the USB request
1802 static void pch_udc_free_request(struct usb_ep *usbep,
1803 struct usb_request *usbreq)
1805 struct pch_udc_ep *ep;
1806 struct pch_udc_request *req;
1807 struct pch_udc_dev *dev;
1809 if (!usbep || !usbreq)
1811 ep = container_of(usbep, struct pch_udc_ep, ep);
1812 req = container_of(usbreq, struct pch_udc_request, req);
1814 if (!list_empty(&req->queue))
1815 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1816 __func__, usbep->name, req);
1817 if (req->td_data != NULL) {
1818 if (req->chain_len > 1)
1819 pch_udc_free_dma_chain(ep->dev, req);
1820 pci_pool_free(ep->dev->data_requests, req->td_data,
1827 * pch_udc_pcd_queue() - This function queues a request packet. It is called
1829 * @usbep: Reference to the USB endpoint structure
1830 * @usbreq: Reference to the USB request
1831 * @gfp: Flag to be used while mapping the data buffer
1835 * linux error number: Failure
1837 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1841 struct pch_udc_ep *ep;
1842 struct pch_udc_dev *dev;
1843 struct pch_udc_request *req;
1844 unsigned long iflags;
1846 if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1848 ep = container_of(usbep, struct pch_udc_ep, ep);
1850 if (!ep->ep.desc && ep->num)
1852 req = container_of(usbreq, struct pch_udc_request, req);
1853 if (!list_empty(&req->queue))
1855 if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1857 spin_lock_irqsave(&dev->lock, iflags);
1858 /* map the buffer for dma */
1859 if (usbreq->length &&
1860 ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1861 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1863 usbreq->dma = dma_map_single(&dev->pdev->dev,
1868 usbreq->dma = dma_map_single(&dev->pdev->dev,
1873 req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1879 memcpy(req->buf, usbreq->buf, usbreq->length);
1880 req->dma = dma_map_single(&dev->pdev->dev,
1885 req->dma = dma_map_single(&dev->pdev->dev,
1890 req->dma_mapped = 1;
1892 if (usbreq->length > 0) {
1893 retval = prepare_dma(ep, req, GFP_ATOMIC);
1898 usbreq->status = -EINPROGRESS;
1900 if (list_empty(&ep->queue) && !ep->halted) {
1901 /* no pending transfer, so start this req */
1902 if (!usbreq->length) {
1903 process_zlp(ep, req);
1908 pch_udc_start_rxrequest(ep, req);
1911 * For IN trfr the descriptors will be programmed and
1912 * P bit will be set when
1913 * we get an IN token
1915 pch_udc_wait_ep_stall(ep);
1916 pch_udc_ep_clear_nak(ep);
1917 pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1920 /* Now add this request to the ep's pending requests */
1922 list_add_tail(&req->queue, &ep->queue);
1925 spin_unlock_irqrestore(&dev->lock, iflags);
1930 * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1931 * It is called by gadget driver
1932 * @usbep: Reference to the USB endpoint structure
1933 * @usbreq: Reference to the USB request
1937 * linux error number: Failure
1939 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1940 struct usb_request *usbreq)
1942 struct pch_udc_ep *ep;
1943 struct pch_udc_request *req;
1944 unsigned long flags;
1947 ep = container_of(usbep, struct pch_udc_ep, ep);
1948 if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1950 req = container_of(usbreq, struct pch_udc_request, req);
1951 spin_lock_irqsave(&ep->dev->lock, flags);
1952 /* make sure it's still queued on this endpoint */
1953 list_for_each_entry(req, &ep->queue, queue) {
1954 if (&req->req == usbreq) {
1955 pch_udc_ep_set_nak(ep);
1956 if (!list_empty(&req->queue))
1957 complete_req(ep, req, -ECONNRESET);
1962 spin_unlock_irqrestore(&ep->dev->lock, flags);
1967 * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1969 * @usbep: Reference to the USB endpoint structure
1970 * @halt: Specifies whether to set or clear the feature
1974 * linux error number: Failure
1976 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1978 struct pch_udc_ep *ep;
1979 unsigned long iflags;
1984 ep = container_of(usbep, struct pch_udc_ep, ep);
1985 if (!ep->ep.desc && !ep->num)
1987 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1989 spin_lock_irqsave(&udc_stall_spinlock, iflags);
1990 if (list_empty(&ep->queue)) {
1992 if (ep->num == PCH_UDC_EP0)
1994 pch_udc_ep_set_stall(ep);
1995 pch_udc_enable_ep_interrupts(
1996 ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1998 pch_udc_ep_clear_stall(ep);
2004 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2009 * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
2011 * @usbep: Reference to the USB endpoint structure
2012 * @halt: Specifies whether to set or clear the feature
2016 * linux error number: Failure
2018 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
2020 struct pch_udc_ep *ep;
2021 unsigned long iflags;
2026 ep = container_of(usbep, struct pch_udc_ep, ep);
2027 if (!ep->ep.desc && !ep->num)
2029 if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2031 spin_lock_irqsave(&udc_stall_spinlock, iflags);
2032 if (!list_empty(&ep->queue)) {
2035 if (ep->num == PCH_UDC_EP0)
2037 pch_udc_ep_set_stall(ep);
2038 pch_udc_enable_ep_interrupts(ep->dev,
2039 PCH_UDC_EPINT(ep->in, ep->num));
2040 ep->dev->prot_stall = 1;
2043 spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2048 * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
2049 * @usbep: Reference to the USB endpoint structure
2051 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
2053 struct pch_udc_ep *ep;
2058 ep = container_of(usbep, struct pch_udc_ep, ep);
2059 if (ep->ep.desc || !ep->num)
2060 pch_udc_ep_fifo_flush(ep, ep->in);
2063 static const struct usb_ep_ops pch_udc_ep_ops = {
2064 .enable = pch_udc_pcd_ep_enable,
2065 .disable = pch_udc_pcd_ep_disable,
2066 .alloc_request = pch_udc_alloc_request,
2067 .free_request = pch_udc_free_request,
2068 .queue = pch_udc_pcd_queue,
2069 .dequeue = pch_udc_pcd_dequeue,
2070 .set_halt = pch_udc_pcd_set_halt,
2071 .set_wedge = pch_udc_pcd_set_wedge,
2072 .fifo_status = NULL,
2073 .fifo_flush = pch_udc_pcd_fifo_flush,
2077 * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2078 * @td_stp: Reference to the SETP buffer structure
2080 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2082 static u32 pky_marker;
2086 td_stp->reserved = ++pky_marker;
2087 memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2088 td_stp->status = PCH_UDC_BS_HST_RDY;
2092 * pch_udc_start_next_txrequest() - This function starts
2093 * the next transmission requirement
2094 * @ep: Reference to the endpoint structure
2096 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2098 struct pch_udc_request *req;
2099 struct pch_udc_data_dma_desc *td_data;
2101 if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2104 if (list_empty(&ep->queue))
2108 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2113 pch_udc_wait_ep_stall(ep);
2115 pch_udc_ep_set_ddptr(ep, 0);
2116 td_data = req->td_data;
2118 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2120 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2122 td_data = phys_to_virt(td_data->next);
2124 pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2125 pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2126 pch_udc_ep_set_pd(ep);
2127 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2128 pch_udc_ep_clear_nak(ep);
2132 * pch_udc_complete_transfer() - This function completes a transfer
2133 * @ep: Reference to the endpoint structure
2135 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2137 struct pch_udc_request *req;
2138 struct pch_udc_dev *dev = ep->dev;
2140 if (list_empty(&ep->queue))
2142 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2143 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2144 PCH_UDC_BS_DMA_DONE)
2146 if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2148 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2149 "epstatus=0x%08x\n",
2150 (req->td_data_last->status & PCH_UDC_RXTX_STS),
2155 req->req.actual = req->req.length;
2156 req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2157 req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2158 complete_req(ep, req, 0);
2160 if (!list_empty(&ep->queue)) {
2161 pch_udc_wait_ep_stall(ep);
2162 pch_udc_ep_clear_nak(ep);
2163 pch_udc_enable_ep_interrupts(ep->dev,
2164 PCH_UDC_EPINT(ep->in, ep->num));
2166 pch_udc_disable_ep_interrupts(ep->dev,
2167 PCH_UDC_EPINT(ep->in, ep->num));
2172 * pch_udc_complete_receiver() - This function completes a receiver
2173 * @ep: Reference to the endpoint structure
2175 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2177 struct pch_udc_request *req;
2178 struct pch_udc_dev *dev = ep->dev;
2180 struct pch_udc_data_dma_desc *td;
2183 if (list_empty(&ep->queue))
2186 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2187 pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2188 pch_udc_ep_set_ddptr(ep, 0);
2189 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2190 PCH_UDC_BS_DMA_DONE)
2191 td = req->td_data_last;
2196 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2197 dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2198 "epstatus=0x%08x\n",
2199 (req->td_data->status & PCH_UDC_RXTX_STS),
2203 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2204 if (td->status & PCH_UDC_DMA_LAST) {
2205 count = td->status & PCH_UDC_RXTX_BYTES;
2208 if (td == req->td_data_last) {
2209 dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2212 addr = (dma_addr_t)td->next;
2213 td = phys_to_virt(addr);
2215 /* on 64k packets the RXBYTES field is zero */
2216 if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2217 count = UDC_DMA_MAXPACKET;
2218 req->td_data->status |= PCH_UDC_DMA_LAST;
2219 td->status |= PCH_UDC_BS_HST_BSY;
2222 req->req.actual = count;
2223 complete_req(ep, req, 0);
2224 /* If there is a new/failed requests try that now */
2225 if (!list_empty(&ep->queue)) {
2226 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2227 pch_udc_start_rxrequest(ep, req);
2232 * pch_udc_svc_data_in() - This function process endpoint interrupts
2234 * @dev: Reference to the device structure
2235 * @ep_num: Endpoint that generated the interrupt
2237 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2240 struct pch_udc_ep *ep;
2242 ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2246 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2247 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2248 UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2250 if ((epsts & UDC_EPSTS_BNA))
2252 if (epsts & UDC_EPSTS_HE)
2254 if (epsts & UDC_EPSTS_RSS) {
2255 pch_udc_ep_set_stall(ep);
2256 pch_udc_enable_ep_interrupts(ep->dev,
2257 PCH_UDC_EPINT(ep->in, ep->num));
2259 if (epsts & UDC_EPSTS_RCS) {
2260 if (!dev->prot_stall) {
2261 pch_udc_ep_clear_stall(ep);
2263 pch_udc_ep_set_stall(ep);
2264 pch_udc_enable_ep_interrupts(ep->dev,
2265 PCH_UDC_EPINT(ep->in, ep->num));
2268 if (epsts & UDC_EPSTS_TDC)
2269 pch_udc_complete_transfer(ep);
2270 /* On IN interrupt, provide data if we have any */
2271 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2272 !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2273 pch_udc_start_next_txrequest(ep);
2277 * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2278 * @dev: Reference to the device structure
2279 * @ep_num: Endpoint that generated the interrupt
2281 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2284 struct pch_udc_ep *ep;
2285 struct pch_udc_request *req = NULL;
2287 ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2291 if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2293 req = list_entry(ep->queue.next, struct pch_udc_request,
2295 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2296 PCH_UDC_BS_DMA_DONE) {
2297 if (!req->dma_going)
2298 pch_udc_start_rxrequest(ep, req);
2302 if (epsts & UDC_EPSTS_HE)
2304 if (epsts & UDC_EPSTS_RSS) {
2305 pch_udc_ep_set_stall(ep);
2306 pch_udc_enable_ep_interrupts(ep->dev,
2307 PCH_UDC_EPINT(ep->in, ep->num));
2309 if (epsts & UDC_EPSTS_RCS) {
2310 if (!dev->prot_stall) {
2311 pch_udc_ep_clear_stall(ep);
2313 pch_udc_ep_set_stall(ep);
2314 pch_udc_enable_ep_interrupts(ep->dev,
2315 PCH_UDC_EPINT(ep->in, ep->num));
2318 if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2319 UDC_EPSTS_OUT_DATA) {
2320 if (ep->dev->prot_stall == 1) {
2321 pch_udc_ep_set_stall(ep);
2322 pch_udc_enable_ep_interrupts(ep->dev,
2323 PCH_UDC_EPINT(ep->in, ep->num));
2325 pch_udc_complete_receiver(ep);
2328 if (list_empty(&ep->queue))
2329 pch_udc_set_dma(dev, DMA_DIR_RX);
2332 static int pch_udc_gadget_setup(struct pch_udc_dev *dev)
2333 __must_hold(&dev->lock)
2337 /* In some cases we can get an interrupt before driver gets setup */
2341 spin_unlock(&dev->lock);
2342 rc = dev->driver->setup(&dev->gadget, &dev->setup_data);
2343 spin_lock(&dev->lock);
2348 * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2349 * @dev: Reference to the device structure
2351 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2354 struct pch_udc_ep *ep;
2355 struct pch_udc_ep *ep_out;
2357 ep = &dev->ep[UDC_EP0IN_IDX];
2358 ep_out = &dev->ep[UDC_EP0OUT_IDX];
2362 if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2363 UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2364 UDC_EPSTS_XFERDONE)))
2366 if ((epsts & UDC_EPSTS_BNA))
2368 if (epsts & UDC_EPSTS_HE)
2370 if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2371 pch_udc_complete_transfer(ep);
2372 pch_udc_clear_dma(dev, DMA_DIR_RX);
2373 ep_out->td_data->status = (ep_out->td_data->status &
2374 ~PCH_UDC_BUFF_STS) |
2376 pch_udc_ep_clear_nak(ep_out);
2377 pch_udc_set_dma(dev, DMA_DIR_RX);
2378 pch_udc_ep_set_rrdy(ep_out);
2380 /* On IN interrupt, provide data if we have any */
2381 if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2382 !(epsts & UDC_EPSTS_TXEMPTY))
2383 pch_udc_start_next_txrequest(ep);
2387 * pch_udc_svc_control_out() - Routine that handle Control
2388 * OUT endpoint interrupts
2389 * @dev: Reference to the device structure
2391 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2392 __releases(&dev->lock)
2393 __acquires(&dev->lock)
2396 int setup_supported;
2397 struct pch_udc_ep *ep;
2399 ep = &dev->ep[UDC_EP0OUT_IDX];
2404 if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2405 UDC_EPSTS_OUT_SETUP) {
2407 dev->ep[UDC_EP0IN_IDX].halted = 0;
2408 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2409 dev->setup_data = ep->td_stp->request;
2410 pch_udc_init_setup_buff(ep->td_stp);
2411 pch_udc_clear_dma(dev, DMA_DIR_RX);
2412 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2413 dev->ep[UDC_EP0IN_IDX].in);
2414 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2415 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2417 dev->gadget.ep0 = &ep->ep;
2418 /* If Mass storage Reset */
2419 if ((dev->setup_data.bRequestType == 0x21) &&
2420 (dev->setup_data.bRequest == 0xFF))
2421 dev->prot_stall = 0;
2422 /* call gadget with setup data received */
2423 setup_supported = pch_udc_gadget_setup(dev);
2425 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2426 ep->td_data->status = (ep->td_data->status &
2427 ~PCH_UDC_BUFF_STS) |
2429 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2431 /* ep0 in returns data on IN phase */
2432 if (setup_supported >= 0 && setup_supported <
2433 UDC_EP0IN_MAX_PKT_SIZE) {
2434 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2435 /* Gadget would have queued a request when
2436 * we called the setup */
2437 if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2438 pch_udc_set_dma(dev, DMA_DIR_RX);
2439 pch_udc_ep_clear_nak(ep);
2441 } else if (setup_supported < 0) {
2442 /* if unsupported request, then stall */
2443 pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2444 pch_udc_enable_ep_interrupts(ep->dev,
2445 PCH_UDC_EPINT(ep->in, ep->num));
2447 pch_udc_set_dma(dev, DMA_DIR_RX);
2449 dev->waiting_zlp_ack = 1;
2451 } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2452 UDC_EPSTS_OUT_DATA) && !dev->stall) {
2453 pch_udc_clear_dma(dev, DMA_DIR_RX);
2454 pch_udc_ep_set_ddptr(ep, 0);
2455 if (!list_empty(&ep->queue)) {
2457 pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2459 pch_udc_set_dma(dev, DMA_DIR_RX);
2461 pch_udc_ep_set_rrdy(ep);
2466 * pch_udc_postsvc_epinters() - This function enables end point interrupts
2467 * and clears NAK status
2468 * @dev: Reference to the device structure
2469 * @ep_num: End point number
2471 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2473 struct pch_udc_ep *ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2474 if (list_empty(&ep->queue))
2476 pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2477 pch_udc_ep_clear_nak(ep);
2481 * pch_udc_read_all_epstatus() - This function read all endpoint status
2482 * @dev: Reference to the device structure
2483 * @ep_intr: Status of endpoint interrupt
2485 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2488 struct pch_udc_ep *ep;
2490 for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2492 if (ep_intr & (0x1 << i)) {
2493 ep = &dev->ep[UDC_EPIN_IDX(i)];
2494 ep->epsts = pch_udc_read_ep_status(ep);
2495 pch_udc_clear_ep_status(ep, ep->epsts);
2498 if (ep_intr & (0x10000 << i)) {
2499 ep = &dev->ep[UDC_EPOUT_IDX(i)];
2500 ep->epsts = pch_udc_read_ep_status(ep);
2501 pch_udc_clear_ep_status(ep, ep->epsts);
2507 * pch_udc_activate_control_ep() - This function enables the control endpoints
2508 * for traffic after a reset
2509 * @dev: Reference to the device structure
2511 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2513 struct pch_udc_ep *ep;
2516 /* Setup the IN endpoint */
2517 ep = &dev->ep[UDC_EP0IN_IDX];
2518 pch_udc_clear_ep_control(ep);
2519 pch_udc_ep_fifo_flush(ep, ep->in);
2520 pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2521 pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2522 /* Initialize the IN EP Descriptor */
2525 ep->td_data_phys = 0;
2526 ep->td_stp_phys = 0;
2528 /* Setup the OUT endpoint */
2529 ep = &dev->ep[UDC_EP0OUT_IDX];
2530 pch_udc_clear_ep_control(ep);
2531 pch_udc_ep_fifo_flush(ep, ep->in);
2532 pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2533 pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2534 val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2535 pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2537 /* Initialize the SETUP buffer */
2538 pch_udc_init_setup_buff(ep->td_stp);
2539 /* Write the pointer address of dma descriptor */
2540 pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2541 /* Write the pointer address of Setup descriptor */
2542 pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2544 /* Initialize the dma descriptor */
2545 ep->td_data->status = PCH_UDC_DMA_LAST;
2546 ep->td_data->dataptr = dev->dma_addr;
2547 ep->td_data->next = ep->td_data_phys;
2549 pch_udc_ep_clear_nak(ep);
2554 * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2555 * @dev: Reference to driver structure
2557 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2559 struct pch_udc_ep *ep;
2562 pch_udc_clear_dma(dev, DMA_DIR_TX);
2563 pch_udc_clear_dma(dev, DMA_DIR_RX);
2564 /* Mask all endpoint interrupts */
2565 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2566 /* clear all endpoint interrupts */
2567 pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2569 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2571 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2572 pch_udc_clear_ep_control(ep);
2573 pch_udc_ep_set_ddptr(ep, 0);
2574 pch_udc_write_csr(ep->dev, 0x00, i);
2577 dev->prot_stall = 0;
2578 dev->waiting_zlp_ack = 0;
2579 dev->set_cfg_not_acked = 0;
2581 /* disable ep to empty req queue. Skip the control EP's */
2582 for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2584 pch_udc_ep_set_nak(ep);
2585 pch_udc_ep_fifo_flush(ep, ep->in);
2586 /* Complete request queue */
2587 empty_req_queue(ep);
2590 spin_unlock(&dev->lock);
2591 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2592 spin_lock(&dev->lock);
2597 * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2599 * @dev: Reference to driver structure
2601 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2603 u32 dev_stat, dev_speed;
2604 u32 speed = USB_SPEED_FULL;
2606 dev_stat = pch_udc_read_device_status(dev);
2607 dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2608 UDC_DEVSTS_ENUM_SPEED_SHIFT;
2609 switch (dev_speed) {
2610 case UDC_DEVSTS_ENUM_SPEED_HIGH:
2611 speed = USB_SPEED_HIGH;
2613 case UDC_DEVSTS_ENUM_SPEED_FULL:
2614 speed = USB_SPEED_FULL;
2616 case UDC_DEVSTS_ENUM_SPEED_LOW:
2617 speed = USB_SPEED_LOW;
2622 dev->gadget.speed = speed;
2623 pch_udc_activate_control_ep(dev);
2624 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2625 pch_udc_set_dma(dev, DMA_DIR_TX);
2626 pch_udc_set_dma(dev, DMA_DIR_RX);
2627 pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2629 /* enable device interrupts */
2630 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2631 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2632 UDC_DEVINT_SI | UDC_DEVINT_SC);
2636 * pch_udc_svc_intf_interrupt() - This function handles a set interface
2638 * @dev: Reference to driver structure
2640 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2642 u32 reg, dev_stat = 0;
2645 dev_stat = pch_udc_read_device_status(dev);
2646 dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2647 UDC_DEVSTS_INTF_SHIFT;
2648 dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2649 UDC_DEVSTS_ALT_SHIFT;
2650 dev->set_cfg_not_acked = 1;
2651 /* Construct the usb request for gadget driver and inform it */
2652 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2653 dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2654 dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2655 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2656 dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2657 /* programm the Endpoint Cfg registers */
2658 /* Only one end point cfg register */
2659 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2660 reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2661 (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2662 reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2663 (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2664 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2665 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2666 /* clear stall bits */
2667 pch_udc_ep_clear_stall(&(dev->ep[i]));
2668 dev->ep[i].halted = 0;
2671 pch_udc_gadget_setup(dev);
2675 * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2677 * @dev: Reference to driver structure
2679 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2682 u32 reg, dev_stat = 0;
2684 dev_stat = pch_udc_read_device_status(dev);
2685 dev->set_cfg_not_acked = 1;
2686 dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2687 UDC_DEVSTS_CFG_SHIFT;
2688 /* make usb request for gadget driver */
2689 memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2690 dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2691 dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2692 /* program the NE registers */
2693 /* Only one end point cfg register */
2694 reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2695 reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2696 (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2697 pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2698 for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2699 /* clear stall bits */
2700 pch_udc_ep_clear_stall(&(dev->ep[i]));
2701 dev->ep[i].halted = 0;
2705 /* call gadget zero with setup data received */
2706 pch_udc_gadget_setup(dev);
2710 * pch_udc_dev_isr() - This function services device interrupts
2711 * by invoking appropriate routines.
2712 * @dev: Reference to the device structure
2713 * @dev_intr: The Device interrupt status.
2715 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2719 /* USB Reset Interrupt */
2720 if (dev_intr & UDC_DEVINT_UR) {
2721 pch_udc_svc_ur_interrupt(dev);
2722 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2724 /* Enumeration Done Interrupt */
2725 if (dev_intr & UDC_DEVINT_ENUM) {
2726 pch_udc_svc_enum_interrupt(dev);
2727 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2729 /* Set Interface Interrupt */
2730 if (dev_intr & UDC_DEVINT_SI)
2731 pch_udc_svc_intf_interrupt(dev);
2732 /* Set Config Interrupt */
2733 if (dev_intr & UDC_DEVINT_SC)
2734 pch_udc_svc_cfg_interrupt(dev);
2735 /* USB Suspend interrupt */
2736 if (dev_intr & UDC_DEVINT_US) {
2738 && dev->driver->suspend) {
2739 spin_unlock(&dev->lock);
2740 dev->driver->suspend(&dev->gadget);
2741 spin_lock(&dev->lock);
2744 vbus = pch_vbus_gpio_get_value(dev);
2745 if ((dev->vbus_session == 0)
2747 if (dev->driver && dev->driver->disconnect) {
2748 spin_unlock(&dev->lock);
2749 dev->driver->disconnect(&dev->gadget);
2750 spin_lock(&dev->lock);
2752 pch_udc_reconnect(dev);
2753 } else if ((dev->vbus_session == 0)
2755 && !dev->vbus_gpio.intr)
2756 schedule_work(&dev->vbus_gpio.irq_work_fall);
2758 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2760 /* Clear the SOF interrupt, if enabled */
2761 if (dev_intr & UDC_DEVINT_SOF)
2762 dev_dbg(&dev->pdev->dev, "SOF\n");
2763 /* ES interrupt, IDLE > 3ms on the USB */
2764 if (dev_intr & UDC_DEVINT_ES)
2765 dev_dbg(&dev->pdev->dev, "ES\n");
2766 /* RWKP interrupt */
2767 if (dev_intr & UDC_DEVINT_RWKP)
2768 dev_dbg(&dev->pdev->dev, "RWKP\n");
2772 * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2773 * @irq: Interrupt request number
2774 * @dev: Reference to the device structure
2776 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2778 struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2779 u32 dev_intr, ep_intr;
2782 dev_intr = pch_udc_read_device_interrupts(dev);
2783 ep_intr = pch_udc_read_ep_interrupts(dev);
2785 /* For a hot plug, this find that the controller is hung up. */
2786 if (dev_intr == ep_intr)
2787 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2788 dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2789 /* The controller is reset */
2790 pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2794 /* Clear device interrupts */
2795 pch_udc_write_device_interrupts(dev, dev_intr);
2797 /* Clear ep interrupts */
2798 pch_udc_write_ep_interrupts(dev, ep_intr);
2799 if (!dev_intr && !ep_intr)
2801 spin_lock(&dev->lock);
2803 pch_udc_dev_isr(dev, dev_intr);
2805 pch_udc_read_all_epstatus(dev, ep_intr);
2806 /* Process Control In interrupts, if present */
2807 if (ep_intr & UDC_EPINT_IN_EP0) {
2808 pch_udc_svc_control_in(dev);
2809 pch_udc_postsvc_epinters(dev, 0);
2811 /* Process Control Out interrupts, if present */
2812 if (ep_intr & UDC_EPINT_OUT_EP0)
2813 pch_udc_svc_control_out(dev);
2814 /* Process data in end point interrupts */
2815 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2816 if (ep_intr & (1 << i)) {
2817 pch_udc_svc_data_in(dev, i);
2818 pch_udc_postsvc_epinters(dev, i);
2821 /* Process data out end point interrupts */
2822 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2823 PCH_UDC_USED_EP_NUM); i++)
2824 if (ep_intr & (1 << i))
2825 pch_udc_svc_data_out(dev, i -
2826 UDC_EPINT_OUT_SHIFT);
2828 spin_unlock(&dev->lock);
2833 * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2834 * @dev: Reference to the device structure
2836 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2838 /* enable ep0 interrupts */
2839 pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2841 /* enable device interrupts */
2842 pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2843 UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2844 UDC_DEVINT_SI | UDC_DEVINT_SC);
2848 * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2849 * @dev: Reference to the driver structure
2851 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2853 const char *const ep_string[] = {
2854 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2855 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2856 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2857 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2858 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2859 "ep15in", "ep15out",
2863 dev->gadget.speed = USB_SPEED_UNKNOWN;
2864 INIT_LIST_HEAD(&dev->gadget.ep_list);
2866 /* Initialize the endpoints structures */
2867 memset(dev->ep, 0, sizeof dev->ep);
2868 for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2869 struct pch_udc_ep *ep = &dev->ep[i];
2874 ep->ep.name = ep_string[i];
2875 ep->ep.ops = &pch_udc_ep_ops;
2877 ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2878 ep->ep.caps.dir_in = true;
2880 ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2882 ep->ep.caps.dir_out = true;
2884 if (i == UDC_EP0IN_IDX || i == UDC_EP0OUT_IDX) {
2885 ep->ep.caps.type_control = true;
2887 ep->ep.caps.type_iso = true;
2888 ep->ep.caps.type_bulk = true;
2889 ep->ep.caps.type_int = true;
2891 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2892 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2893 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2894 INIT_LIST_HEAD(&ep->queue);
2896 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2897 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2899 /* remove ep0 in and out from the list. They have own pointer */
2900 list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2901 list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2903 dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2904 INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2908 * pch_udc_pcd_init() - This API initializes the driver structure
2909 * @dev: Reference to the driver structure
2914 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2917 pch_udc_pcd_reinit(dev);
2918 pch_vbus_gpio_init(dev, vbus_gpio_port);
2923 * init_dma_pools() - create dma pools during initialization
2924 * @pdev: reference to struct pci_dev
2926 static int init_dma_pools(struct pch_udc_dev *dev)
2928 struct pch_udc_stp_dma_desc *td_stp;
2929 struct pch_udc_data_dma_desc *td_data;
2933 dev->data_requests = pci_pool_create("data_requests", dev->pdev,
2934 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2935 if (!dev->data_requests) {
2936 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2941 /* dma desc for setup data */
2942 dev->stp_requests = pci_pool_create("setup requests", dev->pdev,
2943 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2944 if (!dev->stp_requests) {
2945 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2950 td_stp = pci_pool_alloc(dev->stp_requests, GFP_KERNEL,
2951 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2953 dev_err(&dev->pdev->dev,
2954 "%s: can't allocate setup dma descriptor\n", __func__);
2957 dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2959 /* data: 0 packets !? */
2960 td_data = pci_pool_alloc(dev->data_requests, GFP_KERNEL,
2961 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2963 dev_err(&dev->pdev->dev,
2964 "%s: can't allocate data dma descriptor\n", __func__);
2967 dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2968 dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2969 dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2970 dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2971 dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2973 ep0out_buf = devm_kzalloc(&dev->pdev->dev, UDC_EP0OUT_BUFF_SIZE * 4,
2977 dev->dma_addr = dma_map_single(&dev->pdev->dev, ep0out_buf,
2978 UDC_EP0OUT_BUFF_SIZE * 4,
2980 return dma_mapping_error(&dev->pdev->dev, dev->dma_addr);
2983 static int pch_udc_start(struct usb_gadget *g,
2984 struct usb_gadget_driver *driver)
2986 struct pch_udc_dev *dev = to_pch_udc(g);
2988 driver->driver.bus = NULL;
2989 dev->driver = driver;
2991 /* get ready for ep0 traffic */
2992 pch_udc_setup_ep0(dev);
2995 if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr)
2996 pch_udc_clear_disconnect(dev);
3002 static int pch_udc_stop(struct usb_gadget *g)
3004 struct pch_udc_dev *dev = to_pch_udc(g);
3006 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3008 /* Assures that there are no pending requests with this driver */
3013 pch_udc_set_disconnect(dev);
3018 static void pch_udc_shutdown(struct pci_dev *pdev)
3020 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3022 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3023 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3025 /* disable the pullup so the host will think we're gone */
3026 pch_udc_set_disconnect(dev);
3029 static void pch_udc_remove(struct pci_dev *pdev)
3031 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3033 usb_del_gadget_udc(&dev->gadget);
3035 /* gadget driver must not be registered */
3038 "%s: gadget driver still bound!!!\n", __func__);
3039 /* dma pool cleanup */
3040 if (dev->data_requests)
3041 pci_pool_destroy(dev->data_requests);
3043 if (dev->stp_requests) {
3044 /* cleanup DMA desc's for ep0in */
3045 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3046 pci_pool_free(dev->stp_requests,
3047 dev->ep[UDC_EP0OUT_IDX].td_stp,
3048 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3050 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3051 pci_pool_free(dev->stp_requests,
3052 dev->ep[UDC_EP0OUT_IDX].td_data,
3053 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3055 pci_pool_destroy(dev->stp_requests);
3059 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3060 UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3062 pch_vbus_gpio_free(dev);
3067 #ifdef CONFIG_PM_SLEEP
3068 static int pch_udc_suspend(struct device *d)
3070 struct pci_dev *pdev = to_pci_dev(d);
3071 struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3073 pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3074 pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3079 static int pch_udc_resume(struct device *d)
3084 static SIMPLE_DEV_PM_OPS(pch_udc_pm, pch_udc_suspend, pch_udc_resume);
3085 #define PCH_UDC_PM_OPS (&pch_udc_pm)
3087 #define PCH_UDC_PM_OPS NULL
3088 #endif /* CONFIG_PM_SLEEP */
3090 static int pch_udc_probe(struct pci_dev *pdev,
3091 const struct pci_device_id *id)
3095 struct pch_udc_dev *dev;
3098 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3103 retval = pcim_enable_device(pdev);
3107 pci_set_drvdata(pdev, dev);
3109 /* Determine BAR based on PCI ID */
3110 if (id->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC)
3111 bar = PCH_UDC_PCI_BAR_QUARK_X1000;
3113 bar = PCH_UDC_PCI_BAR;
3115 /* PCI resource allocation */
3116 retval = pcim_iomap_regions(pdev, 1 << bar, pci_name(pdev));
3120 dev->base_addr = pcim_iomap_table(pdev)[bar];
3122 /* initialize the hardware */
3123 if (pch_udc_pcd_init(dev))
3126 pci_enable_msi(pdev);
3128 retval = devm_request_irq(&pdev->dev, pdev->irq, pch_udc_isr,
3129 IRQF_SHARED, KBUILD_MODNAME, dev);
3131 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3136 pci_set_master(pdev);
3137 pci_try_set_mwi(pdev);
3139 /* device struct setup */
3140 spin_lock_init(&dev->lock);
3142 dev->gadget.ops = &pch_udc_ops;
3144 retval = init_dma_pools(dev);
3148 dev->gadget.name = KBUILD_MODNAME;
3149 dev->gadget.max_speed = USB_SPEED_HIGH;
3151 /* Put the device in disconnected state till a driver is bound */
3152 pch_udc_set_disconnect(dev);
3153 retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3159 pch_udc_remove(pdev);
3163 static const struct pci_device_id pch_udc_pcidev_id[] = {
3165 PCI_DEVICE(PCI_VENDOR_ID_INTEL,
3166 PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC),
3167 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3168 .class_mask = 0xffffffff,
3171 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3172 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3173 .class_mask = 0xffffffff,
3176 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3177 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3178 .class_mask = 0xffffffff,
3181 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3182 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3183 .class_mask = 0xffffffff,
3188 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3190 static struct pci_driver pch_udc_driver = {
3191 .name = KBUILD_MODNAME,
3192 .id_table = pch_udc_pcidev_id,
3193 .probe = pch_udc_probe,
3194 .remove = pch_udc_remove,
3195 .shutdown = pch_udc_shutdown,
3197 .pm = PCH_UDC_PM_OPS,
3201 module_pci_driver(pch_udc_driver);
3203 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3204 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3205 MODULE_LICENSE("GPL");