drivers/usb/gadget/udc/pch_udc.c

   1 /*
   2  * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  */
   8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/pci.h>
  12 #include <linux/delay.h>
  13 #include <linux/errno.h>
  14 #include <linux/list.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/usb/ch9.h>
  17 #include <linux/usb/gadget.h>
  18 #include <linux/gpio.h>
  19 #include <linux/irq.h>
  20
  21 /* GPIO port for VBUS detecting */
  22 static int vbus_gpio_port = -1;         /* GPIO port number (-1:Not used) */
  23
  24 #define PCH_VBUS_PERIOD         3000    /* VBUS polling period (msec) */
  25 #define PCH_VBUS_INTERVAL       10      /* VBUS polling interval (msec) */
  26
  27 /* Address offset of Registers */
  28 #define UDC_EP_REG_SHIFT        0x20    /* Offset to next EP */
  29
  30 #define UDC_EPCTL_ADDR          0x00    /* Endpoint control */
  31 #define UDC_EPSTS_ADDR          0x04    /* Endpoint status */
  32 #define UDC_BUFIN_FRAMENUM_ADDR 0x08    /* buffer size in / frame number out */
  33 #define UDC_BUFOUT_MAXPKT_ADDR  0x0C    /* buffer size out / maxpkt in */
  34 #define UDC_SUBPTR_ADDR         0x10    /* setup buffer pointer */
  35 #define UDC_DESPTR_ADDR         0x14    /* Data descriptor pointer */
  36 #define UDC_CONFIRM_ADDR        0x18    /* Write/Read confirmation */
  37
  38 #define UDC_DEVCFG_ADDR         0x400   /* Device configuration */
  39 #define UDC_DEVCTL_ADDR         0x404   /* Device control */
  40 #define UDC_DEVSTS_ADDR         0x408   /* Device status */
  41 #define UDC_DEVIRQSTS_ADDR      0x40C   /* Device irq status */
  42 #define UDC_DEVIRQMSK_ADDR      0x410   /* Device irq mask */
  43 #define UDC_EPIRQSTS_ADDR       0x414   /* Endpoint irq status */
  44 #define UDC_EPIRQMSK_ADDR       0x418   /* Endpoint irq mask */
  45 #define UDC_DEVLPM_ADDR         0x41C   /* LPM control / status */
  46 #define UDC_CSR_BUSY_ADDR       0x4f0   /* UDC_CSR_BUSY Status register */
  47 #define UDC_SRST_ADDR           0x4fc   /* SOFT RESET register */
  48 #define UDC_CSR_ADDR            0x500   /* USB_DEVICE endpoint register */
  49
  50 /* Endpoint control register */
  51 /* Bit position */
  52 #define UDC_EPCTL_MRXFLUSH              (1 << 12)
  53 #define UDC_EPCTL_RRDY                  (1 << 9)
  54 #define UDC_EPCTL_CNAK                  (1 << 8)
  55 #define UDC_EPCTL_SNAK                  (1 << 7)
  56 #define UDC_EPCTL_NAK                   (1 << 6)
  57 #define UDC_EPCTL_P                     (1 << 3)
  58 #define UDC_EPCTL_F                     (1 << 1)
  59 #define UDC_EPCTL_S                     (1 << 0)
  60 #define UDC_EPCTL_ET_SHIFT              4
  61 /* Mask patern */
  62 #define UDC_EPCTL_ET_MASK               0x00000030
  63 /* Value for ET field */
  64 #define UDC_EPCTL_ET_CONTROL            0
  65 #define UDC_EPCTL_ET_ISO                1
  66 #define UDC_EPCTL_ET_BULK               2
  67 #define UDC_EPCTL_ET_INTERRUPT          3
  68
  69 /* Endpoint status register */
  70 /* Bit position */
  71 #define UDC_EPSTS_XFERDONE              (1 << 27)
  72 #define UDC_EPSTS_RSS                   (1 << 26)
  73 #define UDC_EPSTS_RCS                   (1 << 25)
  74 #define UDC_EPSTS_TXEMPTY               (1 << 24)
  75 #define UDC_EPSTS_TDC                   (1 << 10)
  76 #define UDC_EPSTS_HE                    (1 << 9)
  77 #define UDC_EPSTS_MRXFIFO_EMP           (1 << 8)
  78 #define UDC_EPSTS_BNA                   (1 << 7)
  79 #define UDC_EPSTS_IN                    (1 << 6)
  80 #define UDC_EPSTS_OUT_SHIFT             4
  81 /* Mask patern */
  82 #define UDC_EPSTS_OUT_MASK              0x00000030
  83 #define UDC_EPSTS_ALL_CLR_MASK          0x1F0006F0
  84 /* Value for OUT field */
  85 #define UDC_EPSTS_OUT_SETUP             2
  86 #define UDC_EPSTS_OUT_DATA              1
  87
  88 /* Device configuration register */
  89 /* Bit position */
  90 #define UDC_DEVCFG_CSR_PRG              (1 << 17)
  91 #define UDC_DEVCFG_SP                   (1 << 3)
  92 /* SPD Valee */
  93 #define UDC_DEVCFG_SPD_HS               0x0
  94 #define UDC_DEVCFG_SPD_FS               0x1
  95 #define UDC_DEVCFG_SPD_LS               0x2
  96
  97 /* Device control register */
  98 /* Bit position */
  99 #define UDC_DEVCTL_THLEN_SHIFT          24
 100 #define UDC_DEVCTL_BRLEN_SHIFT          16
 101 #define UDC_DEVCTL_CSR_DONE             (1 << 13)
 102 #define UDC_DEVCTL_SD                   (1 << 10)
 103 #define UDC_DEVCTL_MODE                 (1 << 9)
 104 #define UDC_DEVCTL_BREN                 (1 << 8)
 105 #define UDC_DEVCTL_THE                  (1 << 7)
 106 #define UDC_DEVCTL_DU                   (1 << 4)
 107 #define UDC_DEVCTL_TDE                  (1 << 3)
 108 #define UDC_DEVCTL_RDE                  (1 << 2)
 109 #define UDC_DEVCTL_RES                  (1 << 0)
 110
 111 /* Device status register */
 112 /* Bit position */
 113 #define UDC_DEVSTS_TS_SHIFT             18
 114 #define UDC_DEVSTS_ENUM_SPEED_SHIFT     13
 115 #define UDC_DEVSTS_ALT_SHIFT            8
 116 #define UDC_DEVSTS_INTF_SHIFT           4
 117 #define UDC_DEVSTS_CFG_SHIFT            0
 118 /* Mask patern */
 119 #define UDC_DEVSTS_TS_MASK              0xfffc0000
 120 #define UDC_DEVSTS_ENUM_SPEED_MASK      0x00006000
 121 #define UDC_DEVSTS_ALT_MASK             0x00000f00
 122 #define UDC_DEVSTS_INTF_MASK            0x000000f0
 123 #define UDC_DEVSTS_CFG_MASK             0x0000000f
 124 /* value for maximum speed for SPEED field */
 125 #define UDC_DEVSTS_ENUM_SPEED_FULL      1
 126 #define UDC_DEVSTS_ENUM_SPEED_HIGH      0
 127 #define UDC_DEVSTS_ENUM_SPEED_LOW       2
 128 #define UDC_DEVSTS_ENUM_SPEED_FULLX     3
 129
 130 /* Device irq register */
 131 /* Bit position */
 132 #define UDC_DEVINT_RWKP                 (1 << 7)
 133 #define UDC_DEVINT_ENUM                 (1 << 6)
 134 #define UDC_DEVINT_SOF                  (1 << 5)
 135 #define UDC_DEVINT_US                   (1 << 4)
 136 #define UDC_DEVINT_UR                   (1 << 3)
 137 #define UDC_DEVINT_ES                   (1 << 2)
 138 #define UDC_DEVINT_SI                   (1 << 1)
 139 #define UDC_DEVINT_SC                   (1 << 0)
 140 /* Mask patern */
 141 #define UDC_DEVINT_MSK                  0x7f
 142
 143 /* Endpoint irq register */
 144 /* Bit position */
 145 #define UDC_EPINT_IN_SHIFT              0
 146 #define UDC_EPINT_OUT_SHIFT             16
 147 #define UDC_EPINT_IN_EP0                (1 << 0)
 148 #define UDC_EPINT_OUT_EP0               (1 << 16)
 149 /* Mask patern */
 150 #define UDC_EPINT_MSK_DISABLE_ALL       0xffffffff
 151
 152 /* UDC_CSR_BUSY Status register */
 153 /* Bit position */
 154 #define UDC_CSR_BUSY                    (1 << 0)
 155
 156 /* SOFT RESET register */
 157 /* Bit position */
 158 #define UDC_PSRST                       (1 << 1)
 159 #define UDC_SRST                        (1 << 0)
 160
 161 /* USB_DEVICE endpoint register */
 162 /* Bit position */
 163 #define UDC_CSR_NE_NUM_SHIFT            0
 164 #define UDC_CSR_NE_DIR_SHIFT            4
 165 #define UDC_CSR_NE_TYPE_SHIFT           5
 166 #define UDC_CSR_NE_CFG_SHIFT            7
 167 #define UDC_CSR_NE_INTF_SHIFT           11
 168 #define UDC_CSR_NE_ALT_SHIFT            15
 169 #define UDC_CSR_NE_MAX_PKT_SHIFT        19
 170 /* Mask patern */
 171 #define UDC_CSR_NE_NUM_MASK             0x0000000f
 172 #define UDC_CSR_NE_DIR_MASK             0x00000010
 173 #define UDC_CSR_NE_TYPE_MASK            0x00000060
 174 #define UDC_CSR_NE_CFG_MASK             0x00000780
 175 #define UDC_CSR_NE_INTF_MASK            0x00007800
 176 #define UDC_CSR_NE_ALT_MASK             0x00078000
 177 #define UDC_CSR_NE_MAX_PKT_MASK         0x3ff80000
 178
 179 #define PCH_UDC_CSR(ep) (UDC_CSR_ADDR + ep*4)
 180 #define PCH_UDC_EPINT(in, num)\
 181                 (1 << (num + (in ? UDC_EPINT_IN_SHIFT : UDC_EPINT_OUT_SHIFT)))
 182
 183 /* Index of endpoint */
 184 #define UDC_EP0IN_IDX           0
 185 #define UDC_EP0OUT_IDX          1
 186 #define UDC_EPIN_IDX(ep)        (ep * 2)
 187 #define UDC_EPOUT_IDX(ep)       (ep * 2 + 1)
 188 #define PCH_UDC_EP0             0
 189 #define PCH_UDC_EP1             1
 190 #define PCH_UDC_EP2             2
 191 #define PCH_UDC_EP3             3
 192
 193 /* Number of endpoint */
 194 #define PCH_UDC_EP_NUM          32      /* Total number of EPs (16 IN,16 OUT) */
 195 #define PCH_UDC_USED_EP_NUM     4       /* EP number of EP's really used */
 196 /* Length Value */
 197 #define PCH_UDC_BRLEN           0x0F    /* Burst length */
 198 #define PCH_UDC_THLEN           0x1F    /* Threshold length */
 199 /* Value of EP Buffer Size */
 200 #define UDC_EP0IN_BUFF_SIZE     16
 201 #define UDC_EPIN_BUFF_SIZE      256
 202 #define UDC_EP0OUT_BUFF_SIZE    16
 203 #define UDC_EPOUT_BUFF_SIZE     256
 204 /* Value of EP maximum packet size */
 205 #define UDC_EP0IN_MAX_PKT_SIZE  64
 206 #define UDC_EP0OUT_MAX_PKT_SIZE 64
 207 #define UDC_BULK_MAX_PKT_SIZE   512
 208
 209 /* DMA */
 210 #define DMA_DIR_RX              1       /* DMA for data receive */
 211 #define DMA_DIR_TX              2       /* DMA for data transmit */
 212 #define DMA_ADDR_INVALID        (~(dma_addr_t)0)
 213 #define UDC_DMA_MAXPACKET       65536   /* maximum packet size for DMA */
 214
 215 /**
 216  * struct pch_udc_data_dma_desc - Structure to hold DMA descriptor information
 217  *                                for data
 218  * @status:             Status quadlet
 219  * @reserved:           Reserved
 220  * @dataptr:            Buffer descriptor
 221  * @next:               Next descriptor
 222  */
 223 struct pch_udc_data_dma_desc {
 224         u32 status;
 225         u32 reserved;
 226         u32 dataptr;
 227         u32 next;
 228 };
 229
 230 /**
 231  * struct pch_udc_stp_dma_desc - Structure to hold DMA descriptor information
 232  *                               for control data
 233  * @status:     Status
 234  * @reserved:   Reserved
 235  * @data12:     First setup word
 236  * @data34:     Second setup word
 237  */
 238 struct pch_udc_stp_dma_desc {
 239         u32 status;
 240         u32 reserved;
 241         struct usb_ctrlrequest request;
 242 } __attribute((packed));
 243
 244 /* DMA status definitions */
 245 /* Buffer status */
 246 #define PCH_UDC_BUFF_STS        0xC0000000
 247 #define PCH_UDC_BS_HST_RDY      0x00000000
 248 #define PCH_UDC_BS_DMA_BSY      0x40000000
 249 #define PCH_UDC_BS_DMA_DONE     0x80000000
 250 #define PCH_UDC_BS_HST_BSY      0xC0000000
 251 /*  Rx/Tx Status */
 252 #define PCH_UDC_RXTX_STS        0x30000000
 253 #define PCH_UDC_RTS_SUCC        0x00000000
 254 #define PCH_UDC_RTS_DESERR      0x10000000
 255 #define PCH_UDC_RTS_BUFERR      0x30000000
 256 /* Last Descriptor Indication */
 257 #define PCH_UDC_DMA_LAST        0x08000000
 258 /* Number of Rx/Tx Bytes Mask */
 259 #define PCH_UDC_RXTX_BYTES      0x0000ffff
 260
 261 /**
 262  * struct pch_udc_cfg_data - Structure to hold current configuration
 263  *                           and interface information
 264  * @cur_cfg:    current configuration in use
 265  * @cur_intf:   current interface in use
 266  * @cur_alt:    current alt interface in use
 267  */
 268 struct pch_udc_cfg_data {
 269         u16 cur_cfg;
 270         u16 cur_intf;
 271         u16 cur_alt;
 272 };
 273
 274 /**
 275  * struct pch_udc_ep - Structure holding a PCH USB device Endpoint information
 276  * @ep:                 embedded ep request
 277  * @td_stp_phys:        for setup request
 278  * @td_data_phys:       for data request
 279  * @td_stp:             for setup request
 280  * @td_data:            for data request
 281  * @dev:                reference to device struct
 282  * @offset_addr:        offset address of ep register
 283  * @desc:               for this ep
 284  * @queue:              queue for requests
 285  * @num:                endpoint number
 286  * @in:                 endpoint is IN
 287  * @halted:             endpoint halted?
 288  * @epsts:              Endpoint status
 289  */
 290 struct pch_udc_ep {
 291         struct usb_ep                   ep;
 292         dma_addr_t                      td_stp_phys;
 293         dma_addr_t                      td_data_phys;
 294         struct pch_udc_stp_dma_desc     *td_stp;
 295         struct pch_udc_data_dma_desc    *td_data;
 296         struct pch_udc_dev              *dev;
 297         unsigned long                   offset_addr;
 298         struct list_head                queue;
 299         unsigned                        num:5,
 300                                         in:1,
 301                                         halted:1;
 302         unsigned long                   epsts;
 303 };
 304
 305 /**
 306  * struct pch_vbus_gpio_data - Structure holding GPIO informaton
 307  *                                      for detecting VBUS
 308  * @port:               gpio port number
 309  * @intr:               gpio interrupt number
 310  * @irq_work_fall       Structure for WorkQueue
 311  * @irq_work_rise       Structure for WorkQueue
 312  */
 313 struct pch_vbus_gpio_data {
 314         int                     port;
 315         int                     intr;
 316         struct work_struct      irq_work_fall;
 317         struct work_struct      irq_work_rise;
 318 };
 319
 320 /**
 321  * struct pch_udc_dev - Structure holding complete information
 322  *                      of the PCH USB device
 323  * @gadget:             gadget driver data
 324  * @driver:             reference to gadget driver bound
 325  * @pdev:               reference to the PCI device
 326  * @ep:                 array of endpoints
 327  * @lock:               protects all state
 328  * @stall:              stall requested
 329  * @prot_stall:         protcol stall requested
 330  * @registered:         driver registered with system
 331  * @suspended:          driver in suspended state
 332  * @connected:          gadget driver associated
 333  * @vbus_session:       required vbus_session state
 334  * @set_cfg_not_acked:  pending acknowledgement 4 setup
 335  * @waiting_zlp_ack:    pending acknowledgement 4 ZLP
 336  * @data_requests:      DMA pool for data requests
 337  * @stp_requests:       DMA pool for setup requests
 338  * @dma_addr:           DMA pool for received
 339  * @setup_data:         Received setup data
 340  * @base_addr:          for mapped device memory
 341  * @cfg_data:           current cfg, intf, and alt in use
 342  * @vbus_gpio:          GPIO informaton for detecting VBUS
 343  */
 344 struct pch_udc_dev {
 345         struct usb_gadget               gadget;
 346         struct usb_gadget_driver        *driver;
 347         struct pci_dev                  *pdev;
 348         struct pch_udc_ep               ep[PCH_UDC_EP_NUM];
 349         spinlock_t                      lock; /* protects all state */
 350         unsigned
 351                         stall:1,
 352                         prot_stall:1,
 353                         suspended:1,
 354                         connected:1,
 355                         vbus_session:1,
 356                         set_cfg_not_acked:1,
 357                         waiting_zlp_ack:1;
 358         struct dma_pool         *data_requests;
 359         struct dma_pool         *stp_requests;
 360         dma_addr_t                      dma_addr;
 361         struct usb_ctrlrequest          setup_data;
 362         void __iomem                    *base_addr;
 363         struct pch_udc_cfg_data         cfg_data;
 364         struct pch_vbus_gpio_data       vbus_gpio;
 365 };
 366 #define to_pch_udc(g)   (container_of((g), struct pch_udc_dev, gadget))
 367
 368 #define PCH_UDC_PCI_BAR_QUARK_X1000     0
 369 #define PCH_UDC_PCI_BAR                 1
 370
 371 #define PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC     0x0939
 372 #define PCI_DEVICE_ID_INTEL_EG20T_UDC           0x8808
 373
 374 #define PCI_VENDOR_ID_ROHM              0x10DB
 375 #define PCI_DEVICE_ID_ML7213_IOH_UDC    0x801D
 376 #define PCI_DEVICE_ID_ML7831_IOH_UDC    0x8808
 377
 378 static const char       ep0_string[] = "ep0in";
 379 static DEFINE_SPINLOCK(udc_stall_spinlock);     /* stall spin lock */
 380 static bool speed_fs;
 381 module_param_named(speed_fs, speed_fs, bool, S_IRUGO);
 382 MODULE_PARM_DESC(speed_fs, "true for Full speed operation");
 383
 384 /**
 385  * struct pch_udc_request - Structure holding a PCH USB device request packet
 386  * @req:                embedded ep request
 387  * @td_data_phys:       phys. address
 388  * @td_data:            first dma desc. of chain
 389  * @td_data_last:       last dma desc. of chain
 390  * @queue:              associated queue
 391  * @dma_going:          DMA in progress for request
 392  * @dma_mapped:         DMA memory mapped for request
 393  * @dma_done:           DMA completed for request
 394  * @chain_len:          chain length
 395  * @buf:                Buffer memory for align adjustment
 396  * @dma:                DMA memory for align adjustment
 397  */
 398 struct pch_udc_request {
 399         struct usb_request              req;
 400         dma_addr_t                      td_data_phys;
 401         struct pch_udc_data_dma_desc    *td_data;
 402         struct pch_udc_data_dma_desc    *td_data_last;
 403         struct list_head                queue;
 404         unsigned                        dma_going:1,
 405                                         dma_mapped:1,
 406                                         dma_done:1;
 407         unsigned                        chain_len;
 408         void                            *buf;
 409         dma_addr_t                      dma;
 410 };
 411
 412 static inline u32 pch_udc_readl(struct pch_udc_dev *dev, unsigned long reg)
 413 {
 414         return ioread32(dev->base_addr + reg);
 415 }
 416
 417 static inline void pch_udc_writel(struct pch_udc_dev *dev,
 418                                     unsigned long val, unsigned long reg)
 419 {
 420         iowrite32(val, dev->base_addr + reg);
 421 }
 422
 423 static inline void pch_udc_bit_set(struct pch_udc_dev *dev,
 424                                      unsigned long reg,
 425                                      unsigned long bitmask)
 426 {
 427         pch_udc_writel(dev, pch_udc_readl(dev, reg) | bitmask, reg);
 428 }
 429
 430 static inline void pch_udc_bit_clr(struct pch_udc_dev *dev,
 431                                      unsigned long reg,
 432                                      unsigned long bitmask)
 433 {
 434         pch_udc_writel(dev, pch_udc_readl(dev, reg) & ~(bitmask), reg);
 435 }
 436
 437 static inline u32 pch_udc_ep_readl(struct pch_udc_ep *ep, unsigned long reg)
 438 {
 439         return ioread32(ep->dev->base_addr + ep->offset_addr + reg);
 440 }
 441
 442 static inline void pch_udc_ep_writel(struct pch_udc_ep *ep,
 443                                     unsigned long val, unsigned long reg)
 444 {
 445         iowrite32(val, ep->dev->base_addr + ep->offset_addr + reg);
 446 }
 447
 448 static inline void pch_udc_ep_bit_set(struct pch_udc_ep *ep,
 449                                      unsigned long reg,
 450                                      unsigned long bitmask)
 451 {
 452         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) | bitmask, reg);
 453 }
 454
 455 static inline void pch_udc_ep_bit_clr(struct pch_udc_ep *ep,
 456                                      unsigned long reg,
 457                                      unsigned long bitmask)
 458 {
 459         pch_udc_ep_writel(ep, pch_udc_ep_readl(ep, reg) & ~(bitmask), reg);
 460 }
 461
 462 /**
 463  * pch_udc_csr_busy() - Wait till idle.
 464  * @dev:        Reference to pch_udc_dev structure
 465  */
 466 static void pch_udc_csr_busy(struct pch_udc_dev *dev)
 467 {
 468         unsigned int count = 200;
 469
 470         /* Wait till idle */
 471         while ((pch_udc_readl(dev, UDC_CSR_BUSY_ADDR) & UDC_CSR_BUSY)
 472                 && --count)
 473                 cpu_relax();
 474         if (!count)
 475                 dev_err(&dev->pdev->dev, "%s: wait error\n", __func__);
 476 }
 477
 478 /**
 479  * pch_udc_write_csr() - Write the command and status registers.
 480  * @dev:        Reference to pch_udc_dev structure
 481  * @val:        value to be written to CSR register
 482  * @addr:       address of CSR register
 483  */
 484 static void pch_udc_write_csr(struct pch_udc_dev *dev, unsigned long val,
 485                                unsigned int ep)
 486 {
 487         unsigned long reg = PCH_UDC_CSR(ep);
 488
 489         pch_udc_csr_busy(dev);          /* Wait till idle */
 490         pch_udc_writel(dev, val, reg);
 491         pch_udc_csr_busy(dev);          /* Wait till idle */
 492 }
 493
 494 /**
 495  * pch_udc_read_csr() - Read the command and status registers.
 496  * @dev:        Reference to pch_udc_dev structure
 497  * @addr:       address of CSR register
 498  *
 499  * Return codes:        content of CSR register
 500  */
 501 static u32 pch_udc_read_csr(struct pch_udc_dev *dev, unsigned int ep)
 502 {
 503         unsigned long reg = PCH_UDC_CSR(ep);
 504
 505         pch_udc_csr_busy(dev);          /* Wait till idle */
 506         pch_udc_readl(dev, reg);        /* Dummy read */
 507         pch_udc_csr_busy(dev);          /* Wait till idle */
 508         return pch_udc_readl(dev, reg);
 509 }
 510
 511 /**
 512  * pch_udc_rmt_wakeup() - Initiate for remote wakeup
 513  * @dev:        Reference to pch_udc_dev structure
 514  */
 515 static inline void pch_udc_rmt_wakeup(struct pch_udc_dev *dev)
 516 {
 517         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 518         mdelay(1);
 519         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 520 }
 521
 522 /**
 523  * pch_udc_get_frame() - Get the current frame from device status register
 524  * @dev:        Reference to pch_udc_dev structure
 525  * Retern       current frame
 526  */
 527 static inline int pch_udc_get_frame(struct pch_udc_dev *dev)
 528 {
 529         u32 frame = pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 530         return (frame & UDC_DEVSTS_TS_MASK) >> UDC_DEVSTS_TS_SHIFT;
 531 }
 532
 533 /**
 534  * pch_udc_clear_selfpowered() - Clear the self power control
 535  * @dev:        Reference to pch_udc_regs structure
 536  */
 537 static inline void pch_udc_clear_selfpowered(struct pch_udc_dev *dev)
 538 {
 539         pch_udc_bit_clr(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 540 }
 541
 542 /**
 543  * pch_udc_set_selfpowered() - Set the self power control
 544  * @dev:        Reference to pch_udc_regs structure
 545  */
 546 static inline void pch_udc_set_selfpowered(struct pch_udc_dev *dev)
 547 {
 548         pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_SP);
 549 }
 550
 551 /**
 552  * pch_udc_set_disconnect() - Set the disconnect status.
 553  * @dev:        Reference to pch_udc_regs structure
 554  */
 555 static inline void pch_udc_set_disconnect(struct pch_udc_dev *dev)
 556 {
 557         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 558 }
 559
 560 /**
 561  * pch_udc_clear_disconnect() - Clear the disconnect status.
 562  * @dev:        Reference to pch_udc_regs structure
 563  */
 564 static void pch_udc_clear_disconnect(struct pch_udc_dev *dev)
 565 {
 566         /* Clear the disconnect */
 567         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 568         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 569         mdelay(1);
 570         /* Resume USB signalling */
 571         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 572 }
 573
 574 /**
 575  * pch_udc_reconnect() - This API initializes usb device controller,
 576  *                                              and clear the disconnect status.
 577  * @dev:                Reference to pch_udc_regs structure
 578  */
 579 static void pch_udc_init(struct pch_udc_dev *dev);
 580 static void pch_udc_reconnect(struct pch_udc_dev *dev)
 581 {
 582         pch_udc_init(dev);
 583
 584         /* enable device interrupts */
 585         /* pch_udc_enable_interrupts() */
 586         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR,
 587                         UDC_DEVINT_UR | UDC_DEVINT_ENUM);
 588
 589         /* Clear the disconnect */
 590         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 591         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_SD);
 592         mdelay(1);
 593         /* Resume USB signalling */
 594         pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RES);
 595 }
 596
 597 /**
 598  * pch_udc_vbus_session() - set or clearr the disconnect status.
 599  * @dev:        Reference to pch_udc_regs structure
 600  * @is_active:  Parameter specifying the action
 601  *                0:   indicating VBUS power is ending
 602  *                !0:  indicating VBUS power is starting
 603  */
 604 static inline void pch_udc_vbus_session(struct pch_udc_dev *dev,
 605                                           int is_active)
 606 {
 607         unsigned long           iflags;
 608
 609         spin_lock_irqsave(&dev->lock, iflags);
 610         if (is_active) {
 611                 pch_udc_reconnect(dev);
 612                 dev->vbus_session = 1;
 613         } else {
 614                 if (dev->driver && dev->driver->disconnect) {
 615                         spin_unlock_irqrestore(&dev->lock, iflags);
 616                         dev->driver->disconnect(&dev->gadget);
 617                         spin_lock_irqsave(&dev->lock, iflags);
 618                 }
 619                 pch_udc_set_disconnect(dev);
 620                 dev->vbus_session = 0;
 621         }
 622         spin_unlock_irqrestore(&dev->lock, iflags);
 623 }
 624
 625 /**
 626  * pch_udc_ep_set_stall() - Set the stall of endpoint
 627  * @ep:         Reference to structure of type pch_udc_ep_regs
 628  */
 629 static void pch_udc_ep_set_stall(struct pch_udc_ep *ep)
 630 {
 631         if (ep->in) {
 632                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 633                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 634         } else {
 635                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 636         }
 637 }
 638
 639 /**
 640  * pch_udc_ep_clear_stall() - Clear the stall of endpoint
 641  * @ep:         Reference to structure of type pch_udc_ep_regs
 642  */
 643 static inline void pch_udc_ep_clear_stall(struct pch_udc_ep *ep)
 644 {
 645         /* Clear the stall */
 646         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_S);
 647         /* Clear NAK by writing CNAK */
 648         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 649 }
 650
 651 /**
 652  * pch_udc_ep_set_trfr_type() - Set the transfer type of endpoint
 653  * @ep:         Reference to structure of type pch_udc_ep_regs
 654  * @type:       Type of endpoint
 655  */
 656 static inline void pch_udc_ep_set_trfr_type(struct pch_udc_ep *ep,
 657                                         u8 type)
 658 {
 659         pch_udc_ep_writel(ep, ((type << UDC_EPCTL_ET_SHIFT) &
 660                                 UDC_EPCTL_ET_MASK), UDC_EPCTL_ADDR);
 661 }
 662
 663 /**
 664  * pch_udc_ep_set_bufsz() - Set the maximum packet size for the endpoint
 665  * @ep:         Reference to structure of type pch_udc_ep_regs
 666  * @buf_size:   The buffer word size
 667  */
 668 static void pch_udc_ep_set_bufsz(struct pch_udc_ep *ep,
 669                                                  u32 buf_size, u32 ep_in)
 670 {
 671         u32 data;
 672         if (ep_in) {
 673                 data = pch_udc_ep_readl(ep, UDC_BUFIN_FRAMENUM_ADDR);
 674                 data = (data & 0xffff0000) | (buf_size & 0xffff);
 675                 pch_udc_ep_writel(ep, data, UDC_BUFIN_FRAMENUM_ADDR);
 676         } else {
 677                 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 678                 data = (buf_size << 16) | (data & 0xffff);
 679                 pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 680         }
 681 }
 682
 683 /**
 684  * pch_udc_ep_set_maxpkt() - Set the Max packet size for the endpoint
 685  * @ep:         Reference to structure of type pch_udc_ep_regs
 686  * @pkt_size:   The packet byte size
 687  */
 688 static void pch_udc_ep_set_maxpkt(struct pch_udc_ep *ep, u32 pkt_size)
 689 {
 690         u32 data = pch_udc_ep_readl(ep, UDC_BUFOUT_MAXPKT_ADDR);
 691         data = (data & 0xffff0000) | (pkt_size & 0xffff);
 692         pch_udc_ep_writel(ep, data, UDC_BUFOUT_MAXPKT_ADDR);
 693 }
 694
 695 /**
 696  * pch_udc_ep_set_subptr() - Set the Setup buffer pointer for the endpoint
 697  * @ep:         Reference to structure of type pch_udc_ep_regs
 698  * @addr:       Address of the register
 699  */
 700 static inline void pch_udc_ep_set_subptr(struct pch_udc_ep *ep, u32 addr)
 701 {
 702         pch_udc_ep_writel(ep, addr, UDC_SUBPTR_ADDR);
 703 }
 704
 705 /**
 706  * pch_udc_ep_set_ddptr() - Set the Data descriptor pointer for the endpoint
 707  * @ep:         Reference to structure of type pch_udc_ep_regs
 708  * @addr:       Address of the register
 709  */
 710 static inline void pch_udc_ep_set_ddptr(struct pch_udc_ep *ep, u32 addr)
 711 {
 712         pch_udc_ep_writel(ep, addr, UDC_DESPTR_ADDR);
 713 }
 714
 715 /**
 716  * pch_udc_ep_set_pd() - Set the poll demand bit for the endpoint
 717  * @ep:         Reference to structure of type pch_udc_ep_regs
 718  */
 719 static inline void pch_udc_ep_set_pd(struct pch_udc_ep *ep)
 720 {
 721         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_P);
 722 }
 723
 724 /**
 725  * pch_udc_ep_set_rrdy() - Set the receive ready bit for the endpoint
 726  * @ep:         Reference to structure of type pch_udc_ep_regs
 727  */
 728 static inline void pch_udc_ep_set_rrdy(struct pch_udc_ep *ep)
 729 {
 730         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 731 }
 732
 733 /**
 734  * pch_udc_ep_clear_rrdy() - Clear the receive ready bit for the endpoint
 735  * @ep:         Reference to structure of type pch_udc_ep_regs
 736  */
 737 static inline void pch_udc_ep_clear_rrdy(struct pch_udc_ep *ep)
 738 {
 739         pch_udc_ep_bit_clr(ep, UDC_EPCTL_ADDR, UDC_EPCTL_RRDY);
 740 }
 741
 742 /**
 743  * pch_udc_set_dma() - Set the 'TDE' or RDE bit of device control
 744  *                      register depending on the direction specified
 745  * @dev:        Reference to structure of type pch_udc_regs
 746  * @dir:        whether Tx or Rx
 747  *                DMA_DIR_RX: Receive
 748  *                DMA_DIR_TX: Transmit
 749  */
 750 static inline void pch_udc_set_dma(struct pch_udc_dev *dev, int dir)
 751 {
 752         if (dir == DMA_DIR_RX)
 753                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 754         else if (dir == DMA_DIR_TX)
 755                 pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 756 }
 757
 758 /**
 759  * pch_udc_clear_dma() - Clear the 'TDE' or RDE bit of device control
 760  *                               register depending on the direction specified
 761  * @dev:        Reference to structure of type pch_udc_regs
 762  * @dir:        Whether Tx or Rx
 763  *                DMA_DIR_RX: Receive
 764  *                DMA_DIR_TX: Transmit
 765  */
 766 static inline void pch_udc_clear_dma(struct pch_udc_dev *dev, int dir)
 767 {
 768         if (dir == DMA_DIR_RX)
 769                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_RDE);
 770         else if (dir == DMA_DIR_TX)
 771                 pch_udc_bit_clr(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_TDE);
 772 }
 773
 774 /**
 775  * pch_udc_set_csr_done() - Set the device control register
 776  *                              CSR done field (bit 13)
 777  * @dev:        reference to structure of type pch_udc_regs
 778  */
 779 static inline void pch_udc_set_csr_done(struct pch_udc_dev *dev)
 780 {
 781         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR, UDC_DEVCTL_CSR_DONE);
 782 }
 783
 784 /**
 785  * pch_udc_disable_interrupts() - Disables the specified interrupts
 786  * @dev:        Reference to structure of type pch_udc_regs
 787  * @mask:       Mask to disable interrupts
 788  */
 789 static inline void pch_udc_disable_interrupts(struct pch_udc_dev *dev,
 790                                             u32 mask)
 791 {
 792         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, mask);
 793 }
 794
 795 /**
 796  * pch_udc_enable_interrupts() - Enable the specified interrupts
 797  * @dev:        Reference to structure of type pch_udc_regs
 798  * @mask:       Mask to enable interrupts
 799  */
 800 static inline void pch_udc_enable_interrupts(struct pch_udc_dev *dev,
 801                                            u32 mask)
 802 {
 803         pch_udc_bit_clr(dev, UDC_DEVIRQMSK_ADDR, mask);
 804 }
 805
 806 /**
 807  * pch_udc_disable_ep_interrupts() - Disable endpoint interrupts
 808  * @dev:        Reference to structure of type pch_udc_regs
 809  * @mask:       Mask to disable interrupts
 810  */
 811 static inline void pch_udc_disable_ep_interrupts(struct pch_udc_dev *dev,
 812                                                 u32 mask)
 813 {
 814         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, mask);
 815 }
 816
 817 /**
 818  * pch_udc_enable_ep_interrupts() - Enable endpoint interrupts
 819  * @dev:        Reference to structure of type pch_udc_regs
 820  * @mask:       Mask to enable interrupts
 821  */
 822 static inline void pch_udc_enable_ep_interrupts(struct pch_udc_dev *dev,
 823                                               u32 mask)
 824 {
 825         pch_udc_bit_clr(dev, UDC_EPIRQMSK_ADDR, mask);
 826 }
 827
 828 /**
 829  * pch_udc_read_device_interrupts() - Read the device interrupts
 830  * @dev:        Reference to structure of type pch_udc_regs
 831  * Retern       The device interrupts
 832  */
 833 static inline u32 pch_udc_read_device_interrupts(struct pch_udc_dev *dev)
 834 {
 835         return pch_udc_readl(dev, UDC_DEVIRQSTS_ADDR);
 836 }
 837
 838 /**
 839  * pch_udc_write_device_interrupts() - Write device interrupts
 840  * @dev:        Reference to structure of type pch_udc_regs
 841  * @val:        The value to be written to interrupt register
 842  */
 843 static inline void pch_udc_write_device_interrupts(struct pch_udc_dev *dev,
 844                                                      u32 val)
 845 {
 846         pch_udc_writel(dev, val, UDC_DEVIRQSTS_ADDR);
 847 }
 848
 849 /**
 850  * pch_udc_read_ep_interrupts() - Read the endpoint interrupts
 851  * @dev:        Reference to structure of type pch_udc_regs
 852  * Retern       The endpoint interrupt
 853  */
 854 static inline u32 pch_udc_read_ep_interrupts(struct pch_udc_dev *dev)
 855 {
 856         return pch_udc_readl(dev, UDC_EPIRQSTS_ADDR);
 857 }
 858
 859 /**
 860  * pch_udc_write_ep_interrupts() - Clear endpoint interupts
 861  * @dev:        Reference to structure of type pch_udc_regs
 862  * @val:        The value to be written to interrupt register
 863  */
 864 static inline void pch_udc_write_ep_interrupts(struct pch_udc_dev *dev,
 865                                              u32 val)
 866 {
 867         pch_udc_writel(dev, val, UDC_EPIRQSTS_ADDR);
 868 }
 869
 870 /**
 871  * pch_udc_read_device_status() - Read the device status
 872  * @dev:        Reference to structure of type pch_udc_regs
 873  * Retern       The device status
 874  */
 875 static inline u32 pch_udc_read_device_status(struct pch_udc_dev *dev)
 876 {
 877         return pch_udc_readl(dev, UDC_DEVSTS_ADDR);
 878 }
 879
 880 /**
 881  * pch_udc_read_ep_control() - Read the endpoint control
 882  * @ep:         Reference to structure of type pch_udc_ep_regs
 883  * Retern       The endpoint control register value
 884  */
 885 static inline u32 pch_udc_read_ep_control(struct pch_udc_ep *ep)
 886 {
 887         return pch_udc_ep_readl(ep, UDC_EPCTL_ADDR);
 888 }
 889
 890 /**
 891  * pch_udc_clear_ep_control() - Clear the endpoint control register
 892  * @ep:         Reference to structure of type pch_udc_ep_regs
 893  * Retern       The endpoint control register value
 894  */
 895 static inline void pch_udc_clear_ep_control(struct pch_udc_ep *ep)
 896 {
 897         return pch_udc_ep_writel(ep, 0, UDC_EPCTL_ADDR);
 898 }
 899
 900 /**
 901  * pch_udc_read_ep_status() - Read the endpoint status
 902  * @ep:         Reference to structure of type pch_udc_ep_regs
 903  * Retern       The endpoint status
 904  */
 905 static inline u32 pch_udc_read_ep_status(struct pch_udc_ep *ep)
 906 {
 907         return pch_udc_ep_readl(ep, UDC_EPSTS_ADDR);
 908 }
 909
 910 /**
 911  * pch_udc_clear_ep_status() - Clear the endpoint status
 912  * @ep:         Reference to structure of type pch_udc_ep_regs
 913  * @stat:       Endpoint status
 914  */
 915 static inline void pch_udc_clear_ep_status(struct pch_udc_ep *ep,
 916                                          u32 stat)
 917 {
 918         return pch_udc_ep_writel(ep, stat, UDC_EPSTS_ADDR);
 919 }
 920
 921 /**
 922  * pch_udc_ep_set_nak() - Set the bit 7 (SNAK field)
 923  *                              of the endpoint control register
 924  * @ep:         Reference to structure of type pch_udc_ep_regs
 925  */
 926 static inline void pch_udc_ep_set_nak(struct pch_udc_ep *ep)
 927 {
 928         pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_SNAK);
 929 }
 930
 931 /**
 932  * pch_udc_ep_clear_nak() - Set the bit 8 (CNAK field)
 933  *                              of the endpoint control register
 934  * @ep:         reference to structure of type pch_udc_ep_regs
 935  */
 936 static void pch_udc_ep_clear_nak(struct pch_udc_ep *ep)
 937 {
 938         unsigned int loopcnt = 0;
 939         struct pch_udc_dev *dev = ep->dev;
 940
 941         if (!(pch_udc_ep_readl(ep, UDC_EPCTL_ADDR) & UDC_EPCTL_NAK))
 942                 return;
 943         if (!ep->in) {
 944                 loopcnt = 10000;
 945                 while (!(pch_udc_read_ep_status(ep) & UDC_EPSTS_MRXFIFO_EMP) &&
 946                         --loopcnt)
 947                         udelay(5);
 948                 if (!loopcnt)
 949                         dev_err(&dev->pdev->dev, "%s: RxFIFO not Empty\n",
 950                                 __func__);
 951         }
 952         loopcnt = 10000;
 953         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_NAK) && --loopcnt) {
 954                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_CNAK);
 955                 udelay(5);
 956         }
 957         if (!loopcnt)
 958                 dev_err(&dev->pdev->dev, "%s: Clear NAK not set for ep%d%s\n",
 959                         __func__, ep->num, (ep->in ? "in" : "out"));
 960 }
 961
 962 /**
 963  * pch_udc_ep_fifo_flush() - Flush the endpoint fifo
 964  * @ep: reference to structure of type pch_udc_ep_regs
 965  * @dir:        direction of endpoint
 966  *                0:  endpoint is OUT
 967  *                !0: endpoint is IN
 968  */
 969 static void pch_udc_ep_fifo_flush(struct pch_udc_ep *ep, int dir)
 970 {
 971         if (dir) {      /* IN ep */
 972                 pch_udc_ep_bit_set(ep, UDC_EPCTL_ADDR, UDC_EPCTL_F);
 973                 return;
 974         }
 975 }
 976
 977 /**
 978  * pch_udc_ep_enable() - This api enables endpoint
 979  * @regs:       Reference to structure pch_udc_ep_regs
 980  * @desc:       endpoint descriptor
 981  */
 982 static void pch_udc_ep_enable(struct pch_udc_ep *ep,
 983                                struct pch_udc_cfg_data *cfg,
 984                                const struct usb_endpoint_descriptor *desc)
 985 {
 986         u32 val = 0;
 987         u32 buff_size = 0;
 988
 989         pch_udc_ep_set_trfr_type(ep, desc->bmAttributes);
 990         if (ep->in)
 991                 buff_size = UDC_EPIN_BUFF_SIZE;
 992         else
 993                 buff_size = UDC_EPOUT_BUFF_SIZE;
 994         pch_udc_ep_set_bufsz(ep, buff_size, ep->in);
 995         pch_udc_ep_set_maxpkt(ep, usb_endpoint_maxp(desc));
 996         pch_udc_ep_set_nak(ep);
 997         pch_udc_ep_fifo_flush(ep, ep->in);
 998         /* Configure the endpoint */
 999         val = ep->num << UDC_CSR_NE_NUM_SHIFT | ep->in << UDC_CSR_NE_DIR_SHIFT |
1000               ((desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) <<
1001                 UDC_CSR_NE_TYPE_SHIFT) |
1002               (cfg->cur_cfg << UDC_CSR_NE_CFG_SHIFT) |
1003               (cfg->cur_intf << UDC_CSR_NE_INTF_SHIFT) |
1004               (cfg->cur_alt << UDC_CSR_NE_ALT_SHIFT) |
1005               usb_endpoint_maxp(desc) << UDC_CSR_NE_MAX_PKT_SHIFT;
1006
1007         if (ep->in)
1008                 pch_udc_write_csr(ep->dev, val, UDC_EPIN_IDX(ep->num));
1009         else
1010                 pch_udc_write_csr(ep->dev, val, UDC_EPOUT_IDX(ep->num));
1011 }
1012
1013 /**
1014  * pch_udc_ep_disable() - This api disables endpoint
1015  * @regs:       Reference to structure pch_udc_ep_regs
1016  */
1017 static void pch_udc_ep_disable(struct pch_udc_ep *ep)
1018 {
1019         if (ep->in) {
1020                 /* flush the fifo */
1021                 pch_udc_ep_writel(ep, UDC_EPCTL_F, UDC_EPCTL_ADDR);
1022                 /* set NAK */
1023                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1024                 pch_udc_ep_bit_set(ep, UDC_EPSTS_ADDR, UDC_EPSTS_IN);
1025         } else {
1026                 /* set NAK */
1027                 pch_udc_ep_writel(ep, UDC_EPCTL_SNAK, UDC_EPCTL_ADDR);
1028         }
1029         /* reset desc pointer */
1030         pch_udc_ep_writel(ep, 0, UDC_DESPTR_ADDR);
1031 }
1032
1033 /**
1034  * pch_udc_wait_ep_stall() - Wait EP stall.
1035  * @dev:        Reference to pch_udc_dev structure
1036  */
1037 static void pch_udc_wait_ep_stall(struct pch_udc_ep *ep)
1038 {
1039         unsigned int count = 10000;
1040
1041         /* Wait till idle */
1042         while ((pch_udc_read_ep_control(ep) & UDC_EPCTL_S) && --count)
1043                 udelay(5);
1044         if (!count)
1045                 dev_err(&ep->dev->pdev->dev, "%s: wait error\n", __func__);
1046 }
1047
1048 /**
1049  * pch_udc_init() - This API initializes usb device controller
1050  * @dev:        Rreference to pch_udc_regs structure
1051  */
1052 static void pch_udc_init(struct pch_udc_dev *dev)
1053 {
1054         if (NULL == dev) {
1055                 pr_err("%s: Invalid address\n", __func__);
1056                 return;
1057         }
1058         /* Soft Reset and Reset PHY */
1059         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1060         pch_udc_writel(dev, UDC_SRST | UDC_PSRST, UDC_SRST_ADDR);
1061         mdelay(1);
1062         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
1063         pch_udc_writel(dev, 0x00, UDC_SRST_ADDR);
1064         mdelay(1);
1065         /* mask and clear all device interrupts */
1066         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1067         pch_udc_bit_set(dev, UDC_DEVIRQSTS_ADDR, UDC_DEVINT_MSK);
1068
1069         /* mask and clear all ep interrupts */
1070         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1071         pch_udc_bit_set(dev, UDC_EPIRQSTS_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1072
1073         /* enable dynamic CSR programmingi, self powered and device speed */
1074         if (speed_fs)
1075                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1076                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_FS);
1077         else /* defaul high speed */
1078                 pch_udc_bit_set(dev, UDC_DEVCFG_ADDR, UDC_DEVCFG_CSR_PRG |
1079                                 UDC_DEVCFG_SP | UDC_DEVCFG_SPD_HS);
1080         pch_udc_bit_set(dev, UDC_DEVCTL_ADDR,
1081                         (PCH_UDC_THLEN << UDC_DEVCTL_THLEN_SHIFT) |
1082                         (PCH_UDC_BRLEN << UDC_DEVCTL_BRLEN_SHIFT) |
1083                         UDC_DEVCTL_MODE | UDC_DEVCTL_BREN |
1084                         UDC_DEVCTL_THE);
1085 }
1086
1087 /**
1088  * pch_udc_exit() - This API exit usb device controller
1089  * @dev:        Reference to pch_udc_regs structure
1090  */
1091 static void pch_udc_exit(struct pch_udc_dev *dev)
1092 {
1093         /* mask all device interrupts */
1094         pch_udc_bit_set(dev, UDC_DEVIRQMSK_ADDR, UDC_DEVINT_MSK);
1095         /* mask all ep interrupts */
1096         pch_udc_bit_set(dev, UDC_EPIRQMSK_ADDR, UDC_EPINT_MSK_DISABLE_ALL);
1097         /* put device in disconnected state */
1098         pch_udc_set_disconnect(dev);
1099 }
1100
1101 /**
1102  * pch_udc_pcd_get_frame() - This API is invoked to get the current frame number
1103  * @gadget:     Reference to the gadget driver
1104  *
1105  * Return codes:
1106  *      0:              Success
1107  *      -EINVAL:        If the gadget passed is NULL
1108  */
1109 static int pch_udc_pcd_get_frame(struct usb_gadget *gadget)
1110 {
1111         struct pch_udc_dev      *dev;
1112
1113         if (!gadget)
1114                 return -EINVAL;
1115         dev = container_of(gadget, struct pch_udc_dev, gadget);
1116         return pch_udc_get_frame(dev);
1117 }
1118
1119 /**
1120  * pch_udc_pcd_wakeup() - This API is invoked to initiate a remote wakeup
1121  * @gadget:     Reference to the gadget driver
1122  *
1123  * Return codes:
1124  *      0:              Success
1125  *      -EINVAL:        If the gadget passed is NULL
1126  */
1127 static int pch_udc_pcd_wakeup(struct usb_gadget *gadget)
1128 {
1129         struct pch_udc_dev      *dev;
1130         unsigned long           flags;
1131
1132         if (!gadget)
1133                 return -EINVAL;
1134         dev = container_of(gadget, struct pch_udc_dev, gadget);
1135         spin_lock_irqsave(&dev->lock, flags);
1136         pch_udc_rmt_wakeup(dev);
1137         spin_unlock_irqrestore(&dev->lock, flags);
1138         return 0;
1139 }
1140
1141 /**
1142  * pch_udc_pcd_selfpowered() - This API is invoked to specify whether the device
1143  *                              is self powered or not
1144  * @gadget:     Reference to the gadget driver
1145  * @value:      Specifies self powered or not
1146  *
1147  * Return codes:
1148  *      0:              Success
1149  *      -EINVAL:        If the gadget passed is NULL
1150  */
1151 static int pch_udc_pcd_selfpowered(struct usb_gadget *gadget, int value)
1152 {
1153         struct pch_udc_dev      *dev;
1154
1155         if (!gadget)
1156                 return -EINVAL;
1157         gadget->is_selfpowered = (value != 0);
1158         dev = container_of(gadget, struct pch_udc_dev, gadget);
1159         if (value)
1160                 pch_udc_set_selfpowered(dev);
1161         else
1162                 pch_udc_clear_selfpowered(dev);
1163         return 0;
1164 }
1165
1166 /**
1167  * pch_udc_pcd_pullup() - This API is invoked to make the device
1168  *                              visible/invisible to the host
1169  * @gadget:     Reference to the gadget driver
1170  * @is_on:      Specifies whether the pull up is made active or inactive
1171  *
1172  * Return codes:
1173  *      0:              Success
1174  *      -EINVAL:        If the gadget passed is NULL
1175  */
1176 static int pch_udc_pcd_pullup(struct usb_gadget *gadget, int is_on)
1177 {
1178         struct pch_udc_dev      *dev;
1179         unsigned long           iflags;
1180
1181         if (!gadget)
1182                 return -EINVAL;
1183
1184         dev = container_of(gadget, struct pch_udc_dev, gadget);
1185
1186         spin_lock_irqsave(&dev->lock, iflags);
1187         if (is_on) {
1188                 pch_udc_reconnect(dev);
1189         } else {
1190                 if (dev->driver && dev->driver->disconnect) {
1191                         spin_unlock_irqrestore(&dev->lock, iflags);
1192                         dev->driver->disconnect(&dev->gadget);
1193                         spin_lock_irqsave(&dev->lock, iflags);
1194                 }
1195                 pch_udc_set_disconnect(dev);
1196         }
1197         spin_unlock_irqrestore(&dev->lock, iflags);
1198
1199         return 0;
1200 }
1201
1202 /**
1203  * pch_udc_pcd_vbus_session() - This API is used by a driver for an external
1204  *                              transceiver (or GPIO) that
1205  *                              detects a VBUS power session starting/ending
1206  * @gadget:     Reference to the gadget driver
1207  * @is_active:  specifies whether the session is starting or ending
1208  *
1209  * Return codes:
1210  *      0:              Success
1211  *      -EINVAL:        If the gadget passed is NULL
1212  */
1213 static int pch_udc_pcd_vbus_session(struct usb_gadget *gadget, int is_active)
1214 {
1215         struct pch_udc_dev      *dev;
1216
1217         if (!gadget)
1218                 return -EINVAL;
1219         dev = container_of(gadget, struct pch_udc_dev, gadget);
1220         pch_udc_vbus_session(dev, is_active);
1221         return 0;
1222 }
1223
1224 /**
1225  * pch_udc_pcd_vbus_draw() - This API is used by gadget drivers during
1226  *                              SET_CONFIGURATION calls to
1227  *                              specify how much power the device can consume
1228  * @gadget:     Reference to the gadget driver
1229  * @mA:         specifies the current limit in 2mA unit
1230  *
1231  * Return codes:
1232  *      -EINVAL:        If the gadget passed is NULL
1233  *      -EOPNOTSUPP:
1234  */
1235 static int pch_udc_pcd_vbus_draw(struct usb_gadget *gadget, unsigned int mA)
1236 {
1237         return -EOPNOTSUPP;
1238 }
1239
1240 static int pch_udc_start(struct usb_gadget *g,
1241                 struct usb_gadget_driver *driver);
1242 static int pch_udc_stop(struct usb_gadget *g);
1243
1244 static const struct usb_gadget_ops pch_udc_ops = {
1245         .get_frame = pch_udc_pcd_get_frame,
1246         .wakeup = pch_udc_pcd_wakeup,
1247         .set_selfpowered = pch_udc_pcd_selfpowered,
1248         .pullup = pch_udc_pcd_pullup,
1249         .vbus_session = pch_udc_pcd_vbus_session,
1250         .vbus_draw = pch_udc_pcd_vbus_draw,
1251         .udc_start = pch_udc_start,
1252         .udc_stop = pch_udc_stop,
1253 };
1254
1255 /**
1256  * pch_vbus_gpio_get_value() - This API gets value of GPIO port as VBUS status.
1257  * @dev:        Reference to the driver structure
1258  *
1259  * Return value:
1260  *      1: VBUS is high
1261  *      0: VBUS is low
1262  *     -1: It is not enable to detect VBUS using GPIO
1263  */
1264 static int pch_vbus_gpio_get_value(struct pch_udc_dev *dev)
1265 {
1266         int vbus = 0;
1267
1268         if (dev->vbus_gpio.port)
1269                 vbus = gpio_get_value(dev->vbus_gpio.port) ? 1 : 0;
1270         else
1271                 vbus = -1;
1272
1273         return vbus;
1274 }
1275
1276 /**
1277  * pch_vbus_gpio_work_fall() - This API keeps watch on VBUS becoming Low.
1278  *                             If VBUS is Low, disconnect is processed
1279  * @irq_work:   Structure for WorkQueue
1280  *
1281  */
1282 static void pch_vbus_gpio_work_fall(struct work_struct *irq_work)
1283 {
1284         struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1285                 struct pch_vbus_gpio_data, irq_work_fall);
1286         struct pch_udc_dev *dev =
1287                 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1288         int vbus_saved = -1;
1289         int vbus;
1290         int count;
1291
1292         if (!dev->vbus_gpio.port)
1293                 return;
1294
1295         for (count = 0; count < (PCH_VBUS_PERIOD / PCH_VBUS_INTERVAL);
1296                 count++) {
1297                 vbus = pch_vbus_gpio_get_value(dev);
1298
1299                 if ((vbus_saved == vbus) && (vbus == 0)) {
1300                         dev_dbg(&dev->pdev->dev, "VBUS fell");
1301                         if (dev->driver
1302                                 && dev->driver->disconnect) {
1303                                 dev->driver->disconnect(
1304                                         &dev->gadget);
1305                         }
1306                         if (dev->vbus_gpio.intr)
1307                                 pch_udc_init(dev);
1308                         else
1309                                 pch_udc_reconnect(dev);
1310                         return;
1311                 }
1312                 vbus_saved = vbus;
1313                 mdelay(PCH_VBUS_INTERVAL);
1314         }
1315 }
1316
1317 /**
1318  * pch_vbus_gpio_work_rise() - This API checks VBUS is High.
1319  *                             If VBUS is High, connect is processed
1320  * @irq_work:   Structure for WorkQueue
1321  *
1322  */
1323 static void pch_vbus_gpio_work_rise(struct work_struct *irq_work)
1324 {
1325         struct pch_vbus_gpio_data *vbus_gpio = container_of(irq_work,
1326                 struct pch_vbus_gpio_data, irq_work_rise);
1327         struct pch_udc_dev *dev =
1328                 container_of(vbus_gpio, struct pch_udc_dev, vbus_gpio);
1329         int vbus;
1330
1331         if (!dev->vbus_gpio.port)
1332                 return;
1333
1334         mdelay(PCH_VBUS_INTERVAL);
1335         vbus = pch_vbus_gpio_get_value(dev);
1336
1337         if (vbus == 1) {
1338                 dev_dbg(&dev->pdev->dev, "VBUS rose");
1339                 pch_udc_reconnect(dev);
1340                 return;
1341         }
1342 }
1343
1344 /**
1345  * pch_vbus_gpio_irq() - IRQ handler for GPIO intrerrupt for changing VBUS
1346  * @irq:        Interrupt request number
1347  * @dev:        Reference to the device structure
1348  *
1349  * Return codes:
1350  *      0: Success
1351  *      -EINVAL: GPIO port is invalid or can't be initialized.
1352  */
1353 static irqreturn_t pch_vbus_gpio_irq(int irq, void *data)
1354 {
1355         struct pch_udc_dev *dev = (struct pch_udc_dev *)data;
1356
1357         if (!dev->vbus_gpio.port || !dev->vbus_gpio.intr)
1358                 return IRQ_NONE;
1359
1360         if (pch_vbus_gpio_get_value(dev))
1361                 schedule_work(&dev->vbus_gpio.irq_work_rise);
1362         else
1363                 schedule_work(&dev->vbus_gpio.irq_work_fall);
1364
1365         return IRQ_HANDLED;
1366 }
1367
1368 /**
1369  * pch_vbus_gpio_init() - This API initializes GPIO port detecting VBUS.
1370  * @dev:        Reference to the driver structure
1371  * @vbus_gpio   Number of GPIO port to detect gpio
1372  *
1373  * Return codes:
1374  *      0: Success
1375  *      -EINVAL: GPIO port is invalid or can't be initialized.
1376  */
1377 static int pch_vbus_gpio_init(struct pch_udc_dev *dev, int vbus_gpio_port)
1378 {
1379         int err;
1380         int irq_num = 0;
1381
1382         dev->vbus_gpio.port = 0;
1383         dev->vbus_gpio.intr = 0;
1384
1385         if (vbus_gpio_port <= -1)
1386                 return -EINVAL;
1387
1388         err = gpio_is_valid(vbus_gpio_port);
1389         if (!err) {
1390                 pr_err("%s: gpio port %d is invalid\n",
1391                         __func__, vbus_gpio_port);
1392                 return -EINVAL;
1393         }
1394
1395         err = gpio_request(vbus_gpio_port, "pch_vbus");
1396         if (err) {
1397                 pr_err("%s: can't request gpio port %d, err: %d\n",
1398                         __func__, vbus_gpio_port, err);
1399                 return -EINVAL;
1400         }
1401
1402         dev->vbus_gpio.port = vbus_gpio_port;
1403         gpio_direction_input(vbus_gpio_port);
1404         INIT_WORK(&dev->vbus_gpio.irq_work_fall, pch_vbus_gpio_work_fall);
1405
1406         irq_num = gpio_to_irq(vbus_gpio_port);
1407         if (irq_num > 0) {
1408                 irq_set_irq_type(irq_num, IRQ_TYPE_EDGE_BOTH);
1409                 err = request_irq(irq_num, pch_vbus_gpio_irq, 0,
1410                         "vbus_detect", dev);
1411                 if (!err) {
1412                         dev->vbus_gpio.intr = irq_num;
1413                         INIT_WORK(&dev->vbus_gpio.irq_work_rise,
1414                                 pch_vbus_gpio_work_rise);
1415                 } else {
1416                         pr_err("%s: can't request irq %d, err: %d\n",
1417                                 __func__, irq_num, err);
1418                 }
1419         }
1420
1421         return 0;
1422 }
1423
1424 /**
1425  * pch_vbus_gpio_free() - This API frees resources of GPIO port
1426  * @dev:        Reference to the driver structure
1427  */
1428 static void pch_vbus_gpio_free(struct pch_udc_dev *dev)
1429 {
1430         if (dev->vbus_gpio.intr)
1431                 free_irq(dev->vbus_gpio.intr, dev);
1432
1433         if (dev->vbus_gpio.port)
1434                 gpio_free(dev->vbus_gpio.port);
1435 }
1436
1437 /**
1438  * complete_req() - This API is invoked from the driver when processing
1439  *                      of a request is complete
1440  * @ep:         Reference to the endpoint structure
1441  * @req:        Reference to the request structure
1442  * @status:     Indicates the success/failure of completion
1443  */
1444 static void complete_req(struct pch_udc_ep *ep, struct pch_udc_request *req,
1445                                                                  int status)
1446         __releases(&dev->lock)
1447         __acquires(&dev->lock)
1448 {
1449         struct pch_udc_dev      *dev;
1450         unsigned halted = ep->halted;
1451
1452         list_del_init(&req->queue);
1453
1454         /* set new status if pending */
1455         if (req->req.status == -EINPROGRESS)
1456                 req->req.status = status;
1457         else
1458                 status = req->req.status;
1459
1460         dev = ep->dev;
1461         if (req->dma_mapped) {
1462                 if (req->dma == DMA_ADDR_INVALID) {
1463                         if (ep->in)
1464                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1465                                                  req->req.length,
1466                                                  DMA_TO_DEVICE);
1467                         else
1468                                 dma_unmap_single(&dev->pdev->dev, req->req.dma,
1469                                                  req->req.length,
1470                                                  DMA_FROM_DEVICE);
1471                         req->req.dma = DMA_ADDR_INVALID;
1472                 } else {
1473                         if (ep->in)
1474                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1475                                                  req->req.length,
1476                                                  DMA_TO_DEVICE);
1477                         else {
1478                                 dma_unmap_single(&dev->pdev->dev, req->dma,
1479                                                  req->req.length,
1480                                                  DMA_FROM_DEVICE);
1481                                 memcpy(req->req.buf, req->buf, req->req.length);
1482                         }
1483                         kfree(req->buf);
1484                         req->dma = DMA_ADDR_INVALID;
1485                 }
1486                 req->dma_mapped = 0;
1487         }
1488         ep->halted = 1;
1489         spin_unlock(&dev->lock);
1490         if (!ep->in)
1491                 pch_udc_ep_clear_rrdy(ep);
1492         usb_gadget_giveback_request(&ep->ep, &req->req);
1493         spin_lock(&dev->lock);
1494         ep->halted = halted;
1495 }
1496
1497 /**
1498  * empty_req_queue() - This API empties the request queue of an endpoint
1499  * @ep:         Reference to the endpoint structure
1500  */
1501 static void empty_req_queue(struct pch_udc_ep *ep)
1502 {
1503         struct pch_udc_request  *req;
1504
1505         ep->halted = 1;
1506         while (!list_empty(&ep->queue)) {
1507                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
1508                 complete_req(ep, req, -ESHUTDOWN);      /* Remove from list */
1509         }
1510 }
1511
1512 /**
1513  * pch_udc_free_dma_chain() - This function frees the DMA chain created
1514  *                              for the request
1515  * @dev         Reference to the driver structure
1516  * @req         Reference to the request to be freed
1517  *
1518  * Return codes:
1519  *      0: Success
1520  */
1521 static void pch_udc_free_dma_chain(struct pch_udc_dev *dev,
1522                                    struct pch_udc_request *req)
1523 {
1524         struct pch_udc_data_dma_desc *td = req->td_data;
1525         unsigned i = req->chain_len;
1526
1527         dma_addr_t addr2;
1528         dma_addr_t addr = (dma_addr_t)td->next;
1529         td->next = 0x00;
1530         for (; i > 1; --i) {
1531                 /* do not free first desc., will be done by free for request */
1532                 td = phys_to_virt(addr);
1533                 addr2 = (dma_addr_t)td->next;
1534                 dma_pool_free(dev->data_requests, td, addr);
1535                 addr = addr2;
1536         }
1537         req->chain_len = 1;
1538 }
1539
1540 /**
1541  * pch_udc_create_dma_chain() - This function creates or reinitializes
1542  *                              a DMA chain
1543  * @ep:         Reference to the endpoint structure
1544  * @req:        Reference to the request
1545  * @buf_len:    The buffer length
1546  * @gfp_flags:  Flags to be used while mapping the data buffer
1547  *
1548  * Return codes:
1549  *      0:              success,
1550  *      -ENOMEM:        dma_pool_alloc invocation fails
1551  */
1552 static int pch_udc_create_dma_chain(struct pch_udc_ep *ep,
1553                                     struct pch_udc_request *req,
1554                                     unsigned long buf_len,
1555                                     gfp_t gfp_flags)
1556 {
1557         struct pch_udc_data_dma_desc *td = req->td_data, *last;
1558         unsigned long bytes = req->req.length, i = 0;
1559         dma_addr_t dma_addr;
1560         unsigned len = 1;
1561
1562         if (req->chain_len > 1)
1563                 pch_udc_free_dma_chain(ep->dev, req);
1564
1565         if (req->dma == DMA_ADDR_INVALID)
1566                 td->dataptr = req->req.dma;
1567         else
1568                 td->dataptr = req->dma;
1569
1570         td->status = PCH_UDC_BS_HST_BSY;
1571         for (; ; bytes -= buf_len, ++len) {
1572                 td->status = PCH_UDC_BS_HST_BSY | min(buf_len, bytes);
1573                 if (bytes <= buf_len)
1574                         break;
1575                 last = td;
1576                 td = dma_pool_alloc(ep->dev->data_requests, gfp_flags,
1577                                     &dma_addr);
1578                 if (!td)
1579                         goto nomem;
1580                 i += buf_len;
1581                 td->dataptr = req->td_data->dataptr + i;
1582                 last->next = dma_addr;
1583         }
1584
1585         req->td_data_last = td;
1586         td->status |= PCH_UDC_DMA_LAST;
1587         td->next = req->td_data_phys;
1588         req->chain_len = len;
1589         return 0;
1590
1591 nomem:
1592         if (len > 1) {
1593                 req->chain_len = len;
1594                 pch_udc_free_dma_chain(ep->dev, req);
1595         }
1596         req->chain_len = 1;
1597         return -ENOMEM;
1598 }
1599
1600 /**
1601  * prepare_dma() - This function creates and initializes the DMA chain
1602  *                      for the request
1603  * @ep:         Reference to the endpoint structure
1604  * @req:        Reference to the request
1605  * @gfp:        Flag to be used while mapping the data buffer
1606  *
1607  * Return codes:
1608  *      0:              Success
1609  *      Other 0:        linux error number on failure
1610  */
1611 static int prepare_dma(struct pch_udc_ep *ep, struct pch_udc_request *req,
1612                           gfp_t gfp)
1613 {
1614         int     retval;
1615
1616         /* Allocate and create a DMA chain */
1617         retval = pch_udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
1618         if (retval) {
1619                 pr_err("%s: could not create DMA chain:%d\n", __func__, retval);
1620                 return retval;
1621         }
1622         if (ep->in)
1623                 req->td_data->status = (req->td_data->status &
1624                                 ~PCH_UDC_BUFF_STS) | PCH_UDC_BS_HST_RDY;
1625         return 0;
1626 }
1627
1628 /**
1629  * process_zlp() - This function process zero length packets
1630  *                      from the gadget driver
1631  * @ep:         Reference to the endpoint structure
1632  * @req:        Reference to the request
1633  */
1634 static void process_zlp(struct pch_udc_ep *ep, struct pch_udc_request *req)
1635 {
1636         struct pch_udc_dev      *dev = ep->dev;
1637
1638         /* IN zlp's are handled by hardware */
1639         complete_req(ep, req, 0);
1640
1641         /* if set_config or set_intf is waiting for ack by zlp
1642          * then set CSR_DONE
1643          */
1644         if (dev->set_cfg_not_acked) {
1645                 pch_udc_set_csr_done(dev);
1646                 dev->set_cfg_not_acked = 0;
1647         }
1648         /* setup command is ACK'ed now by zlp */
1649         if (!dev->stall && dev->waiting_zlp_ack) {
1650                 pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
1651                 dev->waiting_zlp_ack = 0;
1652         }
1653 }
1654
1655 /**
1656  * pch_udc_start_rxrequest() - This function starts the receive requirement.
1657  * @ep:         Reference to the endpoint structure
1658  * @req:        Reference to the request structure
1659  */
1660 static void pch_udc_start_rxrequest(struct pch_udc_ep *ep,
1661                                          struct pch_udc_request *req)
1662 {
1663         struct pch_udc_data_dma_desc *td_data;
1664
1665         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
1666         td_data = req->td_data;
1667         /* Set the status bits for all descriptors */
1668         while (1) {
1669                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
1670                                     PCH_UDC_BS_HST_RDY;
1671                 if ((td_data->status & PCH_UDC_DMA_LAST) ==  PCH_UDC_DMA_LAST)
1672                         break;
1673                 td_data = phys_to_virt(td_data->next);
1674         }
1675         /* Write the descriptor pointer */
1676         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
1677         req->dma_going = 1;
1678         pch_udc_enable_ep_interrupts(ep->dev, UDC_EPINT_OUT_EP0 << ep->num);
1679         pch_udc_set_dma(ep->dev, DMA_DIR_RX);
1680         pch_udc_ep_clear_nak(ep);
1681         pch_udc_ep_set_rrdy(ep);
1682 }
1683
1684 /**
1685  * pch_udc_pcd_ep_enable() - This API enables the endpoint. It is called
1686  *                              from gadget driver
1687  * @usbep:      Reference to the USB endpoint structure
1688  * @desc:       Reference to the USB endpoint descriptor structure
1689  *
1690  * Return codes:
1691  *      0:              Success
1692  *      -EINVAL:
1693  *      -ESHUTDOWN:
1694  */
1695 static int pch_udc_pcd_ep_enable(struct usb_ep *usbep,
1696                                     const struct usb_endpoint_descriptor *desc)
1697 {
1698         struct pch_udc_ep       *ep;
1699         struct pch_udc_dev      *dev;
1700         unsigned long           iflags;
1701
1702         if (!usbep || (usbep->name == ep0_string) || !desc ||
1703             (desc->bDescriptorType != USB_DT_ENDPOINT) || !desc->wMaxPacketSize)
1704                 return -EINVAL;
1705
1706         ep = container_of(usbep, struct pch_udc_ep, ep);
1707         dev = ep->dev;
1708         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1709                 return -ESHUTDOWN;
1710         spin_lock_irqsave(&dev->lock, iflags);
1711         ep->ep.desc = desc;
1712         ep->halted = 0;
1713         pch_udc_ep_enable(ep, &ep->dev->cfg_data, desc);
1714         ep->ep.maxpacket = usb_endpoint_maxp(desc);
1715         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1716         spin_unlock_irqrestore(&dev->lock, iflags);
1717         return 0;
1718 }
1719
1720 /**
1721  * pch_udc_pcd_ep_disable() - This API disables endpoint and is called
1722  *                              from gadget driver
1723  * @usbep       Reference to the USB endpoint structure
1724  *
1725  * Return codes:
1726  *      0:              Success
1727  *      -EINVAL:
1728  */
1729 static int pch_udc_pcd_ep_disable(struct usb_ep *usbep)
1730 {
1731         struct pch_udc_ep       *ep;
1732         unsigned long   iflags;
1733
1734         if (!usbep)
1735                 return -EINVAL;
1736
1737         ep = container_of(usbep, struct pch_udc_ep, ep);
1738         if ((usbep->name == ep0_string) || !ep->ep.desc)
1739                 return -EINVAL;
1740
1741         spin_lock_irqsave(&ep->dev->lock, iflags);
1742         empty_req_queue(ep);
1743         ep->halted = 1;
1744         pch_udc_ep_disable(ep);
1745         pch_udc_disable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1746         ep->ep.desc = NULL;
1747         INIT_LIST_HEAD(&ep->queue);
1748         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1749         return 0;
1750 }
1751
1752 /**
1753  * pch_udc_alloc_request() - This function allocates request structure.
1754  *                              It is called by gadget driver
1755  * @usbep:      Reference to the USB endpoint structure
1756  * @gfp:        Flag to be used while allocating memory
1757  *
1758  * Return codes:
1759  *      NULL:                   Failure
1760  *      Allocated address:      Success
1761  */
1762 static struct usb_request *pch_udc_alloc_request(struct usb_ep *usbep,
1763                                                   gfp_t gfp)
1764 {
1765         struct pch_udc_request          *req;
1766         struct pch_udc_ep               *ep;
1767         struct pch_udc_data_dma_desc    *dma_desc;
1768
1769         if (!usbep)
1770                 return NULL;
1771         ep = container_of(usbep, struct pch_udc_ep, ep);
1772         req = kzalloc(sizeof *req, gfp);
1773         if (!req)
1774                 return NULL;
1775         req->req.dma = DMA_ADDR_INVALID;
1776         req->dma = DMA_ADDR_INVALID;
1777         INIT_LIST_HEAD(&req->queue);
1778         if (!ep->dev->dma_addr)
1779                 return &req->req;
1780         /* ep0 in requests are allocated from data pool here */
1781         dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
1782                                   &req->td_data_phys);
1783         if (NULL == dma_desc) {
1784                 kfree(req);
1785                 return NULL;
1786         }
1787         /* prevent from using desc. - set HOST BUSY */
1788         dma_desc->status |= PCH_UDC_BS_HST_BSY;
1789         dma_desc->dataptr = lower_32_bits(DMA_ADDR_INVALID);
1790         req->td_data = dma_desc;
1791         req->td_data_last = dma_desc;
1792         req->chain_len = 1;
1793         return &req->req;
1794 }
1795
1796 /**
1797  * pch_udc_free_request() - This function frees request structure.
1798  *                              It is called by gadget driver
1799  * @usbep:      Reference to the USB endpoint structure
1800  * @usbreq:     Reference to the USB request
1801  */
1802 static void pch_udc_free_request(struct usb_ep *usbep,
1803                                   struct usb_request *usbreq)
1804 {
1805         struct pch_udc_ep       *ep;
1806         struct pch_udc_request  *req;
1807         struct pch_udc_dev      *dev;
1808
1809         if (!usbep || !usbreq)
1810                 return;
1811         ep = container_of(usbep, struct pch_udc_ep, ep);
1812         req = container_of(usbreq, struct pch_udc_request, req);
1813         dev = ep->dev;
1814         if (!list_empty(&req->queue))
1815                 dev_err(&dev->pdev->dev, "%s: %s req=0x%p queue not empty\n",
1816                         __func__, usbep->name, req);
1817         if (req->td_data != NULL) {
1818                 if (req->chain_len > 1)
1819                         pch_udc_free_dma_chain(ep->dev, req);
1820                 dma_pool_free(ep->dev->data_requests, req->td_data,
1821                               req->td_data_phys);
1822         }
1823         kfree(req);
1824 }
1825
1826 /**
1827  * pch_udc_pcd_queue() - This function queues a request packet. It is called
1828  *                      by gadget driver
1829  * @usbep:      Reference to the USB endpoint structure
1830  * @usbreq:     Reference to the USB request
1831  * @gfp:        Flag to be used while mapping the data buffer
1832  *
1833  * Return codes:
1834  *      0:                      Success
1835  *      linux error number:     Failure
1836  */
1837 static int pch_udc_pcd_queue(struct usb_ep *usbep, struct usb_request *usbreq,
1838                                                                  gfp_t gfp)
1839 {
1840         int retval = 0;
1841         struct pch_udc_ep       *ep;
1842         struct pch_udc_dev      *dev;
1843         struct pch_udc_request  *req;
1844         unsigned long   iflags;
1845
1846         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf)
1847                 return -EINVAL;
1848         ep = container_of(usbep, struct pch_udc_ep, ep);
1849         dev = ep->dev;
1850         if (!ep->ep.desc && ep->num)
1851                 return -EINVAL;
1852         req = container_of(usbreq, struct pch_udc_request, req);
1853         if (!list_empty(&req->queue))
1854                 return -EINVAL;
1855         if (!dev->driver || (dev->gadget.speed == USB_SPEED_UNKNOWN))
1856                 return -ESHUTDOWN;
1857         spin_lock_irqsave(&dev->lock, iflags);
1858         /* map the buffer for dma */
1859         if (usbreq->length &&
1860             ((usbreq->dma == DMA_ADDR_INVALID) || !usbreq->dma)) {
1861                 if (!((unsigned long)(usbreq->buf) & 0x03)) {
1862                         if (ep->in)
1863                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1864                                                              usbreq->buf,
1865                                                              usbreq->length,
1866                                                              DMA_TO_DEVICE);
1867                         else
1868                                 usbreq->dma = dma_map_single(&dev->pdev->dev,
1869                                                              usbreq->buf,
1870                                                              usbreq->length,
1871                                                              DMA_FROM_DEVICE);
1872                 } else {
1873                         req->buf = kzalloc(usbreq->length, GFP_ATOMIC);
1874                         if (!req->buf) {
1875                                 retval = -ENOMEM;
1876                                 goto probe_end;
1877                         }
1878                         if (ep->in) {
1879                                 memcpy(req->buf, usbreq->buf, usbreq->length);
1880                                 req->dma = dma_map_single(&dev->pdev->dev,
1881                                                           req->buf,
1882                                                           usbreq->length,
1883                                                           DMA_TO_DEVICE);
1884                         } else
1885                                 req->dma = dma_map_single(&dev->pdev->dev,
1886                                                           req->buf,
1887                                                           usbreq->length,
1888                                                           DMA_FROM_DEVICE);
1889                 }
1890                 req->dma_mapped = 1;
1891         }
1892         if (usbreq->length > 0) {
1893                 retval = prepare_dma(ep, req, GFP_ATOMIC);
1894                 if (retval)
1895                         goto probe_end;
1896         }
1897         usbreq->actual = 0;
1898         usbreq->status = -EINPROGRESS;
1899         req->dma_done = 0;
1900         if (list_empty(&ep->queue) && !ep->halted) {
1901                 /* no pending transfer, so start this req */
1902                 if (!usbreq->length) {
1903                         process_zlp(ep, req);
1904                         retval = 0;
1905                         goto probe_end;
1906                 }
1907                 if (!ep->in) {
1908                         pch_udc_start_rxrequest(ep, req);
1909                 } else {
1910                         /*
1911                         * For IN trfr the descriptors will be programmed and
1912                         * P bit will be set when
1913                         * we get an IN token
1914                         */
1915                         pch_udc_wait_ep_stall(ep);
1916                         pch_udc_ep_clear_nak(ep);
1917                         pch_udc_enable_ep_interrupts(ep->dev, (1 << ep->num));
1918                 }
1919         }
1920         /* Now add this request to the ep's pending requests */
1921         if (req != NULL)
1922                 list_add_tail(&req->queue, &ep->queue);
1923
1924 probe_end:
1925         spin_unlock_irqrestore(&dev->lock, iflags);
1926         return retval;
1927 }
1928
1929 /**
1930  * pch_udc_pcd_dequeue() - This function de-queues a request packet.
1931  *                              It is called by gadget driver
1932  * @usbep:      Reference to the USB endpoint structure
1933  * @usbreq:     Reference to the USB request
1934  *
1935  * Return codes:
1936  *      0:                      Success
1937  *      linux error number:     Failure
1938  */
1939 static int pch_udc_pcd_dequeue(struct usb_ep *usbep,
1940                                 struct usb_request *usbreq)
1941 {
1942         struct pch_udc_ep       *ep;
1943         struct pch_udc_request  *req;
1944         unsigned long           flags;
1945         int ret = -EINVAL;
1946
1947         ep = container_of(usbep, struct pch_udc_ep, ep);
1948         if (!usbep || !usbreq || (!ep->ep.desc && ep->num))
1949                 return ret;
1950         req = container_of(usbreq, struct pch_udc_request, req);
1951         spin_lock_irqsave(&ep->dev->lock, flags);
1952         /* make sure it's still queued on this endpoint */
1953         list_for_each_entry(req, &ep->queue, queue) {
1954                 if (&req->req == usbreq) {
1955                         pch_udc_ep_set_nak(ep);
1956                         if (!list_empty(&req->queue))
1957                                 complete_req(ep, req, -ECONNRESET);
1958                         ret = 0;
1959                         break;
1960                 }
1961         }
1962         spin_unlock_irqrestore(&ep->dev->lock, flags);
1963         return ret;
1964 }
1965
1966 /**
1967  * pch_udc_pcd_set_halt() - This function Sets or clear the endpoint halt
1968  *                          feature
1969  * @usbep:      Reference to the USB endpoint structure
1970  * @halt:       Specifies whether to set or clear the feature
1971  *
1972  * Return codes:
1973  *      0:                      Success
1974  *      linux error number:     Failure
1975  */
1976 static int pch_udc_pcd_set_halt(struct usb_ep *usbep, int halt)
1977 {
1978         struct pch_udc_ep       *ep;
1979         unsigned long iflags;
1980         int ret;
1981
1982         if (!usbep)
1983                 return -EINVAL;
1984         ep = container_of(usbep, struct pch_udc_ep, ep);
1985         if (!ep->ep.desc && !ep->num)
1986                 return -EINVAL;
1987         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
1988                 return -ESHUTDOWN;
1989         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1990         if (list_empty(&ep->queue)) {
1991                 if (halt) {
1992                         if (ep->num == PCH_UDC_EP0)
1993                                 ep->dev->stall = 1;
1994                         pch_udc_ep_set_stall(ep);
1995                         pch_udc_enable_ep_interrupts(
1996                                 ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
1997                 } else {
1998                         pch_udc_ep_clear_stall(ep);
1999                 }
2000                 ret = 0;
2001         } else {
2002                 ret = -EAGAIN;
2003         }
2004         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2005         return ret;
2006 }
2007
2008 /**
2009  * pch_udc_pcd_set_wedge() - This function Sets or clear the endpoint
2010  *                              halt feature
2011  * @usbep:      Reference to the USB endpoint structure
2012  * @halt:       Specifies whether to set or clear the feature
2013  *
2014  * Return codes:
2015  *      0:                      Success
2016  *      linux error number:     Failure
2017  */
2018 static int pch_udc_pcd_set_wedge(struct usb_ep *usbep)
2019 {
2020         struct pch_udc_ep       *ep;
2021         unsigned long iflags;
2022         int ret;
2023
2024         if (!usbep)
2025                 return -EINVAL;
2026         ep = container_of(usbep, struct pch_udc_ep, ep);
2027         if (!ep->ep.desc && !ep->num)
2028                 return -EINVAL;
2029         if (!ep->dev->driver || (ep->dev->gadget.speed == USB_SPEED_UNKNOWN))
2030                 return -ESHUTDOWN;
2031         spin_lock_irqsave(&udc_stall_spinlock, iflags);
2032         if (!list_empty(&ep->queue)) {
2033                 ret = -EAGAIN;
2034         } else {
2035                 if (ep->num == PCH_UDC_EP0)
2036                         ep->dev->stall = 1;
2037                 pch_udc_ep_set_stall(ep);
2038                 pch_udc_enable_ep_interrupts(ep->dev,
2039                                              PCH_UDC_EPINT(ep->in, ep->num));
2040                 ep->dev->prot_stall = 1;
2041                 ret = 0;
2042         }
2043         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
2044         return ret;
2045 }
2046
2047 /**
2048  * pch_udc_pcd_fifo_flush() - This function Flush the FIFO of specified endpoint
2049  * @usbep:      Reference to the USB endpoint structure
2050  */
2051 static void pch_udc_pcd_fifo_flush(struct usb_ep *usbep)
2052 {
2053         struct pch_udc_ep  *ep;
2054
2055         if (!usbep)
2056                 return;
2057
2058         ep = container_of(usbep, struct pch_udc_ep, ep);
2059         if (ep->ep.desc || !ep->num)
2060                 pch_udc_ep_fifo_flush(ep, ep->in);
2061 }
2062
2063 static const struct usb_ep_ops pch_udc_ep_ops = {
2064         .enable         = pch_udc_pcd_ep_enable,
2065         .disable        = pch_udc_pcd_ep_disable,
2066         .alloc_request  = pch_udc_alloc_request,
2067         .free_request   = pch_udc_free_request,
2068         .queue          = pch_udc_pcd_queue,
2069         .dequeue        = pch_udc_pcd_dequeue,
2070         .set_halt       = pch_udc_pcd_set_halt,
2071         .set_wedge      = pch_udc_pcd_set_wedge,
2072         .fifo_status    = NULL,
2073         .fifo_flush     = pch_udc_pcd_fifo_flush,
2074 };
2075
2076 /**
2077  * pch_udc_init_setup_buff() - This function initializes the SETUP buffer
2078  * @td_stp:     Reference to the SETP buffer structure
2079  */
2080 static void pch_udc_init_setup_buff(struct pch_udc_stp_dma_desc *td_stp)
2081 {
2082         static u32      pky_marker;
2083
2084         if (!td_stp)
2085                 return;
2086         td_stp->reserved = ++pky_marker;
2087         memset(&td_stp->request, 0xFF, sizeof td_stp->request);
2088         td_stp->status = PCH_UDC_BS_HST_RDY;
2089 }
2090
2091 /**
2092  * pch_udc_start_next_txrequest() - This function starts
2093  *                                      the next transmission requirement
2094  * @ep: Reference to the endpoint structure
2095  */
2096 static void pch_udc_start_next_txrequest(struct pch_udc_ep *ep)
2097 {
2098         struct pch_udc_request *req;
2099         struct pch_udc_data_dma_desc *td_data;
2100
2101         if (pch_udc_read_ep_control(ep) & UDC_EPCTL_P)
2102                 return;
2103
2104         if (list_empty(&ep->queue))
2105                 return;
2106
2107         /* next request */
2108         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2109         if (req->dma_going)
2110                 return;
2111         if (!req->td_data)
2112                 return;
2113         pch_udc_wait_ep_stall(ep);
2114         req->dma_going = 1;
2115         pch_udc_ep_set_ddptr(ep, 0);
2116         td_data = req->td_data;
2117         while (1) {
2118                 td_data->status = (td_data->status & ~PCH_UDC_BUFF_STS) |
2119                                    PCH_UDC_BS_HST_RDY;
2120                 if ((td_data->status & PCH_UDC_DMA_LAST) == PCH_UDC_DMA_LAST)
2121                         break;
2122                 td_data = phys_to_virt(td_data->next);
2123         }
2124         pch_udc_ep_set_ddptr(ep, req->td_data_phys);
2125         pch_udc_set_dma(ep->dev, DMA_DIR_TX);
2126         pch_udc_ep_set_pd(ep);
2127         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2128         pch_udc_ep_clear_nak(ep);
2129 }
2130
2131 /**
2132  * pch_udc_complete_transfer() - This function completes a transfer
2133  * @ep:         Reference to the endpoint structure
2134  */
2135 static void pch_udc_complete_transfer(struct pch_udc_ep *ep)
2136 {
2137         struct pch_udc_request *req;
2138         struct pch_udc_dev *dev = ep->dev;
2139
2140         if (list_empty(&ep->queue))
2141                 return;
2142         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2143         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2144             PCH_UDC_BS_DMA_DONE)
2145                 return;
2146         if ((req->td_data_last->status & PCH_UDC_RXTX_STS) !=
2147              PCH_UDC_RTS_SUCC) {
2148                 dev_err(&dev->pdev->dev, "Invalid RXTX status (0x%08x) "
2149                         "epstatus=0x%08x\n",
2150                        (req->td_data_last->status & PCH_UDC_RXTX_STS),
2151                        (int)(ep->epsts));
2152                 return;
2153         }
2154
2155         req->req.actual = req->req.length;
2156         req->td_data_last->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2157         req->td_data->status = PCH_UDC_BS_HST_BSY | PCH_UDC_DMA_LAST;
2158         complete_req(ep, req, 0);
2159         req->dma_going = 0;
2160         if (!list_empty(&ep->queue)) {
2161                 pch_udc_wait_ep_stall(ep);
2162                 pch_udc_ep_clear_nak(ep);
2163                 pch_udc_enable_ep_interrupts(ep->dev,
2164                                              PCH_UDC_EPINT(ep->in, ep->num));
2165         } else {
2166                 pch_udc_disable_ep_interrupts(ep->dev,
2167                                               PCH_UDC_EPINT(ep->in, ep->num));
2168         }
2169 }
2170
2171 /**
2172  * pch_udc_complete_receiver() - This function completes a receiver
2173  * @ep:         Reference to the endpoint structure
2174  */
2175 static void pch_udc_complete_receiver(struct pch_udc_ep *ep)
2176 {
2177         struct pch_udc_request *req;
2178         struct pch_udc_dev *dev = ep->dev;
2179         unsigned int count;
2180         struct pch_udc_data_dma_desc *td;
2181         dma_addr_t addr;
2182
2183         if (list_empty(&ep->queue))
2184                 return;
2185         /* next request */
2186         req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2187         pch_udc_clear_dma(ep->dev, DMA_DIR_RX);
2188         pch_udc_ep_set_ddptr(ep, 0);
2189         if ((req->td_data_last->status & PCH_UDC_BUFF_STS) ==
2190             PCH_UDC_BS_DMA_DONE)
2191                 td = req->td_data_last;
2192         else
2193                 td = req->td_data;
2194
2195         while (1) {
2196                 if ((td->status & PCH_UDC_RXTX_STS) != PCH_UDC_RTS_SUCC) {
2197                         dev_err(&dev->pdev->dev, "Invalid RXTX status=0x%08x "
2198                                 "epstatus=0x%08x\n",
2199                                 (req->td_data->status & PCH_UDC_RXTX_STS),
2200                                 (int)(ep->epsts));
2201                         return;
2202                 }
2203                 if ((td->status & PCH_UDC_BUFF_STS) == PCH_UDC_BS_DMA_DONE)
2204                         if (td->status & PCH_UDC_DMA_LAST) {
2205                                 count = td->status & PCH_UDC_RXTX_BYTES;
2206                                 break;
2207                         }
2208                 if (td == req->td_data_last) {
2209                         dev_err(&dev->pdev->dev, "Not complete RX descriptor");
2210                         return;
2211                 }
2212                 addr = (dma_addr_t)td->next;
2213                 td = phys_to_virt(addr);
2214         }
2215         /* on 64k packets the RXBYTES field is zero */
2216         if (!count && (req->req.length == UDC_DMA_MAXPACKET))
2217                 count = UDC_DMA_MAXPACKET;
2218         req->td_data->status |= PCH_UDC_DMA_LAST;
2219         td->status |= PCH_UDC_BS_HST_BSY;
2220
2221         req->dma_going = 0;
2222         req->req.actual = count;
2223         complete_req(ep, req, 0);
2224         /* If there is a new/failed requests try that now */
2225         if (!list_empty(&ep->queue)) {
2226                 req = list_entry(ep->queue.next, struct pch_udc_request, queue);
2227                 pch_udc_start_rxrequest(ep, req);
2228         }
2229 }
2230
2231 /**
2232  * pch_udc_svc_data_in() - This function process endpoint interrupts
2233  *                              for IN endpoints
2234  * @dev:        Reference to the device structure
2235  * @ep_num:     Endpoint that generated the interrupt
2236  */
2237 static void pch_udc_svc_data_in(struct pch_udc_dev *dev, int ep_num)
2238 {
2239         u32     epsts;
2240         struct pch_udc_ep       *ep;
2241
2242         ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2243         epsts = ep->epsts;
2244         ep->epsts = 0;
2245
2246         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA  | UDC_EPSTS_HE |
2247                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2248                        UDC_EPSTS_RSS | UDC_EPSTS_XFERDONE)))
2249                 return;
2250         if ((epsts & UDC_EPSTS_BNA))
2251                 return;
2252         if (epsts & UDC_EPSTS_HE)
2253                 return;
2254         if (epsts & UDC_EPSTS_RSS) {
2255                 pch_udc_ep_set_stall(ep);
2256                 pch_udc_enable_ep_interrupts(ep->dev,
2257                                              PCH_UDC_EPINT(ep->in, ep->num));
2258         }
2259         if (epsts & UDC_EPSTS_RCS) {
2260                 if (!dev->prot_stall) {
2261                         pch_udc_ep_clear_stall(ep);
2262                 } else {
2263                         pch_udc_ep_set_stall(ep);
2264                         pch_udc_enable_ep_interrupts(ep->dev,
2265                                                 PCH_UDC_EPINT(ep->in, ep->num));
2266                 }
2267         }
2268         if (epsts & UDC_EPSTS_TDC)
2269                 pch_udc_complete_transfer(ep);
2270         /* On IN interrupt, provide data if we have any */
2271         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_RSS) &&
2272             !(epsts & UDC_EPSTS_TDC) && !(epsts & UDC_EPSTS_TXEMPTY))
2273                 pch_udc_start_next_txrequest(ep);
2274 }
2275
2276 /**
2277  * pch_udc_svc_data_out() - Handles interrupts from OUT endpoint
2278  * @dev:        Reference to the device structure
2279  * @ep_num:     Endpoint that generated the interrupt
2280  */
2281 static void pch_udc_svc_data_out(struct pch_udc_dev *dev, int ep_num)
2282 {
2283         u32                     epsts;
2284         struct pch_udc_ep               *ep;
2285         struct pch_udc_request          *req = NULL;
2286
2287         ep = &dev->ep[UDC_EPOUT_IDX(ep_num)];
2288         epsts = ep->epsts;
2289         ep->epsts = 0;
2290
2291         if ((epsts & UDC_EPSTS_BNA) && (!list_empty(&ep->queue))) {
2292                 /* next request */
2293                 req = list_entry(ep->queue.next, struct pch_udc_request,
2294                                  queue);
2295                 if ((req->td_data_last->status & PCH_UDC_BUFF_STS) !=
2296                      PCH_UDC_BS_DMA_DONE) {
2297                         if (!req->dma_going)
2298                                 pch_udc_start_rxrequest(ep, req);
2299                         return;
2300                 }
2301         }
2302         if (epsts & UDC_EPSTS_HE)
2303                 return;
2304         if (epsts & UDC_EPSTS_RSS) {
2305                 pch_udc_ep_set_stall(ep);
2306                 pch_udc_enable_ep_interrupts(ep->dev,
2307                                              PCH_UDC_EPINT(ep->in, ep->num));
2308         }
2309         if (epsts & UDC_EPSTS_RCS) {
2310                 if (!dev->prot_stall) {
2311                         pch_udc_ep_clear_stall(ep);
2312                 } else {
2313                         pch_udc_ep_set_stall(ep);
2314                         pch_udc_enable_ep_interrupts(ep->dev,
2315                                                 PCH_UDC_EPINT(ep->in, ep->num));
2316                 }
2317         }
2318         if (((epsts & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2319             UDC_EPSTS_OUT_DATA) {
2320                 if (ep->dev->prot_stall == 1) {
2321                         pch_udc_ep_set_stall(ep);
2322                         pch_udc_enable_ep_interrupts(ep->dev,
2323                                                 PCH_UDC_EPINT(ep->in, ep->num));
2324                 } else {
2325                         pch_udc_complete_receiver(ep);
2326                 }
2327         }
2328         if (list_empty(&ep->queue))
2329                 pch_udc_set_dma(dev, DMA_DIR_RX);
2330 }
2331
2332 static int pch_udc_gadget_setup(struct pch_udc_dev *dev)
2333         __must_hold(&dev->lock)
2334 {
2335         int rc;
2336
2337         /* In some cases we can get an interrupt before driver gets setup */
2338         if (!dev->driver)
2339                 return -ESHUTDOWN;
2340
2341         spin_unlock(&dev->lock);
2342         rc = dev->driver->setup(&dev->gadget, &dev->setup_data);
2343         spin_lock(&dev->lock);
2344         return rc;
2345 }
2346
2347 /**
2348  * pch_udc_svc_control_in() - Handle Control IN endpoint interrupts
2349  * @dev:        Reference to the device structure
2350  */
2351 static void pch_udc_svc_control_in(struct pch_udc_dev *dev)
2352 {
2353         u32     epsts;
2354         struct pch_udc_ep       *ep;
2355         struct pch_udc_ep       *ep_out;
2356
2357         ep = &dev->ep[UDC_EP0IN_IDX];
2358         ep_out = &dev->ep[UDC_EP0OUT_IDX];
2359         epsts = ep->epsts;
2360         ep->epsts = 0;
2361
2362         if (!(epsts & (UDC_EPSTS_IN | UDC_EPSTS_BNA | UDC_EPSTS_HE |
2363                        UDC_EPSTS_TDC | UDC_EPSTS_RCS | UDC_EPSTS_TXEMPTY |
2364                        UDC_EPSTS_XFERDONE)))
2365                 return;
2366         if ((epsts & UDC_EPSTS_BNA))
2367                 return;
2368         if (epsts & UDC_EPSTS_HE)
2369                 return;
2370         if ((epsts & UDC_EPSTS_TDC) && (!dev->stall)) {
2371                 pch_udc_complete_transfer(ep);
2372                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2373                 ep_out->td_data->status = (ep_out->td_data->status &
2374                                         ~PCH_UDC_BUFF_STS) |
2375                                         PCH_UDC_BS_HST_RDY;
2376                 pch_udc_ep_clear_nak(ep_out);
2377                 pch_udc_set_dma(dev, DMA_DIR_RX);
2378                 pch_udc_ep_set_rrdy(ep_out);
2379         }
2380         /* On IN interrupt, provide data if we have any */
2381         if ((epsts & UDC_EPSTS_IN) && !(epsts & UDC_EPSTS_TDC) &&
2382              !(epsts & UDC_EPSTS_TXEMPTY))
2383                 pch_udc_start_next_txrequest(ep);
2384 }
2385
2386 /**
2387  * pch_udc_svc_control_out() - Routine that handle Control
2388  *                                      OUT endpoint interrupts
2389  * @dev:        Reference to the device structure
2390  */
2391 static void pch_udc_svc_control_out(struct pch_udc_dev *dev)
2392         __releases(&dev->lock)
2393         __acquires(&dev->lock)
2394 {
2395         u32     stat;
2396         int setup_supported;
2397         struct pch_udc_ep       *ep;
2398
2399         ep = &dev->ep[UDC_EP0OUT_IDX];
2400         stat = ep->epsts;
2401         ep->epsts = 0;
2402
2403         /* If setup data */
2404         if (((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2405             UDC_EPSTS_OUT_SETUP) {
2406                 dev->stall = 0;
2407                 dev->ep[UDC_EP0IN_IDX].halted = 0;
2408                 dev->ep[UDC_EP0OUT_IDX].halted = 0;
2409                 dev->setup_data = ep->td_stp->request;
2410                 pch_udc_init_setup_buff(ep->td_stp);
2411                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2412                 pch_udc_ep_fifo_flush(&(dev->ep[UDC_EP0IN_IDX]),
2413                                       dev->ep[UDC_EP0IN_IDX].in);
2414                 if ((dev->setup_data.bRequestType & USB_DIR_IN))
2415                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2416                 else /* OUT */
2417                         dev->gadget.ep0 = &ep->ep;
2418                 /* If Mass storage Reset */
2419                 if ((dev->setup_data.bRequestType == 0x21) &&
2420                     (dev->setup_data.bRequest == 0xFF))
2421                         dev->prot_stall = 0;
2422                 /* call gadget with setup data received */
2423                 setup_supported = pch_udc_gadget_setup(dev);
2424
2425                 if (dev->setup_data.bRequestType & USB_DIR_IN) {
2426                         ep->td_data->status = (ep->td_data->status &
2427                                                 ~PCH_UDC_BUFF_STS) |
2428                                                 PCH_UDC_BS_HST_RDY;
2429                         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2430                 }
2431                 /* ep0 in returns data on IN phase */
2432                 if (setup_supported >= 0 && setup_supported <
2433                                             UDC_EP0IN_MAX_PKT_SIZE) {
2434                         pch_udc_ep_clear_nak(&(dev->ep[UDC_EP0IN_IDX]));
2435                         /* Gadget would have queued a request when
2436                          * we called the setup */
2437                         if (!(dev->setup_data.bRequestType & USB_DIR_IN)) {
2438                                 pch_udc_set_dma(dev, DMA_DIR_RX);
2439                                 pch_udc_ep_clear_nak(ep);
2440                         }
2441                 } else if (setup_supported < 0) {
2442                         /* if unsupported request, then stall */
2443                         pch_udc_ep_set_stall(&(dev->ep[UDC_EP0IN_IDX]));
2444                         pch_udc_enable_ep_interrupts(ep->dev,
2445                                                 PCH_UDC_EPINT(ep->in, ep->num));
2446                         dev->stall = 0;
2447                         pch_udc_set_dma(dev, DMA_DIR_RX);
2448                 } else {
2449                         dev->waiting_zlp_ack = 1;
2450                 }
2451         } else if ((((stat & UDC_EPSTS_OUT_MASK) >> UDC_EPSTS_OUT_SHIFT) ==
2452                      UDC_EPSTS_OUT_DATA) && !dev->stall) {
2453                 pch_udc_clear_dma(dev, DMA_DIR_RX);
2454                 pch_udc_ep_set_ddptr(ep, 0);
2455                 if (!list_empty(&ep->queue)) {
2456                         ep->epsts = stat;
2457                         pch_udc_svc_data_out(dev, PCH_UDC_EP0);
2458                 }
2459                 pch_udc_set_dma(dev, DMA_DIR_RX);
2460         }
2461         pch_udc_ep_set_rrdy(ep);
2462 }
2463
2464
2465 /**
2466  * pch_udc_postsvc_epinters() - This function enables end point interrupts
2467  *                              and clears NAK status
2468  * @dev:        Reference to the device structure
2469  * @ep_num:     End point number
2470  */
2471 static void pch_udc_postsvc_epinters(struct pch_udc_dev *dev, int ep_num)
2472 {
2473         struct pch_udc_ep       *ep = &dev->ep[UDC_EPIN_IDX(ep_num)];
2474         if (list_empty(&ep->queue))
2475                 return;
2476         pch_udc_enable_ep_interrupts(ep->dev, PCH_UDC_EPINT(ep->in, ep->num));
2477         pch_udc_ep_clear_nak(ep);
2478 }
2479
2480 /**
2481  * pch_udc_read_all_epstatus() - This function read all endpoint status
2482  * @dev:        Reference to the device structure
2483  * @ep_intr:    Status of endpoint interrupt
2484  */
2485 static void pch_udc_read_all_epstatus(struct pch_udc_dev *dev, u32 ep_intr)
2486 {
2487         int i;
2488         struct pch_udc_ep       *ep;
2489
2490         for (i = 0; i < PCH_UDC_USED_EP_NUM; i++) {
2491                 /* IN */
2492                 if (ep_intr & (0x1 << i)) {
2493                         ep = &dev->ep[UDC_EPIN_IDX(i)];
2494                         ep->epsts = pch_udc_read_ep_status(ep);
2495                         pch_udc_clear_ep_status(ep, ep->epsts);
2496                 }
2497                 /* OUT */
2498                 if (ep_intr & (0x10000 << i)) {
2499                         ep = &dev->ep[UDC_EPOUT_IDX(i)];
2500                         ep->epsts = pch_udc_read_ep_status(ep);
2501                         pch_udc_clear_ep_status(ep, ep->epsts);
2502                 }
2503         }
2504 }
2505
2506 /**
2507  * pch_udc_activate_control_ep() - This function enables the control endpoints
2508  *                                      for traffic after a reset
2509  * @dev:        Reference to the device structure
2510  */
2511 static void pch_udc_activate_control_ep(struct pch_udc_dev *dev)
2512 {
2513         struct pch_udc_ep       *ep;
2514         u32 val;
2515
2516         /* Setup the IN endpoint */
2517         ep = &dev->ep[UDC_EP0IN_IDX];
2518         pch_udc_clear_ep_control(ep);
2519         pch_udc_ep_fifo_flush(ep, ep->in);
2520         pch_udc_ep_set_bufsz(ep, UDC_EP0IN_BUFF_SIZE, ep->in);
2521         pch_udc_ep_set_maxpkt(ep, UDC_EP0IN_MAX_PKT_SIZE);
2522         /* Initialize the IN EP Descriptor */
2523         ep->td_data      = NULL;
2524         ep->td_stp       = NULL;
2525         ep->td_data_phys = 0;
2526         ep->td_stp_phys  = 0;
2527
2528         /* Setup the OUT endpoint */
2529         ep = &dev->ep[UDC_EP0OUT_IDX];
2530         pch_udc_clear_ep_control(ep);
2531         pch_udc_ep_fifo_flush(ep, ep->in);
2532         pch_udc_ep_set_bufsz(ep, UDC_EP0OUT_BUFF_SIZE, ep->in);
2533         pch_udc_ep_set_maxpkt(ep, UDC_EP0OUT_MAX_PKT_SIZE);
2534         val = UDC_EP0OUT_MAX_PKT_SIZE << UDC_CSR_NE_MAX_PKT_SHIFT;
2535         pch_udc_write_csr(ep->dev, val, UDC_EP0OUT_IDX);
2536
2537         /* Initialize the SETUP buffer */
2538         pch_udc_init_setup_buff(ep->td_stp);
2539         /* Write the pointer address of dma descriptor */
2540         pch_udc_ep_set_subptr(ep, ep->td_stp_phys);
2541         /* Write the pointer address of Setup descriptor */
2542         pch_udc_ep_set_ddptr(ep, ep->td_data_phys);
2543
2544         /* Initialize the dma descriptor */
2545         ep->td_data->status  = PCH_UDC_DMA_LAST;
2546         ep->td_data->dataptr = dev->dma_addr;
2547         ep->td_data->next    = ep->td_data_phys;
2548
2549         pch_udc_ep_clear_nak(ep);
2550 }
2551
2552
2553 /**
2554  * pch_udc_svc_ur_interrupt() - This function handles a USB reset interrupt
2555  * @dev:        Reference to driver structure
2556  */
2557 static void pch_udc_svc_ur_interrupt(struct pch_udc_dev *dev)
2558 {
2559         struct pch_udc_ep       *ep;
2560         int i;
2561
2562         pch_udc_clear_dma(dev, DMA_DIR_TX);
2563         pch_udc_clear_dma(dev, DMA_DIR_RX);
2564         /* Mask all endpoint interrupts */
2565         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2566         /* clear all endpoint interrupts */
2567         pch_udc_write_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
2568
2569         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2570                 ep = &dev->ep[i];
2571                 pch_udc_clear_ep_status(ep, UDC_EPSTS_ALL_CLR_MASK);
2572                 pch_udc_clear_ep_control(ep);
2573                 pch_udc_ep_set_ddptr(ep, 0);
2574                 pch_udc_write_csr(ep->dev, 0x00, i);
2575         }
2576         dev->stall = 0;
2577         dev->prot_stall = 0;
2578         dev->waiting_zlp_ack = 0;
2579         dev->set_cfg_not_acked = 0;
2580
2581         /* disable ep to empty req queue. Skip the control EP's */
2582         for (i = 0; i < (PCH_UDC_USED_EP_NUM*2); i++) {
2583                 ep = &dev->ep[i];
2584                 pch_udc_ep_set_nak(ep);
2585                 pch_udc_ep_fifo_flush(ep, ep->in);
2586                 /* Complete request queue */
2587                 empty_req_queue(ep);
2588         }
2589         if (dev->driver) {
2590                 spin_unlock(&dev->lock);
2591                 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2592                 spin_lock(&dev->lock);
2593         }
2594 }
2595
2596 /**
2597  * pch_udc_svc_enum_interrupt() - This function handles a USB speed enumeration
2598  *                              done interrupt
2599  * @dev:        Reference to driver structure
2600  */
2601 static void pch_udc_svc_enum_interrupt(struct pch_udc_dev *dev)
2602 {
2603         u32 dev_stat, dev_speed;
2604         u32 speed = USB_SPEED_FULL;
2605
2606         dev_stat = pch_udc_read_device_status(dev);
2607         dev_speed = (dev_stat & UDC_DEVSTS_ENUM_SPEED_MASK) >>
2608                                                  UDC_DEVSTS_ENUM_SPEED_SHIFT;
2609         switch (dev_speed) {
2610         case UDC_DEVSTS_ENUM_SPEED_HIGH:
2611                 speed = USB_SPEED_HIGH;
2612                 break;
2613         case  UDC_DEVSTS_ENUM_SPEED_FULL:
2614                 speed = USB_SPEED_FULL;
2615                 break;
2616         case  UDC_DEVSTS_ENUM_SPEED_LOW:
2617                 speed = USB_SPEED_LOW;
2618                 break;
2619         default:
2620                 BUG();
2621         }
2622         dev->gadget.speed = speed;
2623         pch_udc_activate_control_ep(dev);
2624         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 | UDC_EPINT_OUT_EP0);
2625         pch_udc_set_dma(dev, DMA_DIR_TX);
2626         pch_udc_set_dma(dev, DMA_DIR_RX);
2627         pch_udc_ep_set_rrdy(&(dev->ep[UDC_EP0OUT_IDX]));
2628
2629         /* enable device interrupts */
2630         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2631                                         UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2632                                         UDC_DEVINT_SI | UDC_DEVINT_SC);
2633 }
2634
2635 /**
2636  * pch_udc_svc_intf_interrupt() - This function handles a set interface
2637  *                                interrupt
2638  * @dev:        Reference to driver structure
2639  */
2640 static void pch_udc_svc_intf_interrupt(struct pch_udc_dev *dev)
2641 {
2642         u32 reg, dev_stat = 0;
2643         int i;
2644
2645         dev_stat = pch_udc_read_device_status(dev);
2646         dev->cfg_data.cur_intf = (dev_stat & UDC_DEVSTS_INTF_MASK) >>
2647                                                          UDC_DEVSTS_INTF_SHIFT;
2648         dev->cfg_data.cur_alt = (dev_stat & UDC_DEVSTS_ALT_MASK) >>
2649                                                          UDC_DEVSTS_ALT_SHIFT;
2650         dev->set_cfg_not_acked = 1;
2651         /* Construct the usb request for gadget driver and inform it */
2652         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2653         dev->setup_data.bRequest = USB_REQ_SET_INTERFACE;
2654         dev->setup_data.bRequestType = USB_RECIP_INTERFACE;
2655         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_alt);
2656         dev->setup_data.wIndex = cpu_to_le16(dev->cfg_data.cur_intf);
2657         /* programm the Endpoint Cfg registers */
2658         /* Only one end point cfg register */
2659         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2660         reg = (reg & ~UDC_CSR_NE_INTF_MASK) |
2661               (dev->cfg_data.cur_intf << UDC_CSR_NE_INTF_SHIFT);
2662         reg = (reg & ~UDC_CSR_NE_ALT_MASK) |
2663               (dev->cfg_data.cur_alt << UDC_CSR_NE_ALT_SHIFT);
2664         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2665         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2666                 /* clear stall bits */
2667                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2668                 dev->ep[i].halted = 0;
2669         }
2670         dev->stall = 0;
2671         pch_udc_gadget_setup(dev);
2672 }
2673
2674 /**
2675  * pch_udc_svc_cfg_interrupt() - This function handles a set configuration
2676  *                              interrupt
2677  * @dev:        Reference to driver structure
2678  */
2679 static void pch_udc_svc_cfg_interrupt(struct pch_udc_dev *dev)
2680 {
2681         int i;
2682         u32 reg, dev_stat = 0;
2683
2684         dev_stat = pch_udc_read_device_status(dev);
2685         dev->set_cfg_not_acked = 1;
2686         dev->cfg_data.cur_cfg = (dev_stat & UDC_DEVSTS_CFG_MASK) >>
2687                                 UDC_DEVSTS_CFG_SHIFT;
2688         /* make usb request for gadget driver */
2689         memset(&dev->setup_data, 0 , sizeof dev->setup_data);
2690         dev->setup_data.bRequest = USB_REQ_SET_CONFIGURATION;
2691         dev->setup_data.wValue = cpu_to_le16(dev->cfg_data.cur_cfg);
2692         /* program the NE registers */
2693         /* Only one end point cfg register */
2694         reg = pch_udc_read_csr(dev, UDC_EP0OUT_IDX);
2695         reg = (reg & ~UDC_CSR_NE_CFG_MASK) |
2696               (dev->cfg_data.cur_cfg << UDC_CSR_NE_CFG_SHIFT);
2697         pch_udc_write_csr(dev, reg, UDC_EP0OUT_IDX);
2698         for (i = 0; i < PCH_UDC_USED_EP_NUM * 2; i++) {
2699                 /* clear stall bits */
2700                 pch_udc_ep_clear_stall(&(dev->ep[i]));
2701                 dev->ep[i].halted = 0;
2702         }
2703         dev->stall = 0;
2704
2705         /* call gadget zero with setup data received */
2706         pch_udc_gadget_setup(dev);
2707 }
2708
2709 /**
2710  * pch_udc_dev_isr() - This function services device interrupts
2711  *                      by invoking appropriate routines.
2712  * @dev:        Reference to the device structure
2713  * @dev_intr:   The Device interrupt status.
2714  */
2715 static void pch_udc_dev_isr(struct pch_udc_dev *dev, u32 dev_intr)
2716 {
2717         int vbus;
2718
2719         /* USB Reset Interrupt */
2720         if (dev_intr & UDC_DEVINT_UR) {
2721                 pch_udc_svc_ur_interrupt(dev);
2722                 dev_dbg(&dev->pdev->dev, "USB_RESET\n");
2723         }
2724         /* Enumeration Done Interrupt */
2725         if (dev_intr & UDC_DEVINT_ENUM) {
2726                 pch_udc_svc_enum_interrupt(dev);
2727                 dev_dbg(&dev->pdev->dev, "USB_ENUM\n");
2728         }
2729         /* Set Interface Interrupt */
2730         if (dev_intr & UDC_DEVINT_SI)
2731                 pch_udc_svc_intf_interrupt(dev);
2732         /* Set Config Interrupt */
2733         if (dev_intr & UDC_DEVINT_SC)
2734                 pch_udc_svc_cfg_interrupt(dev);
2735         /* USB Suspend interrupt */
2736         if (dev_intr & UDC_DEVINT_US) {
2737                 if (dev->driver
2738                         && dev->driver->suspend) {
2739                         spin_unlock(&dev->lock);
2740                         dev->driver->suspend(&dev->gadget);
2741                         spin_lock(&dev->lock);
2742                 }
2743
2744                 vbus = pch_vbus_gpio_get_value(dev);
2745                 if ((dev->vbus_session == 0)
2746                         && (vbus != 1)) {
2747                         if (dev->driver && dev->driver->disconnect) {
2748                                 spin_unlock(&dev->lock);
2749                                 dev->driver->disconnect(&dev->gadget);
2750                                 spin_lock(&dev->lock);
2751                         }
2752                         pch_udc_reconnect(dev);
2753                 } else if ((dev->vbus_session == 0)
2754                         && (vbus == 1)
2755                         && !dev->vbus_gpio.intr)
2756                         schedule_work(&dev->vbus_gpio.irq_work_fall);
2757
2758                 dev_dbg(&dev->pdev->dev, "USB_SUSPEND\n");
2759         }
2760         /* Clear the SOF interrupt, if enabled */
2761         if (dev_intr & UDC_DEVINT_SOF)
2762                 dev_dbg(&dev->pdev->dev, "SOF\n");
2763         /* ES interrupt, IDLE > 3ms on the USB */
2764         if (dev_intr & UDC_DEVINT_ES)
2765                 dev_dbg(&dev->pdev->dev, "ES\n");
2766         /* RWKP interrupt */
2767         if (dev_intr & UDC_DEVINT_RWKP)
2768                 dev_dbg(&dev->pdev->dev, "RWKP\n");
2769 }
2770
2771 /**
2772  * pch_udc_isr() - This function handles interrupts from the PCH USB Device
2773  * @irq:        Interrupt request number
2774  * @dev:        Reference to the device structure
2775  */
2776 static irqreturn_t pch_udc_isr(int irq, void *pdev)
2777 {
2778         struct pch_udc_dev *dev = (struct pch_udc_dev *) pdev;
2779         u32 dev_intr, ep_intr;
2780         int i;
2781
2782         dev_intr = pch_udc_read_device_interrupts(dev);
2783         ep_intr = pch_udc_read_ep_interrupts(dev);
2784
2785         /* For a hot plug, this find that the controller is hung up. */
2786         if (dev_intr == ep_intr)
2787                 if (dev_intr == pch_udc_readl(dev, UDC_DEVCFG_ADDR)) {
2788                         dev_dbg(&dev->pdev->dev, "UDC: Hung up\n");
2789                         /* The controller is reset */
2790                         pch_udc_writel(dev, UDC_SRST, UDC_SRST_ADDR);
2791                         return IRQ_HANDLED;
2792                 }
2793         if (dev_intr)
2794                 /* Clear device interrupts */
2795                 pch_udc_write_device_interrupts(dev, dev_intr);
2796         if (ep_intr)
2797                 /* Clear ep interrupts */
2798                 pch_udc_write_ep_interrupts(dev, ep_intr);
2799         if (!dev_intr && !ep_intr)
2800                 return IRQ_NONE;
2801         spin_lock(&dev->lock);
2802         if (dev_intr)
2803                 pch_udc_dev_isr(dev, dev_intr);
2804         if (ep_intr) {
2805                 pch_udc_read_all_epstatus(dev, ep_intr);
2806                 /* Process Control In interrupts, if present */
2807                 if (ep_intr & UDC_EPINT_IN_EP0) {
2808                         pch_udc_svc_control_in(dev);
2809                         pch_udc_postsvc_epinters(dev, 0);
2810                 }
2811                 /* Process Control Out interrupts, if present */
2812                 if (ep_intr & UDC_EPINT_OUT_EP0)
2813                         pch_udc_svc_control_out(dev);
2814                 /* Process data in end point interrupts */
2815                 for (i = 1; i < PCH_UDC_USED_EP_NUM; i++) {
2816                         if (ep_intr & (1 <<  i)) {
2817                                 pch_udc_svc_data_in(dev, i);
2818                                 pch_udc_postsvc_epinters(dev, i);
2819                         }
2820                 }
2821                 /* Process data out end point interrupts */
2822                 for (i = UDC_EPINT_OUT_SHIFT + 1; i < (UDC_EPINT_OUT_SHIFT +
2823                                                  PCH_UDC_USED_EP_NUM); i++)
2824                         if (ep_intr & (1 <<  i))
2825                                 pch_udc_svc_data_out(dev, i -
2826                                                          UDC_EPINT_OUT_SHIFT);
2827         }
2828         spin_unlock(&dev->lock);
2829         return IRQ_HANDLED;
2830 }
2831
2832 /**
2833  * pch_udc_setup_ep0() - This function enables control endpoint for traffic
2834  * @dev:        Reference to the device structure
2835  */
2836 static void pch_udc_setup_ep0(struct pch_udc_dev *dev)
2837 {
2838         /* enable ep0 interrupts */
2839         pch_udc_enable_ep_interrupts(dev, UDC_EPINT_IN_EP0 |
2840                                                 UDC_EPINT_OUT_EP0);
2841         /* enable device interrupts */
2842         pch_udc_enable_interrupts(dev, UDC_DEVINT_UR | UDC_DEVINT_US |
2843                                        UDC_DEVINT_ES | UDC_DEVINT_ENUM |
2844                                        UDC_DEVINT_SI | UDC_DEVINT_SC);
2845 }
2846
2847 /**
2848  * pch_udc_pcd_reinit() - This API initializes the endpoint structures
2849  * @dev:        Reference to the driver structure
2850  */
2851 static void pch_udc_pcd_reinit(struct pch_udc_dev *dev)
2852 {
2853         const char *const ep_string[] = {
2854                 ep0_string, "ep0out", "ep1in", "ep1out", "ep2in", "ep2out",
2855                 "ep3in", "ep3out", "ep4in", "ep4out", "ep5in", "ep5out",
2856                 "ep6in", "ep6out", "ep7in", "ep7out", "ep8in", "ep8out",
2857                 "ep9in", "ep9out", "ep10in", "ep10out", "ep11in", "ep11out",
2858                 "ep12in", "ep12out", "ep13in", "ep13out", "ep14in", "ep14out",
2859                 "ep15in", "ep15out",
2860         };
2861         int i;
2862
2863         dev->gadget.speed = USB_SPEED_UNKNOWN;
2864         INIT_LIST_HEAD(&dev->gadget.ep_list);
2865
2866         /* Initialize the endpoints structures */
2867         memset(dev->ep, 0, sizeof dev->ep);
2868         for (i = 0; i < PCH_UDC_EP_NUM; i++) {
2869                 struct pch_udc_ep *ep = &dev->ep[i];
2870                 ep->dev = dev;
2871                 ep->halted = 1;
2872                 ep->num = i / 2;
2873                 ep->in = ~i & 1;
2874                 ep->ep.name = ep_string[i];
2875                 ep->ep.ops = &pch_udc_ep_ops;
2876                 if (ep->in) {
2877                         ep->offset_addr = ep->num * UDC_EP_REG_SHIFT;
2878                         ep->ep.caps.dir_in = true;
2879                 } else {
2880                         ep->offset_addr = (UDC_EPINT_OUT_SHIFT + ep->num) *
2881                                           UDC_EP_REG_SHIFT;
2882                         ep->ep.caps.dir_out = true;
2883                 }
2884                 if (i == UDC_EP0IN_IDX || i == UDC_EP0OUT_IDX) {
2885                         ep->ep.caps.type_control = true;
2886                 } else {
2887                         ep->ep.caps.type_iso = true;
2888                         ep->ep.caps.type_bulk = true;
2889                         ep->ep.caps.type_int = true;
2890                 }
2891                 /* need to set ep->ep.maxpacket and set Default Configuration?*/
2892                 usb_ep_set_maxpacket_limit(&ep->ep, UDC_BULK_MAX_PKT_SIZE);
2893                 list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
2894                 INIT_LIST_HEAD(&ep->queue);
2895         }
2896         usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IDX].ep, UDC_EP0IN_MAX_PKT_SIZE);
2897         usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IDX].ep, UDC_EP0OUT_MAX_PKT_SIZE);
2898
2899         /* remove ep0 in and out from the list.  They have own pointer */
2900         list_del_init(&dev->ep[UDC_EP0IN_IDX].ep.ep_list);
2901         list_del_init(&dev->ep[UDC_EP0OUT_IDX].ep.ep_list);
2902
2903         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IDX].ep;
2904         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
2905 }
2906
2907 /**
2908  * pch_udc_pcd_init() - This API initializes the driver structure
2909  * @dev:        Reference to the driver structure
2910  *
2911  * Return codes:
2912  *      0: Success
2913  */
2914 static int pch_udc_pcd_init(struct pch_udc_dev *dev)
2915 {
2916         pch_udc_init(dev);
2917         pch_udc_pcd_reinit(dev);
2918         pch_vbus_gpio_init(dev, vbus_gpio_port);
2919         return 0;
2920 }
2921
2922 /**
2923  * init_dma_pools() - create dma pools during initialization
2924  * @pdev:       reference to struct pci_dev
2925  */
2926 static int init_dma_pools(struct pch_udc_dev *dev)
2927 {
2928         struct pch_udc_stp_dma_desc     *td_stp;
2929         struct pch_udc_data_dma_desc    *td_data;
2930         void                            *ep0out_buf;
2931
2932         /* DMA setup */
2933         dev->data_requests = dma_pool_create("data_requests", &dev->pdev->dev,
2934                 sizeof(struct pch_udc_data_dma_desc), 0, 0);
2935         if (!dev->data_requests) {
2936                 dev_err(&dev->pdev->dev, "%s: can't get request data pool\n",
2937                         __func__);
2938                 return -ENOMEM;
2939         }
2940
2941         /* dma desc for setup data */
2942         dev->stp_requests = dma_pool_create("setup requests", &dev->pdev->dev,
2943                 sizeof(struct pch_udc_stp_dma_desc), 0, 0);
2944         if (!dev->stp_requests) {
2945                 dev_err(&dev->pdev->dev, "%s: can't get setup request pool\n",
2946                         __func__);
2947                 return -ENOMEM;
2948         }
2949         /* setup */
2950         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
2951                                 &dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
2952         if (!td_stp) {
2953                 dev_err(&dev->pdev->dev,
2954                         "%s: can't allocate setup dma descriptor\n", __func__);
2955                 return -ENOMEM;
2956         }
2957         dev->ep[UDC_EP0OUT_IDX].td_stp = td_stp;
2958
2959         /* data: 0 packets !? */
2960         td_data = dma_pool_alloc(dev->data_requests, GFP_KERNEL,
2961                                 &dev->ep[UDC_EP0OUT_IDX].td_data_phys);
2962         if (!td_data) {
2963                 dev_err(&dev->pdev->dev,
2964                         "%s: can't allocate data dma descriptor\n", __func__);
2965                 return -ENOMEM;
2966         }
2967         dev->ep[UDC_EP0OUT_IDX].td_data = td_data;
2968         dev->ep[UDC_EP0IN_IDX].td_stp = NULL;
2969         dev->ep[UDC_EP0IN_IDX].td_stp_phys = 0;
2970         dev->ep[UDC_EP0IN_IDX].td_data = NULL;
2971         dev->ep[UDC_EP0IN_IDX].td_data_phys = 0;
2972
2973         ep0out_buf = devm_kzalloc(&dev->pdev->dev, UDC_EP0OUT_BUFF_SIZE * 4,
2974                                   GFP_KERNEL);
2975         if (!ep0out_buf)
2976                 return -ENOMEM;
2977         dev->dma_addr = dma_map_single(&dev->pdev->dev, ep0out_buf,
2978                                        UDC_EP0OUT_BUFF_SIZE * 4,
2979                                        DMA_FROM_DEVICE);
2980         return dma_mapping_error(&dev->pdev->dev, dev->dma_addr);
2981 }
2982
2983 static int pch_udc_start(struct usb_gadget *g,
2984                 struct usb_gadget_driver *driver)
2985 {
2986         struct pch_udc_dev      *dev = to_pch_udc(g);
2987
2988         driver->driver.bus = NULL;
2989         dev->driver = driver;
2990
2991         /* get ready for ep0 traffic */
2992         pch_udc_setup_ep0(dev);
2993
2994         /* clear SD */
2995         if ((pch_vbus_gpio_get_value(dev) != 0) || !dev->vbus_gpio.intr)
2996                 pch_udc_clear_disconnect(dev);
2997
2998         dev->connected = 1;
2999         return 0;
3000 }
3001
3002 static int pch_udc_stop(struct usb_gadget *g)
3003 {
3004         struct pch_udc_dev      *dev = to_pch_udc(g);
3005
3006         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3007
3008         /* Assures that there are no pending requests with this driver */
3009         dev->driver = NULL;
3010         dev->connected = 0;
3011
3012         /* set SD */
3013         pch_udc_set_disconnect(dev);
3014
3015         return 0;
3016 }
3017
3018 static void pch_udc_shutdown(struct pci_dev *pdev)
3019 {
3020         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3021
3022         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3023         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3024
3025         /* disable the pullup so the host will think we're gone */
3026         pch_udc_set_disconnect(dev);
3027 }
3028
3029 static void pch_udc_remove(struct pci_dev *pdev)
3030 {
3031         struct pch_udc_dev      *dev = pci_get_drvdata(pdev);
3032
3033         usb_del_gadget_udc(&dev->gadget);
3034
3035         /* gadget driver must not be registered */
3036         if (dev->driver)
3037                 dev_err(&pdev->dev,
3038                         "%s: gadget driver still bound!!!\n", __func__);
3039         /* dma pool cleanup */
3040         dma_pool_destroy(dev->data_requests);
3041
3042         if (dev->stp_requests) {
3043                 /* cleanup DMA desc's for ep0in */
3044                 if (dev->ep[UDC_EP0OUT_IDX].td_stp) {
3045                         dma_pool_free(dev->stp_requests,
3046                                 dev->ep[UDC_EP0OUT_IDX].td_stp,
3047                                 dev->ep[UDC_EP0OUT_IDX].td_stp_phys);
3048                 }
3049                 if (dev->ep[UDC_EP0OUT_IDX].td_data) {
3050                         dma_pool_free(dev->stp_requests,
3051                                 dev->ep[UDC_EP0OUT_IDX].td_data,
3052                                 dev->ep[UDC_EP0OUT_IDX].td_data_phys);
3053                 }
3054                 dma_pool_destroy(dev->stp_requests);
3055         }
3056
3057         if (dev->dma_addr)
3058                 dma_unmap_single(&dev->pdev->dev, dev->dma_addr,
3059                                  UDC_EP0OUT_BUFF_SIZE * 4, DMA_FROM_DEVICE);
3060
3061         pch_vbus_gpio_free(dev);
3062
3063         pch_udc_exit(dev);
3064 }
3065
3066 #ifdef CONFIG_PM_SLEEP
3067 static int pch_udc_suspend(struct device *d)
3068 {
3069         struct pci_dev *pdev = to_pci_dev(d);
3070         struct pch_udc_dev *dev = pci_get_drvdata(pdev);
3071
3072         pch_udc_disable_interrupts(dev, UDC_DEVINT_MSK);
3073         pch_udc_disable_ep_interrupts(dev, UDC_EPINT_MSK_DISABLE_ALL);
3074
3075         return 0;
3076 }
3077
3078 static int pch_udc_resume(struct device *d)
3079 {
3080         return 0;
3081 }
3082
3083 static SIMPLE_DEV_PM_OPS(pch_udc_pm, pch_udc_suspend, pch_udc_resume);
3084 #define PCH_UDC_PM_OPS          (&pch_udc_pm)
3085 #else
3086 #define PCH_UDC_PM_OPS          NULL
3087 #endif /* CONFIG_PM_SLEEP */
3088
3089 static int pch_udc_probe(struct pci_dev *pdev,
3090                           const struct pci_device_id *id)
3091 {
3092         int                     bar;
3093         int                     retval;
3094         struct pch_udc_dev      *dev;
3095
3096         /* init */
3097         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
3098         if (!dev)
3099                 return -ENOMEM;
3100
3101         /* pci setup */
3102         retval = pcim_enable_device(pdev);
3103         if (retval)
3104                 return retval;
3105
3106         pci_set_drvdata(pdev, dev);
3107
3108         /* Determine BAR based on PCI ID */
3109         if (id->device == PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC)
3110                 bar = PCH_UDC_PCI_BAR_QUARK_X1000;
3111         else
3112                 bar = PCH_UDC_PCI_BAR;
3113
3114         /* PCI resource allocation */
3115         retval = pcim_iomap_regions(pdev, 1 << bar, pci_name(pdev));
3116         if (retval)
3117                 return retval;
3118
3119         dev->base_addr = pcim_iomap_table(pdev)[bar];
3120
3121         /* initialize the hardware */
3122         if (pch_udc_pcd_init(dev))
3123                 return -ENODEV;
3124
3125         pci_enable_msi(pdev);
3126
3127         retval = devm_request_irq(&pdev->dev, pdev->irq, pch_udc_isr,
3128                                   IRQF_SHARED, KBUILD_MODNAME, dev);
3129         if (retval) {
3130                 dev_err(&pdev->dev, "%s: request_irq(%d) fail\n", __func__,
3131                         pdev->irq);
3132                 goto finished;
3133         }
3134
3135         pci_set_master(pdev);
3136         pci_try_set_mwi(pdev);
3137
3138         /* device struct setup */
3139         spin_lock_init(&dev->lock);
3140         dev->pdev = pdev;
3141         dev->gadget.ops = &pch_udc_ops;
3142
3143         retval = init_dma_pools(dev);
3144         if (retval)
3145                 goto finished;
3146
3147         dev->gadget.name = KBUILD_MODNAME;
3148         dev->gadget.max_speed = USB_SPEED_HIGH;
3149
3150         /* Put the device in disconnected state till a driver is bound */
3151         pch_udc_set_disconnect(dev);
3152         retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
3153         if (retval)
3154                 goto finished;
3155         return 0;
3156
3157 finished:
3158         pch_udc_remove(pdev);
3159         return retval;
3160 }
3161
3162 static const struct pci_device_id pch_udc_pcidev_id[] = {
3163         {
3164                 PCI_DEVICE(PCI_VENDOR_ID_INTEL,
3165                            PCI_DEVICE_ID_INTEL_QUARK_X1000_UDC),
3166                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3167                 .class_mask = 0xffffffff,
3168         },
3169         {
3170                 PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EG20T_UDC),
3171                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3172                 .class_mask = 0xffffffff,
3173         },
3174         {
3175                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7213_IOH_UDC),
3176                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3177                 .class_mask = 0xffffffff,
3178         },
3179         {
3180                 PCI_DEVICE(PCI_VENDOR_ID_ROHM, PCI_DEVICE_ID_ML7831_IOH_UDC),
3181                 .class = PCI_CLASS_SERIAL_USB_DEVICE,
3182                 .class_mask = 0xffffffff,
3183         },
3184         { 0 },
3185 };
3186
3187 MODULE_DEVICE_TABLE(pci, pch_udc_pcidev_id);
3188
3189 static struct pci_driver pch_udc_driver = {
3190         .name = KBUILD_MODNAME,
3191         .id_table =     pch_udc_pcidev_id,
3192         .probe =        pch_udc_probe,
3193         .remove =       pch_udc_remove,
3194         .shutdown =     pch_udc_shutdown,
3195         .driver = {
3196                 .pm = PCH_UDC_PM_OPS,
3197         },
3198 };
3199
3200 module_pci_driver(pch_udc_driver);
3201
3202 MODULE_DESCRIPTION("Intel EG20T USB Device Controller");
3203 MODULE_AUTHOR("LAPIS Semiconductor, <tomoya-linux@dsn.lapis-semi.com>");
3204 MODULE_LICENSE("GPL");