drivers/usb/gadget/udc/snps_udc_core.c

   1 /*
   2  * amd5536.c -- AMD 5536 UDC high/full speed USB device controller
   3  *
   4  * Copyright (C) 2005-2007 AMD (http://www.amd.com)
   5  * Author: Thomas Dahlmann
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 /*
  14  * This file does the core driver implementation for the UDC that is based
  15  * on Synopsys device controller IP (different than HS OTG IP) that is either
  16  * connected through PCI bus or integrated to SoC platforms.
  17  */
  18
  19 /* Driver strings */
  20 #define UDC_MOD_DESCRIPTION             "Synopsys USB Device Controller"
  21 #define UDC_DRIVER_VERSION_STRING       "01.00.0206"
  22
  23 #include <linux/module.h>
  24 #include <linux/pci.h>
  25 #include <linux/kernel.h>
  26 #include <linux/delay.h>
  27 #include <linux/ioport.h>
  28 #include <linux/sched.h>
  29 #include <linux/slab.h>
  30 #include <linux/errno.h>
  31 #include <linux/timer.h>
  32 #include <linux/list.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ioctl.h>
  35 #include <linux/fs.h>
  36 #include <linux/dmapool.h>
  37 #include <linux/prefetch.h>
  38 #include <linux/moduleparam.h>
  39 #include <asm/byteorder.h>
  40 #include <asm/unaligned.h>
  41 #include "amd5536udc.h"
  42
  43 static void udc_tasklet_disconnect(unsigned long);
  44 static void udc_setup_endpoints(struct udc *dev);
  45 static void udc_soft_reset(struct udc *dev);
  46 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep);
  47 static void udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq);
  48
  49 /* description */
  50 static const char mod_desc[] = UDC_MOD_DESCRIPTION;
  51 static const char name[] = "udc";
  52
  53 /* structure to hold endpoint function pointers */
  54 static const struct usb_ep_ops udc_ep_ops;
  55
  56 /* received setup data */
  57 static union udc_setup_data setup_data;
  58
  59 /* pointer to device object */
  60 static struct udc *udc;
  61
  62 /* irq spin lock for soft reset */
  63 static DEFINE_SPINLOCK(udc_irq_spinlock);
  64 /* stall spin lock */
  65 static DEFINE_SPINLOCK(udc_stall_spinlock);
  66
  67 /*
  68 * slave mode: pending bytes in rx fifo after nyet,
  69 * used if EPIN irq came but no req was available
  70 */
  71 static unsigned int udc_rxfifo_pending;
  72
  73 /* count soft resets after suspend to avoid loop */
  74 static int soft_reset_occured;
  75 static int soft_reset_after_usbreset_occured;
  76
  77 /* timer */
  78 static struct timer_list udc_timer;
  79 static int stop_timer;
  80
  81 /* set_rde -- Is used to control enabling of RX DMA. Problem is
  82  * that UDC has only one bit (RDE) to enable/disable RX DMA for
  83  * all OUT endpoints. So we have to handle race conditions like
  84  * when OUT data reaches the fifo but no request was queued yet.
  85  * This cannot be solved by letting the RX DMA disabled until a
  86  * request gets queued because there may be other OUT packets
  87  * in the FIFO (important for not blocking control traffic).
  88  * The value of set_rde controls the correspondig timer.
  89  *
  90  * set_rde -1 == not used, means it is alloed to be set to 0 or 1
  91  * set_rde  0 == do not touch RDE, do no start the RDE timer
  92  * set_rde  1 == timer function will look whether FIFO has data
  93  * set_rde  2 == set by timer function to enable RX DMA on next call
  94  */
  95 static int set_rde = -1;
  96
  97 static DECLARE_COMPLETION(on_exit);
  98 static struct timer_list udc_pollstall_timer;
  99 static int stop_pollstall_timer;
 100 static DECLARE_COMPLETION(on_pollstall_exit);
 101
 102 /* tasklet for usb disconnect */
 103 static DECLARE_TASKLET(disconnect_tasklet, udc_tasklet_disconnect,
 104                 (unsigned long) &udc);
 105
 106
 107 /* endpoint names used for print */
 108 static const char ep0_string[] = "ep0in";
 109 static const struct {
 110         const char *name;
 111         const struct usb_ep_caps caps;
 112 } ep_info[] = {
 113 #define EP_INFO(_name, _caps) \
 114         { \
 115                 .name = _name, \
 116                 .caps = _caps, \
 117         }
 118
 119         EP_INFO(ep0_string,
 120                 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_IN)),
 121         EP_INFO("ep1in-int",
 122                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 123         EP_INFO("ep2in-bulk",
 124                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 125         EP_INFO("ep3in-bulk",
 126                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 127         EP_INFO("ep4in-bulk",
 128                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 129         EP_INFO("ep5in-bulk",
 130                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 131         EP_INFO("ep6in-bulk",
 132                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 133         EP_INFO("ep7in-bulk",
 134                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 135         EP_INFO("ep8in-bulk",
 136                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 137         EP_INFO("ep9in-bulk",
 138                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 139         EP_INFO("ep10in-bulk",
 140                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 141         EP_INFO("ep11in-bulk",
 142                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 143         EP_INFO("ep12in-bulk",
 144                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 145         EP_INFO("ep13in-bulk",
 146                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 147         EP_INFO("ep14in-bulk",
 148                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 149         EP_INFO("ep15in-bulk",
 150                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_IN)),
 151         EP_INFO("ep0out",
 152                 USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL, USB_EP_CAPS_DIR_OUT)),
 153         EP_INFO("ep1out-bulk",
 154                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 155         EP_INFO("ep2out-bulk",
 156                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 157         EP_INFO("ep3out-bulk",
 158                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 159         EP_INFO("ep4out-bulk",
 160                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 161         EP_INFO("ep5out-bulk",
 162                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 163         EP_INFO("ep6out-bulk",
 164                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 165         EP_INFO("ep7out-bulk",
 166                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 167         EP_INFO("ep8out-bulk",
 168                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 169         EP_INFO("ep9out-bulk",
 170                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 171         EP_INFO("ep10out-bulk",
 172                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 173         EP_INFO("ep11out-bulk",
 174                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 175         EP_INFO("ep12out-bulk",
 176                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 177         EP_INFO("ep13out-bulk",
 178                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 179         EP_INFO("ep14out-bulk",
 180                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 181         EP_INFO("ep15out-bulk",
 182                 USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK, USB_EP_CAPS_DIR_OUT)),
 183
 184 #undef EP_INFO
 185 };
 186
 187 /* buffer fill mode */
 188 static int use_dma_bufferfill_mode;
 189 /* tx buffer size for high speed */
 190 static unsigned long hs_tx_buf = UDC_EPIN_BUFF_SIZE;
 191
 192 /*---------------------------------------------------------------------------*/
 193 /* Prints UDC device registers and endpoint irq registers */
 194 static void print_regs(struct udc *dev)
 195 {
 196         DBG(dev, "------- Device registers -------\n");
 197         DBG(dev, "dev config     = %08x\n", readl(&dev->regs->cfg));
 198         DBG(dev, "dev control    = %08x\n", readl(&dev->regs->ctl));
 199         DBG(dev, "dev status     = %08x\n", readl(&dev->regs->sts));
 200         DBG(dev, "\n");
 201         DBG(dev, "dev int's      = %08x\n", readl(&dev->regs->irqsts));
 202         DBG(dev, "dev intmask    = %08x\n", readl(&dev->regs->irqmsk));
 203         DBG(dev, "\n");
 204         DBG(dev, "dev ep int's   = %08x\n", readl(&dev->regs->ep_irqsts));
 205         DBG(dev, "dev ep intmask = %08x\n", readl(&dev->regs->ep_irqmsk));
 206         DBG(dev, "\n");
 207         DBG(dev, "USE DMA        = %d\n", use_dma);
 208         if (use_dma && use_dma_ppb && !use_dma_ppb_du) {
 209                 DBG(dev, "DMA mode       = PPBNDU (packet per buffer "
 210                         "WITHOUT desc. update)\n");
 211                 dev_info(dev->dev, "DMA mode (%s)\n", "PPBNDU");
 212         } else if (use_dma && use_dma_ppb && use_dma_ppb_du) {
 213                 DBG(dev, "DMA mode       = PPBDU (packet per buffer "
 214                         "WITH desc. update)\n");
 215                 dev_info(dev->dev, "DMA mode (%s)\n", "PPBDU");
 216         }
 217         if (use_dma && use_dma_bufferfill_mode) {
 218                 DBG(dev, "DMA mode       = BF (buffer fill mode)\n");
 219                 dev_info(dev->dev, "DMA mode (%s)\n", "BF");
 220         }
 221         if (!use_dma)
 222                 dev_info(dev->dev, "FIFO mode\n");
 223         DBG(dev, "-------------------------------------------------------\n");
 224 }
 225
 226 /* Masks unused interrupts */
 227 int udc_mask_unused_interrupts(struct udc *dev)
 228 {
 229         u32 tmp;
 230
 231         /* mask all dev interrupts */
 232         tmp =   AMD_BIT(UDC_DEVINT_SVC) |
 233                 AMD_BIT(UDC_DEVINT_ENUM) |
 234                 AMD_BIT(UDC_DEVINT_US) |
 235                 AMD_BIT(UDC_DEVINT_UR) |
 236                 AMD_BIT(UDC_DEVINT_ES) |
 237                 AMD_BIT(UDC_DEVINT_SI) |
 238                 AMD_BIT(UDC_DEVINT_SOF)|
 239                 AMD_BIT(UDC_DEVINT_SC);
 240         writel(tmp, &dev->regs->irqmsk);
 241
 242         /* mask all ep interrupts */
 243         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqmsk);
 244
 245         return 0;
 246 }
 247 EXPORT_SYMBOL_GPL(udc_mask_unused_interrupts);
 248
 249 /* Enables endpoint 0 interrupts */
 250 static int udc_enable_ep0_interrupts(struct udc *dev)
 251 {
 252         u32 tmp;
 253
 254         DBG(dev, "udc_enable_ep0_interrupts()\n");
 255
 256         /* read irq mask */
 257         tmp = readl(&dev->regs->ep_irqmsk);
 258         /* enable ep0 irq's */
 259         tmp &= AMD_UNMASK_BIT(UDC_EPINT_IN_EP0)
 260                 & AMD_UNMASK_BIT(UDC_EPINT_OUT_EP0);
 261         writel(tmp, &dev->regs->ep_irqmsk);
 262
 263         return 0;
 264 }
 265
 266 /* Enables device interrupts for SET_INTF and SET_CONFIG */
 267 int udc_enable_dev_setup_interrupts(struct udc *dev)
 268 {
 269         u32 tmp;
 270
 271         DBG(dev, "enable device interrupts for setup data\n");
 272
 273         /* read irq mask */
 274         tmp = readl(&dev->regs->irqmsk);
 275
 276         /* enable SET_INTERFACE, SET_CONFIG and other needed irq's */
 277         tmp &= AMD_UNMASK_BIT(UDC_DEVINT_SI)
 278                 & AMD_UNMASK_BIT(UDC_DEVINT_SC)
 279                 & AMD_UNMASK_BIT(UDC_DEVINT_UR)
 280                 & AMD_UNMASK_BIT(UDC_DEVINT_SVC)
 281                 & AMD_UNMASK_BIT(UDC_DEVINT_ENUM);
 282         writel(tmp, &dev->regs->irqmsk);
 283
 284         return 0;
 285 }
 286 EXPORT_SYMBOL_GPL(udc_enable_dev_setup_interrupts);
 287
 288 /* Calculates fifo start of endpoint based on preceding endpoints */
 289 static int udc_set_txfifo_addr(struct udc_ep *ep)
 290 {
 291         struct udc      *dev;
 292         u32 tmp;
 293         int i;
 294
 295         if (!ep || !(ep->in))
 296                 return -EINVAL;
 297
 298         dev = ep->dev;
 299         ep->txfifo = dev->txfifo;
 300
 301         /* traverse ep's */
 302         for (i = 0; i < ep->num; i++) {
 303                 if (dev->ep[i].regs) {
 304                         /* read fifo size */
 305                         tmp = readl(&dev->ep[i].regs->bufin_framenum);
 306                         tmp = AMD_GETBITS(tmp, UDC_EPIN_BUFF_SIZE);
 307                         ep->txfifo += tmp;
 308                 }
 309         }
 310         return 0;
 311 }
 312
 313 /* CNAK pending field: bit0 = ep0in, bit16 = ep0out */
 314 static u32 cnak_pending;
 315
 316 static void UDC_QUEUE_CNAK(struct udc_ep *ep, unsigned num)
 317 {
 318         if (readl(&ep->regs->ctl) & AMD_BIT(UDC_EPCTL_NAK)) {
 319                 DBG(ep->dev, "NAK could not be cleared for ep%d\n", num);
 320                 cnak_pending |= 1 << (num);
 321                 ep->naking = 1;
 322         } else
 323                 cnak_pending = cnak_pending & (~(1 << (num)));
 324 }
 325
 326
 327 /* Enables endpoint, is called by gadget driver */
 328 static int
 329 udc_ep_enable(struct usb_ep *usbep, const struct usb_endpoint_descriptor *desc)
 330 {
 331         struct udc_ep           *ep;
 332         struct udc              *dev;
 333         u32                     tmp;
 334         unsigned long           iflags;
 335         u8 udc_csr_epix;
 336         unsigned                maxpacket;
 337
 338         if (!usbep
 339                         || usbep->name == ep0_string
 340                         || !desc
 341                         || desc->bDescriptorType != USB_DT_ENDPOINT)
 342                 return -EINVAL;
 343
 344         ep = container_of(usbep, struct udc_ep, ep);
 345         dev = ep->dev;
 346
 347         DBG(dev, "udc_ep_enable() ep %d\n", ep->num);
 348
 349         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
 350                 return -ESHUTDOWN;
 351
 352         spin_lock_irqsave(&dev->lock, iflags);
 353         ep->ep.desc = desc;
 354
 355         ep->halted = 0;
 356
 357         /* set traffic type */
 358         tmp = readl(&dev->ep[ep->num].regs->ctl);
 359         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_EPCTL_ET);
 360         writel(tmp, &dev->ep[ep->num].regs->ctl);
 361
 362         /* set max packet size */
 363         maxpacket = usb_endpoint_maxp(desc);
 364         tmp = readl(&dev->ep[ep->num].regs->bufout_maxpkt);
 365         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_EP_MAX_PKT_SIZE);
 366         ep->ep.maxpacket = maxpacket;
 367         writel(tmp, &dev->ep[ep->num].regs->bufout_maxpkt);
 368
 369         /* IN ep */
 370         if (ep->in) {
 371
 372                 /* ep ix in UDC CSR register space */
 373                 udc_csr_epix = ep->num;
 374
 375                 /* set buffer size (tx fifo entries) */
 376                 tmp = readl(&dev->ep[ep->num].regs->bufin_framenum);
 377                 /* double buffering: fifo size = 2 x max packet size */
 378                 tmp = AMD_ADDBITS(
 379                                 tmp,
 380                                 maxpacket * UDC_EPIN_BUFF_SIZE_MULT
 381                                           / UDC_DWORD_BYTES,
 382                                 UDC_EPIN_BUFF_SIZE);
 383                 writel(tmp, &dev->ep[ep->num].regs->bufin_framenum);
 384
 385                 /* calc. tx fifo base addr */
 386                 udc_set_txfifo_addr(ep);
 387
 388                 /* flush fifo */
 389                 tmp = readl(&ep->regs->ctl);
 390                 tmp |= AMD_BIT(UDC_EPCTL_F);
 391                 writel(tmp, &ep->regs->ctl);
 392
 393         /* OUT ep */
 394         } else {
 395                 /* ep ix in UDC CSR register space */
 396                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
 397
 398                 /* set max packet size UDC CSR  */
 399                 tmp = readl(&dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 400                 tmp = AMD_ADDBITS(tmp, maxpacket,
 401                                         UDC_CSR_NE_MAX_PKT);
 402                 writel(tmp, &dev->csr->ne[ep->num - UDC_CSR_EP_OUT_IX_OFS]);
 403
 404                 if (use_dma && !ep->in) {
 405                         /* alloc and init BNA dummy request */
 406                         ep->bna_dummy_req = udc_alloc_bna_dummy(ep);
 407                         ep->bna_occurred = 0;
 408                 }
 409
 410                 if (ep->num != UDC_EP0OUT_IX)
 411                         dev->data_ep_enabled = 1;
 412         }
 413
 414         /* set ep values */
 415         tmp = readl(&dev->csr->ne[udc_csr_epix]);
 416         /* max packet */
 417         tmp = AMD_ADDBITS(tmp, maxpacket, UDC_CSR_NE_MAX_PKT);
 418         /* ep number */
 419         tmp = AMD_ADDBITS(tmp, desc->bEndpointAddress, UDC_CSR_NE_NUM);
 420         /* ep direction */
 421         tmp = AMD_ADDBITS(tmp, ep->in, UDC_CSR_NE_DIR);
 422         /* ep type */
 423         tmp = AMD_ADDBITS(tmp, desc->bmAttributes, UDC_CSR_NE_TYPE);
 424         /* ep config */
 425         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config, UDC_CSR_NE_CFG);
 426         /* ep interface */
 427         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf, UDC_CSR_NE_INTF);
 428         /* ep alt */
 429         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt, UDC_CSR_NE_ALT);
 430         /* write reg */
 431         writel(tmp, &dev->csr->ne[udc_csr_epix]);
 432
 433         /* enable ep irq */
 434         tmp = readl(&dev->regs->ep_irqmsk);
 435         tmp &= AMD_UNMASK_BIT(ep->num);
 436         writel(tmp, &dev->regs->ep_irqmsk);
 437
 438         /*
 439          * clear NAK by writing CNAK
 440          * avoid BNA for OUT DMA, don't clear NAK until DMA desc. written
 441          */
 442         if (!use_dma || ep->in) {
 443                 tmp = readl(&ep->regs->ctl);
 444                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 445                 writel(tmp, &ep->regs->ctl);
 446                 ep->naking = 0;
 447                 UDC_QUEUE_CNAK(ep, ep->num);
 448         }
 449         tmp = desc->bEndpointAddress;
 450         DBG(dev, "%s enabled\n", usbep->name);
 451
 452         spin_unlock_irqrestore(&dev->lock, iflags);
 453         return 0;
 454 }
 455
 456 /* Resets endpoint */
 457 static void ep_init(struct udc_regs __iomem *regs, struct udc_ep *ep)
 458 {
 459         u32             tmp;
 460
 461         VDBG(ep->dev, "ep-%d reset\n", ep->num);
 462         ep->ep.desc = NULL;
 463         ep->ep.ops = &udc_ep_ops;
 464         INIT_LIST_HEAD(&ep->queue);
 465
 466         usb_ep_set_maxpacket_limit(&ep->ep,(u16) ~0);
 467         /* set NAK */
 468         tmp = readl(&ep->regs->ctl);
 469         tmp |= AMD_BIT(UDC_EPCTL_SNAK);
 470         writel(tmp, &ep->regs->ctl);
 471         ep->naking = 1;
 472
 473         /* disable interrupt */
 474         tmp = readl(&regs->ep_irqmsk);
 475         tmp |= AMD_BIT(ep->num);
 476         writel(tmp, &regs->ep_irqmsk);
 477
 478         if (ep->in) {
 479                 /* unset P and IN bit of potential former DMA */
 480                 tmp = readl(&ep->regs->ctl);
 481                 tmp &= AMD_UNMASK_BIT(UDC_EPCTL_P);
 482                 writel(tmp, &ep->regs->ctl);
 483
 484                 tmp = readl(&ep->regs->sts);
 485                 tmp |= AMD_BIT(UDC_EPSTS_IN);
 486                 writel(tmp, &ep->regs->sts);
 487
 488                 /* flush the fifo */
 489                 tmp = readl(&ep->regs->ctl);
 490                 tmp |= AMD_BIT(UDC_EPCTL_F);
 491                 writel(tmp, &ep->regs->ctl);
 492
 493         }
 494         /* reset desc pointer */
 495         writel(0, &ep->regs->desptr);
 496 }
 497
 498 /* Disables endpoint, is called by gadget driver */
 499 static int udc_ep_disable(struct usb_ep *usbep)
 500 {
 501         struct udc_ep   *ep = NULL;
 502         unsigned long   iflags;
 503
 504         if (!usbep)
 505                 return -EINVAL;
 506
 507         ep = container_of(usbep, struct udc_ep, ep);
 508         if (usbep->name == ep0_string || !ep->ep.desc)
 509                 return -EINVAL;
 510
 511         DBG(ep->dev, "Disable ep-%d\n", ep->num);
 512
 513         spin_lock_irqsave(&ep->dev->lock, iflags);
 514         udc_free_request(&ep->ep, &ep->bna_dummy_req->req);
 515         empty_req_queue(ep);
 516         ep_init(ep->dev->regs, ep);
 517         spin_unlock_irqrestore(&ep->dev->lock, iflags);
 518
 519         return 0;
 520 }
 521
 522 /* Allocates request packet, called by gadget driver */
 523 static struct usb_request *
 524 udc_alloc_request(struct usb_ep *usbep, gfp_t gfp)
 525 {
 526         struct udc_request      *req;
 527         struct udc_data_dma     *dma_desc;
 528         struct udc_ep   *ep;
 529
 530         if (!usbep)
 531                 return NULL;
 532
 533         ep = container_of(usbep, struct udc_ep, ep);
 534
 535         VDBG(ep->dev, "udc_alloc_req(): ep%d\n", ep->num);
 536         req = kzalloc(sizeof(struct udc_request), gfp);
 537         if (!req)
 538                 return NULL;
 539
 540         req->req.dma = DMA_DONT_USE;
 541         INIT_LIST_HEAD(&req->queue);
 542
 543         if (ep->dma) {
 544                 /* ep0 in requests are allocated from data pool here */
 545                 dma_desc = dma_pool_alloc(ep->dev->data_requests, gfp,
 546                                                 &req->td_phys);
 547                 if (!dma_desc) {
 548                         kfree(req);
 549                         return NULL;
 550                 }
 551
 552                 VDBG(ep->dev, "udc_alloc_req: req = %p dma_desc = %p, "
 553                                 "td_phys = %lx\n",
 554                                 req, dma_desc,
 555                                 (unsigned long)req->td_phys);
 556                 /* prevent from using desc. - set HOST BUSY */
 557                 dma_desc->status = AMD_ADDBITS(dma_desc->status,
 558                                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 559                                                 UDC_DMA_STP_STS_BS);
 560                 dma_desc->bufptr = cpu_to_le32(DMA_DONT_USE);
 561                 req->td_data = dma_desc;
 562                 req->td_data_last = NULL;
 563                 req->chain_len = 1;
 564         }
 565
 566         return &req->req;
 567 }
 568
 569 /* frees pci pool descriptors of a DMA chain */
 570 static void udc_free_dma_chain(struct udc *dev, struct udc_request *req)
 571 {
 572         struct udc_data_dma *td = req->td_data;
 573         unsigned int i;
 574
 575         dma_addr_t addr_next = 0x00;
 576         dma_addr_t addr = (dma_addr_t)td->next;
 577
 578         DBG(dev, "free chain req = %p\n", req);
 579
 580         /* do not free first desc., will be done by free for request */
 581         for (i = 1; i < req->chain_len; i++) {
 582                 td = phys_to_virt(addr);
 583                 addr_next = (dma_addr_t)td->next;
 584                 dma_pool_free(dev->data_requests, td, addr);
 585                 addr = addr_next;
 586         }
 587 }
 588
 589 /* Frees request packet, called by gadget driver */
 590 static void
 591 udc_free_request(struct usb_ep *usbep, struct usb_request *usbreq)
 592 {
 593         struct udc_ep   *ep;
 594         struct udc_request      *req;
 595
 596         if (!usbep || !usbreq)
 597                 return;
 598
 599         ep = container_of(usbep, struct udc_ep, ep);
 600         req = container_of(usbreq, struct udc_request, req);
 601         VDBG(ep->dev, "free_req req=%p\n", req);
 602         BUG_ON(!list_empty(&req->queue));
 603         if (req->td_data) {
 604                 VDBG(ep->dev, "req->td_data=%p\n", req->td_data);
 605
 606                 /* free dma chain if created */
 607                 if (req->chain_len > 1)
 608                         udc_free_dma_chain(ep->dev, req);
 609
 610                 dma_pool_free(ep->dev->data_requests, req->td_data,
 611                                                         req->td_phys);
 612         }
 613         kfree(req);
 614 }
 615
 616 /* Init BNA dummy descriptor for HOST BUSY and pointing to itself */
 617 static void udc_init_bna_dummy(struct udc_request *req)
 618 {
 619         if (req) {
 620                 /* set last bit */
 621                 req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 622                 /* set next pointer to itself */
 623                 req->td_data->next = req->td_phys;
 624                 /* set HOST BUSY */
 625                 req->td_data->status
 626                         = AMD_ADDBITS(req->td_data->status,
 627                                         UDC_DMA_STP_STS_BS_DMA_DONE,
 628                                         UDC_DMA_STP_STS_BS);
 629 #ifdef UDC_VERBOSE
 630                 pr_debug("bna desc = %p, sts = %08x\n",
 631                         req->td_data, req->td_data->status);
 632 #endif
 633         }
 634 }
 635
 636 /* Allocate BNA dummy descriptor */
 637 static struct udc_request *udc_alloc_bna_dummy(struct udc_ep *ep)
 638 {
 639         struct udc_request *req = NULL;
 640         struct usb_request *_req = NULL;
 641
 642         /* alloc the dummy request */
 643         _req = udc_alloc_request(&ep->ep, GFP_ATOMIC);
 644         if (_req) {
 645                 req = container_of(_req, struct udc_request, req);
 646                 ep->bna_dummy_req = req;
 647                 udc_init_bna_dummy(req);
 648         }
 649         return req;
 650 }
 651
 652 /* Write data to TX fifo for IN packets */
 653 static void
 654 udc_txfifo_write(struct udc_ep *ep, struct usb_request *req)
 655 {
 656         u8                      *req_buf;
 657         u32                     *buf;
 658         int                     i, j;
 659         unsigned                bytes = 0;
 660         unsigned                remaining = 0;
 661
 662         if (!req || !ep)
 663                 return;
 664
 665         req_buf = req->buf + req->actual;
 666         prefetch(req_buf);
 667         remaining = req->length - req->actual;
 668
 669         buf = (u32 *) req_buf;
 670
 671         bytes = ep->ep.maxpacket;
 672         if (bytes > remaining)
 673                 bytes = remaining;
 674
 675         /* dwords first */
 676         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
 677                 writel(*(buf + i), ep->txfifo);
 678
 679         /* remaining bytes must be written by byte access */
 680         for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 681                 writeb((u8)(*(buf + i) >> (j << UDC_BITS_PER_BYTE_SHIFT)),
 682                                                         ep->txfifo);
 683         }
 684
 685         /* dummy write confirm */
 686         writel(0, &ep->regs->confirm);
 687 }
 688
 689 /* Read dwords from RX fifo for OUT transfers */
 690 static int udc_rxfifo_read_dwords(struct udc *dev, u32 *buf, int dwords)
 691 {
 692         int i;
 693
 694         VDBG(dev, "udc_read_dwords(): %d dwords\n", dwords);
 695
 696         for (i = 0; i < dwords; i++)
 697                 *(buf + i) = readl(dev->rxfifo);
 698         return 0;
 699 }
 700
 701 /* Read bytes from RX fifo for OUT transfers */
 702 static int udc_rxfifo_read_bytes(struct udc *dev, u8 *buf, int bytes)
 703 {
 704         int i, j;
 705         u32 tmp;
 706
 707         VDBG(dev, "udc_read_bytes(): %d bytes\n", bytes);
 708
 709         /* dwords first */
 710         for (i = 0; i < bytes / UDC_DWORD_BYTES; i++)
 711                 *((u32 *)(buf + (i<<2))) = readl(dev->rxfifo);
 712
 713         /* remaining bytes must be read by byte access */
 714         if (bytes % UDC_DWORD_BYTES) {
 715                 tmp = readl(dev->rxfifo);
 716                 for (j = 0; j < bytes % UDC_DWORD_BYTES; j++) {
 717                         *(buf + (i<<2) + j) = (u8)(tmp & UDC_BYTE_MASK);
 718                         tmp = tmp >> UDC_BITS_PER_BYTE;
 719                 }
 720         }
 721
 722         return 0;
 723 }
 724
 725 /* Read data from RX fifo for OUT transfers */
 726 static int
 727 udc_rxfifo_read(struct udc_ep *ep, struct udc_request *req)
 728 {
 729         u8 *buf;
 730         unsigned buf_space;
 731         unsigned bytes = 0;
 732         unsigned finished = 0;
 733
 734         /* received number bytes */
 735         bytes = readl(&ep->regs->sts);
 736         bytes = AMD_GETBITS(bytes, UDC_EPSTS_RX_PKT_SIZE);
 737
 738         buf_space = req->req.length - req->req.actual;
 739         buf = req->req.buf + req->req.actual;
 740         if (bytes > buf_space) {
 741                 if ((buf_space % ep->ep.maxpacket) != 0) {
 742                         DBG(ep->dev,
 743                                 "%s: rx %d bytes, rx-buf space = %d bytesn\n",
 744                                 ep->ep.name, bytes, buf_space);
 745                         req->req.status = -EOVERFLOW;
 746                 }
 747                 bytes = buf_space;
 748         }
 749         req->req.actual += bytes;
 750
 751         /* last packet ? */
 752         if (((bytes % ep->ep.maxpacket) != 0) || (!bytes)
 753                 || ((req->req.actual == req->req.length) && !req->req.zero))
 754                 finished = 1;
 755
 756         /* read rx fifo bytes */
 757         VDBG(ep->dev, "ep %s: rxfifo read %d bytes\n", ep->ep.name, bytes);
 758         udc_rxfifo_read_bytes(ep->dev, buf, bytes);
 759
 760         return finished;
 761 }
 762
 763 /* Creates or re-inits a DMA chain */
 764 static int udc_create_dma_chain(
 765         struct udc_ep *ep,
 766         struct udc_request *req,
 767         unsigned long buf_len, gfp_t gfp_flags
 768 )
 769 {
 770         unsigned long bytes = req->req.length;
 771         unsigned int i;
 772         dma_addr_t dma_addr;
 773         struct udc_data_dma     *td = NULL;
 774         struct udc_data_dma     *last = NULL;
 775         unsigned long txbytes;
 776         unsigned create_new_chain = 0;
 777         unsigned len;
 778
 779         VDBG(ep->dev, "udc_create_dma_chain: bytes=%ld buf_len=%ld\n",
 780              bytes, buf_len);
 781         dma_addr = DMA_DONT_USE;
 782
 783         /* unset L bit in first desc for OUT */
 784         if (!ep->in)
 785                 req->td_data->status &= AMD_CLEAR_BIT(UDC_DMA_IN_STS_L);
 786
 787         /* alloc only new desc's if not already available */
 788         len = req->req.length / ep->ep.maxpacket;
 789         if (req->req.length % ep->ep.maxpacket)
 790                 len++;
 791
 792         if (len > req->chain_len) {
 793                 /* shorter chain already allocated before */
 794                 if (req->chain_len > 1)
 795                         udc_free_dma_chain(ep->dev, req);
 796                 req->chain_len = len;
 797                 create_new_chain = 1;
 798         }
 799
 800         td = req->td_data;
 801         /* gen. required number of descriptors and buffers */
 802         for (i = buf_len; i < bytes; i += buf_len) {
 803                 /* create or determine next desc. */
 804                 if (create_new_chain) {
 805                         td = dma_pool_alloc(ep->dev->data_requests,
 806                                             gfp_flags, &dma_addr);
 807                         if (!td)
 808                                 return -ENOMEM;
 809
 810                         td->status = 0;
 811                 } else if (i == buf_len) {
 812                         /* first td */
 813                         td = (struct udc_data_dma *)phys_to_virt(
 814                                                 req->td_data->next);
 815                         td->status = 0;
 816                 } else {
 817                         td = (struct udc_data_dma *)phys_to_virt(last->next);
 818                         td->status = 0;
 819                 }
 820
 821                 if (td)
 822                         td->bufptr = req->req.dma + i; /* assign buffer */
 823                 else
 824                         break;
 825
 826                 /* short packet ? */
 827                 if ((bytes - i) >= buf_len) {
 828                         txbytes = buf_len;
 829                 } else {
 830                         /* short packet */
 831                         txbytes = bytes - i;
 832                 }
 833
 834                 /* link td and assign tx bytes */
 835                 if (i == buf_len) {
 836                         if (create_new_chain)
 837                                 req->td_data->next = dma_addr;
 838                         /*
 839                          * else
 840                          *      req->td_data->next = virt_to_phys(td);
 841                          */
 842                         /* write tx bytes */
 843                         if (ep->in) {
 844                                 /* first desc */
 845                                 req->td_data->status =
 846                                         AMD_ADDBITS(req->td_data->status,
 847                                                     ep->ep.maxpacket,
 848                                                     UDC_DMA_IN_STS_TXBYTES);
 849                                 /* second desc */
 850                                 td->status = AMD_ADDBITS(td->status,
 851                                                         txbytes,
 852                                                         UDC_DMA_IN_STS_TXBYTES);
 853                         }
 854                 } else {
 855                         if (create_new_chain)
 856                                 last->next = dma_addr;
 857                         /*
 858                          * else
 859                          *      last->next = virt_to_phys(td);
 860                          */
 861                         if (ep->in) {
 862                                 /* write tx bytes */
 863                                 td->status = AMD_ADDBITS(td->status,
 864                                                         txbytes,
 865                                                         UDC_DMA_IN_STS_TXBYTES);
 866                         }
 867                 }
 868                 last = td;
 869         }
 870         /* set last bit */
 871         if (td) {
 872                 td->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 873                 /* last desc. points to itself */
 874                 req->td_data_last = td;
 875         }
 876
 877         return 0;
 878 }
 879
 880 /* create/re-init a DMA descriptor or a DMA descriptor chain */
 881 static int prep_dma(struct udc_ep *ep, struct udc_request *req, gfp_t gfp)
 882 {
 883         int     retval = 0;
 884         u32     tmp;
 885
 886         VDBG(ep->dev, "prep_dma\n");
 887         VDBG(ep->dev, "prep_dma ep%d req->td_data=%p\n",
 888                         ep->num, req->td_data);
 889
 890         /* set buffer pointer */
 891         req->td_data->bufptr = req->req.dma;
 892
 893         /* set last bit */
 894         req->td_data->status |= AMD_BIT(UDC_DMA_IN_STS_L);
 895
 896         /* build/re-init dma chain if maxpkt scatter mode, not for EP0 */
 897         if (use_dma_ppb) {
 898
 899                 retval = udc_create_dma_chain(ep, req, ep->ep.maxpacket, gfp);
 900                 if (retval != 0) {
 901                         if (retval == -ENOMEM)
 902                                 DBG(ep->dev, "Out of DMA memory\n");
 903                         return retval;
 904                 }
 905                 if (ep->in) {
 906                         if (req->req.length == ep->ep.maxpacket) {
 907                                 /* write tx bytes */
 908                                 req->td_data->status =
 909                                         AMD_ADDBITS(req->td_data->status,
 910                                                 ep->ep.maxpacket,
 911                                                 UDC_DMA_IN_STS_TXBYTES);
 912
 913                         }
 914                 }
 915
 916         }
 917
 918         if (ep->in) {
 919                 VDBG(ep->dev, "IN: use_dma_ppb=%d req->req.len=%d "
 920                                 "maxpacket=%d ep%d\n",
 921                                 use_dma_ppb, req->req.length,
 922                                 ep->ep.maxpacket, ep->num);
 923                 /*
 924                  * if bytes < max packet then tx bytes must
 925                  * be written in packet per buffer mode
 926                  */
 927                 if (!use_dma_ppb || req->req.length < ep->ep.maxpacket
 928                                 || ep->num == UDC_EP0OUT_IX
 929                                 || ep->num == UDC_EP0IN_IX) {
 930                         /* write tx bytes */
 931                         req->td_data->status =
 932                                 AMD_ADDBITS(req->td_data->status,
 933                                                 req->req.length,
 934                                                 UDC_DMA_IN_STS_TXBYTES);
 935                         /* reset frame num */
 936                         req->td_data->status =
 937                                 AMD_ADDBITS(req->td_data->status,
 938                                                 0,
 939                                                 UDC_DMA_IN_STS_FRAMENUM);
 940                 }
 941                 /* set HOST BUSY */
 942                 req->td_data->status =
 943                         AMD_ADDBITS(req->td_data->status,
 944                                 UDC_DMA_STP_STS_BS_HOST_BUSY,
 945                                 UDC_DMA_STP_STS_BS);
 946         } else {
 947                 VDBG(ep->dev, "OUT set host ready\n");
 948                 /* set HOST READY */
 949                 req->td_data->status =
 950                         AMD_ADDBITS(req->td_data->status,
 951                                 UDC_DMA_STP_STS_BS_HOST_READY,
 952                                 UDC_DMA_STP_STS_BS);
 953
 954
 955                         /* clear NAK by writing CNAK */
 956                         if (ep->naking) {
 957                                 tmp = readl(&ep->regs->ctl);
 958                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
 959                                 writel(tmp, &ep->regs->ctl);
 960                                 ep->naking = 0;
 961                                 UDC_QUEUE_CNAK(ep, ep->num);
 962                         }
 963
 964         }
 965
 966         return retval;
 967 }
 968
 969 /* Completes request packet ... caller MUST hold lock */
 970 static void
 971 complete_req(struct udc_ep *ep, struct udc_request *req, int sts)
 972 __releases(ep->dev->lock)
 973 __acquires(ep->dev->lock)
 974 {
 975         struct udc              *dev;
 976         unsigned                halted;
 977
 978         VDBG(ep->dev, "complete_req(): ep%d\n", ep->num);
 979
 980         dev = ep->dev;
 981         /* unmap DMA */
 982         if (ep->dma)
 983                 usb_gadget_unmap_request(&dev->gadget, &req->req, ep->in);
 984
 985         halted = ep->halted;
 986         ep->halted = 1;
 987
 988         /* set new status if pending */
 989         if (req->req.status == -EINPROGRESS)
 990                 req->req.status = sts;
 991
 992         /* remove from ep queue */
 993         list_del_init(&req->queue);
 994
 995         VDBG(ep->dev, "req %p => complete %d bytes at %s with sts %d\n",
 996                 &req->req, req->req.length, ep->ep.name, sts);
 997
 998         spin_unlock(&dev->lock);
 999         usb_gadget_giveback_request(&ep->ep, &req->req);
1000         spin_lock(&dev->lock);
1001         ep->halted = halted;
1002 }
1003
1004 /* Iterates to the end of a DMA chain and returns last descriptor */
1005 static struct udc_data_dma *udc_get_last_dma_desc(struct udc_request *req)
1006 {
1007         struct udc_data_dma     *td;
1008
1009         td = req->td_data;
1010         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L)))
1011                 td = phys_to_virt(td->next);
1012
1013         return td;
1014
1015 }
1016
1017 /* Iterates to the end of a DMA chain and counts bytes received */
1018 static u32 udc_get_ppbdu_rxbytes(struct udc_request *req)
1019 {
1020         struct udc_data_dma     *td;
1021         u32 count;
1022
1023         td = req->td_data;
1024         /* received number bytes */
1025         count = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_RXBYTES);
1026
1027         while (td && !(td->status & AMD_BIT(UDC_DMA_IN_STS_L))) {
1028                 td = phys_to_virt(td->next);
1029                 /* received number bytes */
1030                 if (td) {
1031                         count += AMD_GETBITS(td->status,
1032                                 UDC_DMA_OUT_STS_RXBYTES);
1033                 }
1034         }
1035
1036         return count;
1037
1038 }
1039
1040 /* Enabling RX DMA */
1041 static void udc_set_rde(struct udc *dev)
1042 {
1043         u32 tmp;
1044
1045         VDBG(dev, "udc_set_rde()\n");
1046         /* stop RDE timer */
1047         if (timer_pending(&udc_timer)) {
1048                 set_rde = 0;
1049                 mod_timer(&udc_timer, jiffies - 1);
1050         }
1051         /* set RDE */
1052         tmp = readl(&dev->regs->ctl);
1053         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1054         writel(tmp, &dev->regs->ctl);
1055 }
1056
1057 /* Queues a request packet, called by gadget driver */
1058 static int
1059 udc_queue(struct usb_ep *usbep, struct usb_request *usbreq, gfp_t gfp)
1060 {
1061         int                     retval = 0;
1062         u8                      open_rxfifo = 0;
1063         unsigned long           iflags;
1064         struct udc_ep           *ep;
1065         struct udc_request      *req;
1066         struct udc              *dev;
1067         u32                     tmp;
1068
1069         /* check the inputs */
1070         req = container_of(usbreq, struct udc_request, req);
1071
1072         if (!usbep || !usbreq || !usbreq->complete || !usbreq->buf
1073                         || !list_empty(&req->queue))
1074                 return -EINVAL;
1075
1076         ep = container_of(usbep, struct udc_ep, ep);
1077         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1078                 return -EINVAL;
1079
1080         VDBG(ep->dev, "udc_queue(): ep%d-in=%d\n", ep->num, ep->in);
1081         dev = ep->dev;
1082
1083         if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
1084                 return -ESHUTDOWN;
1085
1086         /* map dma (usually done before) */
1087         if (ep->dma) {
1088                 VDBG(dev, "DMA map req %p\n", req);
1089                 retval = usb_gadget_map_request(&udc->gadget, usbreq, ep->in);
1090                 if (retval)
1091                         return retval;
1092         }
1093
1094         VDBG(dev, "%s queue req %p, len %d req->td_data=%p buf %p\n",
1095                         usbep->name, usbreq, usbreq->length,
1096                         req->td_data, usbreq->buf);
1097
1098         spin_lock_irqsave(&dev->lock, iflags);
1099         usbreq->actual = 0;
1100         usbreq->status = -EINPROGRESS;
1101         req->dma_done = 0;
1102
1103         /* on empty queue just do first transfer */
1104         if (list_empty(&ep->queue)) {
1105                 /* zlp */
1106                 if (usbreq->length == 0) {
1107                         /* IN zlp's are handled by hardware */
1108                         complete_req(ep, req, 0);
1109                         VDBG(dev, "%s: zlp\n", ep->ep.name);
1110                         /*
1111                          * if set_config or set_intf is waiting for ack by zlp
1112                          * then set CSR_DONE
1113                          */
1114                         if (dev->set_cfg_not_acked) {
1115                                 tmp = readl(&dev->regs->ctl);
1116                                 tmp |= AMD_BIT(UDC_DEVCTL_CSR_DONE);
1117                                 writel(tmp, &dev->regs->ctl);
1118                                 dev->set_cfg_not_acked = 0;
1119                         }
1120                         /* setup command is ACK'ed now by zlp */
1121                         if (dev->waiting_zlp_ack_ep0in) {
1122                                 /* clear NAK by writing CNAK in EP0_IN */
1123                                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1124                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1125                                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1126                                 dev->ep[UDC_EP0IN_IX].naking = 0;
1127                                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX],
1128                                                         UDC_EP0IN_IX);
1129                                 dev->waiting_zlp_ack_ep0in = 0;
1130                         }
1131                         goto finished;
1132                 }
1133                 if (ep->dma) {
1134                         retval = prep_dma(ep, req, GFP_ATOMIC);
1135                         if (retval != 0)
1136                                 goto finished;
1137                         /* write desc pointer to enable DMA */
1138                         if (ep->in) {
1139                                 /* set HOST READY */
1140                                 req->td_data->status =
1141                                         AMD_ADDBITS(req->td_data->status,
1142                                                 UDC_DMA_IN_STS_BS_HOST_READY,
1143                                                 UDC_DMA_IN_STS_BS);
1144                         }
1145
1146                         /* disabled rx dma while descriptor update */
1147                         if (!ep->in) {
1148                                 /* stop RDE timer */
1149                                 if (timer_pending(&udc_timer)) {
1150                                         set_rde = 0;
1151                                         mod_timer(&udc_timer, jiffies - 1);
1152                                 }
1153                                 /* clear RDE */
1154                                 tmp = readl(&dev->regs->ctl);
1155                                 tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1156                                 writel(tmp, &dev->regs->ctl);
1157                                 open_rxfifo = 1;
1158
1159                                 /*
1160                                  * if BNA occurred then let BNA dummy desc.
1161                                  * point to current desc.
1162                                  */
1163                                 if (ep->bna_occurred) {
1164                                         VDBG(dev, "copy to BNA dummy desc.\n");
1165                                         memcpy(ep->bna_dummy_req->td_data,
1166                                                 req->td_data,
1167                                                 sizeof(struct udc_data_dma));
1168                                 }
1169                         }
1170                         /* write desc pointer */
1171                         writel(req->td_phys, &ep->regs->desptr);
1172
1173                         /* clear NAK by writing CNAK */
1174                         if (ep->naking) {
1175                                 tmp = readl(&ep->regs->ctl);
1176                                 tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1177                                 writel(tmp, &ep->regs->ctl);
1178                                 ep->naking = 0;
1179                                 UDC_QUEUE_CNAK(ep, ep->num);
1180                         }
1181
1182                         if (ep->in) {
1183                                 /* enable ep irq */
1184                                 tmp = readl(&dev->regs->ep_irqmsk);
1185                                 tmp &= AMD_UNMASK_BIT(ep->num);
1186                                 writel(tmp, &dev->regs->ep_irqmsk);
1187                         }
1188                 } else if (ep->in) {
1189                                 /* enable ep irq */
1190                                 tmp = readl(&dev->regs->ep_irqmsk);
1191                                 tmp &= AMD_UNMASK_BIT(ep->num);
1192                                 writel(tmp, &dev->regs->ep_irqmsk);
1193                         }
1194
1195         } else if (ep->dma) {
1196
1197                 /*
1198                  * prep_dma not used for OUT ep's, this is not possible
1199                  * for PPB modes, because of chain creation reasons
1200                  */
1201                 if (ep->in) {
1202                         retval = prep_dma(ep, req, GFP_ATOMIC);
1203                         if (retval != 0)
1204                                 goto finished;
1205                 }
1206         }
1207         VDBG(dev, "list_add\n");
1208         /* add request to ep queue */
1209         if (req) {
1210
1211                 list_add_tail(&req->queue, &ep->queue);
1212
1213                 /* open rxfifo if out data queued */
1214                 if (open_rxfifo) {
1215                         /* enable DMA */
1216                         req->dma_going = 1;
1217                         udc_set_rde(dev);
1218                         if (ep->num != UDC_EP0OUT_IX)
1219                                 dev->data_ep_queued = 1;
1220                 }
1221                 /* stop OUT naking */
1222                 if (!ep->in) {
1223                         if (!use_dma && udc_rxfifo_pending) {
1224                                 DBG(dev, "udc_queue(): pending bytes in "
1225                                         "rxfifo after nyet\n");
1226                                 /*
1227                                  * read pending bytes afer nyet:
1228                                  * referring to isr
1229                                  */
1230                                 if (udc_rxfifo_read(ep, req)) {
1231                                         /* finish */
1232                                         complete_req(ep, req, 0);
1233                                 }
1234                                 udc_rxfifo_pending = 0;
1235
1236                         }
1237                 }
1238         }
1239
1240 finished:
1241         spin_unlock_irqrestore(&dev->lock, iflags);
1242         return retval;
1243 }
1244
1245 /* Empty request queue of an endpoint; caller holds spinlock */
1246 void empty_req_queue(struct udc_ep *ep)
1247 {
1248         struct udc_request      *req;
1249
1250         ep->halted = 1;
1251         while (!list_empty(&ep->queue)) {
1252                 req = list_entry(ep->queue.next,
1253                         struct udc_request,
1254                         queue);
1255                 complete_req(ep, req, -ESHUTDOWN);
1256         }
1257 }
1258 EXPORT_SYMBOL_GPL(empty_req_queue);
1259
1260 /* Dequeues a request packet, called by gadget driver */
1261 static int udc_dequeue(struct usb_ep *usbep, struct usb_request *usbreq)
1262 {
1263         struct udc_ep           *ep;
1264         struct udc_request      *req;
1265         unsigned                halted;
1266         unsigned long           iflags;
1267
1268         ep = container_of(usbep, struct udc_ep, ep);
1269         if (!usbep || !usbreq || (!ep->ep.desc && (ep->num != 0
1270                                 && ep->num != UDC_EP0OUT_IX)))
1271                 return -EINVAL;
1272
1273         req = container_of(usbreq, struct udc_request, req);
1274
1275         spin_lock_irqsave(&ep->dev->lock, iflags);
1276         halted = ep->halted;
1277         ep->halted = 1;
1278         /* request in processing or next one */
1279         if (ep->queue.next == &req->queue) {
1280                 if (ep->dma && req->dma_going) {
1281                         if (ep->in)
1282                                 ep->cancel_transfer = 1;
1283                         else {
1284                                 u32 tmp;
1285                                 u32 dma_sts;
1286                                 /* stop potential receive DMA */
1287                                 tmp = readl(&udc->regs->ctl);
1288                                 writel(tmp & AMD_UNMASK_BIT(UDC_DEVCTL_RDE),
1289                                                         &udc->regs->ctl);
1290                                 /*
1291                                  * Cancel transfer later in ISR
1292                                  * if descriptor was touched.
1293                                  */
1294                                 dma_sts = AMD_GETBITS(req->td_data->status,
1295                                                         UDC_DMA_OUT_STS_BS);
1296                                 if (dma_sts != UDC_DMA_OUT_STS_BS_HOST_READY)
1297                                         ep->cancel_transfer = 1;
1298                                 else {
1299                                         udc_init_bna_dummy(ep->req);
1300                                         writel(ep->bna_dummy_req->td_phys,
1301                                                 &ep->regs->desptr);
1302                                 }
1303                                 writel(tmp, &udc->regs->ctl);
1304                         }
1305                 }
1306         }
1307         complete_req(ep, req, -ECONNRESET);
1308         ep->halted = halted;
1309
1310         spin_unlock_irqrestore(&ep->dev->lock, iflags);
1311         return 0;
1312 }
1313
1314 /* Halt or clear halt of endpoint */
1315 static int
1316 udc_set_halt(struct usb_ep *usbep, int halt)
1317 {
1318         struct udc_ep   *ep;
1319         u32 tmp;
1320         unsigned long iflags;
1321         int retval = 0;
1322
1323         if (!usbep)
1324                 return -EINVAL;
1325
1326         pr_debug("set_halt %s: halt=%d\n", usbep->name, halt);
1327
1328         ep = container_of(usbep, struct udc_ep, ep);
1329         if (!ep->ep.desc && (ep->num != 0 && ep->num != UDC_EP0OUT_IX))
1330                 return -EINVAL;
1331         if (!ep->dev->driver || ep->dev->gadget.speed == USB_SPEED_UNKNOWN)
1332                 return -ESHUTDOWN;
1333
1334         spin_lock_irqsave(&udc_stall_spinlock, iflags);
1335         /* halt or clear halt */
1336         if (halt) {
1337                 if (ep->num == 0)
1338                         ep->dev->stall_ep0in = 1;
1339                 else {
1340                         /*
1341                          * set STALL
1342                          * rxfifo empty not taken into acount
1343                          */
1344                         tmp = readl(&ep->regs->ctl);
1345                         tmp |= AMD_BIT(UDC_EPCTL_S);
1346                         writel(tmp, &ep->regs->ctl);
1347                         ep->halted = 1;
1348
1349                         /* setup poll timer */
1350                         if (!timer_pending(&udc_pollstall_timer)) {
1351                                 udc_pollstall_timer.expires = jiffies +
1352                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1353                                         / (1000 * 1000);
1354                                 if (!stop_pollstall_timer) {
1355                                         DBG(ep->dev, "start polltimer\n");
1356                                         add_timer(&udc_pollstall_timer);
1357                                 }
1358                         }
1359                 }
1360         } else {
1361                 /* ep is halted by set_halt() before */
1362                 if (ep->halted) {
1363                         tmp = readl(&ep->regs->ctl);
1364                         /* clear stall bit */
1365                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
1366                         /* clear NAK by writing CNAK */
1367                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1368                         writel(tmp, &ep->regs->ctl);
1369                         ep->halted = 0;
1370                         UDC_QUEUE_CNAK(ep, ep->num);
1371                 }
1372         }
1373         spin_unlock_irqrestore(&udc_stall_spinlock, iflags);
1374         return retval;
1375 }
1376
1377 /* gadget interface */
1378 static const struct usb_ep_ops udc_ep_ops = {
1379         .enable         = udc_ep_enable,
1380         .disable        = udc_ep_disable,
1381
1382         .alloc_request  = udc_alloc_request,
1383         .free_request   = udc_free_request,
1384
1385         .queue          = udc_queue,
1386         .dequeue        = udc_dequeue,
1387
1388         .set_halt       = udc_set_halt,
1389         /* fifo ops not implemented */
1390 };
1391
1392 /*-------------------------------------------------------------------------*/
1393
1394 /* Get frame counter (not implemented) */
1395 static int udc_get_frame(struct usb_gadget *gadget)
1396 {
1397         return -EOPNOTSUPP;
1398 }
1399
1400 /* Initiates a remote wakeup */
1401 static int udc_remote_wakeup(struct udc *dev)
1402 {
1403         unsigned long flags;
1404         u32 tmp;
1405
1406         DBG(dev, "UDC initiates remote wakeup\n");
1407
1408         spin_lock_irqsave(&dev->lock, flags);
1409
1410         tmp = readl(&dev->regs->ctl);
1411         tmp |= AMD_BIT(UDC_DEVCTL_RES);
1412         writel(tmp, &dev->regs->ctl);
1413         tmp &= AMD_CLEAR_BIT(UDC_DEVCTL_RES);
1414         writel(tmp, &dev->regs->ctl);
1415
1416         spin_unlock_irqrestore(&dev->lock, flags);
1417         return 0;
1418 }
1419
1420 /* Remote wakeup gadget interface */
1421 static int udc_wakeup(struct usb_gadget *gadget)
1422 {
1423         struct udc              *dev;
1424
1425         if (!gadget)
1426                 return -EINVAL;
1427         dev = container_of(gadget, struct udc, gadget);
1428         udc_remote_wakeup(dev);
1429
1430         return 0;
1431 }
1432
1433 static int amd5536_udc_start(struct usb_gadget *g,
1434                 struct usb_gadget_driver *driver);
1435 static int amd5536_udc_stop(struct usb_gadget *g);
1436
1437 static const struct usb_gadget_ops udc_ops = {
1438         .wakeup         = udc_wakeup,
1439         .get_frame      = udc_get_frame,
1440         .udc_start      = amd5536_udc_start,
1441         .udc_stop       = amd5536_udc_stop,
1442 };
1443
1444 /* Setups endpoint parameters, adds endpoints to linked list */
1445 static void make_ep_lists(struct udc *dev)
1446 {
1447         /* make gadget ep lists */
1448         INIT_LIST_HEAD(&dev->gadget.ep_list);
1449         list_add_tail(&dev->ep[UDC_EPIN_STATUS_IX].ep.ep_list,
1450                                                 &dev->gadget.ep_list);
1451         list_add_tail(&dev->ep[UDC_EPIN_IX].ep.ep_list,
1452                                                 &dev->gadget.ep_list);
1453         list_add_tail(&dev->ep[UDC_EPOUT_IX].ep.ep_list,
1454                                                 &dev->gadget.ep_list);
1455
1456         /* fifo config */
1457         dev->ep[UDC_EPIN_STATUS_IX].fifo_depth = UDC_EPIN_SMALLINT_BUFF_SIZE;
1458         if (dev->gadget.speed == USB_SPEED_FULL)
1459                 dev->ep[UDC_EPIN_IX].fifo_depth = UDC_FS_EPIN_BUFF_SIZE;
1460         else if (dev->gadget.speed == USB_SPEED_HIGH)
1461                 dev->ep[UDC_EPIN_IX].fifo_depth = hs_tx_buf;
1462         dev->ep[UDC_EPOUT_IX].fifo_depth = UDC_RXFIFO_SIZE;
1463 }
1464
1465 /* Inits UDC context */
1466 void udc_basic_init(struct udc *dev)
1467 {
1468         u32     tmp;
1469
1470         DBG(dev, "udc_basic_init()\n");
1471
1472         dev->gadget.speed = USB_SPEED_UNKNOWN;
1473
1474         /* stop RDE timer */
1475         if (timer_pending(&udc_timer)) {
1476                 set_rde = 0;
1477                 mod_timer(&udc_timer, jiffies - 1);
1478         }
1479         /* stop poll stall timer */
1480         if (timer_pending(&udc_pollstall_timer))
1481                 mod_timer(&udc_pollstall_timer, jiffies - 1);
1482         /* disable DMA */
1483         tmp = readl(&dev->regs->ctl);
1484         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_RDE);
1485         tmp &= AMD_UNMASK_BIT(UDC_DEVCTL_TDE);
1486         writel(tmp, &dev->regs->ctl);
1487
1488         /* enable dynamic CSR programming */
1489         tmp = readl(&dev->regs->cfg);
1490         tmp |= AMD_BIT(UDC_DEVCFG_CSR_PRG);
1491         /* set self powered */
1492         tmp |= AMD_BIT(UDC_DEVCFG_SP);
1493         /* set remote wakeupable */
1494         tmp |= AMD_BIT(UDC_DEVCFG_RWKP);
1495         writel(tmp, &dev->regs->cfg);
1496
1497         make_ep_lists(dev);
1498
1499         dev->data_ep_enabled = 0;
1500         dev->data_ep_queued = 0;
1501 }
1502 EXPORT_SYMBOL_GPL(udc_basic_init);
1503
1504 /* init registers at driver load time */
1505 static int startup_registers(struct udc *dev)
1506 {
1507         u32 tmp;
1508
1509         /* init controller by soft reset */
1510         udc_soft_reset(dev);
1511
1512         /* mask not needed interrupts */
1513         udc_mask_unused_interrupts(dev);
1514
1515         /* put into initial config */
1516         udc_basic_init(dev);
1517         /* link up all endpoints */
1518         udc_setup_endpoints(dev);
1519
1520         /* program speed */
1521         tmp = readl(&dev->regs->cfg);
1522         if (use_fullspeed)
1523                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1524         else
1525                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_HS, UDC_DEVCFG_SPD);
1526         writel(tmp, &dev->regs->cfg);
1527
1528         return 0;
1529 }
1530
1531 /* Sets initial endpoint parameters */
1532 static void udc_setup_endpoints(struct udc *dev)
1533 {
1534         struct udc_ep   *ep;
1535         u32     tmp;
1536         u32     reg;
1537
1538         DBG(dev, "udc_setup_endpoints()\n");
1539
1540         /* read enum speed */
1541         tmp = readl(&dev->regs->sts);
1542         tmp = AMD_GETBITS(tmp, UDC_DEVSTS_ENUM_SPEED);
1543         if (tmp == UDC_DEVSTS_ENUM_SPEED_HIGH)
1544                 dev->gadget.speed = USB_SPEED_HIGH;
1545         else if (tmp == UDC_DEVSTS_ENUM_SPEED_FULL)
1546                 dev->gadget.speed = USB_SPEED_FULL;
1547
1548         /* set basic ep parameters */
1549         for (tmp = 0; tmp < UDC_EP_NUM; tmp++) {
1550                 ep = &dev->ep[tmp];
1551                 ep->dev = dev;
1552                 ep->ep.name = ep_info[tmp].name;
1553                 ep->ep.caps = ep_info[tmp].caps;
1554                 ep->num = tmp;
1555                 /* txfifo size is calculated at enable time */
1556                 ep->txfifo = dev->txfifo;
1557
1558                 /* fifo size */
1559                 if (tmp < UDC_EPIN_NUM) {
1560                         ep->fifo_depth = UDC_TXFIFO_SIZE;
1561                         ep->in = 1;
1562                 } else {
1563                         ep->fifo_depth = UDC_RXFIFO_SIZE;
1564                         ep->in = 0;
1565
1566                 }
1567                 ep->regs = &dev->ep_regs[tmp];
1568                 /*
1569                  * ep will be reset only if ep was not enabled before to avoid
1570                  * disabling ep interrupts when ENUM interrupt occurs but ep is
1571                  * not enabled by gadget driver
1572                  */
1573                 if (!ep->ep.desc)
1574                         ep_init(dev->regs, ep);
1575
1576                 if (use_dma) {
1577                         /*
1578                          * ep->dma is not really used, just to indicate that
1579                          * DMA is active: remove this
1580                          * dma regs = dev control regs
1581                          */
1582                         ep->dma = &dev->regs->ctl;
1583
1584                         /* nak OUT endpoints until enable - not for ep0 */
1585                         if (tmp != UDC_EP0IN_IX && tmp != UDC_EP0OUT_IX
1586                                                 && tmp > UDC_EPIN_NUM) {
1587                                 /* set NAK */
1588                                 reg = readl(&dev->ep[tmp].regs->ctl);
1589                                 reg |= AMD_BIT(UDC_EPCTL_SNAK);
1590                                 writel(reg, &dev->ep[tmp].regs->ctl);
1591                                 dev->ep[tmp].naking = 1;
1592
1593                         }
1594                 }
1595         }
1596         /* EP0 max packet */
1597         if (dev->gadget.speed == USB_SPEED_FULL) {
1598                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1599                                            UDC_FS_EP0IN_MAX_PKT_SIZE);
1600                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1601                                            UDC_FS_EP0OUT_MAX_PKT_SIZE);
1602         } else if (dev->gadget.speed == USB_SPEED_HIGH) {
1603                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0IN_IX].ep,
1604                                            UDC_EP0IN_MAX_PKT_SIZE);
1605                 usb_ep_set_maxpacket_limit(&dev->ep[UDC_EP0OUT_IX].ep,
1606                                            UDC_EP0OUT_MAX_PKT_SIZE);
1607         }
1608
1609         /*
1610          * with suspend bug workaround, ep0 params for gadget driver
1611          * are set at gadget driver bind() call
1612          */
1613         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
1614         dev->ep[UDC_EP0IN_IX].halted = 0;
1615         INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
1616
1617         /* init cfg/alt/int */
1618         dev->cur_config = 0;
1619         dev->cur_intf = 0;
1620         dev->cur_alt = 0;
1621 }
1622
1623 /* Bringup after Connect event, initial bringup to be ready for ep0 events */
1624 static void usb_connect(struct udc *dev)
1625 {
1626         /* Return if already connected */
1627         if (dev->connected)
1628                 return;
1629
1630         dev_info(dev->dev, "USB Connect\n");
1631
1632         dev->connected = 1;
1633
1634         /* put into initial config */
1635         udc_basic_init(dev);
1636
1637         /* enable device setup interrupts */
1638         udc_enable_dev_setup_interrupts(dev);
1639 }
1640
1641 /*
1642  * Calls gadget with disconnect event and resets the UDC and makes
1643  * initial bringup to be ready for ep0 events
1644  */
1645 static void usb_disconnect(struct udc *dev)
1646 {
1647         /* Return if already disconnected */
1648         if (!dev->connected)
1649                 return;
1650
1651         dev_info(dev->dev, "USB Disconnect\n");
1652
1653         dev->connected = 0;
1654
1655         /* mask interrupts */
1656         udc_mask_unused_interrupts(dev);
1657
1658         /* REVISIT there doesn't seem to be a point to having this
1659          * talk to a tasklet ... do it directly, we already hold
1660          * the spinlock needed to process the disconnect.
1661          */
1662
1663         tasklet_schedule(&disconnect_tasklet);
1664 }
1665
1666 /* Tasklet for disconnect to be outside of interrupt context */
1667 static void udc_tasklet_disconnect(unsigned long par)
1668 {
1669         struct udc *dev = (struct udc *)(*((struct udc **) par));
1670         u32 tmp;
1671
1672         DBG(dev, "Tasklet disconnect\n");
1673         spin_lock_irq(&dev->lock);
1674
1675         if (dev->driver) {
1676                 spin_unlock(&dev->lock);
1677                 dev->driver->disconnect(&dev->gadget);
1678                 spin_lock(&dev->lock);
1679
1680                 /* empty queues */
1681                 for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
1682                         empty_req_queue(&dev->ep[tmp]);
1683
1684         }
1685
1686         /* disable ep0 */
1687         ep_init(dev->regs,
1688                         &dev->ep[UDC_EP0IN_IX]);
1689
1690
1691         if (!soft_reset_occured) {
1692                 /* init controller by soft reset */
1693                 udc_soft_reset(dev);
1694                 soft_reset_occured++;
1695         }
1696
1697         /* re-enable dev interrupts */
1698         udc_enable_dev_setup_interrupts(dev);
1699         /* back to full speed ? */
1700         if (use_fullspeed) {
1701                 tmp = readl(&dev->regs->cfg);
1702                 tmp = AMD_ADDBITS(tmp, UDC_DEVCFG_SPD_FS, UDC_DEVCFG_SPD);
1703                 writel(tmp, &dev->regs->cfg);
1704         }
1705
1706         spin_unlock_irq(&dev->lock);
1707 }
1708
1709 /* Reset the UDC core */
1710 static void udc_soft_reset(struct udc *dev)
1711 {
1712         unsigned long   flags;
1713
1714         DBG(dev, "Soft reset\n");
1715         /*
1716          * reset possible waiting interrupts, because int.
1717          * status is lost after soft reset,
1718          * ep int. status reset
1719          */
1720         writel(UDC_EPINT_MSK_DISABLE_ALL, &dev->regs->ep_irqsts);
1721         /* device int. status reset */
1722         writel(UDC_DEV_MSK_DISABLE, &dev->regs->irqsts);
1723
1724         /* Don't do this for Broadcom UDC since this is a reserved
1725          * bit.
1726          */
1727         if (dev->chiprev != UDC_BCM_REV) {
1728                 spin_lock_irqsave(&udc_irq_spinlock, flags);
1729                 writel(AMD_BIT(UDC_DEVCFG_SOFTRESET), &dev->regs->cfg);
1730                 readl(&dev->regs->cfg);
1731                 spin_unlock_irqrestore(&udc_irq_spinlock, flags);
1732         }
1733 }
1734
1735 /* RDE timer callback to set RDE bit */
1736 static void udc_timer_function(unsigned long v)
1737 {
1738         u32 tmp;
1739
1740         spin_lock_irq(&udc_irq_spinlock);
1741
1742         if (set_rde > 0) {
1743                 /*
1744                  * open the fifo if fifo was filled on last timer call
1745                  * conditionally
1746                  */
1747                 if (set_rde > 1) {
1748                         /* set RDE to receive setup data */
1749                         tmp = readl(&udc->regs->ctl);
1750                         tmp |= AMD_BIT(UDC_DEVCTL_RDE);
1751                         writel(tmp, &udc->regs->ctl);
1752                         set_rde = -1;
1753                 } else if (readl(&udc->regs->sts)
1754                                 & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY)) {
1755                         /*
1756                          * if fifo empty setup polling, do not just
1757                          * open the fifo
1758                          */
1759                         udc_timer.expires = jiffies + HZ/UDC_RDE_TIMER_DIV;
1760                         if (!stop_timer)
1761                                 add_timer(&udc_timer);
1762                 } else {
1763                         /*
1764                          * fifo contains data now, setup timer for opening
1765                          * the fifo when timer expires to be able to receive
1766                          * setup packets, when data packets gets queued by
1767                          * gadget layer then timer will forced to expire with
1768                          * set_rde=0 (RDE is set in udc_queue())
1769                          */
1770                         set_rde++;
1771                         /* debug: lhadmot_timer_start = 221070 */
1772                         udc_timer.expires = jiffies + HZ*UDC_RDE_TIMER_SECONDS;
1773                         if (!stop_timer)
1774                                 add_timer(&udc_timer);
1775                 }
1776
1777         } else
1778                 set_rde = -1; /* RDE was set by udc_queue() */
1779         spin_unlock_irq(&udc_irq_spinlock);
1780         if (stop_timer)
1781                 complete(&on_exit);
1782
1783 }
1784
1785 /* Handle halt state, used in stall poll timer */
1786 static void udc_handle_halt_state(struct udc_ep *ep)
1787 {
1788         u32 tmp;
1789         /* set stall as long not halted */
1790         if (ep->halted == 1) {
1791                 tmp = readl(&ep->regs->ctl);
1792                 /* STALL cleared ? */
1793                 if (!(tmp & AMD_BIT(UDC_EPCTL_S))) {
1794                         /*
1795                          * FIXME: MSC spec requires that stall remains
1796                          * even on receivng of CLEAR_FEATURE HALT. So
1797                          * we would set STALL again here to be compliant.
1798                          * But with current mass storage drivers this does
1799                          * not work (would produce endless host retries).
1800                          * So we clear halt on CLEAR_FEATURE.
1801                          *
1802                         DBG(ep->dev, "ep %d: set STALL again\n", ep->num);
1803                         tmp |= AMD_BIT(UDC_EPCTL_S);
1804                         writel(tmp, &ep->regs->ctl);*/
1805
1806                         /* clear NAK by writing CNAK */
1807                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1808                         writel(tmp, &ep->regs->ctl);
1809                         ep->halted = 0;
1810                         UDC_QUEUE_CNAK(ep, ep->num);
1811                 }
1812         }
1813 }
1814
1815 /* Stall timer callback to poll S bit and set it again after */
1816 static void udc_pollstall_timer_function(unsigned long v)
1817 {
1818         struct udc_ep *ep;
1819         int halted = 0;
1820
1821         spin_lock_irq(&udc_stall_spinlock);
1822         /*
1823          * only one IN and OUT endpoints are handled
1824          * IN poll stall
1825          */
1826         ep = &udc->ep[UDC_EPIN_IX];
1827         udc_handle_halt_state(ep);
1828         if (ep->halted)
1829                 halted = 1;
1830         /* OUT poll stall */
1831         ep = &udc->ep[UDC_EPOUT_IX];
1832         udc_handle_halt_state(ep);
1833         if (ep->halted)
1834                 halted = 1;
1835
1836         /* setup timer again when still halted */
1837         if (!stop_pollstall_timer && halted) {
1838                 udc_pollstall_timer.expires = jiffies +
1839                                         HZ * UDC_POLLSTALL_TIMER_USECONDS
1840                                         / (1000 * 1000);
1841                 add_timer(&udc_pollstall_timer);
1842         }
1843         spin_unlock_irq(&udc_stall_spinlock);
1844
1845         if (stop_pollstall_timer)
1846                 complete(&on_pollstall_exit);
1847 }
1848
1849 /* Inits endpoint 0 so that SETUP packets are processed */
1850 static void activate_control_endpoints(struct udc *dev)
1851 {
1852         u32 tmp;
1853
1854         DBG(dev, "activate_control_endpoints\n");
1855
1856         /* flush fifo */
1857         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1858         tmp |= AMD_BIT(UDC_EPCTL_F);
1859         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1860
1861         /* set ep0 directions */
1862         dev->ep[UDC_EP0IN_IX].in = 1;
1863         dev->ep[UDC_EP0OUT_IX].in = 0;
1864
1865         /* set buffer size (tx fifo entries) of EP0_IN */
1866         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1867         if (dev->gadget.speed == USB_SPEED_FULL)
1868                 tmp = AMD_ADDBITS(tmp, UDC_FS_EPIN0_BUFF_SIZE,
1869                                         UDC_EPIN_BUFF_SIZE);
1870         else if (dev->gadget.speed == USB_SPEED_HIGH)
1871                 tmp = AMD_ADDBITS(tmp, UDC_EPIN0_BUFF_SIZE,
1872                                         UDC_EPIN_BUFF_SIZE);
1873         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufin_framenum);
1874
1875         /* set max packet size of EP0_IN */
1876         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1877         if (dev->gadget.speed == USB_SPEED_FULL)
1878                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0IN_MAX_PKT_SIZE,
1879                                         UDC_EP_MAX_PKT_SIZE);
1880         else if (dev->gadget.speed == USB_SPEED_HIGH)
1881                 tmp = AMD_ADDBITS(tmp, UDC_EP0IN_MAX_PKT_SIZE,
1882                                 UDC_EP_MAX_PKT_SIZE);
1883         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->bufout_maxpkt);
1884
1885         /* set max packet size of EP0_OUT */
1886         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1887         if (dev->gadget.speed == USB_SPEED_FULL)
1888                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1889                                         UDC_EP_MAX_PKT_SIZE);
1890         else if (dev->gadget.speed == USB_SPEED_HIGH)
1891                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1892                                         UDC_EP_MAX_PKT_SIZE);
1893         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->bufout_maxpkt);
1894
1895         /* set max packet size of EP0 in UDC CSR */
1896         tmp = readl(&dev->csr->ne[0]);
1897         if (dev->gadget.speed == USB_SPEED_FULL)
1898                 tmp = AMD_ADDBITS(tmp, UDC_FS_EP0OUT_MAX_PKT_SIZE,
1899                                         UDC_CSR_NE_MAX_PKT);
1900         else if (dev->gadget.speed == USB_SPEED_HIGH)
1901                 tmp = AMD_ADDBITS(tmp, UDC_EP0OUT_MAX_PKT_SIZE,
1902                                         UDC_CSR_NE_MAX_PKT);
1903         writel(tmp, &dev->csr->ne[0]);
1904
1905         if (use_dma) {
1906                 dev->ep[UDC_EP0OUT_IX].td->status |=
1907                         AMD_BIT(UDC_DMA_OUT_STS_L);
1908                 /* write dma desc address */
1909                 writel(dev->ep[UDC_EP0OUT_IX].td_stp_dma,
1910                         &dev->ep[UDC_EP0OUT_IX].regs->subptr);
1911                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
1912                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
1913                 /* stop RDE timer */
1914                 if (timer_pending(&udc_timer)) {
1915                         set_rde = 0;
1916                         mod_timer(&udc_timer, jiffies - 1);
1917                 }
1918                 /* stop pollstall timer */
1919                 if (timer_pending(&udc_pollstall_timer))
1920                         mod_timer(&udc_pollstall_timer, jiffies - 1);
1921                 /* enable DMA */
1922                 tmp = readl(&dev->regs->ctl);
1923                 tmp |= AMD_BIT(UDC_DEVCTL_MODE)
1924                                 | AMD_BIT(UDC_DEVCTL_RDE)
1925                                 | AMD_BIT(UDC_DEVCTL_TDE);
1926                 if (use_dma_bufferfill_mode)
1927                         tmp |= AMD_BIT(UDC_DEVCTL_BF);
1928                 else if (use_dma_ppb_du)
1929                         tmp |= AMD_BIT(UDC_DEVCTL_DU);
1930                 writel(tmp, &dev->regs->ctl);
1931         }
1932
1933         /* clear NAK by writing CNAK for EP0IN */
1934         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
1935         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1936         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
1937         dev->ep[UDC_EP0IN_IX].naking = 0;
1938         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
1939
1940         /* clear NAK by writing CNAK for EP0OUT */
1941         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
1942         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
1943         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
1944         dev->ep[UDC_EP0OUT_IX].naking = 0;
1945         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
1946 }
1947
1948 /* Make endpoint 0 ready for control traffic */
1949 static int setup_ep0(struct udc *dev)
1950 {
1951         activate_control_endpoints(dev);
1952         /* enable ep0 interrupts */
1953         udc_enable_ep0_interrupts(dev);
1954         /* enable device setup interrupts */
1955         udc_enable_dev_setup_interrupts(dev);
1956
1957         return 0;
1958 }
1959
1960 /* Called by gadget driver to register itself */
1961 static int amd5536_udc_start(struct usb_gadget *g,
1962                 struct usb_gadget_driver *driver)
1963 {
1964         struct udc *dev = to_amd5536_udc(g);
1965         u32 tmp;
1966
1967         driver->driver.bus = NULL;
1968         dev->driver = driver;
1969
1970         /* Some gadget drivers use both ep0 directions.
1971          * NOTE: to gadget driver, ep0 is just one endpoint...
1972          */
1973         dev->ep[UDC_EP0OUT_IX].ep.driver_data =
1974                 dev->ep[UDC_EP0IN_IX].ep.driver_data;
1975
1976         /* get ready for ep0 traffic */
1977         setup_ep0(dev);
1978
1979         /* clear SD */
1980         tmp = readl(&dev->regs->ctl);
1981         tmp = tmp & AMD_CLEAR_BIT(UDC_DEVCTL_SD);
1982         writel(tmp, &dev->regs->ctl);
1983
1984         usb_connect(dev);
1985
1986         return 0;
1987 }
1988
1989 /* shutdown requests and disconnect from gadget */
1990 static void
1991 shutdown(struct udc *dev, struct usb_gadget_driver *driver)
1992 __releases(dev->lock)
1993 __acquires(dev->lock)
1994 {
1995         int tmp;
1996
1997         /* empty queues and init hardware */
1998         udc_basic_init(dev);
1999
2000         for (tmp = 0; tmp < UDC_EP_NUM; tmp++)
2001                 empty_req_queue(&dev->ep[tmp]);
2002
2003         udc_setup_endpoints(dev);
2004 }
2005
2006 /* Called by gadget driver to unregister itself */
2007 static int amd5536_udc_stop(struct usb_gadget *g)
2008 {
2009         struct udc *dev = to_amd5536_udc(g);
2010         unsigned long flags;
2011         u32 tmp;
2012
2013         spin_lock_irqsave(&dev->lock, flags);
2014         udc_mask_unused_interrupts(dev);
2015         shutdown(dev, NULL);
2016         spin_unlock_irqrestore(&dev->lock, flags);
2017
2018         dev->driver = NULL;
2019
2020         /* set SD */
2021         tmp = readl(&dev->regs->ctl);
2022         tmp |= AMD_BIT(UDC_DEVCTL_SD);
2023         writel(tmp, &dev->regs->ctl);
2024
2025         return 0;
2026 }
2027
2028 /* Clear pending NAK bits */
2029 static void udc_process_cnak_queue(struct udc *dev)
2030 {
2031         u32 tmp;
2032         u32 reg;
2033
2034         /* check epin's */
2035         DBG(dev, "CNAK pending queue processing\n");
2036         for (tmp = 0; tmp < UDC_EPIN_NUM_USED; tmp++) {
2037                 if (cnak_pending & (1 << tmp)) {
2038                         DBG(dev, "CNAK pending for ep%d\n", tmp);
2039                         /* clear NAK by writing CNAK */
2040                         reg = readl(&dev->ep[tmp].regs->ctl);
2041                         reg |= AMD_BIT(UDC_EPCTL_CNAK);
2042                         writel(reg, &dev->ep[tmp].regs->ctl);
2043                         dev->ep[tmp].naking = 0;
2044                         UDC_QUEUE_CNAK(&dev->ep[tmp], dev->ep[tmp].num);
2045                 }
2046         }
2047         /* ...  and ep0out */
2048         if (cnak_pending & (1 << UDC_EP0OUT_IX)) {
2049                 DBG(dev, "CNAK pending for ep%d\n", UDC_EP0OUT_IX);
2050                 /* clear NAK by writing CNAK */
2051                 reg = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2052                 reg |= AMD_BIT(UDC_EPCTL_CNAK);
2053                 writel(reg, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2054                 dev->ep[UDC_EP0OUT_IX].naking = 0;
2055                 UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX],
2056                                 dev->ep[UDC_EP0OUT_IX].num);
2057         }
2058 }
2059
2060 /* Enabling RX DMA after setup packet */
2061 static void udc_ep0_set_rde(struct udc *dev)
2062 {
2063         if (use_dma) {
2064                 /*
2065                  * only enable RXDMA when no data endpoint enabled
2066                  * or data is queued
2067                  */
2068                 if (!dev->data_ep_enabled || dev->data_ep_queued) {
2069                         udc_set_rde(dev);
2070                 } else {
2071                         /*
2072                          * setup timer for enabling RDE (to not enable
2073                          * RXFIFO DMA for data endpoints to early)
2074                          */
2075                         if (set_rde != 0 && !timer_pending(&udc_timer)) {
2076                                 udc_timer.expires =
2077                                         jiffies + HZ/UDC_RDE_TIMER_DIV;
2078                                 set_rde = 1;
2079                                 if (!stop_timer)
2080                                         add_timer(&udc_timer);
2081                         }
2082                 }
2083         }
2084 }
2085
2086
2087 /* Interrupt handler for data OUT traffic */
2088 static irqreturn_t udc_data_out_isr(struct udc *dev, int ep_ix)
2089 {
2090         irqreturn_t             ret_val = IRQ_NONE;
2091         u32                     tmp;
2092         struct udc_ep           *ep;
2093         struct udc_request      *req;
2094         unsigned int            count;
2095         struct udc_data_dma     *td = NULL;
2096         unsigned                dma_done;
2097
2098         VDBG(dev, "ep%d irq\n", ep_ix);
2099         ep = &dev->ep[ep_ix];
2100
2101         tmp = readl(&ep->regs->sts);
2102         if (use_dma) {
2103                 /* BNA event ? */
2104                 if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2105                         DBG(dev, "BNA ep%dout occurred - DESPTR = %x\n",
2106                                         ep->num, readl(&ep->regs->desptr));
2107                         /* clear BNA */
2108                         writel(tmp | AMD_BIT(UDC_EPSTS_BNA), &ep->regs->sts);
2109                         if (!ep->cancel_transfer)
2110                                 ep->bna_occurred = 1;
2111                         else
2112                                 ep->cancel_transfer = 0;
2113                         ret_val = IRQ_HANDLED;
2114                         goto finished;
2115                 }
2116         }
2117         /* HE event ? */
2118         if (tmp & AMD_BIT(UDC_EPSTS_HE)) {
2119                 dev_err(dev->dev, "HE ep%dout occurred\n", ep->num);
2120
2121                 /* clear HE */
2122                 writel(tmp | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2123                 ret_val = IRQ_HANDLED;
2124                 goto finished;
2125         }
2126
2127         if (!list_empty(&ep->queue)) {
2128
2129                 /* next request */
2130                 req = list_entry(ep->queue.next,
2131                         struct udc_request, queue);
2132         } else {
2133                 req = NULL;
2134                 udc_rxfifo_pending = 1;
2135         }
2136         VDBG(dev, "req = %p\n", req);
2137         /* fifo mode */
2138         if (!use_dma) {
2139
2140                 /* read fifo */
2141                 if (req && udc_rxfifo_read(ep, req)) {
2142                         ret_val = IRQ_HANDLED;
2143
2144                         /* finish */
2145                         complete_req(ep, req, 0);
2146                         /* next request */
2147                         if (!list_empty(&ep->queue) && !ep->halted) {
2148                                 req = list_entry(ep->queue.next,
2149                                         struct udc_request, queue);
2150                         } else
2151                                 req = NULL;
2152                 }
2153
2154         /* DMA */
2155         } else if (!ep->cancel_transfer && req) {
2156                 ret_val = IRQ_HANDLED;
2157
2158                 /* check for DMA done */
2159                 if (!use_dma_ppb) {
2160                         dma_done = AMD_GETBITS(req->td_data->status,
2161                                                 UDC_DMA_OUT_STS_BS);
2162                 /* packet per buffer mode - rx bytes */
2163                 } else {
2164                         /*
2165                          * if BNA occurred then recover desc. from
2166                          * BNA dummy desc.
2167                          */
2168                         if (ep->bna_occurred) {
2169                                 VDBG(dev, "Recover desc. from BNA dummy\n");
2170                                 memcpy(req->td_data, ep->bna_dummy_req->td_data,
2171                                                 sizeof(struct udc_data_dma));
2172                                 ep->bna_occurred = 0;
2173                                 udc_init_bna_dummy(ep->req);
2174                         }
2175                         td = udc_get_last_dma_desc(req);
2176                         dma_done = AMD_GETBITS(td->status, UDC_DMA_OUT_STS_BS);
2177                 }
2178                 if (dma_done == UDC_DMA_OUT_STS_BS_DMA_DONE) {
2179                         /* buffer fill mode - rx bytes */
2180                         if (!use_dma_ppb) {
2181                                 /* received number bytes */
2182                                 count = AMD_GETBITS(req->td_data->status,
2183                                                 UDC_DMA_OUT_STS_RXBYTES);
2184                                 VDBG(dev, "rx bytes=%u\n", count);
2185                         /* packet per buffer mode - rx bytes */
2186                         } else {
2187                                 VDBG(dev, "req->td_data=%p\n", req->td_data);
2188                                 VDBG(dev, "last desc = %p\n", td);
2189                                 /* received number bytes */
2190                                 if (use_dma_ppb_du) {
2191                                         /* every desc. counts bytes */
2192                                         count = udc_get_ppbdu_rxbytes(req);
2193                                 } else {
2194                                         /* last desc. counts bytes */
2195                                         count = AMD_GETBITS(td->status,
2196                                                 UDC_DMA_OUT_STS_RXBYTES);
2197                                         if (!count && req->req.length
2198                                                 == UDC_DMA_MAXPACKET) {
2199                                                 /*
2200                                                  * on 64k packets the RXBYTES
2201                                                  * field is zero
2202                                                  */
2203                                                 count = UDC_DMA_MAXPACKET;
2204                                         }
2205                                 }
2206                                 VDBG(dev, "last desc rx bytes=%u\n", count);
2207                         }
2208
2209                         tmp = req->req.length - req->req.actual;
2210                         if (count > tmp) {
2211                                 if ((tmp % ep->ep.maxpacket) != 0) {
2212                                         DBG(dev, "%s: rx %db, space=%db\n",
2213                                                 ep->ep.name, count, tmp);
2214                                         req->req.status = -EOVERFLOW;
2215                                 }
2216                                 count = tmp;
2217                         }
2218                         req->req.actual += count;
2219                         req->dma_going = 0;
2220                         /* complete request */
2221                         complete_req(ep, req, 0);
2222
2223                         /* next request */
2224                         if (!list_empty(&ep->queue) && !ep->halted) {
2225                                 req = list_entry(ep->queue.next,
2226                                         struct udc_request,
2227                                         queue);
2228                                 /*
2229                                  * DMA may be already started by udc_queue()
2230                                  * called by gadget drivers completion
2231                                  * routine. This happens when queue
2232                                  * holds one request only.
2233                                  */
2234                                 if (req->dma_going == 0) {
2235                                         /* next dma */
2236                                         if (prep_dma(ep, req, GFP_ATOMIC) != 0)
2237                                                 goto finished;
2238                                         /* write desc pointer */
2239                                         writel(req->td_phys,
2240                                                 &ep->regs->desptr);
2241                                         req->dma_going = 1;
2242                                         /* enable DMA */
2243                                         udc_set_rde(dev);
2244                                 }
2245                         } else {
2246                                 /*
2247                                  * implant BNA dummy descriptor to allow
2248                                  * RXFIFO opening by RDE
2249                                  */
2250                                 if (ep->bna_dummy_req) {
2251                                         /* write desc pointer */
2252                                         writel(ep->bna_dummy_req->td_phys,
2253                                                 &ep->regs->desptr);
2254                                         ep->bna_occurred = 0;
2255                                 }
2256
2257                                 /*
2258                                  * schedule timer for setting RDE if queue
2259                                  * remains empty to allow ep0 packets pass
2260                                  * through
2261                                  */
2262                                 if (set_rde != 0
2263                                                 && !timer_pending(&udc_timer)) {
2264                                         udc_timer.expires =
2265                                                 jiffies
2266                                                 + HZ*UDC_RDE_TIMER_SECONDS;
2267                                         set_rde = 1;
2268                                         if (!stop_timer)
2269                                                 add_timer(&udc_timer);
2270                                 }
2271                                 if (ep->num != UDC_EP0OUT_IX)
2272                                         dev->data_ep_queued = 0;
2273                         }
2274
2275                 } else {
2276                         /*
2277                         * RX DMA must be reenabled for each desc in PPBDU mode
2278                         * and must be enabled for PPBNDU mode in case of BNA
2279                         */
2280                         udc_set_rde(dev);
2281                 }
2282
2283         } else if (ep->cancel_transfer) {
2284                 ret_val = IRQ_HANDLED;
2285                 ep->cancel_transfer = 0;
2286         }
2287
2288         /* check pending CNAKS */
2289         if (cnak_pending) {
2290                 /* CNAk processing when rxfifo empty only */
2291                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2292                         udc_process_cnak_queue(dev);
2293         }
2294
2295         /* clear OUT bits in ep status */
2296         writel(UDC_EPSTS_OUT_CLEAR, &ep->regs->sts);
2297 finished:
2298         return ret_val;
2299 }
2300
2301 /* Interrupt handler for data IN traffic */
2302 static irqreturn_t udc_data_in_isr(struct udc *dev, int ep_ix)
2303 {
2304         irqreturn_t ret_val = IRQ_NONE;
2305         u32 tmp;
2306         u32 epsts;
2307         struct udc_ep *ep;
2308         struct udc_request *req;
2309         struct udc_data_dma *td;
2310         unsigned len;
2311
2312         ep = &dev->ep[ep_ix];
2313
2314         epsts = readl(&ep->regs->sts);
2315         if (use_dma) {
2316                 /* BNA ? */
2317                 if (epsts & AMD_BIT(UDC_EPSTS_BNA)) {
2318                         dev_err(dev->dev,
2319                                 "BNA ep%din occurred - DESPTR = %08lx\n",
2320                                 ep->num,
2321                                 (unsigned long) readl(&ep->regs->desptr));
2322
2323                         /* clear BNA */
2324                         writel(epsts, &ep->regs->sts);
2325                         ret_val = IRQ_HANDLED;
2326                         goto finished;
2327                 }
2328         }
2329         /* HE event ? */
2330         if (epsts & AMD_BIT(UDC_EPSTS_HE)) {
2331                 dev_err(dev->dev,
2332                         "HE ep%dn occurred - DESPTR = %08lx\n",
2333                         ep->num, (unsigned long) readl(&ep->regs->desptr));
2334
2335                 /* clear HE */
2336                 writel(epsts | AMD_BIT(UDC_EPSTS_HE), &ep->regs->sts);
2337                 ret_val = IRQ_HANDLED;
2338                 goto finished;
2339         }
2340
2341         /* DMA completion */
2342         if (epsts & AMD_BIT(UDC_EPSTS_TDC)) {
2343                 VDBG(dev, "TDC set- completion\n");
2344                 ret_val = IRQ_HANDLED;
2345                 if (!ep->cancel_transfer && !list_empty(&ep->queue)) {
2346                         req = list_entry(ep->queue.next,
2347                                         struct udc_request, queue);
2348                         /*
2349                          * length bytes transferred
2350                          * check dma done of last desc. in PPBDU mode
2351                          */
2352                         if (use_dma_ppb_du) {
2353                                 td = udc_get_last_dma_desc(req);
2354                                 if (td)
2355                                         req->req.actual = req->req.length;
2356                         } else {
2357                                 /* assume all bytes transferred */
2358                                 req->req.actual = req->req.length;
2359                         }
2360
2361                         if (req->req.actual == req->req.length) {
2362                                 /* complete req */
2363                                 complete_req(ep, req, 0);
2364                                 req->dma_going = 0;
2365                                 /* further request available ? */
2366                                 if (list_empty(&ep->queue)) {
2367                                         /* disable interrupt */
2368                                         tmp = readl(&dev->regs->ep_irqmsk);
2369                                         tmp |= AMD_BIT(ep->num);
2370                                         writel(tmp, &dev->regs->ep_irqmsk);
2371                                 }
2372                         }
2373                 }
2374                 ep->cancel_transfer = 0;
2375
2376         }
2377         /*
2378          * status reg has IN bit set and TDC not set (if TDC was handled,
2379          * IN must not be handled (UDC defect) ?
2380          */
2381         if ((epsts & AMD_BIT(UDC_EPSTS_IN))
2382                         && !(epsts & AMD_BIT(UDC_EPSTS_TDC))) {
2383                 ret_val = IRQ_HANDLED;
2384                 if (!list_empty(&ep->queue)) {
2385                         /* next request */
2386                         req = list_entry(ep->queue.next,
2387                                         struct udc_request, queue);
2388                         /* FIFO mode */
2389                         if (!use_dma) {
2390                                 /* write fifo */
2391                                 udc_txfifo_write(ep, &req->req);
2392                                 len = req->req.length - req->req.actual;
2393                                 if (len > ep->ep.maxpacket)
2394                                         len = ep->ep.maxpacket;
2395                                 req->req.actual += len;
2396                                 if (req->req.actual == req->req.length
2397                                         || (len != ep->ep.maxpacket)) {
2398                                         /* complete req */
2399                                         complete_req(ep, req, 0);
2400                                 }
2401                         /* DMA */
2402                         } else if (req && !req->dma_going) {
2403                                 VDBG(dev, "IN DMA : req=%p req->td_data=%p\n",
2404                                         req, req->td_data);
2405                                 if (req->td_data) {
2406
2407                                         req->dma_going = 1;
2408
2409                                         /*
2410                                          * unset L bit of first desc.
2411                                          * for chain
2412                                          */
2413                                         if (use_dma_ppb && req->req.length >
2414                                                         ep->ep.maxpacket) {
2415                                                 req->td_data->status &=
2416                                                         AMD_CLEAR_BIT(
2417                                                         UDC_DMA_IN_STS_L);
2418                                         }
2419
2420                                         /* write desc pointer */
2421                                         writel(req->td_phys, &ep->regs->desptr);
2422
2423                                         /* set HOST READY */
2424                                         req->td_data->status =
2425                                                 AMD_ADDBITS(
2426                                                 req->td_data->status,
2427                                                 UDC_DMA_IN_STS_BS_HOST_READY,
2428                                                 UDC_DMA_IN_STS_BS);
2429
2430                                         /* set poll demand bit */
2431                                         tmp = readl(&ep->regs->ctl);
2432                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2433                                         writel(tmp, &ep->regs->ctl);
2434                                 }
2435                         }
2436
2437                 } else if (!use_dma && ep->in) {
2438                         /* disable interrupt */
2439                         tmp = readl(
2440                                 &dev->regs->ep_irqmsk);
2441                         tmp |= AMD_BIT(ep->num);
2442                         writel(tmp,
2443                                 &dev->regs->ep_irqmsk);
2444                 }
2445         }
2446         /* clear status bits */
2447         writel(epsts, &ep->regs->sts);
2448
2449 finished:
2450         return ret_val;
2451
2452 }
2453
2454 /* Interrupt handler for Control OUT traffic */
2455 static irqreturn_t udc_control_out_isr(struct udc *dev)
2456 __releases(dev->lock)
2457 __acquires(dev->lock)
2458 {
2459         irqreturn_t ret_val = IRQ_NONE;
2460         u32 tmp;
2461         int setup_supported;
2462         u32 count;
2463         int set = 0;
2464         struct udc_ep   *ep;
2465         struct udc_ep   *ep_tmp;
2466
2467         ep = &dev->ep[UDC_EP0OUT_IX];
2468
2469         /* clear irq */
2470         writel(AMD_BIT(UDC_EPINT_OUT_EP0), &dev->regs->ep_irqsts);
2471
2472         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2473         /* check BNA and clear if set */
2474         if (tmp & AMD_BIT(UDC_EPSTS_BNA)) {
2475                 VDBG(dev, "ep0: BNA set\n");
2476                 writel(AMD_BIT(UDC_EPSTS_BNA),
2477                         &dev->ep[UDC_EP0OUT_IX].regs->sts);
2478                 ep->bna_occurred = 1;
2479                 ret_val = IRQ_HANDLED;
2480                 goto finished;
2481         }
2482
2483         /* type of data: SETUP or DATA 0 bytes */
2484         tmp = AMD_GETBITS(tmp, UDC_EPSTS_OUT);
2485         VDBG(dev, "data_typ = %x\n", tmp);
2486
2487         /* setup data */
2488         if (tmp == UDC_EPSTS_OUT_SETUP) {
2489                 ret_val = IRQ_HANDLED;
2490
2491                 ep->dev->stall_ep0in = 0;
2492                 dev->waiting_zlp_ack_ep0in = 0;
2493
2494                 /* set NAK for EP0_IN */
2495                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2496                 tmp |= AMD_BIT(UDC_EPCTL_SNAK);
2497                 writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2498                 dev->ep[UDC_EP0IN_IX].naking = 1;
2499                 /* get setup data */
2500                 if (use_dma) {
2501
2502                         /* clear OUT bits in ep status */
2503                         writel(UDC_EPSTS_OUT_CLEAR,
2504                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2505
2506                         setup_data.data[0] =
2507                                 dev->ep[UDC_EP0OUT_IX].td_stp->data12;
2508                         setup_data.data[1] =
2509                                 dev->ep[UDC_EP0OUT_IX].td_stp->data34;
2510                         /* set HOST READY */
2511                         dev->ep[UDC_EP0OUT_IX].td_stp->status =
2512                                         UDC_DMA_STP_STS_BS_HOST_READY;
2513                 } else {
2514                         /* read fifo */
2515                         udc_rxfifo_read_dwords(dev, setup_data.data, 2);
2516                 }
2517
2518                 /* determine direction of control data */
2519                 if ((setup_data.request.bRequestType & USB_DIR_IN) != 0) {
2520                         dev->gadget.ep0 = &dev->ep[UDC_EP0IN_IX].ep;
2521                         /* enable RDE */
2522                         udc_ep0_set_rde(dev);
2523                         set = 0;
2524                 } else {
2525                         dev->gadget.ep0 = &dev->ep[UDC_EP0OUT_IX].ep;
2526                         /*
2527                          * implant BNA dummy descriptor to allow RXFIFO opening
2528                          * by RDE
2529                          */
2530                         if (ep->bna_dummy_req) {
2531                                 /* write desc pointer */
2532                                 writel(ep->bna_dummy_req->td_phys,
2533                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2534                                 ep->bna_occurred = 0;
2535                         }
2536
2537                         set = 1;
2538                         dev->ep[UDC_EP0OUT_IX].naking = 1;
2539                         /*
2540                          * setup timer for enabling RDE (to not enable
2541                          * RXFIFO DMA for data to early)
2542                          */
2543                         set_rde = 1;
2544                         if (!timer_pending(&udc_timer)) {
2545                                 udc_timer.expires = jiffies +
2546                                                         HZ/UDC_RDE_TIMER_DIV;
2547                                 if (!stop_timer)
2548                                         add_timer(&udc_timer);
2549                         }
2550                 }
2551
2552                 /*
2553                  * mass storage reset must be processed here because
2554                  * next packet may be a CLEAR_FEATURE HALT which would not
2555                  * clear the stall bit when no STALL handshake was received
2556                  * before (autostall can cause this)
2557                  */
2558                 if (setup_data.data[0] == UDC_MSCRES_DWORD0
2559                                 && setup_data.data[1] == UDC_MSCRES_DWORD1) {
2560                         DBG(dev, "MSC Reset\n");
2561                         /*
2562                          * clear stall bits
2563                          * only one IN and OUT endpoints are handled
2564                          */
2565                         ep_tmp = &udc->ep[UDC_EPIN_IX];
2566                         udc_set_halt(&ep_tmp->ep, 0);
2567                         ep_tmp = &udc->ep[UDC_EPOUT_IX];
2568                         udc_set_halt(&ep_tmp->ep, 0);
2569                 }
2570
2571                 /* call gadget with setup data received */
2572                 spin_unlock(&dev->lock);
2573                 setup_supported = dev->driver->setup(&dev->gadget,
2574                                                 &setup_data.request);
2575                 spin_lock(&dev->lock);
2576
2577                 tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2578                 /* ep0 in returns data (not zlp) on IN phase */
2579                 if (setup_supported >= 0 && setup_supported <
2580                                 UDC_EP0IN_MAXPACKET) {
2581                         /* clear NAK by writing CNAK in EP0_IN */
2582                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2583                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2584                         dev->ep[UDC_EP0IN_IX].naking = 0;
2585                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0IN_IX], UDC_EP0IN_IX);
2586
2587                 /* if unsupported request then stall */
2588                 } else if (setup_supported < 0) {
2589                         tmp |= AMD_BIT(UDC_EPCTL_S);
2590                         writel(tmp, &dev->ep[UDC_EP0IN_IX].regs->ctl);
2591                 } else
2592                         dev->waiting_zlp_ack_ep0in = 1;
2593
2594
2595                 /* clear NAK by writing CNAK in EP0_OUT */
2596                 if (!set) {
2597                         tmp = readl(&dev->ep[UDC_EP0OUT_IX].regs->ctl);
2598                         tmp |= AMD_BIT(UDC_EPCTL_CNAK);
2599                         writel(tmp, &dev->ep[UDC_EP0OUT_IX].regs->ctl);
2600                         dev->ep[UDC_EP0OUT_IX].naking = 0;
2601                         UDC_QUEUE_CNAK(&dev->ep[UDC_EP0OUT_IX], UDC_EP0OUT_IX);
2602                 }
2603
2604                 if (!use_dma) {
2605                         /* clear OUT bits in ep status */
2606                         writel(UDC_EPSTS_OUT_CLEAR,
2607                                 &dev->ep[UDC_EP0OUT_IX].regs->sts);
2608                 }
2609
2610         /* data packet 0 bytes */
2611         } else if (tmp == UDC_EPSTS_OUT_DATA) {
2612                 /* clear OUT bits in ep status */
2613                 writel(UDC_EPSTS_OUT_CLEAR, &dev->ep[UDC_EP0OUT_IX].regs->sts);
2614
2615                 /* get setup data: only 0 packet */
2616                 if (use_dma) {
2617                         /* no req if 0 packet, just reactivate */
2618                         if (list_empty(&dev->ep[UDC_EP0OUT_IX].queue)) {
2619                                 VDBG(dev, "ZLP\n");
2620
2621                                 /* set HOST READY */
2622                                 dev->ep[UDC_EP0OUT_IX].td->status =
2623                                         AMD_ADDBITS(
2624                                         dev->ep[UDC_EP0OUT_IX].td->status,
2625                                         UDC_DMA_OUT_STS_BS_HOST_READY,
2626                                         UDC_DMA_OUT_STS_BS);
2627                                 /* enable RDE */
2628                                 udc_ep0_set_rde(dev);
2629                                 ret_val = IRQ_HANDLED;
2630
2631                         } else {
2632                                 /* control write */
2633                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2634                                 /* re-program desc. pointer for possible ZLPs */
2635                                 writel(dev->ep[UDC_EP0OUT_IX].td_phys,
2636                                         &dev->ep[UDC_EP0OUT_IX].regs->desptr);
2637                                 /* enable RDE */
2638                                 udc_ep0_set_rde(dev);
2639                         }
2640                 } else {
2641
2642                         /* received number bytes */
2643                         count = readl(&dev->ep[UDC_EP0OUT_IX].regs->sts);
2644                         count = AMD_GETBITS(count, UDC_EPSTS_RX_PKT_SIZE);
2645                         /* out data for fifo mode not working */
2646                         count = 0;
2647
2648                         /* 0 packet or real data ? */
2649                         if (count != 0) {
2650                                 ret_val |= udc_data_out_isr(dev, UDC_EP0OUT_IX);
2651                         } else {
2652                                 /* dummy read confirm */
2653                                 readl(&dev->ep[UDC_EP0OUT_IX].regs->confirm);
2654                                 ret_val = IRQ_HANDLED;
2655                         }
2656                 }
2657         }
2658
2659         /* check pending CNAKS */
2660         if (cnak_pending) {
2661                 /* CNAk processing when rxfifo empty only */
2662                 if (readl(&dev->regs->sts) & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2663                         udc_process_cnak_queue(dev);
2664         }
2665
2666 finished:
2667         return ret_val;
2668 }
2669
2670 /* Interrupt handler for Control IN traffic */
2671 static irqreturn_t udc_control_in_isr(struct udc *dev)
2672 {
2673         irqreturn_t ret_val = IRQ_NONE;
2674         u32 tmp;
2675         struct udc_ep *ep;
2676         struct udc_request *req;
2677         unsigned len;
2678
2679         ep = &dev->ep[UDC_EP0IN_IX];
2680
2681         /* clear irq */
2682         writel(AMD_BIT(UDC_EPINT_IN_EP0), &dev->regs->ep_irqsts);
2683
2684         tmp = readl(&dev->ep[UDC_EP0IN_IX].regs->sts);
2685         /* DMA completion */
2686         if (tmp & AMD_BIT(UDC_EPSTS_TDC)) {
2687                 VDBG(dev, "isr: TDC clear\n");
2688                 ret_val = IRQ_HANDLED;
2689
2690                 /* clear TDC bit */
2691                 writel(AMD_BIT(UDC_EPSTS_TDC),
2692                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2693
2694         /* status reg has IN bit set ? */
2695         } else if (tmp & AMD_BIT(UDC_EPSTS_IN)) {
2696                 ret_val = IRQ_HANDLED;
2697
2698                 if (ep->dma) {
2699                         /* clear IN bit */
2700                         writel(AMD_BIT(UDC_EPSTS_IN),
2701                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2702                 }
2703                 if (dev->stall_ep0in) {
2704                         DBG(dev, "stall ep0in\n");
2705                         /* halt ep0in */
2706                         tmp = readl(&ep->regs->ctl);
2707                         tmp |= AMD_BIT(UDC_EPCTL_S);
2708                         writel(tmp, &ep->regs->ctl);
2709                 } else {
2710                         if (!list_empty(&ep->queue)) {
2711                                 /* next request */
2712                                 req = list_entry(ep->queue.next,
2713                                                 struct udc_request, queue);
2714
2715                                 if (ep->dma) {
2716                                         /* write desc pointer */
2717                                         writel(req->td_phys, &ep->regs->desptr);
2718                                         /* set HOST READY */
2719                                         req->td_data->status =
2720                                                 AMD_ADDBITS(
2721                                                 req->td_data->status,
2722                                                 UDC_DMA_STP_STS_BS_HOST_READY,
2723                                                 UDC_DMA_STP_STS_BS);
2724
2725                                         /* set poll demand bit */
2726                                         tmp =
2727                                         readl(&dev->ep[UDC_EP0IN_IX].regs->ctl);
2728                                         tmp |= AMD_BIT(UDC_EPCTL_P);
2729                                         writel(tmp,
2730                                         &dev->ep[UDC_EP0IN_IX].regs->ctl);
2731
2732                                         /* all bytes will be transferred */
2733                                         req->req.actual = req->req.length;
2734
2735                                         /* complete req */
2736                                         complete_req(ep, req, 0);
2737
2738                                 } else {
2739                                         /* write fifo */
2740                                         udc_txfifo_write(ep, &req->req);
2741
2742                                         /* lengh bytes transferred */
2743                                         len = req->req.length - req->req.actual;
2744                                         if (len > ep->ep.maxpacket)
2745                                                 len = ep->ep.maxpacket;
2746
2747                                         req->req.actual += len;
2748                                         if (req->req.actual == req->req.length
2749                                                 || (len != ep->ep.maxpacket)) {
2750                                                 /* complete req */
2751                                                 complete_req(ep, req, 0);
2752                                         }
2753                                 }
2754
2755                         }
2756                 }
2757                 ep->halted = 0;
2758                 dev->stall_ep0in = 0;
2759                 if (!ep->dma) {
2760                         /* clear IN bit */
2761                         writel(AMD_BIT(UDC_EPSTS_IN),
2762                                 &dev->ep[UDC_EP0IN_IX].regs->sts);
2763                 }
2764         }
2765
2766         return ret_val;
2767 }
2768
2769
2770 /* Interrupt handler for global device events */
2771 static irqreturn_t udc_dev_isr(struct udc *dev, u32 dev_irq)
2772 __releases(dev->lock)
2773 __acquires(dev->lock)
2774 {
2775         irqreturn_t ret_val = IRQ_NONE;
2776         u32 tmp;
2777         u32 cfg;
2778         struct udc_ep *ep;
2779         u16 i;
2780         u8 udc_csr_epix;
2781
2782         /* SET_CONFIG irq ? */
2783         if (dev_irq & AMD_BIT(UDC_DEVINT_SC)) {
2784                 ret_val = IRQ_HANDLED;
2785
2786                 /* read config value */
2787                 tmp = readl(&dev->regs->sts);
2788                 cfg = AMD_GETBITS(tmp, UDC_DEVSTS_CFG);
2789                 DBG(dev, "SET_CONFIG interrupt: config=%d\n", cfg);
2790                 dev->cur_config = cfg;
2791                 dev->set_cfg_not_acked = 1;
2792
2793                 /* make usb request for gadget driver */
2794                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2795                 setup_data.request.bRequest = USB_REQ_SET_CONFIGURATION;
2796                 setup_data.request.wValue = cpu_to_le16(dev->cur_config);
2797
2798                 /* programm the NE registers */
2799                 for (i = 0; i < UDC_EP_NUM; i++) {
2800                         ep = &dev->ep[i];
2801                         if (ep->in) {
2802
2803                                 /* ep ix in UDC CSR register space */
2804                                 udc_csr_epix = ep->num;
2805
2806
2807                         /* OUT ep */
2808                         } else {
2809                                 /* ep ix in UDC CSR register space */
2810                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2811                         }
2812
2813                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2814                         /* ep cfg */
2815                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_config,
2816                                                 UDC_CSR_NE_CFG);
2817                         /* write reg */
2818                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2819
2820                         /* clear stall bits */
2821                         ep->halted = 0;
2822                         tmp = readl(&ep->regs->ctl);
2823                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2824                         writel(tmp, &ep->regs->ctl);
2825                 }
2826                 /* call gadget zero with setup data received */
2827                 spin_unlock(&dev->lock);
2828                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2829                 spin_lock(&dev->lock);
2830
2831         } /* SET_INTERFACE ? */
2832         if (dev_irq & AMD_BIT(UDC_DEVINT_SI)) {
2833                 ret_val = IRQ_HANDLED;
2834
2835                 dev->set_cfg_not_acked = 1;
2836                 /* read interface and alt setting values */
2837                 tmp = readl(&dev->regs->sts);
2838                 dev->cur_alt = AMD_GETBITS(tmp, UDC_DEVSTS_ALT);
2839                 dev->cur_intf = AMD_GETBITS(tmp, UDC_DEVSTS_INTF);
2840
2841                 /* make usb request for gadget driver */
2842                 memset(&setup_data, 0 , sizeof(union udc_setup_data));
2843                 setup_data.request.bRequest = USB_REQ_SET_INTERFACE;
2844                 setup_data.request.bRequestType = USB_RECIP_INTERFACE;
2845                 setup_data.request.wValue = cpu_to_le16(dev->cur_alt);
2846                 setup_data.request.wIndex = cpu_to_le16(dev->cur_intf);
2847
2848                 DBG(dev, "SET_INTERFACE interrupt: alt=%d intf=%d\n",
2849                                 dev->cur_alt, dev->cur_intf);
2850
2851                 /* programm the NE registers */
2852                 for (i = 0; i < UDC_EP_NUM; i++) {
2853                         ep = &dev->ep[i];
2854                         if (ep->in) {
2855
2856                                 /* ep ix in UDC CSR register space */
2857                                 udc_csr_epix = ep->num;
2858
2859
2860                         /* OUT ep */
2861                         } else {
2862                                 /* ep ix in UDC CSR register space */
2863                                 udc_csr_epix = ep->num - UDC_CSR_EP_OUT_IX_OFS;
2864                         }
2865
2866                         /* UDC CSR reg */
2867                         /* set ep values */
2868                         tmp = readl(&dev->csr->ne[udc_csr_epix]);
2869                         /* ep interface */
2870                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_intf,
2871                                                 UDC_CSR_NE_INTF);
2872                         /* tmp = AMD_ADDBITS(tmp, 2, UDC_CSR_NE_INTF); */
2873                         /* ep alt */
2874                         tmp = AMD_ADDBITS(tmp, ep->dev->cur_alt,
2875                                                 UDC_CSR_NE_ALT);
2876                         /* write reg */
2877                         writel(tmp, &dev->csr->ne[udc_csr_epix]);
2878
2879                         /* clear stall bits */
2880                         ep->halted = 0;
2881                         tmp = readl(&ep->regs->ctl);
2882                         tmp = tmp & AMD_CLEAR_BIT(UDC_EPCTL_S);
2883                         writel(tmp, &ep->regs->ctl);
2884                 }
2885
2886                 /* call gadget zero with setup data received */
2887                 spin_unlock(&dev->lock);
2888                 tmp = dev->driver->setup(&dev->gadget, &setup_data.request);
2889                 spin_lock(&dev->lock);
2890
2891         } /* USB reset */
2892         if (dev_irq & AMD_BIT(UDC_DEVINT_UR)) {
2893                 DBG(dev, "USB Reset interrupt\n");
2894                 ret_val = IRQ_HANDLED;
2895
2896                 /* allow soft reset when suspend occurs */
2897                 soft_reset_occured = 0;
2898
2899                 dev->waiting_zlp_ack_ep0in = 0;
2900                 dev->set_cfg_not_acked = 0;
2901
2902                 /* mask not needed interrupts */
2903                 udc_mask_unused_interrupts(dev);
2904
2905                 /* call gadget to resume and reset configs etc. */
2906                 spin_unlock(&dev->lock);
2907                 if (dev->sys_suspended && dev->driver->resume) {
2908                         dev->driver->resume(&dev->gadget);
2909                         dev->sys_suspended = 0;
2910                 }
2911                 usb_gadget_udc_reset(&dev->gadget, dev->driver);
2912                 spin_lock(&dev->lock);
2913
2914                 /* disable ep0 to empty req queue */
2915                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2916                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2917
2918                 /* soft reset when rxfifo not empty */
2919                 tmp = readl(&dev->regs->sts);
2920                 if (!(tmp & AMD_BIT(UDC_DEVSTS_RXFIFO_EMPTY))
2921                                 && !soft_reset_after_usbreset_occured) {
2922                         udc_soft_reset(dev);
2923                         soft_reset_after_usbreset_occured++;
2924                 }
2925
2926                 /*
2927                  * DMA reset to kill potential old DMA hw hang,
2928                  * POLL bit is already reset by ep_init() through
2929                  * disconnect()
2930                  */
2931                 DBG(dev, "DMA machine reset\n");
2932                 tmp = readl(&dev->regs->cfg);
2933                 writel(tmp | AMD_BIT(UDC_DEVCFG_DMARST), &dev->regs->cfg);
2934                 writel(tmp, &dev->regs->cfg);
2935
2936                 /* put into initial config */
2937                 udc_basic_init(dev);
2938
2939                 /* enable device setup interrupts */
2940                 udc_enable_dev_setup_interrupts(dev);
2941
2942                 /* enable suspend interrupt */
2943                 tmp = readl(&dev->regs->irqmsk);
2944                 tmp &= AMD_UNMASK_BIT(UDC_DEVINT_US);
2945                 writel(tmp, &dev->regs->irqmsk);
2946
2947         } /* USB suspend */
2948         if (dev_irq & AMD_BIT(UDC_DEVINT_US)) {
2949                 DBG(dev, "USB Suspend interrupt\n");
2950                 ret_val = IRQ_HANDLED;
2951                 if (dev->driver->suspend) {
2952                         spin_unlock(&dev->lock);
2953                         dev->sys_suspended = 1;
2954                         dev->driver->suspend(&dev->gadget);
2955                         spin_lock(&dev->lock);
2956                 }
2957         } /* new speed ? */
2958         if (dev_irq & AMD_BIT(UDC_DEVINT_ENUM)) {
2959                 DBG(dev, "ENUM interrupt\n");
2960                 ret_val = IRQ_HANDLED;
2961                 soft_reset_after_usbreset_occured = 0;
2962
2963                 /* disable ep0 to empty req queue */
2964                 empty_req_queue(&dev->ep[UDC_EP0IN_IX]);
2965                 ep_init(dev->regs, &dev->ep[UDC_EP0IN_IX]);
2966
2967                 /* link up all endpoints */
2968                 udc_setup_endpoints(dev);
2969                 dev_info(dev->dev, "Connect: %s\n",
2970                          usb_speed_string(dev->gadget.speed));
2971
2972                 /* init ep 0 */
2973                 activate_control_endpoints(dev);
2974
2975                 /* enable ep0 interrupts */
2976                 udc_enable_ep0_interrupts(dev);
2977         }
2978         /* session valid change interrupt */
2979         if (dev_irq & AMD_BIT(UDC_DEVINT_SVC)) {
2980                 DBG(dev, "USB SVC interrupt\n");
2981                 ret_val = IRQ_HANDLED;
2982
2983                 /* check that session is not valid to detect disconnect */
2984                 tmp = readl(&dev->regs->sts);
2985                 if (!(tmp & AMD_BIT(UDC_DEVSTS_SESSVLD))) {
2986                         /* disable suspend interrupt */
2987                         tmp = readl(&dev->regs->irqmsk);
2988                         tmp |= AMD_BIT(UDC_DEVINT_US);
2989                         writel(tmp, &dev->regs->irqmsk);
2990                         DBG(dev, "USB Disconnect (session valid low)\n");
2991                         /* cleanup on disconnect */
2992                         usb_disconnect(udc);
2993                 }
2994
2995         }
2996
2997         return ret_val;
2998 }
2999
3000 /* Interrupt Service Routine, see Linux Kernel Doc for parameters */
3001 irqreturn_t udc_irq(int irq, void *pdev)
3002 {
3003         struct udc *dev = pdev;
3004         u32 reg;
3005         u16 i;
3006         u32 ep_irq;
3007         irqreturn_t ret_val = IRQ_NONE;
3008
3009         spin_lock(&dev->lock);
3010
3011         /* check for ep irq */
3012         reg = readl(&dev->regs->ep_irqsts);
3013         if (reg) {
3014                 if (reg & AMD_BIT(UDC_EPINT_OUT_EP0))
3015                         ret_val |= udc_control_out_isr(dev);
3016                 if (reg & AMD_BIT(UDC_EPINT_IN_EP0))
3017                         ret_val |= udc_control_in_isr(dev);
3018
3019                 /*
3020                  * data endpoint
3021                  * iterate ep's
3022                  */
3023                 for (i = 1; i < UDC_EP_NUM; i++) {
3024                         ep_irq = 1 << i;
3025                         if (!(reg & ep_irq) || i == UDC_EPINT_OUT_EP0)
3026                                 continue;
3027
3028                         /* clear irq status */
3029                         writel(ep_irq, &dev->regs->ep_irqsts);
3030
3031                         /* irq for out ep ? */
3032                         if (i > UDC_EPIN_NUM)
3033                                 ret_val |= udc_data_out_isr(dev, i);
3034                         else
3035                                 ret_val |= udc_data_in_isr(dev, i);
3036                 }
3037
3038         }
3039
3040
3041         /* check for dev irq */
3042         reg = readl(&dev->regs->irqsts);
3043         if (reg) {
3044                 /* clear irq */
3045                 writel(reg, &dev->regs->irqsts);
3046                 ret_val |= udc_dev_isr(dev, reg);
3047         }
3048
3049
3050         spin_unlock(&dev->lock);
3051         return ret_val;
3052 }
3053 EXPORT_SYMBOL_GPL(udc_irq);
3054
3055 /* Tears down device */
3056 void gadget_release(struct device *pdev)
3057 {
3058         struct amd5536udc *dev = dev_get_drvdata(pdev);
3059         kfree(dev);
3060 }
3061 EXPORT_SYMBOL_GPL(gadget_release);
3062
3063 /* Cleanup on device remove */
3064 void udc_remove(struct udc *dev)
3065 {
3066         /* remove timer */
3067         stop_timer++;
3068         if (timer_pending(&udc_timer))
3069                 wait_for_completion(&on_exit);
3070         if (udc_timer.data)
3071                 del_timer_sync(&udc_timer);
3072         /* remove pollstall timer */
3073         stop_pollstall_timer++;
3074         if (timer_pending(&udc_pollstall_timer))
3075                 wait_for_completion(&on_pollstall_exit);
3076         if (udc_pollstall_timer.data)
3077                 del_timer_sync(&udc_pollstall_timer);
3078         udc = NULL;
3079 }
3080 EXPORT_SYMBOL_GPL(udc_remove);
3081
3082 /* free all the dma pools */
3083 void free_dma_pools(struct udc *dev)
3084 {
3085         dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td,
3086                       dev->ep[UDC_EP0OUT_IX].td_phys);
3087         dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3088                       dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3089         dma_pool_destroy(dev->stp_requests);
3090         dma_pool_destroy(dev->data_requests);
3091 }
3092 EXPORT_SYMBOL_GPL(free_dma_pools);
3093
3094 /* create dma pools on init */
3095 int init_dma_pools(struct udc *dev)
3096 {
3097         struct udc_stp_dma      *td_stp;
3098         struct udc_data_dma     *td_data;
3099         int retval;
3100
3101         /* consistent DMA mode setting ? */
3102         if (use_dma_ppb) {
3103                 use_dma_bufferfill_mode = 0;
3104         } else {
3105                 use_dma_ppb_du = 0;
3106                 use_dma_bufferfill_mode = 1;
3107         }
3108
3109         /* DMA setup */
3110         dev->data_requests = dma_pool_create("data_requests", dev->dev,
3111                 sizeof(struct udc_data_dma), 0, 0);
3112         if (!dev->data_requests) {
3113                 DBG(dev, "can't get request data pool\n");
3114                 return -ENOMEM;
3115         }
3116
3117         /* EP0 in dma regs = dev control regs */
3118         dev->ep[UDC_EP0IN_IX].dma = &dev->regs->ctl;
3119
3120         /* dma desc for setup data */
3121         dev->stp_requests = dma_pool_create("setup requests", dev->dev,
3122                 sizeof(struct udc_stp_dma), 0, 0);
3123         if (!dev->stp_requests) {
3124                 DBG(dev, "can't get stp request pool\n");
3125                 retval = -ENOMEM;
3126                 goto err_create_dma_pool;
3127         }
3128         /* setup */
3129         td_stp = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3130                                 &dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3131         if (!td_stp) {
3132                 retval = -ENOMEM;
3133                 goto err_alloc_dma;
3134         }
3135         dev->ep[UDC_EP0OUT_IX].td_stp = td_stp;
3136
3137         /* data: 0 packets !? */
3138         td_data = dma_pool_alloc(dev->stp_requests, GFP_KERNEL,
3139                                 &dev->ep[UDC_EP0OUT_IX].td_phys);
3140         if (!td_data) {
3141                 retval = -ENOMEM;
3142                 goto err_alloc_phys;
3143         }
3144         dev->ep[UDC_EP0OUT_IX].td = td_data;
3145         return 0;
3146
3147 err_alloc_phys:
3148         dma_pool_free(dev->stp_requests, dev->ep[UDC_EP0OUT_IX].td_stp,
3149                       dev->ep[UDC_EP0OUT_IX].td_stp_dma);
3150 err_alloc_dma:
3151         dma_pool_destroy(dev->stp_requests);
3152         dev->stp_requests = NULL;
3153 err_create_dma_pool:
3154         dma_pool_destroy(dev->data_requests);
3155         dev->data_requests = NULL;
3156         return retval;
3157 }
3158 EXPORT_SYMBOL_GPL(init_dma_pools);
3159
3160 /* general probe */
3161 int udc_probe(struct udc *dev)
3162 {
3163         char            tmp[128];
3164         u32             reg;
3165         int             retval;
3166
3167         /* mark timer as not initialized */
3168         udc_timer.data = 0;
3169         udc_pollstall_timer.data = 0;
3170
3171         /* device struct setup */
3172         dev->gadget.ops = &udc_ops;
3173
3174         dev_set_name(&dev->gadget.dev, "gadget");
3175         dev->gadget.name = name;
3176         dev->gadget.max_speed = USB_SPEED_HIGH;
3177
3178         /* init registers, interrupts, ... */
3179         startup_registers(dev);
3180
3181         dev_info(dev->dev, "%s\n", mod_desc);
3182
3183         snprintf(tmp, sizeof(tmp), "%d", dev->irq);
3184
3185         /* Print this device info for AMD chips only*/
3186         if (dev->chiprev == UDC_HSA0_REV ||
3187             dev->chiprev == UDC_HSB1_REV) {
3188                 dev_info(dev->dev, "irq %s, pci mem %08lx, chip rev %02x(Geode5536 %s)\n",
3189                          tmp, dev->phys_addr, dev->chiprev,
3190                          (dev->chiprev == UDC_HSA0_REV) ?
3191                          "A0" : "B1");
3192                 strcpy(tmp, UDC_DRIVER_VERSION_STRING);
3193                 if (dev->chiprev == UDC_HSA0_REV) {
3194                         dev_err(dev->dev, "chip revision is A0; too old\n");
3195                         retval = -ENODEV;
3196                         goto finished;
3197                 }
3198                 dev_info(dev->dev,
3199                          "driver version: %s(for Geode5536 B1)\n", tmp);
3200         }
3201
3202         udc = dev;
3203
3204         retval = usb_add_gadget_udc_release(udc->dev, &dev->gadget,
3205                                             gadget_release);
3206         if (retval)
3207                 goto finished;
3208
3209         /* timer init */
3210         init_timer(&udc_timer);
3211         udc_timer.function = udc_timer_function;
3212         udc_timer.data = 1;
3213         /* timer pollstall init */
3214         init_timer(&udc_pollstall_timer);
3215         udc_pollstall_timer.function = udc_pollstall_timer_function;
3216         udc_pollstall_timer.data = 1;
3217
3218         /* set SD */
3219         reg = readl(&dev->regs->ctl);
3220         reg |= AMD_BIT(UDC_DEVCTL_SD);
3221         writel(reg, &dev->regs->ctl);
3222
3223         /* print dev register info */
3224         print_regs(dev);
3225
3226         return 0;
3227
3228 finished:
3229         return retval;
3230 }
3231 EXPORT_SYMBOL_GPL(udc_probe);
3232
3233 MODULE_DESCRIPTION(UDC_MOD_DESCRIPTION);
3234 MODULE_AUTHOR("Thomas Dahlmann");
3235 MODULE_LICENSE("GPL");