drivers/usb/host/ehci-fsl.c

   1 /*
   2  * Copyright 2005-2009 MontaVista Software, Inc.
   3  * Copyright 2008,2012,2015      Freescale Semiconductor, Inc.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License as published by the
   7  * Free Software Foundation; either version 2 of the License, or (at your
   8  * option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful, but
  11  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  12  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software Foundation,
  17  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  *
  19  * Ported to 834x by Randy Vinson <rvinson@mvista.com> using code provided
  20  * by Hunter Wu.
  21  * Power Management support by Dave Liu <daveliu@freescale.com>,
  22  * Jerry Huang <Chang-Ming.Huang@freescale.com> and
  23  * Anton Vorontsov <avorontsov@ru.mvista.com>.
  24  */
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/types.h>
  29 #include <linux/delay.h>
  30 #include <linux/pm.h>
  31 #include <linux/err.h>
  32 #include <linux/usb.h>
  33 #include <linux/usb/ehci_def.h>
  34 #include <linux/usb/hcd.h>
  35 #include <linux/usb/otg.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/fsl_devices.h>
  38 #include <linux/of_platform.h>
  39
  40 #include "ehci.h"
  41 #include "ehci-fsl.h"
  42
  43 #define DRIVER_DESC "Freescale EHCI Host controller driver"
  44 #define DRV_NAME "ehci-fsl"
  45
  46 static struct hc_driver __read_mostly fsl_ehci_hc_driver;
  47
  48 /* configure so an HC device and id are always provided */
  49 /* always called with process context; sleeping is OK */
  50
  51 /*
  52  * fsl_ehci_drv_probe - initialize FSL-based HCDs
  53  * @pdev: USB Host Controller being probed
  54  * Context: !in_interrupt()
  55  *
  56  * Allocates basic resources for this USB host controller.
  57  *
  58  */
  59 static int fsl_ehci_drv_probe(struct platform_device *pdev)
  60 {
  61         struct fsl_usb2_platform_data *pdata;
  62         struct usb_hcd *hcd;
  63         struct resource *res;
  64         int irq;
  65         int retval;
  66
  67         pr_debug("initializing FSL-SOC USB Controller\n");
  68
  69         /* Need platform data for setup */
  70         pdata = dev_get_platdata(&pdev->dev);
  71         if (!pdata) {
  72                 dev_err(&pdev->dev,
  73                         "No platform data for %s.\n", dev_name(&pdev->dev));
  74                 return -ENODEV;
  75         }
  76
  77         /*
  78          * This is a host mode driver, verify that we're supposed to be
  79          * in host mode.
  80          */
  81         if (!((pdata->operating_mode == FSL_USB2_DR_HOST) ||
  82               (pdata->operating_mode == FSL_USB2_MPH_HOST) ||
  83               (pdata->operating_mode == FSL_USB2_DR_OTG))) {
  84                 dev_err(&pdev->dev,
  85                         "Non Host Mode configured for %s. Wrong driver linked.\n",
  86                         dev_name(&pdev->dev));
  87                 return -ENODEV;
  88         }
  89
  90         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  91         if (!res) {
  92                 dev_err(&pdev->dev,
  93                         "Found HC with no IRQ. Check %s setup!\n",
  94                         dev_name(&pdev->dev));
  95                 return -ENODEV;
  96         }
  97         irq = res->start;
  98
  99         hcd = usb_create_hcd(&fsl_ehci_hc_driver, &pdev->dev,
 100                                 dev_name(&pdev->dev));
 101         if (!hcd) {
 102                 retval = -ENOMEM;
 103                 goto err1;
 104         }
 105
 106         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 107         hcd->regs = devm_ioremap_resource(&pdev->dev, res);
 108         if (IS_ERR(hcd->regs)) {
 109                 retval = PTR_ERR(hcd->regs);
 110                 goto err2;
 111         }
 112
 113         hcd->rsrc_start = res->start;
 114         hcd->rsrc_len = resource_size(res);
 115
 116         pdata->regs = hcd->regs;
 117
 118         if (pdata->power_budget)
 119                 hcd->power_budget = pdata->power_budget;
 120
 121         /*
 122          * do platform specific init: check the clock, grab/config pins, etc.
 123          */
 124         if (pdata->init && pdata->init(pdev)) {
 125                 retval = -ENODEV;
 126                 goto err2;
 127         }
 128
 129         /* Enable USB controller, 83xx or 8536 */
 130         if (pdata->have_sysif_regs && pdata->controller_ver < FSL_USB_VER_1_6)
 131                 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
 132                                 CONTROL_REGISTER_W1C_MASK, 0x4);
 133
 134         /*
 135          * Enable UTMI phy and program PTS field in UTMI mode before asserting
 136          * controller reset for USB Controller version 2.5
 137          */
 138         if (pdata->has_fsl_erratum_a007792) {
 139                 clrsetbits_be32(hcd->regs + FSL_SOC_USB_CTRL,
 140                                 CONTROL_REGISTER_W1C_MASK, CTRL_UTMI_PHY_EN);
 141                 writel(PORT_PTS_UTMI, hcd->regs + FSL_SOC_USB_PORTSC1);
 142         }
 143
 144         /* Don't need to set host mode here. It will be done by tdi_reset() */
 145
 146         retval = usb_add_hcd(hcd, irq, IRQF_SHARED);
 147         if (retval != 0)
 148                 goto err2;
 149         device_wakeup_enable(hcd->self.controller);
 150
 151 #ifdef CONFIG_USB_OTG
 152         if (pdata->operating_mode == FSL_USB2_DR_OTG) {
 153                 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 154
 155                 hcd->usb_phy = usb_get_phy(USB_PHY_TYPE_USB2);
 156                 dev_dbg(&pdev->dev, "hcd=0x%p  ehci=0x%p, phy=0x%p\n",
 157                         hcd, ehci, hcd->usb_phy);
 158
 159                 if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 160                         retval = otg_set_host(hcd->usb_phy->otg,
 161                                               &ehci_to_hcd(ehci)->self);
 162                         if (retval) {
 163                                 usb_put_phy(hcd->usb_phy);
 164                                 goto err2;
 165                         }
 166                 } else {
 167                         dev_err(&pdev->dev, "can't find phy\n");
 168                         retval = -ENODEV;
 169                         goto err2;
 170                 }
 171         }
 172 #endif
 173         return retval;
 174
 175       err2:
 176         usb_put_hcd(hcd);
 177       err1:
 178         dev_err(&pdev->dev, "init %s fail, %d\n", dev_name(&pdev->dev), retval);
 179         if (pdata->exit)
 180                 pdata->exit(pdev);
 181         return retval;
 182 }
 183
 184 static int ehci_fsl_setup_phy(struct usb_hcd *hcd,
 185                                enum fsl_usb2_phy_modes phy_mode,
 186                                unsigned int port_offset)
 187 {
 188         u32 portsc;
 189         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 190         void __iomem *non_ehci = hcd->regs;
 191         struct device *dev = hcd->self.controller;
 192         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 193
 194         if (pdata->controller_ver < 0) {
 195                 dev_warn(hcd->self.controller, "Could not get controller version\n");
 196                 return -ENODEV;
 197         }
 198
 199         portsc = ehci_readl(ehci, &ehci->regs->port_status[port_offset]);
 200         portsc &= ~(PORT_PTS_MSK | PORT_PTS_PTW);
 201
 202         switch (phy_mode) {
 203         case FSL_USB2_PHY_ULPI:
 204                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 205                         /* controller version 1.6 or above */
 206                         clrbits32(non_ehci + FSL_SOC_USB_CTRL,
 207                                   CONTROL_REGISTER_W1C_MASK | UTMI_PHY_EN);
 208                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 209                                         CONTROL_REGISTER_W1C_MASK,
 210                                         ULPI_PHY_CLK_SEL | USB_CTRL_USB_EN);
 211                 }
 212                 portsc |= PORT_PTS_ULPI;
 213                 break;
 214         case FSL_USB2_PHY_SERIAL:
 215                 portsc |= PORT_PTS_SERIAL;
 216                 break;
 217         case FSL_USB2_PHY_UTMI_WIDE:
 218                 portsc |= PORT_PTS_PTW;
 219                 /* fall through */
 220         case FSL_USB2_PHY_UTMI:
 221         case FSL_USB2_PHY_UTMI_DUAL:
 222                 if (pdata->have_sysif_regs && pdata->controller_ver) {
 223                         /* controller version 1.6 or above */
 224                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 225                                         CONTROL_REGISTER_W1C_MASK, UTMI_PHY_EN);
 226                         mdelay(FSL_UTMI_PHY_DLY);  /* Delay for UTMI PHY CLK to
 227                                                 become stable - 10ms*/
 228                 }
 229                 /* enable UTMI PHY */
 230                 if (pdata->have_sysif_regs)
 231                         clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 232                                         CONTROL_REGISTER_W1C_MASK,
 233                                         CTRL_UTMI_PHY_EN);
 234                 portsc |= PORT_PTS_UTMI;
 235                 break;
 236         case FSL_USB2_PHY_NONE:
 237                 break;
 238         }
 239
 240         /*
 241          * check PHY_CLK_VALID to determine phy clock presence before writing
 242          * to portsc
 243          */
 244         if (pdata->check_phy_clk_valid) {
 245                 if (!(ioread32be(non_ehci + FSL_SOC_USB_CTRL) &
 246                     PHY_CLK_VALID)) {
 247                         dev_warn(hcd->self.controller,
 248                                  "USB PHY clock invalid\n");
 249                         return -EINVAL;
 250                 }
 251         }
 252
 253         ehci_writel(ehci, portsc, &ehci->regs->port_status[port_offset]);
 254
 255         if (phy_mode != FSL_USB2_PHY_ULPI && pdata->have_sysif_regs)
 256                 clrsetbits_be32(non_ehci + FSL_SOC_USB_CTRL,
 257                                 CONTROL_REGISTER_W1C_MASK, USB_CTRL_USB_EN);
 258
 259         return 0;
 260 }
 261
 262 static int ehci_fsl_usb_setup(struct ehci_hcd *ehci)
 263 {
 264         struct usb_hcd *hcd = ehci_to_hcd(ehci);
 265         struct fsl_usb2_platform_data *pdata;
 266         void __iomem *non_ehci = hcd->regs;
 267
 268         pdata = dev_get_platdata(hcd->self.controller);
 269
 270         if (pdata->have_sysif_regs) {
 271                 /*
 272                 * Turn on cache snooping hardware, since some PowerPC platforms
 273                 * wholly rely on hardware to deal with cache coherent
 274                 */
 275
 276                 /* Setup Snooping for all the 4GB space */
 277                 /* SNOOP1 starts from 0x0, size 2G */
 278                 iowrite32be(0x0 | SNOOP_SIZE_2GB,
 279                             non_ehci + FSL_SOC_USB_SNOOP1);
 280                 /* SNOOP2 starts from 0x80000000, size 2G */
 281                 iowrite32be(0x80000000 | SNOOP_SIZE_2GB,
 282                             non_ehci + FSL_SOC_USB_SNOOP2);
 283         }
 284
 285         /* Deal with USB erratum A-005275 */
 286         if (pdata->has_fsl_erratum_a005275 == 1)
 287                 ehci->has_fsl_hs_errata = 1;
 288
 289         if ((pdata->operating_mode == FSL_USB2_DR_HOST) ||
 290                         (pdata->operating_mode == FSL_USB2_DR_OTG))
 291                 if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 292                         return -EINVAL;
 293
 294         if (pdata->operating_mode == FSL_USB2_MPH_HOST) {
 295                 unsigned int chip, rev, svr;
 296
 297                 svr = mfspr(SPRN_SVR);
 298                 chip = svr >> 16;
 299                 rev = (svr >> 4) & 0xf;
 300
 301                 /* Deal with USB Erratum #14 on MPC834x Rev 1.0 & 1.1 chips */
 302                 if ((rev == 1) && (chip >= 0x8050) && (chip <= 0x8055))
 303                         ehci->has_fsl_port_bug = 1;
 304
 305                 if (pdata->port_enables & FSL_USB2_PORT0_ENABLED)
 306                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 0))
 307                                 return -EINVAL;
 308
 309                 if (pdata->port_enables & FSL_USB2_PORT1_ENABLED)
 310                         if (ehci_fsl_setup_phy(hcd, pdata->phy_mode, 1))
 311                                 return -EINVAL;
 312         }
 313
 314         if (pdata->have_sysif_regs) {
 315 #ifdef CONFIG_FSL_SOC_BOOKE
 316                 iowrite32be(0x00000008, non_ehci + FSL_SOC_USB_PRICTRL);
 317                 iowrite32be(0x00000080, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
 318 #else
 319                 iowrite32be(0x0000000c, non_ehci + FSL_SOC_USB_PRICTRL);
 320                 iowrite32be(0x00000040, non_ehci + FSL_SOC_USB_AGECNTTHRSH);
 321 #endif
 322                 iowrite32be(0x00000001, non_ehci + FSL_SOC_USB_SICTRL);
 323         }
 324
 325         return 0;
 326 }
 327
 328 /* called after powerup, by probe or system-pm "wakeup" */
 329 static int ehci_fsl_reinit(struct ehci_hcd *ehci)
 330 {
 331         if (ehci_fsl_usb_setup(ehci))
 332                 return -EINVAL;
 333
 334         return 0;
 335 }
 336
 337 /* called during probe() after chip reset completes */
 338 static int ehci_fsl_setup(struct usb_hcd *hcd)
 339 {
 340         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 341         int retval;
 342         struct fsl_usb2_platform_data *pdata;
 343         struct device *dev;
 344
 345         dev = hcd->self.controller;
 346         pdata = dev_get_platdata(hcd->self.controller);
 347         ehci->big_endian_desc = pdata->big_endian_desc;
 348         ehci->big_endian_mmio = pdata->big_endian_mmio;
 349
 350         /* EHCI registers start at offset 0x100 */
 351         ehci->caps = hcd->regs + 0x100;
 352
 353 #ifdef CONFIG_PPC_83xx
 354         /*
 355          * Deal with MPC834X that need port power to be cycled after the power
 356          * fault condition is removed. Otherwise the state machine does not
 357          * reflect PORTSC[CSC] correctly.
 358          */
 359         ehci->need_oc_pp_cycle = 1;
 360 #endif
 361
 362         hcd->has_tt = 1;
 363
 364         retval = ehci_setup(hcd);
 365         if (retval)
 366                 return retval;
 367
 368         if (of_device_is_compatible(dev->parent->of_node,
 369                                     "fsl,mpc5121-usb2-dr")) {
 370                 /*
 371                  * set SBUSCFG:AHBBRST so that control msgs don't
 372                  * fail when doing heavy PATA writes.
 373                  */
 374                 ehci_writel(ehci, SBUSCFG_INCR8,
 375                             hcd->regs + FSL_SOC_USB_SBUSCFG);
 376         }
 377
 378         retval = ehci_fsl_reinit(ehci);
 379         return retval;
 380 }
 381
 382 struct ehci_fsl {
 383         struct ehci_hcd ehci;
 384
 385 #ifdef CONFIG_PM
 386         /* Saved USB PHY settings, need to restore after deep sleep. */
 387         u32 usb_ctrl;
 388 #endif
 389 };
 390
 391 #ifdef CONFIG_PM
 392
 393 #ifdef CONFIG_PPC_MPC512x
 394 static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 395 {
 396         struct usb_hcd *hcd = dev_get_drvdata(dev);
 397         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 398         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 399         u32 tmp;
 400
 401 #ifdef CONFIG_DYNAMIC_DEBUG
 402         u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
 403         mode &= USBMODE_CM_MASK;
 404         tmp = ehci_readl(ehci, hcd->regs + 0x140);      /* usbcmd */
 405
 406         dev_dbg(dev, "suspend=%d already_suspended=%d "
 407                 "mode=%d  usbcmd %08x\n", pdata->suspended,
 408                 pdata->already_suspended, mode, tmp);
 409 #endif
 410
 411         /*
 412          * If the controller is already suspended, then this must be a
 413          * PM suspend.  Remember this fact, so that we will leave the
 414          * controller suspended at PM resume time.
 415          */
 416         if (pdata->suspended) {
 417                 dev_dbg(dev, "already suspended, leaving early\n");
 418                 pdata->already_suspended = 1;
 419                 return 0;
 420         }
 421
 422         dev_dbg(dev, "suspending...\n");
 423
 424         ehci->rh_state = EHCI_RH_SUSPENDED;
 425         dev->power.power_state = PMSG_SUSPEND;
 426
 427         /* ignore non-host interrupts */
 428         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 429
 430         /* stop the controller */
 431         tmp = ehci_readl(ehci, &ehci->regs->command);
 432         tmp &= ~CMD_RUN;
 433         ehci_writel(ehci, tmp, &ehci->regs->command);
 434
 435         /* save EHCI registers */
 436         pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
 437         pdata->pm_command &= ~CMD_RUN;
 438         pdata->pm_status  = ehci_readl(ehci, &ehci->regs->status);
 439         pdata->pm_intr_enable  = ehci_readl(ehci, &ehci->regs->intr_enable);
 440         pdata->pm_frame_index  = ehci_readl(ehci, &ehci->regs->frame_index);
 441         pdata->pm_segment  = ehci_readl(ehci, &ehci->regs->segment);
 442         pdata->pm_frame_list  = ehci_readl(ehci, &ehci->regs->frame_list);
 443         pdata->pm_async_next  = ehci_readl(ehci, &ehci->regs->async_next);
 444         pdata->pm_configured_flag  =
 445                 ehci_readl(ehci, &ehci->regs->configured_flag);
 446         pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
 447         pdata->pm_usbgenctrl = ehci_readl(ehci,
 448                                           hcd->regs + FSL_SOC_USB_USBGENCTRL);
 449
 450         /* clear the W1C bits */
 451         pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
 452
 453         pdata->suspended = 1;
 454
 455         /* clear PP to cut power to the port */
 456         tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
 457         tmp &= ~PORT_POWER;
 458         ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
 459
 460         return 0;
 461 }
 462
 463 static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 464 {
 465         struct usb_hcd *hcd = dev_get_drvdata(dev);
 466         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 467         struct fsl_usb2_platform_data *pdata = dev_get_platdata(dev);
 468         u32 tmp;
 469
 470         dev_dbg(dev, "suspend=%d already_suspended=%d\n",
 471                 pdata->suspended, pdata->already_suspended);
 472
 473         /*
 474          * If the controller was already suspended at suspend time,
 475          * then don't resume it now.
 476          */
 477         if (pdata->already_suspended) {
 478                 dev_dbg(dev, "already suspended, leaving early\n");
 479                 pdata->already_suspended = 0;
 480                 return 0;
 481         }
 482
 483         if (!pdata->suspended) {
 484                 dev_dbg(dev, "not suspended, leaving early\n");
 485                 return 0;
 486         }
 487
 488         pdata->suspended = 0;
 489
 490         dev_dbg(dev, "resuming...\n");
 491
 492         /* set host mode */
 493         tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
 494         ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
 495
 496         ehci_writel(ehci, pdata->pm_usbgenctrl,
 497                     hcd->regs + FSL_SOC_USB_USBGENCTRL);
 498         ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
 499                     hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
 500
 501         ehci_writel(ehci, SBUSCFG_INCR8, hcd->regs + FSL_SOC_USB_SBUSCFG);
 502
 503         /* restore EHCI registers */
 504         ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
 505         ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
 506         ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
 507         ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
 508         ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
 509         ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
 510         ehci_writel(ehci, pdata->pm_configured_flag,
 511                     &ehci->regs->configured_flag);
 512         ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
 513
 514         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 515         ehci->rh_state = EHCI_RH_RUNNING;
 516         dev->power.power_state = PMSG_ON;
 517
 518         tmp = ehci_readl(ehci, &ehci->regs->command);
 519         tmp |= CMD_RUN;
 520         ehci_writel(ehci, tmp, &ehci->regs->command);
 521
 522         usb_hcd_resume_root_hub(hcd);
 523
 524         return 0;
 525 }
 526 #else
 527 static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
 528 {
 529         return 0;
 530 }
 531
 532 static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
 533 {
 534         return 0;
 535 }
 536 #endif /* CONFIG_PPC_MPC512x */
 537
 538 static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
 539 {
 540         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 541
 542         return container_of(ehci, struct ehci_fsl, ehci);
 543 }
 544
 545 static int ehci_fsl_drv_suspend(struct device *dev)
 546 {
 547         struct usb_hcd *hcd = dev_get_drvdata(dev);
 548         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 549         void __iomem *non_ehci = hcd->regs;
 550
 551         if (of_device_is_compatible(dev->parent->of_node,
 552                                     "fsl,mpc5121-usb2-dr")) {
 553                 return ehci_fsl_mpc512x_drv_suspend(dev);
 554         }
 555
 556         ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
 557                         device_may_wakeup(dev));
 558         if (!fsl_deep_sleep())
 559                 return 0;
 560
 561         ehci_fsl->usb_ctrl = ioread32be(non_ehci + FSL_SOC_USB_CTRL);
 562         return 0;
 563 }
 564
 565 static int ehci_fsl_drv_resume(struct device *dev)
 566 {
 567         struct usb_hcd *hcd = dev_get_drvdata(dev);
 568         struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
 569         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 570         void __iomem *non_ehci = hcd->regs;
 571
 572         if (of_device_is_compatible(dev->parent->of_node,
 573                                     "fsl,mpc5121-usb2-dr")) {
 574                 return ehci_fsl_mpc512x_drv_resume(dev);
 575         }
 576
 577         ehci_prepare_ports_for_controller_resume(ehci);
 578         if (!fsl_deep_sleep())
 579                 return 0;
 580
 581         usb_root_hub_lost_power(hcd->self.root_hub);
 582
 583         /* Restore USB PHY settings and enable the controller. */
 584         iowrite32be(ehci_fsl->usb_ctrl, non_ehci + FSL_SOC_USB_CTRL);
 585
 586         ehci_reset(ehci);
 587         ehci_fsl_reinit(ehci);
 588
 589         return 0;
 590 }
 591
 592 static int ehci_fsl_drv_restore(struct device *dev)
 593 {
 594         struct usb_hcd *hcd = dev_get_drvdata(dev);
 595
 596         usb_root_hub_lost_power(hcd->self.root_hub);
 597         return 0;
 598 }
 599
 600 static struct dev_pm_ops ehci_fsl_pm_ops = {
 601         .suspend = ehci_fsl_drv_suspend,
 602         .resume = ehci_fsl_drv_resume,
 603         .restore = ehci_fsl_drv_restore,
 604 };
 605
 606 #define EHCI_FSL_PM_OPS         (&ehci_fsl_pm_ops)
 607 #else
 608 #define EHCI_FSL_PM_OPS         NULL
 609 #endif /* CONFIG_PM */
 610
 611 #ifdef CONFIG_USB_OTG
 612 static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
 613 {
 614         struct ehci_hcd *ehci = hcd_to_ehci(hcd);
 615         u32 status;
 616
 617         if (!port)
 618                 return -EINVAL;
 619
 620         port--;
 621
 622         /* start port reset before HNP protocol time out */
 623         status = readl(&ehci->regs->port_status[port]);
 624         if (!(status & PORT_CONNECT))
 625                 return -ENODEV;
 626
 627         /* hub_wq will finish the reset later */
 628         if (ehci_is_TDI(ehci)) {
 629                 writel(PORT_RESET |
 630                        (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
 631                        &ehci->regs->port_status[port]);
 632         } else {
 633                 writel(PORT_RESET, &ehci->regs->port_status[port]);
 634         }
 635
 636         return 0;
 637 }
 638 #else
 639 #define ehci_start_port_reset   NULL
 640 #endif /* CONFIG_USB_OTG */
 641
 642 static struct ehci_driver_overrides ehci_fsl_overrides __initdata = {
 643         .extra_priv_size = sizeof(struct ehci_fsl),
 644         .reset = ehci_fsl_setup,
 645 };
 646
 647 /**
 648  * fsl_ehci_drv_remove - shutdown processing for FSL-based HCDs
 649  * @dev: USB Host Controller being removed
 650  * Context: !in_interrupt()
 651  *
 652  * Reverses the effect of usb_hcd_fsl_probe().
 653  *
 654  */
 655
 656 static int fsl_ehci_drv_remove(struct platform_device *pdev)
 657 {
 658         struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
 659         struct usb_hcd *hcd = platform_get_drvdata(pdev);
 660
 661         if (!IS_ERR_OR_NULL(hcd->usb_phy)) {
 662                 otg_set_host(hcd->usb_phy->otg, NULL);
 663                 usb_put_phy(hcd->usb_phy);
 664         }
 665
 666         usb_remove_hcd(hcd);
 667
 668         /*
 669          * do platform specific un-initialization:
 670          * release iomux pins, disable clock, etc.
 671          */
 672         if (pdata->exit)
 673                 pdata->exit(pdev);
 674         usb_put_hcd(hcd);
 675
 676         return 0;
 677 }
 678
 679 static struct platform_driver ehci_fsl_driver = {
 680         .probe = fsl_ehci_drv_probe,
 681         .remove = fsl_ehci_drv_remove,
 682         .shutdown = usb_hcd_platform_shutdown,
 683         .driver = {
 684                 .name = "fsl-ehci",
 685                 .pm = EHCI_FSL_PM_OPS,
 686         },
 687 };
 688
 689 static int __init ehci_fsl_init(void)
 690 {
 691         if (usb_disabled())
 692                 return -ENODEV;
 693
 694         pr_info(DRV_NAME ": " DRIVER_DESC "\n");
 695
 696         ehci_init_driver(&fsl_ehci_hc_driver, &ehci_fsl_overrides);
 697
 698         fsl_ehci_hc_driver.product_desc =
 699                         "Freescale On-Chip EHCI Host Controller";
 700         fsl_ehci_hc_driver.start_port_reset = ehci_start_port_reset;
 701
 702
 703         return platform_driver_register(&ehci_fsl_driver);
 704 }
 705 module_init(ehci_fsl_init);
 706
 707 static void __exit ehci_fsl_cleanup(void)
 708 {
 709         platform_driver_unregister(&ehci_fsl_driver);
 710 }
 711 module_exit(ehci_fsl_cleanup);
 712
 713 MODULE_DESCRIPTION(DRIVER_DESC);
 714 MODULE_LICENSE("GPL");
 715 MODULE_ALIAS("platform:" DRV_NAME);